2021-12-16 20:07:50 +08:00
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export RV_ROOT = ${PWD}/../..
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2021-12-17 21:29:59 +08:00
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LLVMINSTALL = /home/colin/develop/llvm-build/install
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2022-01-27 16:42:31 +08:00
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GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
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2021-12-17 21:29:59 +08:00
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2022-01-17 20:18:33 +08:00
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DEMODIR = ${PWD}
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BUILD_DIR = ${DEMODIR}/build
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2021-12-17 21:29:59 +08:00
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RV_DESIGN = ${RV_ROOT}/design
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2022-01-17 19:53:50 +08:00
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RV_SOC = ${RV_ROOT}/soc
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2021-12-16 20:07:50 +08:00
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TEST = hello_world
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ifdef debug
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DEBUG_PLUS = +dumpon
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VERILATOR_DEBUG = --trace
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endif
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2022-01-17 20:18:33 +08:00
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LINK = $(DEMODIR)/link.ld
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2021-12-16 20:07:50 +08:00
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# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
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CFLAGS += "-std=c++11"
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# Optimization for better performance; alternative is nothing for slower runtime (faster compiles)
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# -O2 for faster runtime (slower compiles), or -O for balance.
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VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
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# Targets
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all: clean verilator
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clean:
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rm -rf build obj_dir
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2022-01-19 17:57:37 +08:00
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swerv_define :
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2022-02-17 19:35:01 +08:00
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BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set iccm_enable
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2021-12-16 20:07:50 +08:00
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##################### Verilog Builds #####################################
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2022-01-19 17:57:37 +08:00
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verilator-build: swerv_define
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2021-12-16 20:07:50 +08:00
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echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
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2022-01-19 17:57:37 +08:00
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verilator --cc -CFLAGS ${CFLAGS} \
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2022-01-19 20:32:39 +08:00
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$(BUILD_DIR)/common_defines.vh \
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-I${BUILD_DIR} \
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2021-12-16 20:07:50 +08:00
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-Wno-UNOPTFLAT \
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2022-02-15 16:27:53 +08:00
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-F ${RV_SOC}/soc_top.mk \
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-F ${RV_SOC}/soc_sim.mk \
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2022-02-14 20:32:21 +08:00
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$(RV_SOC)/soc_sim.sv \
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--top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG)
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cp ${DEMODIR}/test_soc_sim.cpp obj_dir
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$(MAKE) -j -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)
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2021-12-16 20:07:50 +08:00
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##################### Simulation Runs #####################################
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verilator: program.hex verilator-build
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2022-02-14 20:32:21 +08:00
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cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}
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2021-12-16 20:07:50 +08:00
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2022-01-19 17:57:37 +08:00
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##################### Test hex Build #####################################
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2021-12-16 20:07:50 +08:00
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2022-01-20 11:44:59 +08:00
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program.hex: $(TEST).out
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2022-01-04 20:39:14 +08:00
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@echo Building $(TEST)
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$(GCC_PREFIX)-objcopy -O verilog $(BUILD_DIR)/$(TEST).out $(BUILD_DIR)/program.hex
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$(GCC_PREFIX)-objdump -S $(BUILD_DIR)/$(TEST).out > $(BUILD_DIR)/$(TEST).dis
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2021-12-16 20:07:50 +08:00
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2022-01-20 11:44:59 +08:00
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build: $(TEST).out
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2022-01-04 20:39:14 +08:00
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@echo Completed building $(TEST)
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2022-01-19 17:57:37 +08:00
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%.out : %.c swerv_define
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2022-01-04 20:39:14 +08:00
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$(LLVMINSTALL)/bin/clang --target=riscv32 -march=rv32gc $*.c -S -o $(BUILD_DIR)/$*.s -mno-relax
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2021-12-17 21:29:59 +08:00
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$(LLVMINSTALL)/bin/clang --target=riscv32 -march=rv32gc $*.c -c -o $(BUILD_DIR)/$*.o -mno-relax
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2022-01-04 20:39:14 +08:00
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$(LLVMINSTALL)/bin/ld.lld $(BUILD_DIR)/$*.o -Map=$(BUILD_DIR)/$(TEST).map -T$(LINK) -o $(BUILD_DIR)/$*.out
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@echo Completed building $(TEST)
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2021-12-16 20:07:50 +08:00
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help:
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@echo Possible targets: verilator help clean all verilator-build program.hex
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2022-01-27 16:42:31 +08:00
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.PHONY: help clean verilator
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