abstractaccelerator/fpga/ram/Makefile

TARGET=top

OBJS+=top.sv
OBJS+=bram.sv

all: ${TARGET}.bit

$(TARGET).json: $(OBJS)
	yosys -p "read_verilog -sv $(OBJS); synth_ecp5 -top ${TARGET} -json $@"

$(TARGET).config: $(TARGET).json
	nextpnr-ecp5 --25k --package CABGA381 --speed 6 --json $< --textcfg $@ --lpf $(TARGET).lpf --freq 65

$(TARGET).bit: $(TARGET).config
	ecppack --svf ${TARGET}.svf $< $@

${TARGET}.svf : ${TARGET}.bit

prog: ${TARGET}.svf
	# openFPGALoader -c digilent_hs2 $(TARGET).bit
	./dapprog ${TARGET}.svf 

clean:
	rm -rf *.svf *.bit *.config *.ys *.json obj_dir logs

verilator:
	rm -rf obj_dir logs
	verilator -Wall --cc --exe --build --trace sim_main.cpp $(OBJS)
	obj_dir/Vtop +trace

.PHONY: prog clean