178 lines
2.8 KiB
ArmAsm
178 lines
2.8 KiB
ArmAsm
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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.text
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.global __start
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__start:
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#enable btb & bht
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# csrr x3, mhcr
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# ori x3, x3, 0x20
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# csrw mhcr, x3
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#
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# li x3, 0x1000
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# csrrs x0, mhcr, x3
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#la x3, 0x20000
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la x2, __kernel_stack
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#Init_Stack:
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#
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# sw x0, 0(x2)
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# addi x2, x2, -4
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# addi x3, x3, -4
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# bnez x3, Init_Stack
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la x3, __erodata
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la x4, __data_start__
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la x5, __data_end__
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sub x5, x5, x4
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beqz x5, L_loop0_done
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L_loop0:
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lw x6, 0(x3)
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sw x6, 0(x4)
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addi x3, x3, 0x4
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addi x4, x4, 0x4
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addi x5, x5, -4
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bnez x5, L_loop0
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L_loop0_done:
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la x3, __data_end__
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la x4, __bss_end__
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li x5, 0
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sub x4, x4, x3
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beqz x4, L_loop1_done
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L_loop1:
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sw x5, 0(x3)
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addi x3, x3, 0x4
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addi x4, x4, -4
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bnez x4, L_loop1
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L_loop1_done:
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la x3, trap_handler
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csrw mtvec, x3
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la x3, vector_table
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addi x3, x3, 64
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csrw mtvt, x3
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li a5, 0xeffff000
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li a6, 0x20000
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sw a6, 0(a5)
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li a7, 0xc
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sw a7, 4(a5)
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li a6, 0x40000
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li a7, 0xc
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sw a6, 8(a5)
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sw a7, 12(a5)
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li a6, 0x50000
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li a7, 0x10
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sw a6, 16(a5)
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sw a7, 20(a5)
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li a5, 0x40011000
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li a6, 0xff
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sw a6, 0(a5)
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li a6, 0x3
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sw a6, 8(a5)
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lw a6, 4(a5)
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# enable mie
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li x3,0x88
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csrw mstatus,x3
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# enable fpu
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li x3, 0x2000
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csrs mstatus,x3
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li x3,0x103f
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csrw mhcr,x3
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li x3,0x400c
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csrw mhint,x3
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__to_main:
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jal main
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.global __exit
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__exit:
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fence.i
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fence
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li x4, 0x6000fff8
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addi x3, x0,0xFF
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slli x3, x3,0x4
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addi x3, x3, 0xf #0xFFF
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sw x3, 0(x4)
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.global __fail
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__fail:
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fence.i
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fence
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li x4, 0x6000fff8
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addi x3, x0,0xEE
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slli x3, x3,0x4
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addi x3, x3,0xe #0xEEE
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sw x3, 0(x4)
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.align 6
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.global trap_handler
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trap_handler:
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j __synchronous_exception
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.align 2
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j __fail
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__synchronous_exception:
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sw x13,-4(x2)
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sw x14,-8(x2)
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sw x15,-12(x2)
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csrr x14,mcause
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andi x15,x14,0xff #cause
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srli x14,x14,0x1b #int
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andi x14,x14,0x10 #mask bit
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add x14,x14,x15 #{int,cause}
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slli x14,x14,0x2 #offset
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la x15,vector_table
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add x15,x14,x15 #target pc
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lw x14, 0(x15) #get exception addr
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lw x13, -4(x2) #recover x16
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lw x15, -12(x2) #recover x15
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#addi x14,x14,-4
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jr x14
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.global vector_table
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.align 6
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vector_table: #totally 256 entries
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.rept 256
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.long __dummy
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.endr
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.global __dummy
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__dummy:
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j __fail
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.data
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.long 0
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