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fix synthesis syntax in rvdffe in beh_lib.sv

This commit is contained in:
Joseph Rahmeh 2019-08-08 07:51:56 -07:00
parent 0dacc978da
commit 1cf98e765d
1 changed files with 6 additions and 0 deletions
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6
design/lib/beh_lib.sv
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@ -144,9 +144,15 @@ module rvdffe #( parameter WIDTH=1 )
logic l1clk; logic l1clk;
`ifdef RV_FPGA_OPTIMIZE `ifdef RV_FPGA_OPTIMIZE
`ifndef PHYSICAL
begin: genblock begin: genblock
`endif
rvdffs #(WIDTH) dff ( .* ); rvdffs #(WIDTH) dff ( .* );
`ifndef PHYSICAL
end end
`endif
`else `else
`ifndef PHYSICAL `ifndef PHYSICAL