fix synthesis syntax in rvdffe in beh_lib.sv

2019-08-08 07:51:56 -07:00 · 2019-08-08 07:51:56 -07:00 · 1cf98e765d
parent 0dacc978da
commit 1cf98e765d
1 changed files with 6 additions and 0 deletions
--- a/design/lib/beh_lib.sv
+++ b/design/lib/beh_lib.sv
@ -144,9 +144,15 @@ module rvdffe #( parameter WIDTH=1 )
   logic 		      l1clk;

 `ifdef RV_FPGA_OPTIMIZE
+
+`ifndef PHYSICAL   
   begin: genblock
+`endif
     rvdffs #(WIDTH) dff ( .* );
+`ifndef PHYSICAL   
   end
+`endif
+
 `else
   
 `ifndef PHYSICAL