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Update led display.

This commit is contained in:
Colin 2025-04-20 21:31:53 +08:00
parent 4a1d9bd7d5
commit 834f964547
1 changed files with 14 additions and 7 deletions
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21
fpga/xc7z010/led.v
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@ -3,11 +3,11 @@ module led(
output reg led // led 输出(高电平有效) output reg led // led 输出(高电平有效)
); );
localparam MAX_DELAY_CNT = 1000000, localparam MAX_DELAY_CNT = 50000000,
CYCLE_NUMBER = 100; //占空比分为0~100个级别 CYCLE_NUMBER = 100; //占空比分为0~100个级别
reg myclk; reg myclk;
reg [23:0] delay_cnt; reg [31:0] delay_cnt;
reg [7:0] current_cycle; reg [7:0] current_cycle;
reg flag; reg flag;
reg [7:0] cycle; reg [7:0] cycle;
@ -18,8 +18,8 @@ always@(posedge clk) begin
if(delay_cnt < MAX_DELAY_CNT) if(delay_cnt < MAX_DELAY_CNT)
delay_cnt <= delay_cnt + 1'b1; delay_cnt <= delay_cnt + 1'b1;
else begin else begin
delay_cnt <= 24'd1; delay_cnt <= 32'd1;
myclk <= ~myclk; myclk <= ~myclk; // 100Mhz
end end
end end
@ -52,10 +52,17 @@ always@(posedge clk)
//-------------------------------------------------------- //--------------------------------------------------------
// cycle小于current_cycle的时候是低电平 // cycle小于current_cycle的时候是低电平
// cycle大于current_cycle并且小于CYCLE_NUMBER的时候是高电平 // cycle大于current_cycle并且小于CYCLE_NUMBER的时候是高电平
// always@(posedge clk)
// if((cycle == CYCLE_NUMBER) && (current_cycle != 0))
// led <= 1'b1;
// else if(cycle < current_cycle)
// led <= 1'b1;
// else
// led <= 1'b0;
always@(posedge clk) always@(posedge clk)
if((cycle == CYCLE_NUMBER) && (current_cycle != 0)) if((delay_cnt[20:14] ==0) && myclk)
led <= 1'b1;
else if(cycle < current_cycle)
led <= 1'b1; led <= 1'b1;
else else
led <= 1'b0; led <= 1'b0;