add VexRiscv remote-bitbang support, but fail current.
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Colin
parent
3ca3f614fe
commit
973950cc1b
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@ -1,13 +1,13 @@
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#include "VMurax.h"
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#include "VMurax_Murax.h"
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#include "Vsoc.h"
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#include "Vsoc_soc.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include "../common/framework.h"
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#include "../common/jtag.h"
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// #include "../common/jtag.h"
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#include "../common/uart.h"
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class MuraxWorkspace : public Workspace<VMurax>{
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class MuraxWorkspace : public Workspace<Vsoc>{
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public:
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MuraxWorkspace() : Workspace("Murax"){
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ClockDomain *mainClk = new ClockDomain(&top->io_mainClk,NULL,83333,300000);
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@ -20,8 +20,8 @@ public:
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timeProcesses.push_back(uartRx);
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timeProcesses.push_back(uartTx);
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Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,83333*4);
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timeProcesses.push_back(jtag);
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// Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,83333*4);
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// timeProcesses.push_back(jtag);
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#ifdef TRACE
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//speedFactor = 10e-3;
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@ -21,18 +21,20 @@ endif
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ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START}
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FILELIST = -F ./dpi/jtag.fl
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all: clean compile
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run: compile
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./obj_dir/VMurax
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./obj_dir/Vsoc
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verilate: ./Murax.v
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verilator -cc ./Murax.v ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp
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verilate: ./soc.v
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verilator -cc ./soc.v ./Murax.v ${FILELIST} ${ADDCFLAGS} \
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-Wno-WIDTH -Wno-UNOPTFLAT -Wno-TIMESCALEMOD \
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--x-assign unique --exe main.cpp --gdbbt ${VERILATOR_ARGS}
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compile: verilate
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make -j -C obj_dir/ -f VMurax.mk VMurax
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make -j -C obj_dir/ -f Vsoc.mk Vsoc
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clean:
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rm -rf obj_dir
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@ -0,0 +1,58 @@
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`timescale 1ns/1ps
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module soc (
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input wire io_asyncReset,
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input wire io_mainClk,
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input wire [31:0] io_gpioA_read,
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output wire [31:0] io_gpioA_write,
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output wire [31:0] io_gpioA_writeEnable,
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output wire io_uart_txd,
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input wire io_uart_rxd
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);
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wire jtag_tck;
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wire jtag_tms;
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wire jtag_tdi;
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wire jtag_tdo;
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bit [31:0] cycleCnt;
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always @(posedge io_mainClk) begin
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cycleCnt <= cycleCnt + 1;
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end
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wire clk;
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assign clk = cycleCnt[2];
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logic rst_l;
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assign rst_l = cycleCnt > 100;
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Murax murax(
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.io_asyncReset(io_asyncReset),
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.io_mainClk(io_mainClk),
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.io_jtag_tms(jtag_tms),
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.io_jtag_tdi(jtag_tdi),
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.io_jtag_tdo(jtag_tdo),
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.io_jtag_tck(jtag_tck),
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.io_gpioA_read(io_gpioA_read),
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.io_gpioA_write(io_gpioA_write),
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.io_gpioA_writeEnable(io_gpioA_writeEnable),
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.io_uart_txd(io_uart_txd),
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.io_uart_rxd(io_uart_rxd)
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);
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jtagdpi jtagdpi (
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.clk_i (io_mainClk),
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.rst_ni(rst_l),
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.jtag_tck(jtag_tck),
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.jtag_tms(jtag_tms),
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.jtag_tdi(jtag_tdi),
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.jtag_tdo(jtag_tdo),
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.jtag_trst_n(),
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.jtag_srst_n()
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);
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endmodule
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@ -44,7 +44,9 @@ verilator: verilator-build
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##################### openocd #####################################
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openocd:
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openocd -f jtag_tcp.cfg -c "set MURAX_CPU0_YAML cpu0.yaml" -f murax.cfg
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# openocd -f jtag_tcp.cfg -c "set MURAX_CPU0_YAML cpu0.yaml" -f murax.cfg
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# openocd -c "set MURAX_CPU0_YAML cpu0.yaml" -f murax.cfg
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openocd -f murax.cfg
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gdb:
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$(GDB_PREFIX) -x gdbinit ./hello_world.elf
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@ -1,30 +1,54 @@
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transport select jtag
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set _ENDIAN little
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set _TAP_TYPE 1234
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adapter driver remote_bitbang
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remote_bitbang host localhost
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remote_bitbang port 44853
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# transport select jtag
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# set _ENDIAN little
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# set _TAP_TYPE 1234
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# set useful default
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set _CPUTAPID 0x10001fff
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set _CPUTAPID 0x10001fff
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}
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adapter_khz 800
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adapter_nsrst_delay 260
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jtag_ntrst_delay 250
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# adapter_khz 800
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# adapter_nsrst_delay 260
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# jtag_ntrst_delay 250
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set _CHIPNAME fpga_spinal
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jtag newtap $_CHIPNAME bridge -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0xF
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set _CHIPNAME murax
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set _TARGETNAME $_CHIPNAME.tap
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target create $_CHIPNAME.cpu0 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge -coreid 0 -dbgbase 0xF00F0000
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vexriscv readWaitCycles 12
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vexriscv cpuConfigFile $MURAX_CPU0_YAML
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jtag newtap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
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poll_period 50
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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# vexriscv readWaitCycles 12
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# vexriscv cpuConfigFile $MURAX_CPU0_YAML
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# Be verbose about GDB errors
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gdb_report_data_abort enable
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gdb_report_register_access_error enable
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#poll_period 50
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# Conclude OpenOCD configuration
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init
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#echo "Halting processor"
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soft_reset_halt
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sleep 1000
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# Halt the target
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halt
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# init
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# #echo "Halting processor"
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# soft_reset_halt
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# sleep 1000
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@ -0,0 +1,39 @@
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# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket
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# speaking the remote_bitbang protocol. The adapter is implemented as
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# SystemVerilog DPI module.
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# reset_config srst_only # donot support TRST, use five tms=1
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# adapter_nsrst_assert_width 100
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adapter driver remote_bitbang
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remote_bitbang host localhost
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remote_bitbang port 44853
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# Target configuration for the riscv chip
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set _CHIPNAME riscv
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set _TARGETNAME $_CHIPNAME.tap
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jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x10000B6F
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# {4'h1, 16'h0, 12'b1011_011_0111_1};
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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# Configure work area in on-chip SRAM
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# $_TARGETNAME configure -work-area-phys 0x1000e000 -work-area-size 1000 -work-area-backup 0
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riscv expose_csrs 1988
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# Be verbose about GDB errors
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gdb_report_data_abort enable
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gdb_report_register_access_error enable
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# Increase timeouts in simulation
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riscv set_command_timeout_sec 1200
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# Conclude OpenOCD configuration
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init
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# Halt the target
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halt
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