Set DCCM and ICCM size to 32KB
This commit is contained in:
colin
parent
547f0dbdc3
commit
a6038fde4a
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@ -1,6 +1,7 @@
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{
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{
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"files.associations": {
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"files.associations": {
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"BUILD": "bazel",
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"BUILD": "bazel",
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"memory": "cpp"
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"memory": "cpp",
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"stdarg.h": "c"
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}
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}
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}
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}
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@ -1,4 +1,3 @@
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int STACK = 0x8000;
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#define STDOUT 0xd0580000
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#define STDOUT 0xd0580000
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__asm(".section .text_init, \"ax\"");
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__asm(".section .text_init, \"ax\"");
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@ -1,81 +0,0 @@
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// Assembly code for Hello World
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// Not using only ALU ops for creating the string
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#include "defines.h"
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#define STDOUT 0xd0580000
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// Code to execute
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.section .text
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.global _start
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_start:
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// Clear minstret
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csrw minstret, zero
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csrw minstreth, zero
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// Set up MTVEC - not expecting to use it though
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li x1, RV_ICCM_SADR
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csrw mtvec, x1
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// Enable Caches in MRAC
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li x1, 0x5f555555
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csrw 0x7c0, x1
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// Load string from hw_data
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// and write to stdout address
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li x3, STDOUT
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la x4, hw_data
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loop:
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lb x5, 0(x4)
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sb x5, 0(x3)
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addi x4, x4, 1
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bnez x5, loop
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li x3, STDOUT
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la x4, hw_data
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loop2:
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lb x5, 0(x4)
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sb x5, 0(x3)
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addi x4, x4, 1
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bnez x5, loop2
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// Write 0xff to STDOUT for TB to terminate test.
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_finish:
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li x3, STDOUT
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addi x5, x0, 0xff
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sb x5, 0(x3)
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beq x0, x0, _finish
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.rept 100
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nop
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.endr
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.global hw_data
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.data
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hw_data:
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.ascii "----------------------------------\n"
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.ascii "Hello World Colin.liang EH1@WDC !!\n"
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.ascii "----------------------------------\n"
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.byte 0
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@ -8,8 +8,8 @@ SECTIONS
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.text_init : { *(.text_init*) }
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.text_init : { *(.text_init*) }
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.text : { *(.text*) }
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.text : { *(.text*) }
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_end = .;
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_end = .;
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. = 0x10000;
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. = 0x4000;
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.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
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.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; }
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.bss : { *(.bss) }
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.bss : { *(.bss) }
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. = 0xd0580000;
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. = 0xd0580000;
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.data.io : { *(.data.io) }
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.data.io : { *(.data.io) }
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@ -60,18 +60,20 @@ loop2:
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lb x5, 0(x4)
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lb x5, 0(x4)
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sb x5, 0(x3)
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sb x5, 0(x3)
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addi x4, x4, 1
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addi x4, x4, 1
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# bnez x5, loop2
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bnez x5, loop2
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beq x0, x0, loop2
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loop3:
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beq x0, x0, loop3
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// Write 0xff to STDOUT for TB to terminate test.
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// Write 0xff to STDOUT for TB to terminate test.
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# _finish:
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_finish:
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# li x3, STDOUT
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li x3, STDOUT
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# addi x5, x0, 0xff
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addi x5, x0, 0xff
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# sb x5, 0(x3)
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sb x5, 0(x3)
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# beq x0, x0, _finish
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beq x0, x0, _finish
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# .rept 100
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.rept 100
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# nop
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nop
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# .endr
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.endr
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.global hw_data
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.global hw_data
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.data
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.data
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@ -8,8 +8,8 @@ SECTIONS
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.text_init : { *(.text_init*) }
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.text_init : { *(.text_init*) }
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.text : { *(.text*) }
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.text : { *(.text*) }
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_end = .;
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_end = .;
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. = 0x10000;
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. = 0x4000;
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.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
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.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; }
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.bss : { *(.bss) }
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.bss : { *(.bss) }
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. = 0xd0580000;
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. = 0xd0580000;
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.data.io : { *(.data.io) }
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.data.io : { *(.data.io) }
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@ -34,13 +34,17 @@ output logic [63:0] HRDATA
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);
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);
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parameter MAILBOX_ADDR = 32'hD0580000;
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parameter MAILBOX_ADDR = 32'hD0580000;
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// `define RV_ICCM_SADR 32'hee000000
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// `define RV_DCCM_SADR 32'hf0040000
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parameter OFFSET_ADDR = 32'h00000000;
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parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k
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logic write;
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logic write;
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logic [31:0] laddr, addr;
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logic [31:0] laddr, addr;
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logic [7:0] strb_lat;
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logic [7:0] strb_lat;
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logic [63:0] rdata;
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logic [63:0] rdata;
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bit [7:0] mem [bit[31:0]];
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bit [7:0] mem [bit[MEM_DEPTH-1:0]];
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bit [7:0] wscnt;
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bit [7:0] wscnt;
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int dws = 0;
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int dws = 0;
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int iws = 0;
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int iws = 0;
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@ -54,6 +58,7 @@ wire [7:0] strb = HSIZE == 3'b000 ? 8'h1 << HADDR[2:0] :
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HSIZE == 3'b001 ? 8'h3 << {HADDR[2:1],1'b0} :
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HSIZE == 3'b001 ? 8'h3 << {HADDR[2:1],1'b0} :
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HSIZE == 3'b010 ? 8'hf << {HADDR[2],2'b0} : 8'hff;
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HSIZE == 3'b010 ? 8'hf << {HADDR[2],2'b0} : 8'hff;
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wire [31:0] RDDR = HADDR - OFFSET_ADDR;
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wire mailbox_write = write && laddr==MAILBOX_ADDR;
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wire mailbox_write = write && laddr==MAILBOX_ADDR;
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@ -69,16 +74,16 @@ end
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always @ (negedge HCLK ) begin
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always @ (negedge HCLK ) begin
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if(HREADY)
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if(HREADY)
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addr = HADDR;
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addr = RDDR;
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if (write & HREADY) begin
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if (write & HREADY) begin
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if(strb_lat[7]) mem[{laddr[31:3],3'd7}] = HWDATA[63:56];
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if(strb_lat[7]) mem[{laddr[MEM_DEPTH-1:3],3'd7}] = HWDATA[63:56];
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if(strb_lat[6]) mem[{laddr[31:3],3'd6}] = HWDATA[55:48];
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if(strb_lat[6]) mem[{laddr[MEM_DEPTH-1:3],3'd6}] = HWDATA[55:48];
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if(strb_lat[5]) mem[{laddr[31:3],3'd5}] = HWDATA[47:40];
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if(strb_lat[5]) mem[{laddr[MEM_DEPTH-1:3],3'd5}] = HWDATA[47:40];
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if(strb_lat[4]) mem[{laddr[31:3],3'd4}] = HWDATA[39:32];
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if(strb_lat[4]) mem[{laddr[MEM_DEPTH-1:3],3'd4}] = HWDATA[39:32];
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if(strb_lat[3]) mem[{laddr[31:3],3'd3}] = HWDATA[31:24];
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if(strb_lat[3]) mem[{laddr[MEM_DEPTH-1:3],3'd3}] = HWDATA[31:24];
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if(strb_lat[2]) mem[{laddr[31:3],3'd2}] = HWDATA[23:16];
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if(strb_lat[2]) mem[{laddr[MEM_DEPTH-1:3],3'd2}] = HWDATA[23:16];
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if(strb_lat[1]) mem[{laddr[31:3],3'd1}] = HWDATA[15:08];
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if(strb_lat[1]) mem[{laddr[MEM_DEPTH-1:3],3'd1}] = HWDATA[15:08];
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if(strb_lat[0]) mem[{laddr[31:3],3'd0}] = HWDATA[07:00];
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if(strb_lat[0]) mem[{laddr[MEM_DEPTH-1:3],3'd0}] = HWDATA[07:00];
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end
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end
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if(HREADY & HSEL & |HTRANS) begin
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if(HREADY & HSEL & |HTRANS) begin
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`ifdef VERILATOR
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`ifdef VERILATOR
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@ -109,17 +114,17 @@ always @(posedge HCLK or negedge HRESETn) begin
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end
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end
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else begin
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else begin
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if(HREADY & HSEL) begin
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if(HREADY & HSEL) begin
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laddr <= HADDR;
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laddr <= RDDR;
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write <= HWRITE & |HTRANS;
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write <= HWRITE & |HTRANS;
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if(|HTRANS & ~HWRITE)
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if(|HTRANS & ~HWRITE)
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rdata <= {mem[{addr[31:3],3'd7}],
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rdata <= {mem[{addr[MEM_DEPTH-1:3],3'd7}],
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mem[{addr[31:3],3'd6}],
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mem[{addr[MEM_DEPTH-1:3],3'd6}],
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mem[{addr[31:3],3'd5}],
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mem[{addr[MEM_DEPTH-1:3],3'd5}],
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mem[{addr[31:3],3'd4}],
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mem[{addr[MEM_DEPTH-1:3],3'd4}],
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mem[{addr[31:3],3'd3}],
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mem[{addr[MEM_DEPTH-1:3],3'd3}],
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mem[{addr[31:3],3'd2}],
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mem[{addr[MEM_DEPTH-1:3],3'd2}],
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mem[{addr[31:3],3'd1}],
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mem[{addr[MEM_DEPTH-1:3],3'd1}],
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mem[{addr[31:3],3'd0}]};
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mem[{addr[MEM_DEPTH-1:3],3'd0}]};
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strb_lat <= strb;
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strb_lat <= strb;
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end
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end
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end
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end
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endmodule
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endmodule
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`endif
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`endif
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`ifdef RV_BUILD_AXI4
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module axi_slv #(TAGW=1) (
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input aclk,
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input rst_l,
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input arvalid,
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output reg arready,
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input [31:0] araddr,
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input [TAGW-1:0] arid,
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input [7:0] arlen,
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input [1:0] arburst,
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input [2:0] arsize,
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output reg rvalid,
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input rready,
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output reg [63:0] rdata,
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output reg [1:0] rresp,
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output reg [TAGW-1:0] rid,
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output rlast,
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input awvalid,
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output awready,
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input [31:0] awaddr,
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input [TAGW-1:0] awid,
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input [7:0] awlen,
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input [1:0] awburst,
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input [2:0] awsize,
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input [63:0] wdata,
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input [7:0] wstrb,
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input wvalid,
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output wready,
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output reg bvalid,
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input bready,
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output reg [1:0] bresp,
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output reg [TAGW-1:0] bid
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);
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parameter MAILBOX_ADDR = 32'hD0580000;
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parameter MEM_SIZE_DW = 8192;
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bit [7:0] mem [bit[31:0]];
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bit [63:0] memdata;
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wire [63:0] WriteData;
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wire mailbox_write;
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assign mailbox_write = awvalid && awaddr==MAILBOX_ADDR && rst_l;
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assign WriteData = wdata;
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always @ ( posedge aclk or negedge rst_l) begin
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if(!rst_l) begin
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rvalid <= 0;
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bvalid <= 0;
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end
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else begin
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bid <= awid;
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rid <= arid;
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rvalid <= arvalid;
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bvalid <= awvalid;
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rdata <= memdata;
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end
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end
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always @ ( negedge aclk) begin
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if(arvalid) memdata <= {mem[araddr+7], mem[araddr+6], mem[araddr+5], mem[araddr+4],
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mem[araddr+3], mem[araddr+2], mem[araddr+1], mem[araddr]};
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if(awvalid) begin
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if(wstrb[7]) mem[awaddr+7] = wdata[63:56];
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if(wstrb[6]) mem[awaddr+6] = wdata[55:48];
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if(wstrb[5]) mem[awaddr+5] = wdata[47:40];
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if(wstrb[4]) mem[awaddr+4] = wdata[39:32];
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if(wstrb[3]) mem[awaddr+3] = wdata[31:24];
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if(wstrb[2]) mem[awaddr+2] = wdata[23:16];
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if(wstrb[1]) mem[awaddr+1] = wdata[15:08];
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if(wstrb[0]) mem[awaddr+0] = wdata[07:00];
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end
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end
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assign arready = 1'b1;
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assign awready = 1'b1;
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assign wready = 1'b1;
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assign rresp = 2'b0;
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assign bresp = 2'b0;
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assign rlast = 1'b1;
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endmodule
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`endif
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@ -226,8 +226,6 @@ module soc_top;
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$fwrite (el, "//---------------------------------------------------------------\n");
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$fwrite (el, "//---------------------------------------------------------------\n");
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fd = $fopen("console.log","w");
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fd = $fopen("console.log","w");
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commit_count = 0;
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commit_count = 0;
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preload_dccm();
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preload_iccm();
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`ifndef VERILATOR
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`ifndef VERILATOR
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if($test$plusargs("dumpon")) $dumpvars;
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if($test$plusargs("dumpon")) $dumpvars;
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@ -423,64 +421,7 @@ ahb_sif lmem (
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`endif
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`endif
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task preload_iccm;
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bit[31:0] data;
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bit[31:0] addr, eaddr, saddr;
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/*
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addresses:
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0xfffffff0 - ICCM start address to load
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0xfffffff4 - ICCM end address to load
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*/
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addr = 'hffff_fff0;
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saddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
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if ( (saddr < `RV_ICCM_SADR) || (saddr > `RV_ICCM_EADR)) return;
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`ifndef RV_ICCM_ENABLE
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$display("********************************************************");
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||||||
$display("ICCM preload: there is no ICCM in SweRV, terminating !!!");
|
|
||||||
$display("********************************************************");
|
|
||||||
$finish;
|
|
||||||
`endif
|
|
||||||
addr += 4;
|
|
||||||
eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
|
||||||
$display("ICCM pre-load from %h to %h", saddr, eaddr);
|
|
||||||
|
|
||||||
for(addr= saddr; addr <= eaddr; addr+=4) begin
|
|
||||||
data = {imem.mem[addr+3],imem.mem[addr+2],imem.mem[addr+1],imem.mem[addr]};
|
|
||||||
slam_iccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data});
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
|
|
||||||
task preload_dccm;
|
|
||||||
bit[31:0] data;
|
|
||||||
bit[31:0] addr, saddr, eaddr;
|
|
||||||
|
|
||||||
/*
|
|
||||||
addresses:
|
|
||||||
0xffff_fff8 - DCCM start address to load
|
|
||||||
0xffff_fffc - DCCM end address to load
|
|
||||||
*/
|
|
||||||
|
|
||||||
addr = 'hffff_fff8;
|
|
||||||
saddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
|
||||||
if (saddr < `RV_DCCM_SADR || saddr > `RV_DCCM_EADR) return;
|
|
||||||
`ifndef RV_DCCM_ENABLE
|
|
||||||
$display("********************************************************");
|
|
||||||
$display("DCCM preload: there is no DCCM in SweRV, terminating !!!");
|
|
||||||
$display("********************************************************");
|
|
||||||
$finish;
|
|
||||||
`endif
|
|
||||||
addr += 4;
|
|
||||||
eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
|
||||||
$display("DCCM pre-load from %h to %h", saddr, eaddr);
|
|
||||||
|
|
||||||
for(addr=saddr; addr <= eaddr; addr+=4) begin
|
|
||||||
data = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
|
||||||
slam_dccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data});
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
`define DRAM(bank) \
|
`define DRAM(bank) \
|
||||||
rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].dccm_bank.ram_core
|
rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].dccm_bank.ram_core
|
||||||
|
|
@ -492,88 +433,6 @@ endtask
|
||||||
`define IRAM3(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi1.ram_core
|
`define IRAM3(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi1.ram_core
|
||||||
|
|
||||||
|
|
||||||
task slam_iccm_ram(input [31:0] addr, input[38:0] data);
|
|
||||||
int bank, indx;
|
|
||||||
`ifdef RV_ICCM_ENABLE
|
|
||||||
`ifdef RV_ICCM_NUM_BANKS_4
|
|
||||||
indx = int'(addr[`RV_ICCM_BITS-1:4]);
|
|
||||||
bank = int'( addr[3:2]);
|
|
||||||
`elsif RV_ICCM_NUM_BANKS_8
|
|
||||||
indx = int'(addr[`RV_ICCM_BITS-1:5]);
|
|
||||||
bank = int'(addr[4:2]);
|
|
||||||
`else
|
|
||||||
indx = int'(addr[`RV_ICCM_BITS-1:6]);
|
|
||||||
bank = int'( addr[5:2]);
|
|
||||||
`endif
|
|
||||||
case(bank)
|
|
||||||
0: `IRAM0(0)[indx] = data;
|
|
||||||
1: `IRAM1(0)[indx] = data;
|
|
||||||
2: `IRAM2(0)[indx] = data;
|
|
||||||
3: `IRAM3(0)[indx] = data;
|
|
||||||
`ifdef RV_ICCM_NUM_BANKS_8
|
|
||||||
4: `IRAM0(1)[indx] = data;
|
|
||||||
5: `IRAM1(1)[indx] = data;
|
|
||||||
6: `IRAM2(1)[indx] = data;
|
|
||||||
7: `IRAM3(1)[indx] = data;
|
|
||||||
`endif
|
|
||||||
`ifdef RV_ICCM_NUM_BANKS_16
|
|
||||||
8: `IRAM0(2)[indx] = data;
|
|
||||||
9: `IRAM1(2)[indx] = data;
|
|
||||||
10: `IRAM2(2)[indx] = data;
|
|
||||||
11: `IRAM3(2)[indx] = data;
|
|
||||||
12: `IRAM0(3)[indx] = data;
|
|
||||||
13: `IRAM1(3)[indx] = data;
|
|
||||||
14: `IRAM2(3)[indx] = data;
|
|
||||||
15: `IRAM3(3)[indx] = data;
|
|
||||||
`endif
|
|
||||||
endcase
|
|
||||||
`endif
|
|
||||||
endtask
|
|
||||||
|
|
||||||
task slam_dccm_ram(input [31:0] addr, input[38:0] data);
|
|
||||||
int bank, indx;
|
|
||||||
`ifdef RV_DCCM_ENABLE
|
|
||||||
`ifdef RV_DCCM_NUM_BANKS_2
|
|
||||||
indx = int'(addr[`RV_DCCM_BITS-1:3]);
|
|
||||||
bank = int'( addr[2]);
|
|
||||||
`elsif RV_DCCM_NUM_BANKS_4
|
|
||||||
indx = int'(addr[`RV_DCCM_BITS-1:4]);
|
|
||||||
bank = int'(addr[3:2]);
|
|
||||||
`elsif RV_DCCM_NUM_BANKS_8
|
|
||||||
indx = int'(addr[`RV_DCCM_BITS-1:5]);
|
|
||||||
bank = int'( addr[4:2]);
|
|
||||||
`endif
|
|
||||||
case(bank)
|
|
||||||
0: `DRAM(0)[indx] = data;
|
|
||||||
1: `DRAM(1)[indx] = data;
|
|
||||||
`ifdef RV_DCCM_NUM_BANKS_4
|
|
||||||
2: `DRAM(2)[indx] = data;
|
|
||||||
3: `DRAM(3)[indx] = data;
|
|
||||||
`endif
|
|
||||||
`ifdef RV_DCCM_NUM_BANKS_8
|
|
||||||
2: `DRAM(2)[indx] = data;
|
|
||||||
3: `DRAM(3)[indx] = data;
|
|
||||||
4: `DRAM(4)[indx] = data;
|
|
||||||
5: `DRAM(5)[indx] = data;
|
|
||||||
6: `DRAM(6)[indx] = data;
|
|
||||||
7: `DRAM(7)[indx] = data;
|
|
||||||
`endif
|
|
||||||
endcase
|
|
||||||
`endif
|
|
||||||
endtask
|
|
||||||
|
|
||||||
function[6:0] riscv_ecc32(input[31:0] data);
|
|
||||||
reg[6:0] synd;
|
|
||||||
synd[0] = ^(data & 32'h56aa_ad5b);
|
|
||||||
synd[1] = ^(data & 32'h9b33_366d);
|
|
||||||
synd[2] = ^(data & 32'he3c3_c78e);
|
|
||||||
synd[3] = ^(data & 32'h03fc_07f0);
|
|
||||||
synd[4] = ^(data & 32'h03ff_f800);
|
|
||||||
synd[5] = ^(data & 32'hfc00_0000);
|
|
||||||
synd[6] = ^{data, synd[5:0]};
|
|
||||||
return synd;
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
||||||
/* verilator lint_off CASEINCOMPLETE */
|
/* verilator lint_off CASEINCOMPLETE */
|
||||||
`include "dasm.svi"
|
`include "dasm.svi"
|
||||||
|
|
|
||||||
|
|
@ -284,12 +284,12 @@ elsif ($target eq "default_ahb") {
|
||||||
if (!defined($dccm_enable)) { $dccm_enable=1; }
|
if (!defined($dccm_enable)) { $dccm_enable=1; }
|
||||||
if (!defined($dccm_region)) { $dccm_region="0xf"; }
|
if (!defined($dccm_region)) { $dccm_region="0xf"; }
|
||||||
if (!defined($dccm_offset)) { $dccm_offset="0x40000"; } #1*256*1024
|
if (!defined($dccm_offset)) { $dccm_offset="0x40000"; } #1*256*1024
|
||||||
if (!defined($dccm_size)) { $dccm_size=64; }
|
if (!defined($dccm_size)) { $dccm_size=32; }
|
||||||
if (!defined($dccm_num_banks)) { $dccm_num_banks=8; }
|
if (!defined($dccm_num_banks)) { $dccm_num_banks=8; }
|
||||||
if (!defined($iccm_enable)) { $iccm_enable=0; }
|
if (!defined($iccm_enable)) { $iccm_enable=0; }
|
||||||
if (!defined($iccm_region)) { $iccm_region="0xe"; }
|
if (!defined($iccm_region)) { $iccm_region="0xe"; }
|
||||||
if (!defined($iccm_offset)) { $iccm_offset="0xe000000"; } #0x380*256*1024
|
if (!defined($iccm_offset)) { $iccm_offset="0xe000000"; } #0x380*256*1024
|
||||||
if (!defined($iccm_size)) { $iccm_size=512; }
|
if (!defined($iccm_size)) { $iccm_size=32; }
|
||||||
if (!defined($iccm_num_banks)) { $iccm_num_banks=8; }
|
if (!defined($iccm_num_banks)) { $iccm_num_banks=8; }
|
||||||
if (!defined($icache_enable)) { $icache_enable=1; }
|
if (!defined($icache_enable)) { $icache_enable=1; }
|
||||||
if (!defined($icache_ecc)) { $icache_ecc=0; }
|
if (!defined($icache_ecc)) { $icache_ecc=0; }
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue