Set DCCM and ICCM size to 32KB

This commit is contained in:
colin 2022-02-11 12:17:21 +00:00
parent 547f0dbdc3
commit a6038fde4a
9 changed files with 44 additions and 350 deletions

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@ -1,6 +1,7 @@
{
"files.associations": {
"BUILD": "bazel",
"memory": "cpp"
"memory": "cpp",
"stdarg.h": "c"
}
}

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@ -1,4 +1,3 @@
int STACK = 0x8000;
#define STDOUT 0xd0580000
__asm(".section .text_init, \"ax\"");

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@ -1,81 +0,0 @@
// SPDX-License-Identifier: Apache-2.0
// Copyright 2019 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// Assembly code for Hello World
// Not using only ALU ops for creating the string
#include "defines.h"
#define STDOUT 0xd0580000
// Code to execute
.section .text
.global _start
_start:
// Clear minstret
csrw minstret, zero
csrw minstreth, zero
// Set up MTVEC - not expecting to use it though
li x1, RV_ICCM_SADR
csrw mtvec, x1
// Enable Caches in MRAC
li x1, 0x5f555555
csrw 0x7c0, x1
// Load string from hw_data
// and write to stdout address
li x3, STDOUT
la x4, hw_data
loop:
lb x5, 0(x4)
sb x5, 0(x3)
addi x4, x4, 1
bnez x5, loop
li x3, STDOUT
la x4, hw_data
loop2:
lb x5, 0(x4)
sb x5, 0(x3)
addi x4, x4, 1
bnez x5, loop2
// Write 0xff to STDOUT for TB to terminate test.
_finish:
li x3, STDOUT
addi x5, x0, 0xff
sb x5, 0(x3)
beq x0, x0, _finish
.rept 100
nop
.endr
.global hw_data
.data
hw_data:
.ascii "----------------------------------\n"
.ascii "Hello World Colin.liang EH1@WDC !!\n"
.ascii "----------------------------------\n"
.byte 0

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@ -8,8 +8,8 @@ SECTIONS
.text_init : { *(.text_init*) }
.text : { *(.text*) }
_end = .;
. = 0x10000;
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
. = 0x4000;
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; }
.bss : { *(.bss) }
. = 0xd0580000;
.data.io : { *(.data.io) }

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@ -60,18 +60,20 @@ loop2:
lb x5, 0(x4)
sb x5, 0(x3)
addi x4, x4, 1
# bnez x5, loop2
beq x0, x0, loop2
bnez x5, loop2
loop3:
beq x0, x0, loop3
// Write 0xff to STDOUT for TB to terminate test.
# _finish:
# li x3, STDOUT
# addi x5, x0, 0xff
# sb x5, 0(x3)
# beq x0, x0, _finish
# .rept 100
# nop
# .endr
_finish:
li x3, STDOUT
addi x5, x0, 0xff
sb x5, 0(x3)
beq x0, x0, _finish
.rept 100
nop
.endr
.global hw_data
.data

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@ -8,8 +8,8 @@ SECTIONS
.text_init : { *(.text_init*) }
.text : { *(.text*) }
_end = .;
. = 0x10000;
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
. = 0x4000;
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; }
.bss : { *(.bss) }
. = 0xd0580000;
.data.io : { *(.data.io) }

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@ -34,13 +34,17 @@ output logic [63:0] HRDATA
);
parameter MAILBOX_ADDR = 32'hD0580000;
// `define RV_ICCM_SADR 32'hee000000
// `define RV_DCCM_SADR 32'hf0040000
parameter OFFSET_ADDR = 32'h00000000;
parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k
logic write;
logic [31:0] laddr, addr;
logic [7:0] strb_lat;
logic [63:0] rdata;
bit [7:0] mem [bit[31:0]];
bit [7:0] mem [bit[MEM_DEPTH-1:0]];
bit [7:0] wscnt;
int dws = 0;
int iws = 0;
@ -54,6 +58,7 @@ wire [7:0] strb = HSIZE == 3'b000 ? 8'h1 << HADDR[2:0] :
HSIZE == 3'b001 ? 8'h3 << {HADDR[2:1],1'b0} :
HSIZE == 3'b010 ? 8'hf << {HADDR[2],2'b0} : 8'hff;
wire [31:0] RDDR = HADDR - OFFSET_ADDR;
wire mailbox_write = write && laddr==MAILBOX_ADDR;
@ -69,16 +74,16 @@ end
always @ (negedge HCLK ) begin
if(HREADY)
addr = HADDR;
addr = RDDR;
if (write & HREADY) begin
if(strb_lat[7]) mem[{laddr[31:3],3'd7}] = HWDATA[63:56];
if(strb_lat[6]) mem[{laddr[31:3],3'd6}] = HWDATA[55:48];
if(strb_lat[5]) mem[{laddr[31:3],3'd5}] = HWDATA[47:40];
if(strb_lat[4]) mem[{laddr[31:3],3'd4}] = HWDATA[39:32];
if(strb_lat[3]) mem[{laddr[31:3],3'd3}] = HWDATA[31:24];
if(strb_lat[2]) mem[{laddr[31:3],3'd2}] = HWDATA[23:16];
if(strb_lat[1]) mem[{laddr[31:3],3'd1}] = HWDATA[15:08];
if(strb_lat[0]) mem[{laddr[31:3],3'd0}] = HWDATA[07:00];
if(strb_lat[7]) mem[{laddr[MEM_DEPTH-1:3],3'd7}] = HWDATA[63:56];
if(strb_lat[6]) mem[{laddr[MEM_DEPTH-1:3],3'd6}] = HWDATA[55:48];
if(strb_lat[5]) mem[{laddr[MEM_DEPTH-1:3],3'd5}] = HWDATA[47:40];
if(strb_lat[4]) mem[{laddr[MEM_DEPTH-1:3],3'd4}] = HWDATA[39:32];
if(strb_lat[3]) mem[{laddr[MEM_DEPTH-1:3],3'd3}] = HWDATA[31:24];
if(strb_lat[2]) mem[{laddr[MEM_DEPTH-1:3],3'd2}] = HWDATA[23:16];
if(strb_lat[1]) mem[{laddr[MEM_DEPTH-1:3],3'd1}] = HWDATA[15:08];
if(strb_lat[0]) mem[{laddr[MEM_DEPTH-1:3],3'd0}] = HWDATA[07:00];
end
if(HREADY & HSEL & |HTRANS) begin
`ifdef VERILATOR
@ -109,17 +114,17 @@ always @(posedge HCLK or negedge HRESETn) begin
end
else begin
if(HREADY & HSEL) begin
laddr <= HADDR;
laddr <= RDDR;
write <= HWRITE & |HTRANS;
if(|HTRANS & ~HWRITE)
rdata <= {mem[{addr[31:3],3'd7}],
mem[{addr[31:3],3'd6}],
mem[{addr[31:3],3'd5}],
mem[{addr[31:3],3'd4}],
mem[{addr[31:3],3'd3}],
mem[{addr[31:3],3'd2}],
mem[{addr[31:3],3'd1}],
mem[{addr[31:3],3'd0}]};
rdata <= {mem[{addr[MEM_DEPTH-1:3],3'd7}],
mem[{addr[MEM_DEPTH-1:3],3'd6}],
mem[{addr[MEM_DEPTH-1:3],3'd5}],
mem[{addr[MEM_DEPTH-1:3],3'd4}],
mem[{addr[MEM_DEPTH-1:3],3'd3}],
mem[{addr[MEM_DEPTH-1:3],3'd2}],
mem[{addr[MEM_DEPTH-1:3],3'd1}],
mem[{addr[MEM_DEPTH-1:3],3'd0}]};
strb_lat <= strb;
end
end
@ -132,94 +137,3 @@ end
endmodule
`endif
`ifdef RV_BUILD_AXI4
module axi_slv #(TAGW=1) (
input aclk,
input rst_l,
input arvalid,
output reg arready,
input [31:0] araddr,
input [TAGW-1:0] arid,
input [7:0] arlen,
input [1:0] arburst,
input [2:0] arsize,
output reg rvalid,
input rready,
output reg [63:0] rdata,
output reg [1:0] rresp,
output reg [TAGW-1:0] rid,
output rlast,
input awvalid,
output awready,
input [31:0] awaddr,
input [TAGW-1:0] awid,
input [7:0] awlen,
input [1:0] awburst,
input [2:0] awsize,
input [63:0] wdata,
input [7:0] wstrb,
input wvalid,
output wready,
output reg bvalid,
input bready,
output reg [1:0] bresp,
output reg [TAGW-1:0] bid
);
parameter MAILBOX_ADDR = 32'hD0580000;
parameter MEM_SIZE_DW = 8192;
bit [7:0] mem [bit[31:0]];
bit [63:0] memdata;
wire [63:0] WriteData;
wire mailbox_write;
assign mailbox_write = awvalid && awaddr==MAILBOX_ADDR && rst_l;
assign WriteData = wdata;
always @ ( posedge aclk or negedge rst_l) begin
if(!rst_l) begin
rvalid <= 0;
bvalid <= 0;
end
else begin
bid <= awid;
rid <= arid;
rvalid <= arvalid;
bvalid <= awvalid;
rdata <= memdata;
end
end
always @ ( negedge aclk) begin
if(arvalid) memdata <= {mem[araddr+7], mem[araddr+6], mem[araddr+5], mem[araddr+4],
mem[araddr+3], mem[araddr+2], mem[araddr+1], mem[araddr]};
if(awvalid) begin
if(wstrb[7]) mem[awaddr+7] = wdata[63:56];
if(wstrb[6]) mem[awaddr+6] = wdata[55:48];
if(wstrb[5]) mem[awaddr+5] = wdata[47:40];
if(wstrb[4]) mem[awaddr+4] = wdata[39:32];
if(wstrb[3]) mem[awaddr+3] = wdata[31:24];
if(wstrb[2]) mem[awaddr+2] = wdata[23:16];
if(wstrb[1]) mem[awaddr+1] = wdata[15:08];
if(wstrb[0]) mem[awaddr+0] = wdata[07:00];
end
end
assign arready = 1'b1;
assign awready = 1'b1;
assign wready = 1'b1;
assign rresp = 2'b0;
assign bresp = 2'b0;
assign rlast = 1'b1;
endmodule
`endif

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@ -226,8 +226,6 @@ module soc_top;
$fwrite (el, "//---------------------------------------------------------------\n");
fd = $fopen("console.log","w");
commit_count = 0;
preload_dccm();
preload_iccm();
`ifndef VERILATOR
if($test$plusargs("dumpon")) $dumpvars;
@ -423,64 +421,7 @@ ahb_sif lmem (
`endif
task preload_iccm;
bit[31:0] data;
bit[31:0] addr, eaddr, saddr;
/*
addresses:
0xfffffff0 - ICCM start address to load
0xfffffff4 - ICCM end address to load
*/
addr = 'hffff_fff0;
saddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
if ( (saddr < `RV_ICCM_SADR) || (saddr > `RV_ICCM_EADR)) return;
`ifndef RV_ICCM_ENABLE
$display("********************************************************");
$display("ICCM preload: there is no ICCM in SweRV, terminating !!!");
$display("********************************************************");
$finish;
`endif
addr += 4;
eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
$display("ICCM pre-load from %h to %h", saddr, eaddr);
for(addr= saddr; addr <= eaddr; addr+=4) begin
data = {imem.mem[addr+3],imem.mem[addr+2],imem.mem[addr+1],imem.mem[addr]};
slam_iccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data});
end
endtask
task preload_dccm;
bit[31:0] data;
bit[31:0] addr, saddr, eaddr;
/*
addresses:
0xffff_fff8 - DCCM start address to load
0xffff_fffc - DCCM end address to load
*/
addr = 'hffff_fff8;
saddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
if (saddr < `RV_DCCM_SADR || saddr > `RV_DCCM_EADR) return;
`ifndef RV_DCCM_ENABLE
$display("********************************************************");
$display("DCCM preload: there is no DCCM in SweRV, terminating !!!");
$display("********************************************************");
$finish;
`endif
addr += 4;
eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
$display("DCCM pre-load from %h to %h", saddr, eaddr);
for(addr=saddr; addr <= eaddr; addr+=4) begin
data = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
slam_dccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data});
end
endtask
`define DRAM(bank) \
rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].dccm_bank.ram_core
@ -492,88 +433,6 @@ endtask
`define IRAM3(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi1.ram_core
task slam_iccm_ram(input [31:0] addr, input[38:0] data);
int bank, indx;
`ifdef RV_ICCM_ENABLE
`ifdef RV_ICCM_NUM_BANKS_4
indx = int'(addr[`RV_ICCM_BITS-1:4]);
bank = int'( addr[3:2]);
`elsif RV_ICCM_NUM_BANKS_8
indx = int'(addr[`RV_ICCM_BITS-1:5]);
bank = int'(addr[4:2]);
`else
indx = int'(addr[`RV_ICCM_BITS-1:6]);
bank = int'( addr[5:2]);
`endif
case(bank)
0: `IRAM0(0)[indx] = data;
1: `IRAM1(0)[indx] = data;
2: `IRAM2(0)[indx] = data;
3: `IRAM3(0)[indx] = data;
`ifdef RV_ICCM_NUM_BANKS_8
4: `IRAM0(1)[indx] = data;
5: `IRAM1(1)[indx] = data;
6: `IRAM2(1)[indx] = data;
7: `IRAM3(1)[indx] = data;
`endif
`ifdef RV_ICCM_NUM_BANKS_16
8: `IRAM0(2)[indx] = data;
9: `IRAM1(2)[indx] = data;
10: `IRAM2(2)[indx] = data;
11: `IRAM3(2)[indx] = data;
12: `IRAM0(3)[indx] = data;
13: `IRAM1(3)[indx] = data;
14: `IRAM2(3)[indx] = data;
15: `IRAM3(3)[indx] = data;
`endif
endcase
`endif
endtask
task slam_dccm_ram(input [31:0] addr, input[38:0] data);
int bank, indx;
`ifdef RV_DCCM_ENABLE
`ifdef RV_DCCM_NUM_BANKS_2
indx = int'(addr[`RV_DCCM_BITS-1:3]);
bank = int'( addr[2]);
`elsif RV_DCCM_NUM_BANKS_4
indx = int'(addr[`RV_DCCM_BITS-1:4]);
bank = int'(addr[3:2]);
`elsif RV_DCCM_NUM_BANKS_8
indx = int'(addr[`RV_DCCM_BITS-1:5]);
bank = int'( addr[4:2]);
`endif
case(bank)
0: `DRAM(0)[indx] = data;
1: `DRAM(1)[indx] = data;
`ifdef RV_DCCM_NUM_BANKS_4
2: `DRAM(2)[indx] = data;
3: `DRAM(3)[indx] = data;
`endif
`ifdef RV_DCCM_NUM_BANKS_8
2: `DRAM(2)[indx] = data;
3: `DRAM(3)[indx] = data;
4: `DRAM(4)[indx] = data;
5: `DRAM(5)[indx] = data;
6: `DRAM(6)[indx] = data;
7: `DRAM(7)[indx] = data;
`endif
endcase
`endif
endtask
function[6:0] riscv_ecc32(input[31:0] data);
reg[6:0] synd;
synd[0] = ^(data & 32'h56aa_ad5b);
synd[1] = ^(data & 32'h9b33_366d);
synd[2] = ^(data & 32'he3c3_c78e);
synd[3] = ^(data & 32'h03fc_07f0);
synd[4] = ^(data & 32'h03ff_f800);
synd[5] = ^(data & 32'hfc00_0000);
synd[6] = ^{data, synd[5:0]};
return synd;
endfunction
/* verilator lint_off WIDTH */
/* verilator lint_off CASEINCOMPLETE */
`include "dasm.svi"

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@ -284,12 +284,12 @@ elsif ($target eq "default_ahb") {
if (!defined($dccm_enable)) { $dccm_enable=1; }
if (!defined($dccm_region)) { $dccm_region="0xf"; }
if (!defined($dccm_offset)) { $dccm_offset="0x40000"; } #1*256*1024
if (!defined($dccm_size)) { $dccm_size=64; }
if (!defined($dccm_size)) { $dccm_size=32; }
if (!defined($dccm_num_banks)) { $dccm_num_banks=8; }
if (!defined($iccm_enable)) { $iccm_enable=0; }
if (!defined($iccm_region)) { $iccm_region="0xe"; }
if (!defined($iccm_offset)) { $iccm_offset="0xe000000"; } #0x380*256*1024
if (!defined($iccm_size)) { $iccm_size=512; }
if (!defined($iccm_size)) { $iccm_size=32; }
if (!defined($iccm_num_banks)) { $iccm_num_banks=8; }
if (!defined($icache_enable)) { $icache_enable=1; }
if (!defined($icache_ecc)) { $icache_ecc=0; }