colin
/
abstractaccelerator
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add clean before fpga ram make all

This commit is contained in:
colin 2022-02-17 06:20:57 +00:00
parent 8e190efed0
commit cffec82632
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
fpga/ram/Makefile
View File

@ -3,7 +3,7 @@ TARGET=top
OBJS+=top.sv OBJS+=top.sv
OBJS+=bram.sv OBJS+=bram.sv
all: ${TARGET}.bit all: clean ${TARGET}.bit
$(TARGET).json: $(OBJS) $(TARGET).json: $(OBJS)
yosys -p "read_verilog -sv $(OBJS); synth_ecp5 -top ${TARGET} -json $@" yosys -p "read_verilog -sv $(OBJS); synth_ecp5 -top ${TARGET} -json $@"