Add clean before fpga ram make all

2022-02-17 06:20:57 +00:00 · 2022-02-17 06:20:57 +00:00 · cffec82632
parent 8e190efed0
commit cffec82632
1 changed files with 1 additions and 1 deletions
--- a/fpga/ram/Makefile
+++ b/fpga/ram/Makefile
@ -3,7 +3,7 @@ TARGET=top
 OBJS+=top.sv
 OBJS+=bram.sv

-all: ${TARGET}.bit
+all: clean ${TARGET}.bit

 $(TARGET).json: $(OBJS)
 	yosys -p "read_verilog -sv $(OBJS); synth_ecp5 -top ${TARGET} -json $@"