Commit Graph

16 Commits

Author SHA1 Message Date
colin.liang 44161e293f Reset Readme. 2023-01-04 22:40:08 +08:00
colin 32fff97ff5 Update gnu build. 2022-07-07 12:06:04 +00:00
colin 388db4a82e Delete quasar in Cores-SweRV. 2022-03-22 23:24:01 +00:00
colin beab126fc5 add quasar fpga. 2022-03-09 11:16:13 +00:00
colin 33885bbccb Add Bit-Vector install in readme 2022-03-07 04:08:12 +00:00
colin 27fade0b6d Add EL2 cores implement by Chisel in quaser. 2022-03-06 04:22:17 +00:00
colin 0a00e20cfe Update riscv gcc version and usage. 2022-03-06 04:21:41 +00:00
colin 3da81c5916 Add install commond in riscv gnu tools. 2022-03-01 13:22:23 +00:00
colin 3972a891ca Add fpga demo in Cores. 2022-02-21 07:52:52 +00:00
colin 3edc87e0ea Switch mem bus from ahb to axi. 2022-02-17 11:35:01 +00:00
colin 8e190efed0 Split from soc.mk to soc_sim.mk and soc_top.mk 2022-02-15 08:31:00 +00:00
colin 1f222dd1e3 Split soc and verilator to two part system verilog. 2022-02-14 12:32:21 +00:00
colin a6038fde4a Set DCCM and ICCM size to 32KB 2022-02-11 12:17:21 +00:00
colin 547f0dbdc3 remove axi4 in demo soc use ahb as default 2022-02-10 12:17:10 +00:00
colin 3370d01917 Add verilator install method in readme. 2022-02-07 08:13:16 +00:00
colin 853d12f17c Init to abstract accelerator project 2022-02-02 03:34:37 +00:00