Commit Graph

220 Commits

Author SHA1 Message Date
Colin cb27ddb1cf Refine cmsis openocd program. 2025-04-01 19:03:29 +08:00
Colin 7f321ae7a9 Add cmsis driver install. 2025-04-01 19:01:00 +08:00
Colin 975a3320a3 Update openocd build config. 2025-04-01 15:12:36 +08:00
Colin 4bdaedee09 Update jlink readme. 2025-04-01 10:32:58 +08:00
Colin 0fbe2ff871 Add Colorlight-FPGA-Projects 2025-04-01 10:32:16 +08:00
Colin afe4932c12 Fix synth.sh path error. 2025-03-31 14:07:06 +08:00
Colin 61937a2c69 Update blink demo of ecp5 fpga. 2025-03-30 23:48:50 +08:00
colin 0d7f1f8511 更新 Readme.md 2025-03-29 00:13:02 +08:00
colin 8d862ff126 更新 Readme.md 2025-03-26 10:50:06 +08:00
Colin 973950cc1b add VexRiscv remote-bitbang support, but fail current. 2025-03-25 11:11:31 +08:00
Colin 3ca3f614fe Add jtag dpi in murax. 2025-03-25 11:11:31 +08:00
Colin 202042c913 Add Vexriscv demo and murax. 2025-03-25 11:11:31 +08:00
colin f03117dfd7 更新 Readme.md 2025-03-24 20:35:07 +08:00
colin 21c76636a6 更新 Readme.md 2025-03-24 20:06:12 +08:00
colin 901194a252 更新 Readme.md 2025-03-24 19:53:45 +08:00
colin 0ad3f6a5dc 更新 Readme.md 2025-03-24 19:43:29 +08:00
colin 1c449f1f68 更新 Readme.md 2025-03-24 17:35:10 +08:00
Colin 1f1ed068a0 Update 325T 2024-11-08 01:27:22 +08:00
colin.liang cca9d908ef Add program hex support in uriscv. 2023-01-07 16:15:54 +08:00
colin.liang c2e4068c8a Add uriscv/tb. 2023-01-07 16:14:56 +08:00
colin.liang 5fb3787307 reset from top.v. 2023-01-06 21:19:54 +08:00
colin.liang 31c90f22f6 Refine top.v. 2023-01-06 16:15:04 +08:00
colin.liang c57450fa1c Add ivlpp to gen single file of RTL. 2023-01-05 21:28:53 +08:00
colin.liang 44161e293f Reset Readme. 2023-01-04 22:40:08 +08:00
colin.liang 270f695fbf Update Readme 2022-11-03 17:00:26 +08:00
colin 32fff97ff5 Update gnu build. 2022-07-07 12:06:04 +00:00
colin e23aca0cfc Delete rvdff by fpga. 2022-05-23 15:37:09 +00:00
colin a8c8d46382 Remove ahb connect axi4. 2022-05-23 14:51:42 +00:00
colin 902f44a21c Default use axi4 without ahb_lite. 2022-05-23 14:45:23 +00:00
colin 6bf845bb46 Format sv and v code. 2022-05-23 14:16:04 +00:00
colin 2f8715aeb6 Delete unuse file and configs. 2022-05-23 13:53:58 +00:00
colin a9bfa80cc1 Test jtag demo will incorrect when add instruction in loop3. 2022-05-11 03:31:51 +00:00
colin 29696841ff Refine flow asm code. 2022-05-10 13:44:14 +00:00
colin fd64d8618a Copy Cores-SweRV-EL2 to flow. 2022-05-10 13:07:33 +00:00
colin 11312aee91 Refine uriscv to verilator. 2022-05-10 12:50:30 +00:00
colin ded2df85f8 Refine Readme of uriscv. 2022-05-10 04:20:23 +00:00
colin 1dfaaa39ef Add uriscv, a smallest riscv implementation. 2022-05-10 04:19:18 +00:00
colin 15467611cf Update Readme. 2022-03-27 09:56:02 +00:00
colin 937a29de67 Update Cores-EL2 and Quasar. 2022-03-27 09:55:41 +00:00
colin bd392cfb7c Refine reset vector in Cores-SweRV. 2022-03-22 23:25:11 +00:00
colin 5b6bdcc8b0 Update .gitignore. 2022-03-22 23:24:30 +00:00
colin 388db4a82e Delete quasar in Cores-SweRV. 2022-03-22 23:24:01 +00:00
colin 386e1f1a54 Add Miner420T submodule 2022-03-22 23:14:02 +00:00
colin be80eb1063 Update Quasar. 2022-03-20 09:06:23 +00:00
colin 49c8aab2fd Update Readme. 2022-03-20 09:06:02 +00:00
colin 03549f1f93 Update Quasar 2022-03-18 10:06:26 +00:00
colin b2c15ca508 Update xilinx Readme. 2022-03-11 05:08:19 +00:00
colin b9d70b7a1c Update Quasar 2022-03-10 13:15:49 +00:00
colin d806515276 Add submodule of quasar. 2022-03-10 08:58:15 +00:00
colin 2be1901f7b update EL2 2022-03-09 14:46:24 +00:00