0dacc978da
Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
...
not start an SB write access when sbreadonaddr/dbreadondata is set.
Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
8c413fd1e2
Removed invalid include statement.
2019-07-12 11:26:03 -07:00
e40f01e15d
Moved flist.questa to testbench directory.
2019-07-12 11:25:07 -07:00
0f3f246df5
Remove spurious carriage return characters.
2019-07-12 06:22:01 -07:00
412c128fb0
Removed duplicate declaration of finished for Verilator.
2019-06-20 09:50:50 -07:00
c0f7e509cc
SweRV 1.1
2019-06-04 07:57:48 -07:00
Joseph Rahmeh