3820e84e20
Move declarations to top of Verilog file to fix fpga compile issues.
2019-10-15 13:14:36 -07:00
811e9c3d24
Change clock header instance name in beh_lib.sv
2019-09-04 14:39:10 -07:00
4e161e6c3b
Minor cleanup in config script.
2019-08-13 15:47:53 -07:00
d9bb036633
Updated hello world message. Updated last compilation time.
2019-08-13 12:57:04 -07:00
ac92841999
Adjust CSR MFDC reset value for the AXI bus.
2019-08-13 12:38:50 -07:00
0dacc978da
Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
...
not start an SB write access when sbreadonaddr/dbreadondata is set.
Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
c0f7e509cc
SweRV 1.1
2019-06-04 07:57:48 -07:00
Joseph Rahmeh