ec254f5491
Version 1.9.
2021-01-27 09:36:43 -08:00
8caf5f69b0
Added testbench/hex directory.
2020-09-18 13:47:53 -07:00
5e613582c2
New branch: branch1.8
2020-09-18 13:34:02 -07:00
ee77552301
Version 1.5
2020-02-19 18:57:15 -08:00
0dacc978da
Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
...
not start an SB write access when sbreadonaddr/dbreadondata is set.
Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
0f3f246df5
Remove spurious carriage return characters.
2019-07-12 06:22:01 -07:00
c0f7e509cc
SweRV 1.1
2019-06-04 07:57:48 -07:00
Joseph Rahmeh