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4 Commits

Author SHA1 Message Date
Arup De aa2bc2269d Fixed FPGA build error 2019-12-06 09:50:38 -08:00
Joseph Rahmeh 0dacc978da Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 
not start an SB write access when sbreadonaddr/dbreadondata is set.

Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
 2019-08-07 17:04:48 -07:00
Joseph Rahmeh 0f3f246df5 Remove spurious carriage return characters. 2019-07-12 06:22:01 -07:00
Joseph Rahmeh c0f7e509cc SweRV 1.1 2019-06-04 07:57:48 -07:00