6a528a9a8b
Ignore ebreak/ecall w.r.t MINSTRET
2019-08-09 19:18:41 -07:00
1cf98e765d
fix synthesis syntax in rvdffe in beh_lib.sv
2019-08-08 07:51:56 -07:00
0dacc978da
Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
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not start an SB write access when sbreadonaddr/dbreadondata is set.
Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
bc367eaf3a
Update README.md
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Added description of "espresso".
2019-07-20 08:28:44 -05:00
8c413fd1e2
Removed invalid include statement.
2019-07-12 11:26:03 -07:00
e40f01e15d
Moved flist.questa to testbench directory.
2019-07-12 11:25:07 -07:00
0f3f246df5
Remove spurious carriage return characters.
2019-07-12 06:22:01 -07:00
5990932214
Removed apostrophe from comment.
2019-07-12 06:04:31 -07:00
412c128fb0
Removed duplicate declaration of finished for Verilator.
2019-06-20 09:50:50 -07:00
8f92cd5033
Added .gitignore file.
2019-06-20 08:48:50 -07:00
48dc8668cb
Update README.md
2019-06-09 19:50:35 -05:00
166274de5e
Update README.md
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Added reference to version 1.0.
2019-06-06 11:32:35 -05:00
56db557851
Update release-notes.md
2019-06-04 11:31:56 -05:00
d33df11a5b
Added release notes.
2019-06-04 09:29:22 -07:00
9c6d925379
Create RISC-V SweRV EH1 PRM.pdf
2019-06-04 10:54:09 -05:00
de6978de5d
SweRV 1.1
2019-06-04 07:58:40 -07:00
c0f7e509cc
SweRV 1.1
2019-06-04 07:57:48 -07:00
6ccfce0957
Update README.md
2019-06-01 23:45:59 -07:00
1abeb9a380
Update README.md
2019-06-01 23:44:30 -07:00
763cd3d38a
Create README.md
2019-06-01 23:43:28 -07:00
8f1c48c0ab
Initial commit
2019-06-01 23:32:39 -07:00
Joseph Rahmeh
jrahmeh
Zvonimir Bandic