abstractaccelerator/design
Joseph Rahmeh 0dacc978da Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
not start an SB write access when sbreadonaddr/dbreadondata is set.

Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
..
dbg Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00
dec Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00
dmi Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00
exu Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00
ifu Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00
include SweRV 1.1 2019-06-04 07:57:48 -07:00
lib Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00
lsu Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00
dma_ctrl.sv Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00
mem.sv SweRV 1.1 2019-06-04 07:57:48 -07:00
pic_ctrl.sv Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00
swerv.sv Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00
swerv_wrapper.sv SweRV 1.1 2019-06-04 07:57:48 -07:00