0dacc978da
not start an SB write access when sbreadonaddr/dbreadondata is set. Add fpga_optimize option to swerv.config; eliminates over 90% of clock-gating to support faster FPGA simulation. |
||
|---|---|---|
| .. | ||
| ahb_to_axi4.sv | ||
| axi4_to_ahb.sv | ||
| beh_lib.sv | ||
| mem_lib.sv | ||