Joseph Rahmeh 0dacc978da Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does ... not start an SB write access when sbreadonaddr/dbreadondata is set. Add fpga_optimize option to swerv.config; eliminates over 90% of clock-gating to support faster FPGA simulation.		2019-08-07 17:04:48 -07:00
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asm	SweRV 1.1	2019-06-04 07:57:48 -07:00
hex	Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does	2019-08-07 17:04:48 -07:00
ahb_sif.sv	SweRV 1.1	2019-06-04 07:57:48 -07:00
flist.questa	Removed invalid include statement.	2019-07-12 11:26:03 -07:00
flist.spyglass	SweRV 1.1	2019-06-04 07:57:48 -07:00
flist.vcs	SweRV 1.1	2019-06-04 07:57:48 -07:00
flist.verilator	SweRV 1.1	2019-06-04 07:57:48 -07:00
flist.vlog	SweRV 1.1	2019-06-04 07:57:48 -07:00
input.tcl	SweRV 1.1	2019-06-04 07:57:48 -07:00
link.ld	SweRV 1.1	2019-06-04 07:57:48 -07:00
tb_top.sv	Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does	2019-08-07 17:04:48 -07:00
test_tb_top.cpp	SweRV 1.1	2019-06-04 07:57:48 -07:00