This adds an initial FuseSoC core description file for SweRV EL2.
In addition to the core file there is also a python wrapper for
the core configuration (configs/swerv_config_gen.py) that is used
as a FuseSoC generator. There is also a tcl file (tools/vivado.tcl)
with Vivado-specific options that FuseSoC will pick up automatically
when Vivado is used.
It has been successfully tested in a modified SweRVolf SoC to boot
Zephyr OS in a Verilator simulation and on the Nexys A7 FPGA board.
TODO:
- Add target for running the bundled SweRV EL2 testbench
- Add Model/Questasim support
aprnath
Olof Kindgren
Joseph Rahmeh
tmw-wdc
jrahmeh