3 Commits

Author	SHA1	Message	Date
colin	94c3d5f8ad	Splite ram and rom to bank=8.	2022-03-23 13:00:34 +00:00
colin	dc1509b921	Add temp fpga file : synth.sh	2022-03-09 14:44:11 +00:00
colin	ddf80fde8d	Add jtag	2022-03-07 13:08:10 +00:00