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81 Commits

Author SHA1 Message Date
Tommy Thorn 2cce6f4e8b Enable the use of 64-bit riscv tools 
Many Linux distributions now include the tools for RISC-V (for example
Ubuntu 20.04 has gcc-riscv64-unknown-elf) but in order for

  make TOOLCHAIN_PREFIX=riscv64-unknown-elf-

to work we need to be explicit about compiling for 32-bit.
 2020-06-03 09:27:30 -07:00
Larry Doolittle 9129d18bf5 Cleanup whitespaces 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-23 17:59:17 +02:00
Claire Wolf 409d0dfd67
Merge pull request #145 from Novakov/patch-1 
spimemio documentation: read latency reset value
 2020-04-22 17:32:19 +02:00
Claire Wolf 65e72ea49e
Merge pull request #156 from dehann/patch-1 
fix readme icebreaker links
 2020-04-22 17:25:28 +02:00
Claire Wolf fb34c8aca9
Merge pull request #148 from splinedrive/disable_memory_test 
Workarround: Disable cmd_memtest() when starting firmware.
 2020-04-22 17:25:05 +02:00
René Rebe a7ff70dfb4 added default clk divider parameter to simpleuart 2020-04-15 13:25:57 +02:00
dehann b428e843cd
fix icebreaker links 2020-04-12 14:42:45 -04:00
Hirosh Dabui 1b6821d1a1 Workarround: Disable cmd_memtest() when starting firmware. 
It destroys bss and data section memory.
You are not able to use static or global vars.
 2020-01-27 02:19:56 +01:00
Maciej T. Nowak 0201e8ff02
spimemio documentation: read latency reset value 
According to c06ba38113/picosoc/spimemio.v (L111) the reset value for `Read latency (dummy) cycles` is 8 cycles, not 0.
 2020-01-03 21:57:19 +01:00
René Rebe 1e24e99970 added CROSS prefix and CFLAGS to the picsoc/Makefile 
so one can run it with other toolchains, e.g.
CROSS=riscv64-t2-linux-gnu- CFLAGS=-mabi=ilp32, too
 2019-11-14 12:31:20 +01:00
Pascal Cotret 415382761c
Short modification in the error string 2019-10-29 16:42:24 +01:00
Clifford Wolf 77277a0d32 Fix typo, closes #136 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-25 11:28:08 +02:00
Chris Clark 7ac4102fc4 fix typo in picosoc/Makefile for hx8k board 2019-03-01 19:57:22 -05:00
Clifford Wolf 358dde2376
Merge branch 'master' into icebreaker-spram 2019-02-13 14:13:23 +01:00
Steffen Vogel 3710a86b81 icebreaker: artificially limit available RAM to speed-up simulation 2019-02-12 00:13:33 +01:00
Steffen Vogel eb64df6c3e picosoc: use preprocessor for generating target-specific linker script 2019-02-11 23:44:47 +01:00
Steffen Vogel f3b1246c86 picosoc: added memtest 2019-02-11 23:14:56 +01:00
Steffen Vogel d21937bafc picosoc: increase available memory by using SPRAM instead of BRAM for the Icebreaker example 2019-02-11 23:13:05 +01:00
Steffen Vogel 672c99b71e added echo command for testing simpleuart 2019-02-11 21:26:45 +01:00
Miodrag Milanovic 2f16c46918 Alignment fix for global symbols fixes #97 2018-10-28 18:48:19 +01:00
Jörg Mische cb766a3757 Fix PicoSoC firmware filename for simulation 2018-10-01 14:00:21 +02:00
Olof Kindgren 7b9641ad97 Add FuseSoC support for icebreaker 2018-09-02 22:48:47 +02:00
matt venn fabb3eaf70 fix firmware recipes 2018-08-30 22:27:34 +02:00
matt venn fe1867817d fix ifdef to include flash functions for hx8k 2018-08-30 22:27:18 +02:00
Clifford Wolf 2d6d5c055b More PicoSoC firmware improvements for icebreaker 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 14:39:20 +02:00
Clifford Wolf 68c69136b9 Add icebreaker example PicoSoC implementation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 13:38:59 +02:00
Clifford Wolf 1afe3af452 Add PicoSoC IceBreaker demo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 20:17:21 +02:00
Olof Kindgren 75aa1055f8 Expose ENABLE_IRQ_QREGS and PROGADDR_IRQ from picosoc.v 2018-08-16 22:06:26 +02:00
Clifford Wolf 7c256656c2 PicoSoC: Use RDSR1+RDCR1+WRR instead of RDAR+WRAR 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-16 14:09:12 +02:00
Clifford Wolf 4c1e0f47a6 Add rs232 decode to picosoc hx8kdemo test bench 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 14:27:09 +02:00
Clifford Wolf 28d6f97b00 Fix picosoc quad spi mode (flashio_worker must be multiple of 4 bytes) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 14:26:49 +02:00
Clifford Wolf b3f292a988 Improve picosoc demo firmware, picosoc firmware build fixes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 13:49:08 +02:00
Clifford Wolf ce9d92939a
Merge pull request #61 from mmicko/linker-script 
Created lds file (section mapping) and init for data and bss sections
 2018-08-14 13:05:56 +02:00
Olof Kindgren 12274e9f8a Add FuseSoC .core file for hx8kdemo 
The core file specifies targets for FPGA implementation (fusesoc
build hx8kdemo) and simulation (fusesoc run --tool=<tool>
--target=sim hx8kdemo --firmware=path/to/firmware.he).

Simulation has been tested successfully with icarus, modelsim and xsim
 2018-07-27 23:23:41 +02:00
Olof Kindgren 80f128713d Add FuseSoC .core file for picosoc 
This allows other cores to depend on the generic parts of picosoc
and use that as a base design.
 2018-07-27 23:23:41 +02:00
Olof Kindgren 262da6444c Add FuseSoC .core file for SPI Flash model 
This allows other cores to depend on spiflash. Can also be used to
run the spiflash testbench with

fusesoc run --tool=<tool> spiflash --firmware=path/to/firmware.hex

This has been tested with icarus, modelsim and xsim. Fails with isim
If --tool is left out, icarus will be used as default
 2018-07-26 23:26:43 +02:00
Olof Kindgren 2ceb472178 Bypass picosoc compile order check if PICORV32_REGS is defined. 
Previously, picosoc.v needed to be sourced before picorv32.v to
ensure that the PICORV32_REGS `define (used to select implementation
for the register file) was set to picosoc_regs

This allows for overriding PICORV32_REGS, e.g. by setting it
externally in the EDA tool invocation. In this case, the compile
order between picorv32.v and picosoc.v is not important.

Note: This change will break the safety check if PICORV32_REGS
is defined between sourcing picorv32.v and picosoc.v
 2018-05-18 23:52:31 +02:00
Olof Kindgren c9470e3e04 spiflash: Allow setting firmware from plusarg 2018-05-15 09:53:33 +02:00
Olof Kindgren d26e505251 Fix spiflash_tb 
Update expected two first Flash words to reflect changes in start.s

Add dummy SPI cycles to account for latency
 2018-05-11 22:56:52 +02:00
Larry Doolittle 8b32bc5bd6 Fix miscellaneous typos in documentation 2018-04-17 17:53:08 +02:00
Miodrag Milanovic 9300a510c5 Created lfs file (section mappint) and init for data and bss sections 2018-04-16 20:04:01 +02:00
Luke Valenty a0d5f8efd7
add .data and .bss segments to picosoc 
added .data and .bss segments to picosoc firmware linker script so that static variables may be used.
 2018-04-07 18:42:59 -07:00
Clifford Wolf 65f32c38db Fix picosoc hx8kdemo_tb 2017-11-11 19:49:01 +01:00
Clifford Wolf ad08edd2e5 Add PICORV32_REGS mechanism for ASIC sram instantiation 2017-10-01 15:45:46 +02:00
Clifford Wolf 500db14e44 Improve PicoSoC overview.svg 2017-09-22 05:09:03 +02:00
Clifford Wolf 694b9390fd Enable a bunch of PicoRV32 features in PicoSoC 2017-09-22 04:52:44 +02:00
Clifford Wolf 9e5903fbbe Update PicoSoC README 2017-09-21 19:58:55 +02:00
Clifford Wolf ae0e5a6c94 Remove generic PicoSoC testbench 2017-09-21 19:45:41 +02:00
Clifford Wolf 8b5f2aeff3 Merge branch 'master' of github.com:cliffordwolf/picorv32 2017-09-21 19:37:12 +02:00
Clifford Wolf 29b1d0d7de Resize overview.svg 2017-09-21 19:37:04 +02:00