Clifford Wolf
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32208c0b70
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Improved timing for "decoded_imm_uj"
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2015-06-07 22:50:49 +02:00 |
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Clifford Wolf
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06ba3a1a57
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README Updates
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2015-06-07 20:59:20 +02:00 |
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Clifford Wolf
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34d9dea8c7
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Added support for dual-port register file
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2015-06-07 20:53:19 +02:00 |
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Clifford Wolf
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60867e10a9
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minor optimizations
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2015-06-07 20:08:04 +02:00 |
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Clifford Wolf
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8e3e0bfba0
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Improved "decoder_trigger" handling
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2015-06-07 19:49:38 +02:00 |
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Clifford Wolf
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bbbcea2faa
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Added look-ahead write interface
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2015-06-07 12:11:20 +02:00 |
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Clifford Wolf
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e84f044bc5
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Major redesign of main FSM
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2015-06-07 11:49:47 +02:00 |
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Clifford Wolf
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491cd5e15d
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Using libc assembler code in dhrystone stdlib.c
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2015-06-07 07:29:13 +02:00 |
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Clifford Wolf
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44ea992fed
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Updated CPI table in README
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2015-06-06 21:43:33 +02:00 |
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Clifford Wolf
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90ff3380a4
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Updated README
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2015-06-06 21:27:58 +02:00 |
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Clifford Wolf
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2107a328c4
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Added insn timing hack to dryhstone testbench
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2015-06-06 21:27:07 +02:00 |
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Clifford Wolf
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bc8ffd2ecb
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Added memory "look-ahead" read interface
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2015-06-06 20:50:53 +02:00 |
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Clifford Wolf
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9df9d7ff90
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Improved Xilinx example
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2015-06-06 20:14:58 +02:00 |
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Clifford Wolf
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abe0465753
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Faster memory model in dhrystone testbench
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2015-06-06 19:35:07 +02:00 |
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Clifford Wolf
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c55d537401
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Improved AXI tests
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2015-06-06 19:22:28 +02:00 |
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Clifford Wolf
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f9ae73066b
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Added license info to README
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2015-06-06 17:24:11 +02:00 |
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Clifford Wolf
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7fd24a96b2
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Improved AXI Interface Testbench
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2015-06-06 17:15:09 +02:00 |
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Clifford Wolf
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77ba5a1897
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Initial import
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2015-06-06 14:14:32 +02:00 |