2020-10-22 17:52:47 +08:00
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_div_ctl|el2_exu_div_ctl>io_finish_dly",
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"sources":[
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"~el2_exu_div_ctl|el2_exu_div_ctl>io_cancel"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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2020-11-06 18:05:28 +08:00
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"el2_exu_div_ctl.TEC_RV_ICG",
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"resourceId":"/vsrc/TEC_RV_ICG.v"
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},
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2020-10-22 17:52:47 +08:00
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"el2_exu_div_ctl"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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