lsu updated
This commit is contained in:
laraibkhan119
parent
4e107cc640
commit
4b73eb7a6f
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@ -5,31 +5,35 @@ circuit dmi_jtag_to_core_sync :
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input reset : AsyncReset
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output io : {flip rd_en : UInt<1>, flip wr_en : UInt<1>, reg_en : UInt<1>, reg_wr_en : UInt<1>}
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io.reg_en <= UInt<1>("h00") @[dmi_jtag_to_core_sync.scala 19:16]
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io.reg_wr_en <= UInt<1>("h00") @[dmi_jtag_to_core_sync.scala 20:16]
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wire c_rd_en : UInt<1>
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c_rd_en <= UInt<1>("h00")
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wire c_wr_en : UInt<1>
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c_wr_en <= UInt<1>("h00")
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wire rden : UInt<3>
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rden <= UInt<1>("h00")
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rden <= UInt<3>("h00")
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wire wren : UInt<3>
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wren <= UInt<1>("h00")
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node _T = bits(rden, 1, 0) @[dmi_jtag_to_core_sync.scala 25:27]
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wren <= UInt<3>("h00")
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node _T = bits(rden, 1, 0) @[dmi_jtag_to_core_sync.scala 26:27]
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node _T_1 = cat(_T, io.rd_en) @[Cat.scala 29:58]
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reg _T_2 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 25:18]
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_T_2 <= _T_1 @[dmi_jtag_to_core_sync.scala 25:18]
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rden <= _T_2 @[dmi_jtag_to_core_sync.scala 25:8]
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node _T_3 = bits(wren, 1, 0) @[dmi_jtag_to_core_sync.scala 26:27]
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reg _T_2 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 26:18]
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_T_2 <= _T_1 @[dmi_jtag_to_core_sync.scala 26:18]
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rden <= _T_2 @[dmi_jtag_to_core_sync.scala 26:8]
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node _T_3 = bits(wren, 1, 0) @[dmi_jtag_to_core_sync.scala 27:27]
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node _T_4 = cat(_T_3, io.wr_en) @[Cat.scala 29:58]
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reg _T_5 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 26:18]
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_T_5 <= _T_4 @[dmi_jtag_to_core_sync.scala 26:18]
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wren <= _T_5 @[dmi_jtag_to_core_sync.scala 26:8]
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node _T_6 = bits(rden, 1, 1) @[dmi_jtag_to_core_sync.scala 28:21]
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node _T_7 = bits(rden, 2, 2) @[dmi_jtag_to_core_sync.scala 28:32]
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node _T_8 = eq(_T_7, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 28:27]
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node c_rd_en = and(_T_6, _T_8) @[dmi_jtag_to_core_sync.scala 28:25]
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node _T_9 = bits(wren, 1, 1) @[dmi_jtag_to_core_sync.scala 29:21]
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node _T_10 = bits(wren, 2, 2) @[dmi_jtag_to_core_sync.scala 29:32]
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node _T_11 = eq(_T_10, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 29:27]
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node c_wr_en = and(_T_9, _T_11) @[dmi_jtag_to_core_sync.scala 29:25]
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node _T_12 = or(c_wr_en, c_rd_en) @[dmi_jtag_to_core_sync.scala 31:24]
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io.reg_en <= _T_12 @[dmi_jtag_to_core_sync.scala 31:13]
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io.reg_wr_en <= c_wr_en @[dmi_jtag_to_core_sync.scala 32:16]
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reg _T_5 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 27:18]
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_T_5 <= _T_4 @[dmi_jtag_to_core_sync.scala 27:18]
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wren <= _T_5 @[dmi_jtag_to_core_sync.scala 27:8]
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node _T_6 = bits(rden, 1, 1) @[dmi_jtag_to_core_sync.scala 28:17]
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node _T_7 = bits(rden, 2, 2) @[dmi_jtag_to_core_sync.scala 28:28]
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node _T_8 = eq(_T_7, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 28:23]
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node _T_9 = and(_T_6, _T_8) @[dmi_jtag_to_core_sync.scala 28:21]
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c_rd_en <= _T_9 @[dmi_jtag_to_core_sync.scala 28:10]
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node _T_10 = bits(wren, 1, 1) @[dmi_jtag_to_core_sync.scala 29:17]
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node _T_11 = bits(wren, 2, 2) @[dmi_jtag_to_core_sync.scala 29:28]
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node _T_12 = eq(_T_11, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 29:23]
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node _T_13 = and(_T_10, _T_12) @[dmi_jtag_to_core_sync.scala 29:21]
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c_wr_en <= _T_13 @[dmi_jtag_to_core_sync.scala 29:10]
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node _T_14 = or(c_wr_en, c_rd_en) @[dmi_jtag_to_core_sync.scala 31:28]
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io.reg_en <= _T_14 @[dmi_jtag_to_core_sync.scala 31:17]
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io.reg_wr_en <= c_wr_en @[dmi_jtag_to_core_sync.scala 32:17]
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@ -10,14 +10,14 @@ module dmi_jtag_to_core_sync(
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reg [31:0] _RAND_0;
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reg [31:0] _RAND_1;
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`endif // RANDOMIZE_REG_INIT
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reg [2:0] rden; // @[dmi_jtag_to_core_sync.scala 25:18]
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reg [2:0] wren; // @[dmi_jtag_to_core_sync.scala 26:18]
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wire _T_8 = ~rden[2]; // @[dmi_jtag_to_core_sync.scala 28:27]
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wire c_rd_en = rden[1] & _T_8; // @[dmi_jtag_to_core_sync.scala 28:25]
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wire _T_11 = ~wren[2]; // @[dmi_jtag_to_core_sync.scala 29:27]
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wire c_wr_en = wren[1] & _T_11; // @[dmi_jtag_to_core_sync.scala 29:25]
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assign io_reg_en = c_wr_en | c_rd_en; // @[dmi_jtag_to_core_sync.scala 19:16 dmi_jtag_to_core_sync.scala 31:13]
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assign io_reg_wr_en = wren[1] & _T_11; // @[dmi_jtag_to_core_sync.scala 20:16 dmi_jtag_to_core_sync.scala 32:16]
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reg [2:0] rden; // @[dmi_jtag_to_core_sync.scala 26:18]
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reg [2:0] wren; // @[dmi_jtag_to_core_sync.scala 27:18]
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wire _T_8 = ~rden[2]; // @[dmi_jtag_to_core_sync.scala 28:23]
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wire c_rd_en = rden[1] & _T_8; // @[dmi_jtag_to_core_sync.scala 28:21]
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wire _T_12 = ~wren[2]; // @[dmi_jtag_to_core_sync.scala 29:23]
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wire c_wr_en = wren[1] & _T_12; // @[dmi_jtag_to_core_sync.scala 29:21]
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assign io_reg_en = c_wr_en | c_rd_en; // @[dmi_jtag_to_core_sync.scala 31:17]
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assign io_reg_wr_en = wren[1] & _T_12; // @[dmi_jtag_to_core_sync.scala 32:17]
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`ifdef RANDOMIZE_GARBAGE_ASSIGN
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`define RANDOMIZE
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`endif
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@ -10,6 +10,11 @@
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"el2_exu_div_ctl.TEC_RV_ICG",
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"resourceId":"/vsrc/TEC_RV_ICG.v"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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3295
el2_exu_div_ctl.fir
3295
el2_exu_div_ctl.fir
File diff suppressed because it is too large
Load Diff
1103
el2_exu_div_ctl.v
1103
el2_exu_div_ctl.v
File diff suppressed because it is too large
Load Diff
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@ -3,6 +3,11 @@
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"el2_exu_mul_ctl.TEC_RV_ICG",
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"resourceId":"/vsrc/TEC_RV_ICG.v"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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@ -1,5 +1,77 @@
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_exu_mul_ctl :
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extmodule TEC_RV_ICG :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_2 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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module el2_exu_mul_ctl :
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input clock : Clock
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input reset : AsyncReset
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@ -9,47 +81,65 @@ circuit el2_exu_mul_ctl :
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rs1_ext_in <= asSInt(UInt<1>("h00"))
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wire rs2_ext_in : SInt<33>
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rs2_ext_in <= asSInt(UInt<1>("h00"))
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wire rs1_x : SInt<33>
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rs1_x <= asSInt(UInt<1>("h00"))
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wire rs2_x : SInt<33>
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rs2_x <= asSInt(UInt<1>("h00"))
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wire prod_x : SInt<66>
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prod_x <= asSInt(UInt<1>("h00"))
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wire low_x : UInt<1>
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low_x <= UInt<1>("h00")
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node _T = bits(io.rs1_in, 31, 31) @[el2_exu_mul_ctl.scala 23:50]
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node _T_1 = and(io.mul_p.rs1_sign, _T) @[el2_exu_mul_ctl.scala 23:39]
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node _T = bits(io.rs1_in, 31, 31) @[el2_exu_mul_ctl.scala 26:50]
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node _T_1 = and(io.mul_p.rs1_sign, _T) @[el2_exu_mul_ctl.scala 26:39]
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node _T_2 = cat(_T_1, io.rs1_in) @[Cat.scala 29:58]
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node _T_3 = asSInt(_T_2) @[el2_exu_mul_ctl.scala 23:66]
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rs1_ext_in <= _T_3 @[el2_exu_mul_ctl.scala 23:14]
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node _T_4 = bits(io.rs2_in, 31, 31) @[el2_exu_mul_ctl.scala 24:50]
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node _T_5 = and(io.mul_p.rs2_sign, _T_4) @[el2_exu_mul_ctl.scala 24:39]
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node _T_3 = asSInt(_T_2) @[el2_exu_mul_ctl.scala 26:66]
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rs1_ext_in <= _T_3 @[el2_exu_mul_ctl.scala 26:14]
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node _T_4 = bits(io.rs2_in, 31, 31) @[el2_exu_mul_ctl.scala 27:50]
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node _T_5 = and(io.mul_p.rs2_sign, _T_4) @[el2_exu_mul_ctl.scala 27:39]
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node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58]
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node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 24:66]
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rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 24:14]
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node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 27:55]
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reg _T_9 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_8 : @[Reg.scala 28:19]
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_T_9 <= io.mul_p.low @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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low_x <= _T_9 @[el2_exu_mul_ctl.scala 27:9]
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node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 28:56]
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reg rs1_x : SInt, clock with : (reset => (reset, asSInt(UInt<1>("h00")))) @[Reg.scala 27:20]
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when _T_10 : @[Reg.scala 28:19]
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rs1_x <= rs1_ext_in @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_11 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 29:56]
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reg rs2_x : SInt, clock with : (reset => (reset, asSInt(UInt<1>("h00")))) @[Reg.scala 27:20]
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when _T_11 : @[Reg.scala 28:19]
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rs2_x <= rs2_ext_in @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_12 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 31:20]
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prod_x <= _T_12 @[el2_exu_mul_ctl.scala 31:10]
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node _T_13 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 32:36]
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node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 32:29]
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node _T_15 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 32:52]
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node _T_16 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 32:67]
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node _T_17 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 32:83]
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node _T_18 = mux(_T_14, _T_15, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_19 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_20 = or(_T_18, _T_19) @[Mux.scala 27:72]
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wire _T_21 : UInt<32> @[Mux.scala 27:72]
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_T_21 <= _T_20 @[Mux.scala 27:72]
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io.result_x <= _T_21 @[el2_exu_mul_ctl.scala 32:15]
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node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 27:66]
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rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 27:14]
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node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 36:47]
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inst rvclkhdr of rvclkhdr @[beh_lib.scala 352:21]
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rvclkhdr.clock <= clock
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rvclkhdr.reset <= reset
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rvclkhdr.io.clk <= clock @[beh_lib.scala 354:16]
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rvclkhdr.io.en <= _T_8 @[beh_lib.scala 355:15]
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rvclkhdr.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22]
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reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14]
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_T_9 <= io.mul_p.low @[beh_lib.scala 358:14]
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low_x <= _T_9 @[el2_exu_mul_ctl.scala 36:9]
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node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 37:44]
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inst rvclkhdr_1 of rvclkhdr_1 @[beh_lib.scala 372:21]
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rvclkhdr_1.clock <= clock
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rvclkhdr_1.reset <= reset
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rvclkhdr_1.io.clk <= clock @[beh_lib.scala 374:16]
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rvclkhdr_1.io.en <= _T_10 @[beh_lib.scala 375:15]
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rvclkhdr_1.io.scan_mode <= io.scan_mode @[beh_lib.scala 376:22]
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reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[beh_lib.scala 378:14]
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_T_11 <= rs1_ext_in @[beh_lib.scala 378:14]
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rs1_x <= _T_11 @[el2_exu_mul_ctl.scala 37:9]
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node _T_12 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 38:45]
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inst rvclkhdr_2 of rvclkhdr_2 @[beh_lib.scala 372:21]
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rvclkhdr_2.clock <= clock
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rvclkhdr_2.reset <= reset
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rvclkhdr_2.io.clk <= clock @[beh_lib.scala 374:16]
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rvclkhdr_2.io.en <= _T_12 @[beh_lib.scala 375:15]
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rvclkhdr_2.io.scan_mode <= io.scan_mode @[beh_lib.scala 376:22]
|
||||
reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[beh_lib.scala 378:14]
|
||||
_T_13 <= rs2_ext_in @[beh_lib.scala 378:14]
|
||||
rs2_x <= _T_13 @[el2_exu_mul_ctl.scala 38:9]
|
||||
node _T_14 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 40:20]
|
||||
prod_x <= _T_14 @[el2_exu_mul_ctl.scala 40:10]
|
||||
node _T_15 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:36]
|
||||
node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 41:29]
|
||||
node _T_17 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 41:52]
|
||||
node _T_18 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:67]
|
||||
node _T_19 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 41:83]
|
||||
node _T_20 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_21 = mux(_T_18, _T_19, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72]
|
||||
wire _T_23 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_23 <= _T_22 @[Mux.scala 27:72]
|
||||
io.result_x <= _T_23 @[el2_exu_mul_ctl.scala 41:15]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,24 @@
|
|||
module rvclkhdr(
|
||||
output io_l1clk,
|
||||
input io_clk,
|
||||
input io_en,
|
||||
input io_scan_mode
|
||||
);
|
||||
wire clkhdr_Q; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_CK; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_EN; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_SE; // @[beh_lib.scala 332:24]
|
||||
TEC_RV_ICG clkhdr ( // @[beh_lib.scala 332:24]
|
||||
.Q(clkhdr_Q),
|
||||
.CK(clkhdr_CK),
|
||||
.EN(clkhdr_EN),
|
||||
.SE(clkhdr_SE)
|
||||
);
|
||||
assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 333:12]
|
||||
assign clkhdr_CK = io_clk; // @[beh_lib.scala 334:16]
|
||||
assign clkhdr_EN = io_en; // @[beh_lib.scala 335:16]
|
||||
assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 336:16]
|
||||
endmodule
|
||||
module el2_exu_mul_ctl(
|
||||
input clock,
|
||||
input reset,
|
||||
|
|
@ -30,18 +51,55 @@ module el2_exu_mul_ctl(
|
|||
reg [63:0] _RAND_1;
|
||||
reg [63:0] _RAND_2;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire _T_1 = io_mul_p_rs1_sign & io_rs1_in[31]; // @[el2_exu_mul_ctl.scala 23:39]
|
||||
wire [32:0] rs1_ext_in = {_T_1,io_rs1_in}; // @[el2_exu_mul_ctl.scala 23:66]
|
||||
wire _T_5 = io_mul_p_rs2_sign & io_rs2_in[31]; // @[el2_exu_mul_ctl.scala 24:39]
|
||||
wire [32:0] rs2_ext_in = {_T_5,io_rs2_in}; // @[el2_exu_mul_ctl.scala 24:66]
|
||||
reg low_x; // @[Reg.scala 27:20]
|
||||
reg [32:0] rs1_x; // @[Reg.scala 27:20]
|
||||
reg [32:0] rs2_x; // @[Reg.scala 27:20]
|
||||
wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 31:20]
|
||||
wire _T_14 = ~low_x; // @[el2_exu_mul_ctl.scala 32:29]
|
||||
wire [31:0] _T_18 = _T_14 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_19 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
assign io_result_x = _T_18 | _T_19; // @[el2_exu_mul_ctl.scala 32:15]
|
||||
wire rvclkhdr_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_1_io_clk; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_1_io_en; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_2_io_l1clk; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_2_io_clk; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_2_io_en; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_2_io_scan_mode; // @[beh_lib.scala 372:21]
|
||||
wire _T_1 = io_mul_p_rs1_sign & io_rs1_in[31]; // @[el2_exu_mul_ctl.scala 26:39]
|
||||
wire _T_5 = io_mul_p_rs2_sign & io_rs2_in[31]; // @[el2_exu_mul_ctl.scala 27:39]
|
||||
reg low_x; // @[beh_lib.scala 358:14]
|
||||
reg [32:0] rs1_x; // @[beh_lib.scala 378:14]
|
||||
reg [32:0] rs2_x; // @[beh_lib.scala 378:14]
|
||||
wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 40:20]
|
||||
wire _T_16 = ~low_x; // @[el2_exu_mul_ctl.scala 41:29]
|
||||
wire [31:0] _T_20 = _T_16 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_21 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
rvclkhdr rvclkhdr ( // @[beh_lib.scala 352:21]
|
||||
.io_l1clk(rvclkhdr_io_l1clk),
|
||||
.io_clk(rvclkhdr_io_clk),
|
||||
.io_en(rvclkhdr_io_en),
|
||||
.io_scan_mode(rvclkhdr_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 372:21]
|
||||
.io_l1clk(rvclkhdr_1_io_l1clk),
|
||||
.io_clk(rvclkhdr_1_io_clk),
|
||||
.io_en(rvclkhdr_1_io_en),
|
||||
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_2 ( // @[beh_lib.scala 372:21]
|
||||
.io_l1clk(rvclkhdr_2_io_l1clk),
|
||||
.io_clk(rvclkhdr_2_io_clk),
|
||||
.io_en(rvclkhdr_2_io_en),
|
||||
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
||||
);
|
||||
assign io_result_x = _T_20 | _T_21; // @[el2_exu_mul_ctl.scala 41:15]
|
||||
assign rvclkhdr_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_io_en = io_mul_p_valid; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[beh_lib.scala 374:16]
|
||||
assign rvclkhdr_1_io_en = io_mul_p_valid; // @[beh_lib.scala 375:15]
|
||||
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 376:22]
|
||||
assign rvclkhdr_2_io_clk = clock; // @[beh_lib.scala 374:16]
|
||||
assign rvclkhdr_2_io_en = io_mul_p_valid; // @[beh_lib.scala 375:15]
|
||||
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[beh_lib.scala 376:22]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -99,25 +157,25 @@ end // initial
|
|||
`FIRRTL_AFTER_INITIAL
|
||||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
low_x <= 1'h0;
|
||||
end else if (io_mul_p_valid) begin
|
||||
end else begin
|
||||
low_x <= io_mul_p_low;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
rs1_x <= 33'sh0;
|
||||
end else if (io_mul_p_valid) begin
|
||||
rs1_x <= rs1_ext_in;
|
||||
end else begin
|
||||
rs1_x <= {_T_1,io_rs1_in};
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
rs2_x <= 33'sh0;
|
||||
end else if (io_mul_p_valid) begin
|
||||
rs2_x <= rs2_ext_in;
|
||||
end else begin
|
||||
rs2_x <= {_T_5,io_rs2_in};
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -87,8 +87,8 @@
|
|||
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
|
||||
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
|
||||
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
|
||||
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_rs1_region_d",
|
||||
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
|
||||
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_rs1_region_d",
|
||||
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
|
||||
]
|
||||
},
|
||||
|
|
|
|||
|
|
@ -1,304 +1,252 @@
|
|||
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
|
||||
circuit el2_lsu_addrcheck :
|
||||
module rvrangecheck :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
|
||||
|
||||
node _T = bits(io.addr, 31, 28) @[beh_lib.scala 113:30]
|
||||
node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 113:52]
|
||||
io.in_region <= _T_1 @[beh_lib.scala 113:19]
|
||||
node _T_2 = bits(io.addr, 31, 16) @[beh_lib.scala 117:30]
|
||||
node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[beh_lib.scala 117:45]
|
||||
io.in_range <= _T_3 @[beh_lib.scala 117:19]
|
||||
|
||||
module rvrangecheck_1 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
|
||||
|
||||
node _T = bits(io.addr, 31, 28) @[beh_lib.scala 113:30]
|
||||
node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 113:52]
|
||||
io.in_region <= _T_1 @[beh_lib.scala 113:19]
|
||||
node _T_2 = bits(io.addr, 31, 16) @[beh_lib.scala 117:30]
|
||||
node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[beh_lib.scala 117:45]
|
||||
io.in_range <= _T_3 @[beh_lib.scala 117:19]
|
||||
|
||||
module rvrangecheck_2 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
|
||||
|
||||
node _T = bits(io.addr, 31, 28) @[beh_lib.scala 113:30]
|
||||
node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 113:52]
|
||||
io.in_region <= _T_1 @[beh_lib.scala 113:19]
|
||||
node _T_2 = bits(io.addr, 31, 15) @[beh_lib.scala 117:30]
|
||||
node _T_3 = eq(_T_2, UInt<17>("h01e018")) @[beh_lib.scala 117:45]
|
||||
io.in_range <= _T_3 @[beh_lib.scala 117:19]
|
||||
|
||||
module rvrangecheck_3 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
|
||||
|
||||
node _T = bits(io.addr, 31, 28) @[beh_lib.scala 113:30]
|
||||
node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 113:52]
|
||||
io.in_region <= _T_1 @[beh_lib.scala 113:19]
|
||||
node _T_2 = bits(io.addr, 31, 15) @[beh_lib.scala 117:30]
|
||||
node _T_3 = eq(_T_2, UInt<17>("h01e018")) @[beh_lib.scala 117:45]
|
||||
io.in_range <= _T_3 @[beh_lib.scala 117:19]
|
||||
|
||||
module el2_lsu_addrcheck :
|
||||
input clock : Clock
|
||||
input reset : AsyncReset
|
||||
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
wire start_addr_in_dccm_d : UInt<1>
|
||||
start_addr_in_dccm_d <= UInt<1>("h00")
|
||||
wire start_addr_in_dccm_region_d : UInt<1>
|
||||
start_addr_in_dccm_region_d <= UInt<1>("h00")
|
||||
wire end_addr_in_dccm_d : UInt<1>
|
||||
end_addr_in_dccm_d <= UInt<1>("h00")
|
||||
wire end_addr_in_dccm_region_d : UInt<1>
|
||||
end_addr_in_dccm_region_d <= UInt<1>("h00")
|
||||
inst rvrangecheck of rvrangecheck @[el2_lsu_addrcheck.scala 45:44]
|
||||
rvrangecheck.clock <= clock
|
||||
rvrangecheck.reset <= reset
|
||||
rvrangecheck.io.addr <= io.start_addr_d @[el2_lsu_addrcheck.scala 46:41]
|
||||
start_addr_in_dccm_d <= rvrangecheck.io.in_range @[el2_lsu_addrcheck.scala 47:41]
|
||||
start_addr_in_dccm_region_d <= rvrangecheck.io.in_region @[el2_lsu_addrcheck.scala 48:41]
|
||||
inst rvrangecheck_1 of rvrangecheck_1 @[el2_lsu_addrcheck.scala 51:44]
|
||||
rvrangecheck_1.clock <= clock
|
||||
rvrangecheck_1.reset <= reset
|
||||
rvrangecheck_1.io.addr <= io.end_addr_d @[el2_lsu_addrcheck.scala 52:41]
|
||||
end_addr_in_dccm_d <= rvrangecheck_1.io.in_range @[el2_lsu_addrcheck.scala 53:41]
|
||||
end_addr_in_dccm_region_d <= rvrangecheck_1.io.in_region @[el2_lsu_addrcheck.scala 54:41]
|
||||
node _T = bits(io.start_addr_d, 31, 28) @[el2_lib.scala 253:27]
|
||||
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 253:49]
|
||||
wire start_addr_in_dccm_d : UInt<1> @[el2_lib.scala 254:26]
|
||||
node _T_1 = bits(io.start_addr_d, 31, 16) @[el2_lib.scala 258:24]
|
||||
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[el2_lib.scala 258:39]
|
||||
start_addr_in_dccm_d <= _T_2 @[el2_lib.scala 258:16]
|
||||
node _T_3 = bits(io.end_addr_d, 31, 28) @[el2_lib.scala 253:27]
|
||||
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[el2_lib.scala 253:49]
|
||||
wire end_addr_in_dccm_d : UInt<1> @[el2_lib.scala 254:26]
|
||||
node _T_4 = bits(io.end_addr_d, 31, 16) @[el2_lib.scala 258:24]
|
||||
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[el2_lib.scala 258:39]
|
||||
end_addr_in_dccm_d <= _T_5 @[el2_lib.scala 258:16]
|
||||
wire addr_in_iccm : UInt<1>
|
||||
addr_in_iccm <= UInt<1>("h00")
|
||||
node _T = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 65:37]
|
||||
node _T_1 = eq(_T, UInt<4>("h0e")) @[el2_lsu_addrcheck.scala 65:45]
|
||||
addr_in_iccm <= _T_1 @[el2_lsu_addrcheck.scala 65:18]
|
||||
inst start_addr_pic_rangecheck of rvrangecheck_2 @[el2_lsu_addrcheck.scala 74:41]
|
||||
start_addr_pic_rangecheck.clock <= clock
|
||||
start_addr_pic_rangecheck.reset <= reset
|
||||
node _T_2 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 75:55]
|
||||
start_addr_pic_rangecheck.io.addr <= _T_2 @[el2_lsu_addrcheck.scala 75:37]
|
||||
inst end_addr_pic_rangecheck of rvrangecheck_3 @[el2_lsu_addrcheck.scala 80:39]
|
||||
end_addr_pic_rangecheck.clock <= clock
|
||||
end_addr_pic_rangecheck.reset <= reset
|
||||
node _T_3 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 81:51]
|
||||
end_addr_pic_rangecheck.io.addr <= _T_3 @[el2_lsu_addrcheck.scala 81:35]
|
||||
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[el2_lsu_addrcheck.scala 85:60]
|
||||
node _T_4 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 86:48]
|
||||
node _T_5 = eq(_T_4, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 86:54]
|
||||
node _T_6 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 86:92]
|
||||
node _T_7 = eq(_T_6, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 86:98]
|
||||
node base_reg_dccm_or_pic = or(_T_5, _T_7) @[el2_lsu_addrcheck.scala 86:74]
|
||||
node _T_8 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 87:57]
|
||||
io.addr_in_dccm_d <= _T_8 @[el2_lsu_addrcheck.scala 87:32]
|
||||
node _T_9 = and(start_addr_pic_rangecheck.io.in_range, end_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 88:56]
|
||||
io.addr_in_pic_d <= _T_9 @[el2_lsu_addrcheck.scala 88:32]
|
||||
node _T_10 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[el2_lsu_addrcheck.scala 90:63]
|
||||
node _T_11 = not(_T_10) @[el2_lsu_addrcheck.scala 90:33]
|
||||
io.addr_external_d <= _T_11 @[el2_lsu_addrcheck.scala 90:30]
|
||||
node _T_12 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 91:51]
|
||||
node csr_idx = cat(_T_12, UInt<1>("h01")) @[Cat.scala 29:58]
|
||||
node _T_13 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[el2_lsu_addrcheck.scala 92:50]
|
||||
node _T_14 = bits(_T_13, 0, 0) @[el2_lsu_addrcheck.scala 92:50]
|
||||
node _T_15 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[el2_lsu_addrcheck.scala 92:92]
|
||||
node _T_16 = or(_T_15, addr_in_iccm) @[el2_lsu_addrcheck.scala 92:121]
|
||||
node _T_17 = not(_T_16) @[el2_lsu_addrcheck.scala 92:62]
|
||||
node _T_18 = and(_T_14, _T_17) @[el2_lsu_addrcheck.scala 92:60]
|
||||
node _T_19 = and(_T_18, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 92:137]
|
||||
node _T_20 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[el2_lsu_addrcheck.scala 92:180]
|
||||
node is_sideeffects_d = and(_T_19, _T_20) @[el2_lsu_addrcheck.scala 92:158]
|
||||
node _T_21 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 93:69]
|
||||
node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:75]
|
||||
node _T_23 = and(io.lsu_pkt_d.word, _T_22) @[el2_lsu_addrcheck.scala 93:51]
|
||||
node _T_24 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 93:124]
|
||||
node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:128]
|
||||
node _T_26 = and(io.lsu_pkt_d.half, _T_25) @[el2_lsu_addrcheck.scala 93:106]
|
||||
node _T_27 = or(_T_23, _T_26) @[el2_lsu_addrcheck.scala 93:85]
|
||||
node is_aligned_d = or(_T_27, io.lsu_pkt_d.by) @[el2_lsu_addrcheck.scala 93:138]
|
||||
node _T_28 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_29 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_30 = cat(_T_29, _T_28) @[Cat.scala 29:58]
|
||||
node _T_31 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
||||
node _T_32 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
||||
node _T_33 = cat(_T_32, _T_31) @[Cat.scala 29:58]
|
||||
node _T_34 = cat(_T_33, _T_30) @[Cat.scala 29:58]
|
||||
node _T_35 = orr(_T_34) @[el2_lsu_addrcheck.scala 97:99]
|
||||
node _T_36 = not(_T_35) @[el2_lsu_addrcheck.scala 96:33]
|
||||
node _T_37 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 98:50]
|
||||
node _T_38 = or(_T_37, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 98:57]
|
||||
node _T_39 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 98:108]
|
||||
node _T_40 = eq(_T_38, _T_39) @[el2_lsu_addrcheck.scala 98:82]
|
||||
node _T_41 = and(UInt<1>("h01"), _T_40) @[el2_lsu_addrcheck.scala 98:31]
|
||||
node _T_42 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 99:50]
|
||||
node _T_43 = or(_T_42, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 99:57]
|
||||
node _T_44 = or(UInt<32>("h0c0000000"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 99:108]
|
||||
node _T_45 = eq(_T_43, _T_44) @[el2_lsu_addrcheck.scala 99:82]
|
||||
node _T_46 = and(UInt<1>("h01"), _T_45) @[el2_lsu_addrcheck.scala 99:31]
|
||||
node _T_47 = or(_T_41, _T_46) @[el2_lsu_addrcheck.scala 98:133]
|
||||
node _T_48 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 100:50]
|
||||
node _T_49 = or(_T_48, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 100:57]
|
||||
node _T_50 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 100:108]
|
||||
node _T_51 = eq(_T_49, _T_50) @[el2_lsu_addrcheck.scala 100:82]
|
||||
node _T_52 = and(UInt<1>("h01"), _T_51) @[el2_lsu_addrcheck.scala 100:31]
|
||||
node _T_53 = or(_T_47, _T_52) @[el2_lsu_addrcheck.scala 99:133]
|
||||
node _T_54 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 101:50]
|
||||
node _T_55 = or(_T_54, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 101:57]
|
||||
node _T_56 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 101:108]
|
||||
node _T_57 = eq(_T_55, _T_56) @[el2_lsu_addrcheck.scala 101:82]
|
||||
node _T_58 = and(UInt<1>("h01"), _T_57) @[el2_lsu_addrcheck.scala 101:31]
|
||||
node _T_59 = or(_T_53, _T_58) @[el2_lsu_addrcheck.scala 100:133]
|
||||
node _T_60 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 102:50]
|
||||
node _T_61 = or(_T_60, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 102:57]
|
||||
node _T_62 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 102:108]
|
||||
node _T_63 = eq(_T_61, _T_62) @[el2_lsu_addrcheck.scala 102:82]
|
||||
node _T_64 = and(UInt<1>("h00"), _T_63) @[el2_lsu_addrcheck.scala 102:31]
|
||||
node _T_65 = or(_T_59, _T_64) @[el2_lsu_addrcheck.scala 101:133]
|
||||
node _T_66 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 103:50]
|
||||
node _T_67 = or(_T_66, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 103:57]
|
||||
node _T_68 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 103:108]
|
||||
node _T_69 = eq(_T_67, _T_68) @[el2_lsu_addrcheck.scala 103:82]
|
||||
node _T_70 = and(UInt<1>("h00"), _T_69) @[el2_lsu_addrcheck.scala 103:31]
|
||||
node _T_71 = or(_T_65, _T_70) @[el2_lsu_addrcheck.scala 102:133]
|
||||
node _T_72 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 104:50]
|
||||
node _T_73 = or(_T_72, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 104:57]
|
||||
node _T_74 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 104:108]
|
||||
node _T_75 = eq(_T_73, _T_74) @[el2_lsu_addrcheck.scala 104:82]
|
||||
node _T_76 = and(UInt<1>("h00"), _T_75) @[el2_lsu_addrcheck.scala 104:31]
|
||||
node _T_77 = or(_T_71, _T_76) @[el2_lsu_addrcheck.scala 103:133]
|
||||
node _T_78 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 105:50]
|
||||
node _T_79 = or(_T_78, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 105:57]
|
||||
node _T_80 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 105:108]
|
||||
node _T_81 = eq(_T_79, _T_80) @[el2_lsu_addrcheck.scala 105:82]
|
||||
node _T_82 = and(UInt<1>("h00"), _T_81) @[el2_lsu_addrcheck.scala 105:31]
|
||||
node _T_83 = or(_T_77, _T_82) @[el2_lsu_addrcheck.scala 104:133]
|
||||
node _T_84 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 107:49]
|
||||
node _T_85 = or(_T_84, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 107:58]
|
||||
node _T_86 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 107:109]
|
||||
node _T_87 = eq(_T_85, _T_86) @[el2_lsu_addrcheck.scala 107:83]
|
||||
node _T_88 = and(UInt<1>("h01"), _T_87) @[el2_lsu_addrcheck.scala 107:32]
|
||||
node _T_89 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 108:50]
|
||||
node _T_90 = or(_T_89, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 108:59]
|
||||
node _T_91 = or(UInt<32>("h0c0000000"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 108:110]
|
||||
node _T_92 = eq(_T_90, _T_91) @[el2_lsu_addrcheck.scala 108:84]
|
||||
node _T_93 = and(UInt<1>("h01"), _T_92) @[el2_lsu_addrcheck.scala 108:33]
|
||||
node _T_94 = or(_T_88, _T_93) @[el2_lsu_addrcheck.scala 107:134]
|
||||
node _T_95 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 109:50]
|
||||
node _T_96 = or(_T_95, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 109:59]
|
||||
node _T_97 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 109:110]
|
||||
node _T_98 = eq(_T_96, _T_97) @[el2_lsu_addrcheck.scala 109:84]
|
||||
node _T_99 = and(UInt<1>("h01"), _T_98) @[el2_lsu_addrcheck.scala 109:33]
|
||||
node _T_100 = or(_T_94, _T_99) @[el2_lsu_addrcheck.scala 108:135]
|
||||
node _T_101 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 110:50]
|
||||
node _T_102 = or(_T_101, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 110:59]
|
||||
node _T_103 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 110:110]
|
||||
node _T_104 = eq(_T_102, _T_103) @[el2_lsu_addrcheck.scala 110:84]
|
||||
node _T_105 = and(UInt<1>("h01"), _T_104) @[el2_lsu_addrcheck.scala 110:33]
|
||||
node _T_106 = or(_T_100, _T_105) @[el2_lsu_addrcheck.scala 109:135]
|
||||
node _T_107 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 111:50]
|
||||
node _T_108 = or(_T_107, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 111:59]
|
||||
node _T_109 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 111:110]
|
||||
node _T_110 = eq(_T_108, _T_109) @[el2_lsu_addrcheck.scala 111:84]
|
||||
node _T_111 = and(UInt<1>("h00"), _T_110) @[el2_lsu_addrcheck.scala 111:33]
|
||||
node _T_112 = or(_T_106, _T_111) @[el2_lsu_addrcheck.scala 110:135]
|
||||
node _T_113 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 112:50]
|
||||
node _T_114 = or(_T_113, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 112:59]
|
||||
node _T_115 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 112:110]
|
||||
node _T_116 = eq(_T_114, _T_115) @[el2_lsu_addrcheck.scala 112:84]
|
||||
node _T_117 = and(UInt<1>("h00"), _T_116) @[el2_lsu_addrcheck.scala 112:33]
|
||||
node _T_118 = or(_T_112, _T_117) @[el2_lsu_addrcheck.scala 111:135]
|
||||
node _T_119 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 113:50]
|
||||
node _T_120 = or(_T_119, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 113:59]
|
||||
node _T_121 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 113:110]
|
||||
node _T_122 = eq(_T_120, _T_121) @[el2_lsu_addrcheck.scala 113:84]
|
||||
node _T_123 = and(UInt<1>("h00"), _T_122) @[el2_lsu_addrcheck.scala 113:33]
|
||||
node _T_124 = or(_T_118, _T_123) @[el2_lsu_addrcheck.scala 112:135]
|
||||
node _T_125 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 114:50]
|
||||
node _T_126 = or(_T_125, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 114:59]
|
||||
node _T_127 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 114:110]
|
||||
node _T_128 = eq(_T_126, _T_127) @[el2_lsu_addrcheck.scala 114:84]
|
||||
node _T_129 = and(UInt<1>("h00"), _T_128) @[el2_lsu_addrcheck.scala 114:33]
|
||||
node _T_130 = or(_T_124, _T_129) @[el2_lsu_addrcheck.scala 113:135]
|
||||
node _T_131 = and(_T_83, _T_130) @[el2_lsu_addrcheck.scala 106:7]
|
||||
node non_dccm_access_ok = or(_T_36, _T_131) @[el2_lsu_addrcheck.scala 97:104]
|
||||
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[el2_lsu_addrcheck.scala 116:57]
|
||||
node _T_132 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 117:70]
|
||||
node _T_133 = neq(_T_132, UInt<2>("h00")) @[el2_lsu_addrcheck.scala 117:76]
|
||||
node _T_134 = not(io.lsu_pkt_d.word) @[el2_lsu_addrcheck.scala 117:92]
|
||||
node _T_135 = or(_T_133, _T_134) @[el2_lsu_addrcheck.scala 117:90]
|
||||
node picm_access_fault_d = and(io.addr_in_pic_d, _T_135) @[el2_lsu_addrcheck.scala 117:51]
|
||||
node _T_6 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 42:37]
|
||||
node _T_7 = eq(_T_6, UInt<4>("h0e")) @[el2_lsu_addrcheck.scala 42:45]
|
||||
addr_in_iccm <= _T_7 @[el2_lsu_addrcheck.scala 42:18]
|
||||
node _T_8 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 50:89]
|
||||
node _T_9 = bits(_T_8, 31, 28) @[el2_lib.scala 253:27]
|
||||
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[el2_lib.scala 253:49]
|
||||
wire start_addr_in_pic_d : UInt<1> @[el2_lib.scala 254:26]
|
||||
node _T_10 = bits(_T_8, 31, 15) @[el2_lib.scala 258:24]
|
||||
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[el2_lib.scala 258:39]
|
||||
start_addr_in_pic_d <= _T_11 @[el2_lib.scala 258:16]
|
||||
node _T_12 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 52:83]
|
||||
node _T_13 = bits(_T_12, 31, 28) @[el2_lib.scala 253:27]
|
||||
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[el2_lib.scala 253:49]
|
||||
wire end_addr_in_pic_d : UInt<1> @[el2_lib.scala 254:26]
|
||||
node _T_14 = bits(_T_12, 31, 15) @[el2_lib.scala 258:24]
|
||||
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[el2_lib.scala 258:39]
|
||||
end_addr_in_pic_d <= _T_15 @[el2_lib.scala 258:16]
|
||||
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 54:60]
|
||||
node _T_16 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 55:48]
|
||||
node _T_17 = eq(_T_16, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 55:54]
|
||||
node _T_18 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 55:91]
|
||||
node _T_19 = eq(_T_18, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 55:97]
|
||||
node base_reg_dccm_or_pic = or(_T_17, _T_19) @[el2_lsu_addrcheck.scala 55:73]
|
||||
node _T_20 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 56:57]
|
||||
io.addr_in_dccm_d <= _T_20 @[el2_lsu_addrcheck.scala 56:32]
|
||||
node _T_21 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 57:56]
|
||||
io.addr_in_pic_d <= _T_21 @[el2_lsu_addrcheck.scala 57:32]
|
||||
node _T_22 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 59:63]
|
||||
node _T_23 = not(_T_22) @[el2_lsu_addrcheck.scala 59:33]
|
||||
io.addr_external_d <= _T_23 @[el2_lsu_addrcheck.scala 59:30]
|
||||
node _T_24 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 60:51]
|
||||
node csr_idx = cat(_T_24, UInt<1>("h01")) @[Cat.scala 29:58]
|
||||
node _T_25 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[el2_lsu_addrcheck.scala 61:50]
|
||||
node _T_26 = bits(_T_25, 0, 0) @[el2_lsu_addrcheck.scala 61:50]
|
||||
node _T_27 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 61:92]
|
||||
node _T_28 = or(_T_27, addr_in_iccm) @[el2_lsu_addrcheck.scala 61:121]
|
||||
node _T_29 = eq(_T_28, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 61:62]
|
||||
node _T_30 = and(_T_26, _T_29) @[el2_lsu_addrcheck.scala 61:60]
|
||||
node _T_31 = and(_T_30, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 61:137]
|
||||
node _T_32 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[el2_lsu_addrcheck.scala 61:180]
|
||||
node is_sideeffects_d = and(_T_31, _T_32) @[el2_lsu_addrcheck.scala 61:158]
|
||||
node _T_33 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 62:69]
|
||||
node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:75]
|
||||
node _T_35 = and(io.lsu_pkt_d.word, _T_34) @[el2_lsu_addrcheck.scala 62:51]
|
||||
node _T_36 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 62:124]
|
||||
node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:128]
|
||||
node _T_38 = and(io.lsu_pkt_d.half, _T_37) @[el2_lsu_addrcheck.scala 62:106]
|
||||
node _T_39 = or(_T_35, _T_38) @[el2_lsu_addrcheck.scala 62:85]
|
||||
node is_aligned_d = or(_T_39, io.lsu_pkt_d.by) @[el2_lsu_addrcheck.scala 62:138]
|
||||
node _T_40 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_42 = cat(_T_41, _T_40) @[Cat.scala 29:58]
|
||||
node _T_43 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
||||
node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
||||
node _T_45 = cat(_T_44, _T_43) @[Cat.scala 29:58]
|
||||
node _T_46 = cat(_T_45, _T_42) @[Cat.scala 29:58]
|
||||
node _T_47 = orr(_T_46) @[el2_lsu_addrcheck.scala 66:87]
|
||||
node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 65:33]
|
||||
node _T_49 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 67:47]
|
||||
node _T_50 = or(_T_49, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:54]
|
||||
node _T_51 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:99]
|
||||
node _T_52 = eq(_T_50, _T_51) @[el2_lsu_addrcheck.scala 67:76]
|
||||
node _T_53 = and(UInt<1>("h01"), _T_52) @[el2_lsu_addrcheck.scala 67:28]
|
||||
node _T_54 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 68:47]
|
||||
node _T_55 = or(_T_54, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:54]
|
||||
node _T_56 = or(UInt<32>("h00"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:99]
|
||||
node _T_57 = eq(_T_55, _T_56) @[el2_lsu_addrcheck.scala 68:76]
|
||||
node _T_58 = and(UInt<1>("h01"), _T_57) @[el2_lsu_addrcheck.scala 68:28]
|
||||
node _T_59 = or(_T_53, _T_58) @[el2_lsu_addrcheck.scala 67:121]
|
||||
node _T_60 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 69:47]
|
||||
node _T_61 = or(_T_60, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:54]
|
||||
node _T_62 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:99]
|
||||
node _T_63 = eq(_T_61, _T_62) @[el2_lsu_addrcheck.scala 69:76]
|
||||
node _T_64 = and(UInt<1>("h01"), _T_63) @[el2_lsu_addrcheck.scala 69:28]
|
||||
node _T_65 = or(_T_59, _T_64) @[el2_lsu_addrcheck.scala 68:121]
|
||||
node _T_66 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 70:47]
|
||||
node _T_67 = or(_T_66, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:54]
|
||||
node _T_68 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:99]
|
||||
node _T_69 = eq(_T_67, _T_68) @[el2_lsu_addrcheck.scala 70:76]
|
||||
node _T_70 = and(UInt<1>("h01"), _T_69) @[el2_lsu_addrcheck.scala 70:28]
|
||||
node _T_71 = or(_T_65, _T_70) @[el2_lsu_addrcheck.scala 69:121]
|
||||
node _T_72 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 71:47]
|
||||
node _T_73 = or(_T_72, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:54]
|
||||
node _T_74 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:99]
|
||||
node _T_75 = eq(_T_73, _T_74) @[el2_lsu_addrcheck.scala 71:76]
|
||||
node _T_76 = and(UInt<1>("h00"), _T_75) @[el2_lsu_addrcheck.scala 71:28]
|
||||
node _T_77 = or(_T_71, _T_76) @[el2_lsu_addrcheck.scala 70:121]
|
||||
node _T_78 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 72:47]
|
||||
node _T_79 = or(_T_78, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:54]
|
||||
node _T_80 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:99]
|
||||
node _T_81 = eq(_T_79, _T_80) @[el2_lsu_addrcheck.scala 72:76]
|
||||
node _T_82 = and(UInt<1>("h00"), _T_81) @[el2_lsu_addrcheck.scala 72:28]
|
||||
node _T_83 = or(_T_77, _T_82) @[el2_lsu_addrcheck.scala 71:121]
|
||||
node _T_84 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 73:47]
|
||||
node _T_85 = or(_T_84, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:54]
|
||||
node _T_86 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:99]
|
||||
node _T_87 = eq(_T_85, _T_86) @[el2_lsu_addrcheck.scala 73:76]
|
||||
node _T_88 = and(UInt<1>("h00"), _T_87) @[el2_lsu_addrcheck.scala 73:28]
|
||||
node _T_89 = or(_T_83, _T_88) @[el2_lsu_addrcheck.scala 72:121]
|
||||
node _T_90 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 74:47]
|
||||
node _T_91 = or(_T_90, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:54]
|
||||
node _T_92 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:99]
|
||||
node _T_93 = eq(_T_91, _T_92) @[el2_lsu_addrcheck.scala 74:76]
|
||||
node _T_94 = and(UInt<1>("h00"), _T_93) @[el2_lsu_addrcheck.scala 74:28]
|
||||
node _T_95 = or(_T_89, _T_94) @[el2_lsu_addrcheck.scala 73:121]
|
||||
node _T_96 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 76:46]
|
||||
node _T_97 = or(_T_96, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:55]
|
||||
node _T_98 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:100]
|
||||
node _T_99 = eq(_T_97, _T_98) @[el2_lsu_addrcheck.scala 76:77]
|
||||
node _T_100 = and(UInt<1>("h01"), _T_99) @[el2_lsu_addrcheck.scala 76:29]
|
||||
node _T_101 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 77:47]
|
||||
node _T_102 = or(_T_101, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:56]
|
||||
node _T_103 = or(UInt<32>("h00"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:101]
|
||||
node _T_104 = eq(_T_102, _T_103) @[el2_lsu_addrcheck.scala 77:78]
|
||||
node _T_105 = and(UInt<1>("h01"), _T_104) @[el2_lsu_addrcheck.scala 77:30]
|
||||
node _T_106 = or(_T_100, _T_105) @[el2_lsu_addrcheck.scala 76:122]
|
||||
node _T_107 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 78:47]
|
||||
node _T_108 = or(_T_107, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:56]
|
||||
node _T_109 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:101]
|
||||
node _T_110 = eq(_T_108, _T_109) @[el2_lsu_addrcheck.scala 78:78]
|
||||
node _T_111 = and(UInt<1>("h01"), _T_110) @[el2_lsu_addrcheck.scala 78:30]
|
||||
node _T_112 = or(_T_106, _T_111) @[el2_lsu_addrcheck.scala 77:123]
|
||||
node _T_113 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 79:47]
|
||||
node _T_114 = or(_T_113, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:56]
|
||||
node _T_115 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:101]
|
||||
node _T_116 = eq(_T_114, _T_115) @[el2_lsu_addrcheck.scala 79:78]
|
||||
node _T_117 = and(UInt<1>("h01"), _T_116) @[el2_lsu_addrcheck.scala 79:30]
|
||||
node _T_118 = or(_T_112, _T_117) @[el2_lsu_addrcheck.scala 78:123]
|
||||
node _T_119 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 80:47]
|
||||
node _T_120 = or(_T_119, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:56]
|
||||
node _T_121 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:101]
|
||||
node _T_122 = eq(_T_120, _T_121) @[el2_lsu_addrcheck.scala 80:78]
|
||||
node _T_123 = and(UInt<1>("h00"), _T_122) @[el2_lsu_addrcheck.scala 80:30]
|
||||
node _T_124 = or(_T_118, _T_123) @[el2_lsu_addrcheck.scala 79:123]
|
||||
node _T_125 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 81:47]
|
||||
node _T_126 = or(_T_125, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:56]
|
||||
node _T_127 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:101]
|
||||
node _T_128 = eq(_T_126, _T_127) @[el2_lsu_addrcheck.scala 81:78]
|
||||
node _T_129 = and(UInt<1>("h00"), _T_128) @[el2_lsu_addrcheck.scala 81:30]
|
||||
node _T_130 = or(_T_124, _T_129) @[el2_lsu_addrcheck.scala 80:123]
|
||||
node _T_131 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 82:47]
|
||||
node _T_132 = or(_T_131, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:56]
|
||||
node _T_133 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:101]
|
||||
node _T_134 = eq(_T_132, _T_133) @[el2_lsu_addrcheck.scala 82:78]
|
||||
node _T_135 = and(UInt<1>("h00"), _T_134) @[el2_lsu_addrcheck.scala 82:30]
|
||||
node _T_136 = or(_T_130, _T_135) @[el2_lsu_addrcheck.scala 81:123]
|
||||
node _T_137 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 83:47]
|
||||
node _T_138 = or(_T_137, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:56]
|
||||
node _T_139 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:101]
|
||||
node _T_140 = eq(_T_138, _T_139) @[el2_lsu_addrcheck.scala 83:78]
|
||||
node _T_141 = and(UInt<1>("h00"), _T_140) @[el2_lsu_addrcheck.scala 83:30]
|
||||
node _T_142 = or(_T_136, _T_141) @[el2_lsu_addrcheck.scala 82:123]
|
||||
node _T_143 = and(_T_95, _T_142) @[el2_lsu_addrcheck.scala 75:7]
|
||||
node non_dccm_access_ok = or(_T_48, _T_143) @[el2_lsu_addrcheck.scala 66:92]
|
||||
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[el2_lsu_addrcheck.scala 85:57]
|
||||
node _T_144 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 86:70]
|
||||
node _T_145 = neq(_T_144, UInt<2>("h00")) @[el2_lsu_addrcheck.scala 86:76]
|
||||
node _T_146 = eq(io.lsu_pkt_d.word, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 86:92]
|
||||
node _T_147 = or(_T_145, _T_146) @[el2_lsu_addrcheck.scala 86:90]
|
||||
node picm_access_fault_d = and(io.addr_in_pic_d, _T_147) @[el2_lsu_addrcheck.scala 86:51]
|
||||
wire unmapped_access_fault_d : UInt<1>
|
||||
unmapped_access_fault_d <= UInt<1>("h01")
|
||||
wire mpu_access_fault_d : UInt<1>
|
||||
mpu_access_fault_d <= UInt<1>("h01")
|
||||
node _T_136 = or(start_addr_in_dccm_d, start_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 122:87]
|
||||
node _T_137 = not(_T_136) @[el2_lsu_addrcheck.scala 122:64]
|
||||
node _T_138 = and(start_addr_in_dccm_region_d, _T_137) @[el2_lsu_addrcheck.scala 122:62]
|
||||
node _T_139 = or(end_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 124:57]
|
||||
node _T_140 = not(_T_139) @[el2_lsu_addrcheck.scala 124:36]
|
||||
node _T_141 = and(end_addr_in_dccm_region_d, _T_140) @[el2_lsu_addrcheck.scala 124:34]
|
||||
node _T_142 = or(_T_138, _T_141) @[el2_lsu_addrcheck.scala 122:112]
|
||||
node _T_143 = and(start_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 126:29]
|
||||
node _T_144 = or(_T_142, _T_143) @[el2_lsu_addrcheck.scala 124:85]
|
||||
node _T_145 = and(start_addr_pic_rangecheck.io.in_range, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 128:29]
|
||||
node _T_146 = or(_T_144, _T_145) @[el2_lsu_addrcheck.scala 126:85]
|
||||
unmapped_access_fault_d <= _T_146 @[el2_lsu_addrcheck.scala 122:29]
|
||||
node _T_147 = not(start_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 130:33]
|
||||
node _T_148 = not(non_dccm_access_ok) @[el2_lsu_addrcheck.scala 130:64]
|
||||
node _T_149 = and(_T_147, _T_148) @[el2_lsu_addrcheck.scala 130:62]
|
||||
mpu_access_fault_d <= _T_149 @[el2_lsu_addrcheck.scala 130:29]
|
||||
node _T_150 = or(unmapped_access_fault_d, mpu_access_fault_d) @[el2_lsu_addrcheck.scala 142:49]
|
||||
node _T_151 = or(_T_150, picm_access_fault_d) @[el2_lsu_addrcheck.scala 142:70]
|
||||
node _T_152 = or(_T_151, regpred_access_fault_d) @[el2_lsu_addrcheck.scala 142:92]
|
||||
node _T_153 = and(_T_152, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 142:118]
|
||||
node _T_154 = not(io.lsu_pkt_d.dma) @[el2_lsu_addrcheck.scala 142:141]
|
||||
node _T_155 = and(_T_153, _T_154) @[el2_lsu_addrcheck.scala 142:139]
|
||||
io.access_fault_d <= _T_155 @[el2_lsu_addrcheck.scala 142:21]
|
||||
node _T_156 = bits(unmapped_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:60]
|
||||
node _T_157 = bits(mpu_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:100]
|
||||
node _T_158 = bits(regpred_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:144]
|
||||
node _T_159 = bits(picm_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:185]
|
||||
node _T_160 = mux(_T_159, UInt<4>("h06"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 143:164]
|
||||
node _T_161 = mux(_T_158, UInt<4>("h05"), _T_160) @[el2_lsu_addrcheck.scala 143:120]
|
||||
node _T_162 = mux(_T_157, UInt<4>("h03"), _T_161) @[el2_lsu_addrcheck.scala 143:80]
|
||||
node access_fault_mscause_d = mux(_T_156, UInt<4>("h02"), _T_162) @[el2_lsu_addrcheck.scala 143:35]
|
||||
node _T_163 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 144:53]
|
||||
node _T_164 = bits(io.end_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 144:78]
|
||||
node regcross_misaligned_fault_d = neq(_T_163, _T_164) @[el2_lsu_addrcheck.scala 144:61]
|
||||
node _T_165 = not(is_aligned_d) @[el2_lsu_addrcheck.scala 145:59]
|
||||
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_165) @[el2_lsu_addrcheck.scala 145:57]
|
||||
node _T_166 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[el2_lsu_addrcheck.scala 146:90]
|
||||
node _T_167 = or(regcross_misaligned_fault_d, _T_166) @[el2_lsu_addrcheck.scala 146:57]
|
||||
node _T_168 = and(_T_167, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 146:113]
|
||||
node _T_169 = not(io.lsu_pkt_d.dma) @[el2_lsu_addrcheck.scala 146:136]
|
||||
node _T_170 = and(_T_168, _T_169) @[el2_lsu_addrcheck.scala 146:134]
|
||||
io.misaligned_fault_d <= _T_170 @[el2_lsu_addrcheck.scala 146:25]
|
||||
node _T_171 = bits(sideeffect_misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 147:111]
|
||||
node _T_172 = mux(_T_171, UInt<4>("h01"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 147:80]
|
||||
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_172) @[el2_lsu_addrcheck.scala 147:39]
|
||||
node _T_173 = bits(io.misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 148:50]
|
||||
node _T_174 = bits(misaligned_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 148:84]
|
||||
node _T_175 = bits(access_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 148:113]
|
||||
node _T_176 = mux(_T_173, _T_174, _T_175) @[el2_lsu_addrcheck.scala 148:27]
|
||||
io.exc_mscause_d <= _T_176 @[el2_lsu_addrcheck.scala 148:21]
|
||||
node _T_177 = not(start_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 149:66]
|
||||
node _T_178 = and(start_addr_in_dccm_region_d, _T_177) @[el2_lsu_addrcheck.scala 149:64]
|
||||
node _T_179 = not(end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 149:120]
|
||||
node _T_180 = and(end_addr_in_dccm_region_d, _T_179) @[el2_lsu_addrcheck.scala 149:118]
|
||||
node _T_181 = or(_T_178, _T_180) @[el2_lsu_addrcheck.scala 149:88]
|
||||
node _T_182 = and(_T_181, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 149:142]
|
||||
node _T_183 = and(_T_182, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 149:163]
|
||||
io.fir_dccm_access_error_d <= _T_183 @[el2_lsu_addrcheck.scala 149:31]
|
||||
node _T_184 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 150:66]
|
||||
node _T_185 = not(_T_184) @[el2_lsu_addrcheck.scala 150:36]
|
||||
node _T_186 = and(_T_185, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 150:95]
|
||||
node _T_187 = and(_T_186, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 150:116]
|
||||
io.fir_nondccm_access_error_d <= _T_187 @[el2_lsu_addrcheck.scala 150:33]
|
||||
reg _T_188 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 152:60]
|
||||
_T_188 <= is_sideeffects_d @[el2_lsu_addrcheck.scala 152:60]
|
||||
io.is_sideeffects_m <= _T_188 @[el2_lsu_addrcheck.scala 152:50]
|
||||
node _T_148 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[el2_lsu_addrcheck.scala 91:87]
|
||||
node _T_149 = eq(_T_148, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 91:64]
|
||||
node _T_150 = and(start_addr_in_dccm_region_d, _T_149) @[el2_lsu_addrcheck.scala 91:62]
|
||||
node _T_151 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 93:57]
|
||||
node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:36]
|
||||
node _T_153 = and(end_addr_in_dccm_region_d, _T_152) @[el2_lsu_addrcheck.scala 93:34]
|
||||
node _T_154 = or(_T_150, _T_153) @[el2_lsu_addrcheck.scala 91:112]
|
||||
node _T_155 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 95:29]
|
||||
node _T_156 = or(_T_154, _T_155) @[el2_lsu_addrcheck.scala 93:85]
|
||||
node _T_157 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 97:29]
|
||||
node _T_158 = or(_T_156, _T_157) @[el2_lsu_addrcheck.scala 95:85]
|
||||
unmapped_access_fault_d <= _T_158 @[el2_lsu_addrcheck.scala 91:29]
|
||||
node _T_159 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 99:33]
|
||||
node _T_160 = eq(non_dccm_access_ok, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 99:64]
|
||||
node _T_161 = and(_T_159, _T_160) @[el2_lsu_addrcheck.scala 99:62]
|
||||
mpu_access_fault_d <= _T_161 @[el2_lsu_addrcheck.scala 99:29]
|
||||
node _T_162 = or(unmapped_access_fault_d, mpu_access_fault_d) @[el2_lsu_addrcheck.scala 111:49]
|
||||
node _T_163 = or(_T_162, picm_access_fault_d) @[el2_lsu_addrcheck.scala 111:70]
|
||||
node _T_164 = or(_T_163, regpred_access_fault_d) @[el2_lsu_addrcheck.scala 111:92]
|
||||
node _T_165 = and(_T_164, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 111:118]
|
||||
node _T_166 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 111:141]
|
||||
node _T_167 = and(_T_165, _T_166) @[el2_lsu_addrcheck.scala 111:139]
|
||||
io.access_fault_d <= _T_167 @[el2_lsu_addrcheck.scala 111:21]
|
||||
node _T_168 = bits(unmapped_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:60]
|
||||
node _T_169 = bits(mpu_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:100]
|
||||
node _T_170 = bits(regpred_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:144]
|
||||
node _T_171 = bits(picm_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:185]
|
||||
node _T_172 = mux(_T_171, UInt<4>("h06"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 112:164]
|
||||
node _T_173 = mux(_T_170, UInt<4>("h05"), _T_172) @[el2_lsu_addrcheck.scala 112:120]
|
||||
node _T_174 = mux(_T_169, UInt<4>("h03"), _T_173) @[el2_lsu_addrcheck.scala 112:80]
|
||||
node access_fault_mscause_d = mux(_T_168, UInt<4>("h02"), _T_174) @[el2_lsu_addrcheck.scala 112:35]
|
||||
node _T_175 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 113:53]
|
||||
node _T_176 = bits(io.end_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 113:78]
|
||||
node regcross_misaligned_fault_d = neq(_T_175, _T_176) @[el2_lsu_addrcheck.scala 113:61]
|
||||
node _T_177 = eq(is_aligned_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 114:59]
|
||||
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_177) @[el2_lsu_addrcheck.scala 114:57]
|
||||
node _T_178 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[el2_lsu_addrcheck.scala 115:90]
|
||||
node _T_179 = or(regcross_misaligned_fault_d, _T_178) @[el2_lsu_addrcheck.scala 115:57]
|
||||
node _T_180 = and(_T_179, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 115:113]
|
||||
node _T_181 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 115:136]
|
||||
node _T_182 = and(_T_180, _T_181) @[el2_lsu_addrcheck.scala 115:134]
|
||||
io.misaligned_fault_d <= _T_182 @[el2_lsu_addrcheck.scala 115:25]
|
||||
node _T_183 = bits(sideeffect_misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 116:111]
|
||||
node _T_184 = mux(_T_183, UInt<4>("h01"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 116:80]
|
||||
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_184) @[el2_lsu_addrcheck.scala 116:39]
|
||||
node _T_185 = bits(io.misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 117:50]
|
||||
node _T_186 = bits(misaligned_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 117:84]
|
||||
node _T_187 = bits(access_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 117:113]
|
||||
node _T_188 = mux(_T_185, _T_186, _T_187) @[el2_lsu_addrcheck.scala 117:27]
|
||||
io.exc_mscause_d <= _T_188 @[el2_lsu_addrcheck.scala 117:21]
|
||||
node _T_189 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 118:66]
|
||||
node _T_190 = and(start_addr_in_dccm_region_d, _T_189) @[el2_lsu_addrcheck.scala 118:64]
|
||||
node _T_191 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 118:120]
|
||||
node _T_192 = and(end_addr_in_dccm_region_d, _T_191) @[el2_lsu_addrcheck.scala 118:118]
|
||||
node _T_193 = or(_T_190, _T_192) @[el2_lsu_addrcheck.scala 118:88]
|
||||
node _T_194 = and(_T_193, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 118:142]
|
||||
node _T_195 = and(_T_194, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 118:163]
|
||||
io.fir_dccm_access_error_d <= _T_195 @[el2_lsu_addrcheck.scala 118:31]
|
||||
node _T_196 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 119:66]
|
||||
node _T_197 = eq(_T_196, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 119:36]
|
||||
node _T_198 = and(_T_197, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 119:95]
|
||||
node _T_199 = and(_T_198, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 119:116]
|
||||
io.fir_nondccm_access_error_d <= _T_199 @[el2_lsu_addrcheck.scala 119:33]
|
||||
reg _T_200 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 121:60]
|
||||
_T_200 <= is_sideeffects_d @[el2_lsu_addrcheck.scala 121:60]
|
||||
io.is_sideeffects_m <= _T_200 @[el2_lsu_addrcheck.scala 121:50]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,19 +1,3 @@
|
|||
module rvrangecheck(
|
||||
input [31:0] io_addr,
|
||||
output io_in_range,
|
||||
output io_in_region
|
||||
);
|
||||
assign io_in_range = io_addr[31:16] == 16'hf004; // @[beh_lib.scala 117:19]
|
||||
assign io_in_region = io_addr[31:28] == 4'hf; // @[beh_lib.scala 113:19]
|
||||
endmodule
|
||||
module rvrangecheck_2(
|
||||
input [31:0] io_addr,
|
||||
output io_in_range,
|
||||
output io_in_region
|
||||
);
|
||||
assign io_in_range = io_addr[31:15] == 17'h1e018; // @[beh_lib.scala 117:19]
|
||||
assign io_in_region = io_addr[31:28] == 4'hf; // @[beh_lib.scala 113:19]
|
||||
endmodule
|
||||
module el2_lsu_addrcheck(
|
||||
input clock,
|
||||
input reset,
|
||||
|
|
@ -50,142 +34,108 @@ module el2_lsu_addrcheck(
|
|||
`ifdef RANDOMIZE_REG_INIT
|
||||
reg [31:0] _RAND_0;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire [31:0] rvrangecheck_io_addr; // @[el2_lsu_addrcheck.scala 45:44]
|
||||
wire rvrangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 45:44]
|
||||
wire rvrangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 45:44]
|
||||
wire [31:0] rvrangecheck_1_io_addr; // @[el2_lsu_addrcheck.scala 51:44]
|
||||
wire rvrangecheck_1_io_in_range; // @[el2_lsu_addrcheck.scala 51:44]
|
||||
wire rvrangecheck_1_io_in_region; // @[el2_lsu_addrcheck.scala 51:44]
|
||||
wire [31:0] start_addr_pic_rangecheck_io_addr; // @[el2_lsu_addrcheck.scala 74:41]
|
||||
wire start_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 74:41]
|
||||
wire start_addr_pic_rangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 74:41]
|
||||
wire [31:0] end_addr_pic_rangecheck_io_addr; // @[el2_lsu_addrcheck.scala 80:39]
|
||||
wire end_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 80:39]
|
||||
wire end_addr_pic_rangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 80:39]
|
||||
wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[el2_lsu_addrcheck.scala 65:45]
|
||||
wire start_addr_in_dccm_region_d = rvrangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 48:41]
|
||||
wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_pic_rangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 85:60]
|
||||
wire _T_5 = io_rs1_region_d == 4'hf; // @[el2_lsu_addrcheck.scala 86:54]
|
||||
wire base_reg_dccm_or_pic = _T_5 | _T_5; // @[el2_lsu_addrcheck.scala 86:74]
|
||||
wire start_addr_in_dccm_d = rvrangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 47:41]
|
||||
wire end_addr_in_dccm_d = rvrangecheck_1_io_in_range; // @[el2_lsu_addrcheck.scala 53:41]
|
||||
wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[el2_lib.scala 253:49]
|
||||
wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 258:39]
|
||||
wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[el2_lib.scala 253:49]
|
||||
wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 258:39]
|
||||
wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[el2_lsu_addrcheck.scala 42:45]
|
||||
wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 258:39]
|
||||
wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 258:39]
|
||||
wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 54:60]
|
||||
wire _T_17 = io_rs1_region_d == 4'hf; // @[el2_lsu_addrcheck.scala 55:54]
|
||||
wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[el2_lsu_addrcheck.scala 55:73]
|
||||
wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_13 = io_dec_tlu_mrac_ff >> csr_idx; // @[el2_lsu_addrcheck.scala 92:50]
|
||||
wire _T_16 = start_addr_dccm_or_pic | addr_in_iccm; // @[el2_lsu_addrcheck.scala 92:121]
|
||||
wire _T_17 = ~_T_16; // @[el2_lsu_addrcheck.scala 92:62]
|
||||
wire _T_18 = _T_13[0] & _T_17; // @[el2_lsu_addrcheck.scala 92:60]
|
||||
wire _T_19 = _T_18 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 92:137]
|
||||
wire _T_20 = io_lsu_pkt_d_store | io_lsu_pkt_d_load; // @[el2_lsu_addrcheck.scala 92:180]
|
||||
wire is_sideeffects_d = _T_19 & _T_20; // @[el2_lsu_addrcheck.scala 92:158]
|
||||
wire _T_22 = io_start_addr_d[1:0] == 2'h0; // @[el2_lsu_addrcheck.scala 93:75]
|
||||
wire _T_23 = io_lsu_pkt_d_word & _T_22; // @[el2_lsu_addrcheck.scala 93:51]
|
||||
wire _T_25 = ~io_start_addr_d[0]; // @[el2_lsu_addrcheck.scala 93:128]
|
||||
wire _T_26 = io_lsu_pkt_d_half & _T_25; // @[el2_lsu_addrcheck.scala 93:106]
|
||||
wire _T_27 = _T_23 | _T_26; // @[el2_lsu_addrcheck.scala 93:85]
|
||||
wire is_aligned_d = _T_27 | io_lsu_pkt_d_by; // @[el2_lsu_addrcheck.scala 93:138]
|
||||
wire [31:0] _T_38 = io_start_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 98:57]
|
||||
wire _T_40 = _T_38 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 98:82]
|
||||
wire [31:0] _T_43 = io_start_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 99:57]
|
||||
wire _T_45 = _T_43 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 99:82]
|
||||
wire _T_47 = _T_40 | _T_45; // @[el2_lsu_addrcheck.scala 98:133]
|
||||
wire [31:0] _T_49 = io_start_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 100:57]
|
||||
wire _T_51 = _T_49 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 100:82]
|
||||
wire _T_53 = _T_47 | _T_51; // @[el2_lsu_addrcheck.scala 99:133]
|
||||
wire [31:0] _T_55 = io_start_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 101:57]
|
||||
wire _T_57 = _T_55 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 101:82]
|
||||
wire _T_59 = _T_53 | _T_57; // @[el2_lsu_addrcheck.scala 100:133]
|
||||
wire [31:0] _T_85 = io_end_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 107:58]
|
||||
wire _T_87 = _T_85 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 107:83]
|
||||
wire [31:0] _T_90 = io_end_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 108:59]
|
||||
wire _T_92 = _T_90 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 108:84]
|
||||
wire _T_94 = _T_87 | _T_92; // @[el2_lsu_addrcheck.scala 107:134]
|
||||
wire [31:0] _T_96 = io_end_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 109:59]
|
||||
wire _T_98 = _T_96 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 109:84]
|
||||
wire _T_100 = _T_94 | _T_98; // @[el2_lsu_addrcheck.scala 108:135]
|
||||
wire [31:0] _T_102 = io_end_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 110:59]
|
||||
wire _T_104 = _T_102 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 110:84]
|
||||
wire _T_106 = _T_100 | _T_104; // @[el2_lsu_addrcheck.scala 109:135]
|
||||
wire non_dccm_access_ok = _T_59 & _T_106; // @[el2_lsu_addrcheck.scala 106:7]
|
||||
wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[el2_lsu_addrcheck.scala 116:57]
|
||||
wire _T_133 = io_start_addr_d[1:0] != 2'h0; // @[el2_lsu_addrcheck.scala 117:76]
|
||||
wire _T_134 = ~io_lsu_pkt_d_word; // @[el2_lsu_addrcheck.scala 117:92]
|
||||
wire _T_135 = _T_133 | _T_134; // @[el2_lsu_addrcheck.scala 117:90]
|
||||
wire picm_access_fault_d = io_addr_in_pic_d & _T_135; // @[el2_lsu_addrcheck.scala 117:51]
|
||||
wire _T_136 = start_addr_in_dccm_d | start_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 122:87]
|
||||
wire _T_137 = ~_T_136; // @[el2_lsu_addrcheck.scala 122:64]
|
||||
wire _T_138 = start_addr_in_dccm_region_d & _T_137; // @[el2_lsu_addrcheck.scala 122:62]
|
||||
wire _T_139 = end_addr_in_dccm_d | end_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 124:57]
|
||||
wire _T_140 = ~_T_139; // @[el2_lsu_addrcheck.scala 124:36]
|
||||
wire end_addr_in_dccm_region_d = rvrangecheck_1_io_in_region; // @[el2_lsu_addrcheck.scala 54:41]
|
||||
wire _T_141 = end_addr_in_dccm_region_d & _T_140; // @[el2_lsu_addrcheck.scala 124:34]
|
||||
wire _T_142 = _T_138 | _T_141; // @[el2_lsu_addrcheck.scala 122:112]
|
||||
wire _T_143 = start_addr_in_dccm_d & end_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 126:29]
|
||||
wire _T_144 = _T_142 | _T_143; // @[el2_lsu_addrcheck.scala 124:85]
|
||||
wire _T_145 = start_addr_pic_rangecheck_io_in_range & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 128:29]
|
||||
wire unmapped_access_fault_d = _T_144 | _T_145; // @[el2_lsu_addrcheck.scala 126:85]
|
||||
wire _T_147 = ~start_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 130:33]
|
||||
wire _T_148 = ~non_dccm_access_ok; // @[el2_lsu_addrcheck.scala 130:64]
|
||||
wire mpu_access_fault_d = _T_147 & _T_148; // @[el2_lsu_addrcheck.scala 130:62]
|
||||
wire _T_150 = unmapped_access_fault_d | mpu_access_fault_d; // @[el2_lsu_addrcheck.scala 142:49]
|
||||
wire _T_151 = _T_150 | picm_access_fault_d; // @[el2_lsu_addrcheck.scala 142:70]
|
||||
wire _T_152 = _T_151 | regpred_access_fault_d; // @[el2_lsu_addrcheck.scala 142:92]
|
||||
wire _T_153 = _T_152 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 142:118]
|
||||
wire _T_154 = ~io_lsu_pkt_d_dma; // @[el2_lsu_addrcheck.scala 142:141]
|
||||
wire [3:0] _T_160 = picm_access_fault_d ? 4'h6 : 4'h0; // @[el2_lsu_addrcheck.scala 143:164]
|
||||
wire [3:0] _T_161 = regpred_access_fault_d ? 4'h5 : _T_160; // @[el2_lsu_addrcheck.scala 143:120]
|
||||
wire [3:0] _T_162 = mpu_access_fault_d ? 4'h3 : _T_161; // @[el2_lsu_addrcheck.scala 143:80]
|
||||
wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_162; // @[el2_lsu_addrcheck.scala 143:35]
|
||||
wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[el2_lsu_addrcheck.scala 144:61]
|
||||
wire _T_165 = ~is_aligned_d; // @[el2_lsu_addrcheck.scala 145:59]
|
||||
wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_165; // @[el2_lsu_addrcheck.scala 145:57]
|
||||
wire _T_166 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[el2_lsu_addrcheck.scala 146:90]
|
||||
wire _T_167 = regcross_misaligned_fault_d | _T_166; // @[el2_lsu_addrcheck.scala 146:57]
|
||||
wire _T_168 = _T_167 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 146:113]
|
||||
wire [3:0] _T_172 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[el2_lsu_addrcheck.scala 147:80]
|
||||
wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_172; // @[el2_lsu_addrcheck.scala 147:39]
|
||||
wire _T_177 = ~start_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 149:66]
|
||||
wire _T_178 = start_addr_in_dccm_region_d & _T_177; // @[el2_lsu_addrcheck.scala 149:64]
|
||||
wire _T_179 = ~end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 149:120]
|
||||
wire _T_180 = end_addr_in_dccm_region_d & _T_179; // @[el2_lsu_addrcheck.scala 149:118]
|
||||
wire _T_181 = _T_178 | _T_180; // @[el2_lsu_addrcheck.scala 149:88]
|
||||
wire _T_182 = _T_181 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 149:142]
|
||||
wire _T_184 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 150:66]
|
||||
wire _T_185 = ~_T_184; // @[el2_lsu_addrcheck.scala 150:36]
|
||||
wire _T_186 = _T_185 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 150:95]
|
||||
reg _T_188; // @[el2_lsu_addrcheck.scala 152:60]
|
||||
rvrangecheck rvrangecheck ( // @[el2_lsu_addrcheck.scala 45:44]
|
||||
.io_addr(rvrangecheck_io_addr),
|
||||
.io_in_range(rvrangecheck_io_in_range),
|
||||
.io_in_region(rvrangecheck_io_in_region)
|
||||
);
|
||||
rvrangecheck rvrangecheck_1 ( // @[el2_lsu_addrcheck.scala 51:44]
|
||||
.io_addr(rvrangecheck_1_io_addr),
|
||||
.io_in_range(rvrangecheck_1_io_in_range),
|
||||
.io_in_region(rvrangecheck_1_io_in_region)
|
||||
);
|
||||
rvrangecheck_2 start_addr_pic_rangecheck ( // @[el2_lsu_addrcheck.scala 74:41]
|
||||
.io_addr(start_addr_pic_rangecheck_io_addr),
|
||||
.io_in_range(start_addr_pic_rangecheck_io_in_range),
|
||||
.io_in_region(start_addr_pic_rangecheck_io_in_region)
|
||||
);
|
||||
rvrangecheck_2 end_addr_pic_rangecheck ( // @[el2_lsu_addrcheck.scala 80:39]
|
||||
.io_addr(end_addr_pic_rangecheck_io_addr),
|
||||
.io_in_range(end_addr_pic_rangecheck_io_in_range),
|
||||
.io_in_region(end_addr_pic_rangecheck_io_in_region)
|
||||
);
|
||||
assign io_is_sideeffects_m = _T_188; // @[el2_lsu_addrcheck.scala 152:50]
|
||||
assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 87:32]
|
||||
assign io_addr_in_pic_d = start_addr_pic_rangecheck_io_in_range & end_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 88:32]
|
||||
assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[el2_lsu_addrcheck.scala 90:30]
|
||||
assign io_access_fault_d = _T_153 & _T_154; // @[el2_lsu_addrcheck.scala 142:21]
|
||||
assign io_misaligned_fault_d = _T_168 & _T_154; // @[el2_lsu_addrcheck.scala 146:25]
|
||||
assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[el2_lsu_addrcheck.scala 148:21]
|
||||
assign io_fir_dccm_access_error_d = _T_182 & io_lsu_pkt_d_fast_int; // @[el2_lsu_addrcheck.scala 149:31]
|
||||
assign io_fir_nondccm_access_error_d = _T_186 & io_lsu_pkt_d_fast_int; // @[el2_lsu_addrcheck.scala 150:33]
|
||||
assign rvrangecheck_io_addr = io_start_addr_d; // @[el2_lsu_addrcheck.scala 46:41]
|
||||
assign rvrangecheck_1_io_addr = io_end_addr_d; // @[el2_lsu_addrcheck.scala 52:41]
|
||||
assign start_addr_pic_rangecheck_io_addr = io_start_addr_d; // @[el2_lsu_addrcheck.scala 75:37]
|
||||
assign end_addr_pic_rangecheck_io_addr = io_end_addr_d; // @[el2_lsu_addrcheck.scala 81:35]
|
||||
wire [31:0] _T_25 = io_dec_tlu_mrac_ff >> csr_idx; // @[el2_lsu_addrcheck.scala 61:50]
|
||||
wire _T_28 = start_addr_dccm_or_pic | addr_in_iccm; // @[el2_lsu_addrcheck.scala 61:121]
|
||||
wire _T_29 = ~_T_28; // @[el2_lsu_addrcheck.scala 61:62]
|
||||
wire _T_30 = _T_25[0] & _T_29; // @[el2_lsu_addrcheck.scala 61:60]
|
||||
wire _T_31 = _T_30 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 61:137]
|
||||
wire _T_32 = io_lsu_pkt_d_store | io_lsu_pkt_d_load; // @[el2_lsu_addrcheck.scala 61:180]
|
||||
wire is_sideeffects_d = _T_31 & _T_32; // @[el2_lsu_addrcheck.scala 61:158]
|
||||
wire _T_34 = io_start_addr_d[1:0] == 2'h0; // @[el2_lsu_addrcheck.scala 62:75]
|
||||
wire _T_35 = io_lsu_pkt_d_word & _T_34; // @[el2_lsu_addrcheck.scala 62:51]
|
||||
wire _T_37 = ~io_start_addr_d[0]; // @[el2_lsu_addrcheck.scala 62:128]
|
||||
wire _T_38 = io_lsu_pkt_d_half & _T_37; // @[el2_lsu_addrcheck.scala 62:106]
|
||||
wire _T_39 = _T_35 | _T_38; // @[el2_lsu_addrcheck.scala 62:85]
|
||||
wire is_aligned_d = _T_39 | io_lsu_pkt_d_by; // @[el2_lsu_addrcheck.scala 62:138]
|
||||
wire [31:0] _T_50 = io_start_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:54]
|
||||
wire _T_52 = _T_50 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:76]
|
||||
wire [31:0] _T_55 = io_start_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 68:54]
|
||||
wire _T_57 = _T_55 == 32'h3fffffff; // @[el2_lsu_addrcheck.scala 68:76]
|
||||
wire _T_59 = _T_52 | _T_57; // @[el2_lsu_addrcheck.scala 67:121]
|
||||
wire [31:0] _T_61 = io_start_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 69:54]
|
||||
wire _T_63 = _T_61 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 69:76]
|
||||
wire _T_65 = _T_59 | _T_63; // @[el2_lsu_addrcheck.scala 68:121]
|
||||
wire [31:0] _T_67 = io_start_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 70:54]
|
||||
wire _T_69 = _T_67 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 70:76]
|
||||
wire _T_71 = _T_65 | _T_69; // @[el2_lsu_addrcheck.scala 69:121]
|
||||
wire [31:0] _T_97 = io_end_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 76:55]
|
||||
wire _T_99 = _T_97 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 76:77]
|
||||
wire [31:0] _T_102 = io_end_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 77:56]
|
||||
wire _T_104 = _T_102 == 32'h3fffffff; // @[el2_lsu_addrcheck.scala 77:78]
|
||||
wire _T_106 = _T_99 | _T_104; // @[el2_lsu_addrcheck.scala 76:122]
|
||||
wire [31:0] _T_108 = io_end_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 78:56]
|
||||
wire _T_110 = _T_108 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 78:78]
|
||||
wire _T_112 = _T_106 | _T_110; // @[el2_lsu_addrcheck.scala 77:123]
|
||||
wire [31:0] _T_114 = io_end_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 79:56]
|
||||
wire _T_116 = _T_114 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 79:78]
|
||||
wire _T_118 = _T_112 | _T_116; // @[el2_lsu_addrcheck.scala 78:123]
|
||||
wire non_dccm_access_ok = _T_71 & _T_118; // @[el2_lsu_addrcheck.scala 75:7]
|
||||
wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[el2_lsu_addrcheck.scala 85:57]
|
||||
wire _T_145 = io_start_addr_d[1:0] != 2'h0; // @[el2_lsu_addrcheck.scala 86:76]
|
||||
wire _T_146 = ~io_lsu_pkt_d_word; // @[el2_lsu_addrcheck.scala 86:92]
|
||||
wire _T_147 = _T_145 | _T_146; // @[el2_lsu_addrcheck.scala 86:90]
|
||||
wire picm_access_fault_d = io_addr_in_pic_d & _T_147; // @[el2_lsu_addrcheck.scala 86:51]
|
||||
wire _T_148 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 91:87]
|
||||
wire _T_149 = ~_T_148; // @[el2_lsu_addrcheck.scala 91:64]
|
||||
wire _T_150 = start_addr_in_dccm_region_d & _T_149; // @[el2_lsu_addrcheck.scala 91:62]
|
||||
wire _T_151 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 93:57]
|
||||
wire _T_152 = ~_T_151; // @[el2_lsu_addrcheck.scala 93:36]
|
||||
wire _T_153 = end_addr_in_dccm_region_d & _T_152; // @[el2_lsu_addrcheck.scala 93:34]
|
||||
wire _T_154 = _T_150 | _T_153; // @[el2_lsu_addrcheck.scala 91:112]
|
||||
wire _T_155 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 95:29]
|
||||
wire _T_156 = _T_154 | _T_155; // @[el2_lsu_addrcheck.scala 93:85]
|
||||
wire _T_157 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 97:29]
|
||||
wire unmapped_access_fault_d = _T_156 | _T_157; // @[el2_lsu_addrcheck.scala 95:85]
|
||||
wire _T_159 = ~start_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 99:33]
|
||||
wire _T_160 = ~non_dccm_access_ok; // @[el2_lsu_addrcheck.scala 99:64]
|
||||
wire mpu_access_fault_d = _T_159 & _T_160; // @[el2_lsu_addrcheck.scala 99:62]
|
||||
wire _T_162 = unmapped_access_fault_d | mpu_access_fault_d; // @[el2_lsu_addrcheck.scala 111:49]
|
||||
wire _T_163 = _T_162 | picm_access_fault_d; // @[el2_lsu_addrcheck.scala 111:70]
|
||||
wire _T_164 = _T_163 | regpred_access_fault_d; // @[el2_lsu_addrcheck.scala 111:92]
|
||||
wire _T_165 = _T_164 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 111:118]
|
||||
wire _T_166 = ~io_lsu_pkt_d_dma; // @[el2_lsu_addrcheck.scala 111:141]
|
||||
wire [3:0] _T_172 = picm_access_fault_d ? 4'h6 : 4'h0; // @[el2_lsu_addrcheck.scala 112:164]
|
||||
wire [3:0] _T_173 = regpred_access_fault_d ? 4'h5 : _T_172; // @[el2_lsu_addrcheck.scala 112:120]
|
||||
wire [3:0] _T_174 = mpu_access_fault_d ? 4'h3 : _T_173; // @[el2_lsu_addrcheck.scala 112:80]
|
||||
wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_174; // @[el2_lsu_addrcheck.scala 112:35]
|
||||
wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[el2_lsu_addrcheck.scala 113:61]
|
||||
wire _T_177 = ~is_aligned_d; // @[el2_lsu_addrcheck.scala 114:59]
|
||||
wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_177; // @[el2_lsu_addrcheck.scala 114:57]
|
||||
wire _T_178 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[el2_lsu_addrcheck.scala 115:90]
|
||||
wire _T_179 = regcross_misaligned_fault_d | _T_178; // @[el2_lsu_addrcheck.scala 115:57]
|
||||
wire _T_180 = _T_179 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 115:113]
|
||||
wire [3:0] _T_184 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[el2_lsu_addrcheck.scala 116:80]
|
||||
wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_184; // @[el2_lsu_addrcheck.scala 116:39]
|
||||
wire _T_189 = ~start_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 118:66]
|
||||
wire _T_190 = start_addr_in_dccm_region_d & _T_189; // @[el2_lsu_addrcheck.scala 118:64]
|
||||
wire _T_191 = ~end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 118:120]
|
||||
wire _T_192 = end_addr_in_dccm_region_d & _T_191; // @[el2_lsu_addrcheck.scala 118:118]
|
||||
wire _T_193 = _T_190 | _T_192; // @[el2_lsu_addrcheck.scala 118:88]
|
||||
wire _T_194 = _T_193 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 118:142]
|
||||
wire _T_196 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 119:66]
|
||||
wire _T_197 = ~_T_196; // @[el2_lsu_addrcheck.scala 119:36]
|
||||
wire _T_198 = _T_197 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 119:95]
|
||||
reg _T_200; // @[el2_lsu_addrcheck.scala 121:60]
|
||||
assign io_is_sideeffects_m = _T_200; // @[el2_lsu_addrcheck.scala 121:50]
|
||||
assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 56:32]
|
||||
assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 57:32]
|
||||
assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[el2_lsu_addrcheck.scala 59:30]
|
||||
assign io_access_fault_d = _T_165 & _T_166; // @[el2_lsu_addrcheck.scala 111:21]
|
||||
assign io_misaligned_fault_d = _T_180 & _T_166; // @[el2_lsu_addrcheck.scala 115:25]
|
||||
assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[el2_lsu_addrcheck.scala 117:21]
|
||||
assign io_fir_dccm_access_error_d = _T_194 & io_lsu_pkt_d_fast_int; // @[el2_lsu_addrcheck.scala 118:31]
|
||||
assign io_fir_nondccm_access_error_d = _T_198 & io_lsu_pkt_d_fast_int; // @[el2_lsu_addrcheck.scala 119:33]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -222,10 +172,10 @@ initial begin
|
|||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
_RAND_0 = {1{`RANDOM}};
|
||||
_T_188 = _RAND_0[0:0];
|
||||
_T_200 = _RAND_0[0:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
if (reset) begin
|
||||
_T_188 = 1'h0;
|
||||
_T_200 = 1'h0;
|
||||
end
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
|
|
@ -235,9 +185,9 @@ end // initial
|
|||
`endif // SYNTHESIS
|
||||
always @(posedge io_lsu_c2_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_188 <= 1'h0;
|
||||
_T_200 <= 1'h0;
|
||||
end else begin
|
||||
_T_188 <= _T_19 & _T_20;
|
||||
_T_200 <= _T_31 & _T_32;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -0,0 +1,177 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_valid_m",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_full_hit_m",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_m_load",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_flush_m_up",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_m_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_trxn",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arvalid",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arready",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awvalid",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awready",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wvalid",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_valid",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_addr_any",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_tag",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_inv_r",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_commit_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_load_any",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_araddr",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awaddr"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_lo",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_misaligned",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_commit_r",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arsize",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awsize"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_buffer_full_any",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_d",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_m",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_busy",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arvalid",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awvalid",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wvalid",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arready",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awready",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_error",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_load_any",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arcache",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awcache"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_tag_m",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_hi",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_tag"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"el2_lsu_bus_buffer"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,97 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_misaligned",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_bus_read_data_m",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_store_data_r",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_by",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_word",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_half"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_inv_r",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_trxn",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_busy",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_valid_m",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_load",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_flush_m_up",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_valid",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_is_sideeffects_m",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_by",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_word",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_half",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_bus_buffer_full_any",
|
||||
"sources":[
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_d",
|
||||
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"el2_lsu_bus_intf"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -14,15 +14,15 @@ circuit el2_lsu_clkdomain :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG @[beh_lib.scala 330:26]
|
||||
inst clkhdr of TEC_RV_ICG @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_1 :
|
||||
output Q : Clock
|
||||
|
|
@ -38,15 +38,15 @@ circuit el2_lsu_clkdomain :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 330:26]
|
||||
inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_2 :
|
||||
output Q : Clock
|
||||
|
|
@ -62,15 +62,15 @@ circuit el2_lsu_clkdomain :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 330:26]
|
||||
inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_3 :
|
||||
output Q : Clock
|
||||
|
|
@ -86,15 +86,15 @@ circuit el2_lsu_clkdomain :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_3 @[beh_lib.scala 330:26]
|
||||
inst clkhdr of TEC_RV_ICG_3 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_4 :
|
||||
output Q : Clock
|
||||
|
|
@ -110,15 +110,15 @@ circuit el2_lsu_clkdomain :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_4 @[beh_lib.scala 330:26]
|
||||
inst clkhdr of TEC_RV_ICG_4 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_5 :
|
||||
output Q : Clock
|
||||
|
|
@ -134,15 +134,15 @@ circuit el2_lsu_clkdomain :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_5 @[beh_lib.scala 330:26]
|
||||
inst clkhdr of TEC_RV_ICG_5 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_6 :
|
||||
output Q : Clock
|
||||
|
|
@ -158,15 +158,15 @@ circuit el2_lsu_clkdomain :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_6 @[beh_lib.scala 330:26]
|
||||
inst clkhdr of TEC_RV_ICG_6 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_7 :
|
||||
output Q : Clock
|
||||
|
|
@ -182,15 +182,15 @@ circuit el2_lsu_clkdomain :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_7 @[beh_lib.scala 330:26]
|
||||
inst clkhdr of TEC_RV_ICG_7 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_8 :
|
||||
output Q : Clock
|
||||
|
|
@ -206,15 +206,15 @@ circuit el2_lsu_clkdomain :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_8 @[beh_lib.scala 330:26]
|
||||
inst clkhdr of TEC_RV_ICG_8 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_9 :
|
||||
output Q : Clock
|
||||
|
|
@ -230,15 +230,15 @@ circuit el2_lsu_clkdomain :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_9 @[beh_lib.scala 330:26]
|
||||
inst clkhdr of TEC_RV_ICG_9 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_10 :
|
||||
output Q : Clock
|
||||
|
|
@ -254,15 +254,15 @@ circuit el2_lsu_clkdomain :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_10 @[beh_lib.scala 330:26]
|
||||
inst clkhdr of TEC_RV_ICG_10 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_11 :
|
||||
output Q : Clock
|
||||
|
|
@ -278,153 +278,166 @@ circuit el2_lsu_clkdomain :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_11 @[beh_lib.scala 330:26]
|
||||
inst clkhdr of TEC_RV_ICG_11 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
module el2_lsu_clkdomain :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
input reset : AsyncReset
|
||||
output io : {flip free_clk : Clock, flip clk_override : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>}
|
||||
|
||||
wire lsu_c1_d_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 60:36]
|
||||
wire lsu_c1_m_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 61:36]
|
||||
wire lsu_c1_r_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 62:36]
|
||||
wire lsu_free_c1_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 63:36]
|
||||
node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[el2_lsu_clkdomain.scala 64:51]
|
||||
node lsu_c1_d_clken = or(_T, io.clk_override) @[el2_lsu_clkdomain.scala 64:70]
|
||||
node _T_1 = or(io.lsu_pkt_d.valid, lsu_c1_d_clken_q) @[el2_lsu_clkdomain.scala 65:51]
|
||||
node lsu_c1_m_clken = or(_T_1, io.clk_override) @[el2_lsu_clkdomain.scala 65:70]
|
||||
node _T_2 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 66:51]
|
||||
node lsu_c1_r_clken = or(_T_2, io.clk_override) @[el2_lsu_clkdomain.scala 66:70]
|
||||
node _T_3 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 68:47]
|
||||
node lsu_c2_m_clken = or(_T_3, io.clk_override) @[el2_lsu_clkdomain.scala 68:66]
|
||||
node _T_4 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[el2_lsu_clkdomain.scala 69:47]
|
||||
node lsu_c2_r_clken = or(_T_4, io.clk_override) @[el2_lsu_clkdomain.scala 69:66]
|
||||
node _T_5 = and(lsu_c1_m_clken, io.lsu_pkt_d.store) @[el2_lsu_clkdomain.scala 71:49]
|
||||
node lsu_store_c1_m_clken = or(_T_5, io.clk_override) @[el2_lsu_clkdomain.scala 71:71]
|
||||
node _T_6 = and(lsu_c1_r_clken, io.lsu_pkt_m.store) @[el2_lsu_clkdomain.scala 72:49]
|
||||
node lsu_store_c1_r_clken = or(_T_6, io.clk_override) @[el2_lsu_clkdomain.scala 72:71]
|
||||
node _T_7 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[el2_lsu_clkdomain.scala 73:55]
|
||||
node _T_8 = or(_T_7, io.stbuf_reqvld_flushed_any) @[el2_lsu_clkdomain.scala 73:77]
|
||||
node lsu_stbuf_c1_clken = or(_T_8, io.clk_override) @[el2_lsu_clkdomain.scala 73:107]
|
||||
node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[el2_lsu_clkdomain.scala 74:49]
|
||||
node _T_9 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 75:61]
|
||||
node _T_10 = or(_T_9, io.clk_override) @[el2_lsu_clkdomain.scala 75:79]
|
||||
node lsu_bus_obuf_c1_clken = and(_T_10, io.lsu_bus_clk_en) @[el2_lsu_clkdomain.scala 75:98]
|
||||
node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 76:32]
|
||||
node _T_12 = or(_T_11, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 76:61]
|
||||
node lsu_bus_buf_c1_clken = or(_T_12, io.clk_override) @[el2_lsu_clkdomain.scala 76:79]
|
||||
node _T_13 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[el2_lsu_clkdomain.scala 78:48]
|
||||
node _T_14 = or(_T_13, io.lsu_pkt_m.valid) @[el2_lsu_clkdomain.scala 78:69]
|
||||
node _T_15 = or(_T_14, io.lsu_pkt_r.valid) @[el2_lsu_clkdomain.scala 78:90]
|
||||
node _T_16 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 78:114]
|
||||
node _T_17 = or(_T_15, _T_16) @[el2_lsu_clkdomain.scala 78:112]
|
||||
node _T_18 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 78:145]
|
||||
node _T_19 = or(_T_17, _T_18) @[el2_lsu_clkdomain.scala 78:143]
|
||||
node lsu_free_c1_clken = or(_T_19, io.clk_override) @[el2_lsu_clkdomain.scala 78:169]
|
||||
node _T_20 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[el2_lsu_clkdomain.scala 79:50]
|
||||
node lsu_free_c2_clken = or(_T_20, io.clk_override) @[el2_lsu_clkdomain.scala 79:72]
|
||||
reg _T_21 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 82:60]
|
||||
_T_21 <= lsu_free_c1_clken @[el2_lsu_clkdomain.scala 82:60]
|
||||
lsu_free_c1_clken_q <= _T_21 @[el2_lsu_clkdomain.scala 82:26]
|
||||
reg _T_22 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 84:67]
|
||||
_T_22 <= lsu_c1_d_clken @[el2_lsu_clkdomain.scala 84:67]
|
||||
lsu_c1_d_clken_q <= _T_22 @[el2_lsu_clkdomain.scala 84:26]
|
||||
reg _T_23 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 85:67]
|
||||
_T_23 <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 85:67]
|
||||
lsu_c1_m_clken_q <= _T_23 @[el2_lsu_clkdomain.scala 85:26]
|
||||
reg _T_24 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 86:67]
|
||||
_T_24 <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 86:67]
|
||||
lsu_c1_r_clken_q <= _T_24 @[el2_lsu_clkdomain.scala 86:26]
|
||||
inst lsu_c1m_cgc of rvclkhdr @[el2_lsu_clkdomain.scala 88:35]
|
||||
lsu_c1m_cgc.clock <= clock
|
||||
lsu_c1m_cgc.reset <= reset
|
||||
lsu_c1m_cgc.io.en <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 88:77]
|
||||
io.lsu_c1_m_clk <= lsu_c1m_cgc.io.l1clk @[el2_lsu_clkdomain.scala 88:127]
|
||||
inst lsu_c1r_cgc of rvclkhdr_1 @[el2_lsu_clkdomain.scala 89:35]
|
||||
lsu_c1r_cgc.clock <= clock
|
||||
lsu_c1r_cgc.reset <= reset
|
||||
lsu_c1r_cgc.io.en <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 89:77]
|
||||
io.lsu_c1_r_clk <= lsu_c1r_cgc.io.l1clk @[el2_lsu_clkdomain.scala 89:127]
|
||||
inst lsu_c2m_cgc of rvclkhdr_2 @[el2_lsu_clkdomain.scala 90:35]
|
||||
lsu_c2m_cgc.clock <= clock
|
||||
lsu_c2m_cgc.reset <= reset
|
||||
lsu_c2m_cgc.io.en <= lsu_c2_m_clken @[el2_lsu_clkdomain.scala 90:77]
|
||||
io.lsu_c2_m_clk <= lsu_c2m_cgc.io.l1clk @[el2_lsu_clkdomain.scala 90:127]
|
||||
inst lsu_c2r_cgc of rvclkhdr_3 @[el2_lsu_clkdomain.scala 91:35]
|
||||
lsu_c2r_cgc.clock <= clock
|
||||
lsu_c2r_cgc.reset <= reset
|
||||
lsu_c2r_cgc.io.en <= lsu_c2_r_clken @[el2_lsu_clkdomain.scala 91:77]
|
||||
io.lsu_c2_r_clk <= lsu_c2r_cgc.io.l1clk @[el2_lsu_clkdomain.scala 91:127]
|
||||
inst lsu_store_c1m_cgc of rvclkhdr_4 @[el2_lsu_clkdomain.scala 92:35]
|
||||
lsu_store_c1m_cgc.clock <= clock
|
||||
lsu_store_c1m_cgc.reset <= reset
|
||||
lsu_store_c1m_cgc.io.en <= lsu_store_c1_m_clken @[el2_lsu_clkdomain.scala 92:77]
|
||||
io.lsu_store_c1_m_clk <= lsu_store_c1m_cgc.io.l1clk @[el2_lsu_clkdomain.scala 92:127]
|
||||
inst lsu_store_c1r_cgc of rvclkhdr_5 @[el2_lsu_clkdomain.scala 93:35]
|
||||
lsu_store_c1r_cgc.clock <= clock
|
||||
lsu_store_c1r_cgc.reset <= reset
|
||||
lsu_store_c1r_cgc.io.en <= lsu_store_c1_r_clken @[el2_lsu_clkdomain.scala 93:77]
|
||||
io.lsu_store_c1_r_clk <= lsu_store_c1r_cgc.io.l1clk @[el2_lsu_clkdomain.scala 93:127]
|
||||
inst lsu_stbuf_c1_cgc of rvclkhdr_6 @[el2_lsu_clkdomain.scala 94:35]
|
||||
lsu_stbuf_c1_cgc.clock <= clock
|
||||
lsu_stbuf_c1_cgc.reset <= reset
|
||||
lsu_stbuf_c1_cgc.io.en <= lsu_stbuf_c1_clken @[el2_lsu_clkdomain.scala 94:77]
|
||||
io.lsu_stbuf_c1_clk <= lsu_stbuf_c1_cgc.io.l1clk @[el2_lsu_clkdomain.scala 94:127]
|
||||
inst lsu_bus_ibuf_c1_cgc of rvclkhdr_7 @[el2_lsu_clkdomain.scala 95:35]
|
||||
lsu_bus_ibuf_c1_cgc.clock <= clock
|
||||
lsu_bus_ibuf_c1_cgc.reset <= reset
|
||||
lsu_bus_ibuf_c1_cgc.io.en <= lsu_bus_ibuf_c1_clken @[el2_lsu_clkdomain.scala 95:77]
|
||||
io.lsu_bus_ibuf_c1_clk <= lsu_bus_ibuf_c1_cgc.io.l1clk @[el2_lsu_clkdomain.scala 95:127]
|
||||
inst lsu_bus_obuf_c1_cgc of rvclkhdr_8 @[el2_lsu_clkdomain.scala 96:35]
|
||||
lsu_bus_obuf_c1_cgc.clock <= clock
|
||||
lsu_bus_obuf_c1_cgc.reset <= reset
|
||||
lsu_bus_obuf_c1_cgc.io.en <= lsu_bus_obuf_c1_clken @[el2_lsu_clkdomain.scala 96:77]
|
||||
io.lsu_bus_obuf_c1_clk <= lsu_bus_obuf_c1_cgc.io.l1clk @[el2_lsu_clkdomain.scala 96:127]
|
||||
inst lsu_bus_buf_c1_cgc of rvclkhdr_9 @[el2_lsu_clkdomain.scala 97:35]
|
||||
lsu_bus_buf_c1_cgc.clock <= clock
|
||||
lsu_bus_buf_c1_cgc.reset <= reset
|
||||
lsu_bus_buf_c1_cgc.io.en <= lsu_bus_buf_c1_clken @[el2_lsu_clkdomain.scala 97:77]
|
||||
io.lsu_bus_buf_c1_clk <= lsu_bus_buf_c1_cgc.io.l1clk @[el2_lsu_clkdomain.scala 97:127]
|
||||
inst lsu_busm_cgc of rvclkhdr_10 @[el2_lsu_clkdomain.scala 98:35]
|
||||
lsu_busm_cgc.clock <= clock
|
||||
lsu_busm_cgc.reset <= reset
|
||||
lsu_busm_cgc.io.en <= io.lsu_bus_clk_en @[el2_lsu_clkdomain.scala 98:77]
|
||||
io.lsu_busm_clk <= lsu_busm_cgc.io.l1clk @[el2_lsu_clkdomain.scala 98:127]
|
||||
inst lsu_free_cgc of rvclkhdr_11 @[el2_lsu_clkdomain.scala 99:35]
|
||||
lsu_free_cgc.clock <= clock
|
||||
lsu_free_cgc.reset <= reset
|
||||
lsu_free_cgc.io.en <= lsu_free_c2_clken @[el2_lsu_clkdomain.scala 99:77]
|
||||
io.lsu_free_c2_clk <= lsu_free_cgc.io.l1clk @[el2_lsu_clkdomain.scala 99:127]
|
||||
lsu_c1m_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 101:30]
|
||||
lsu_c1m_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 101:75]
|
||||
lsu_c1r_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 102:30]
|
||||
lsu_c1r_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 102:75]
|
||||
lsu_c2m_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 103:30]
|
||||
lsu_c2m_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 103:75]
|
||||
lsu_c2r_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 104:30]
|
||||
lsu_c2r_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 104:75]
|
||||
lsu_store_c1m_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 105:30]
|
||||
lsu_store_c1m_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 105:75]
|
||||
lsu_store_c1r_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 106:30]
|
||||
lsu_store_c1r_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 106:75]
|
||||
lsu_stbuf_c1_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 107:30]
|
||||
lsu_stbuf_c1_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 107:75]
|
||||
lsu_bus_ibuf_c1_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 108:30]
|
||||
lsu_bus_ibuf_c1_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 108:75]
|
||||
lsu_bus_obuf_c1_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 109:30]
|
||||
lsu_bus_obuf_c1_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 109:75]
|
||||
lsu_bus_buf_c1_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 110:30]
|
||||
lsu_bus_buf_c1_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 110:75]
|
||||
lsu_busm_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 111:30]
|
||||
lsu_busm_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 111:75]
|
||||
lsu_free_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 112:30]
|
||||
lsu_free_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 112:75]
|
||||
wire lsu_c1_d_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 58:37]
|
||||
wire lsu_c1_m_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 59:37]
|
||||
wire lsu_c1_r_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 60:37]
|
||||
wire lsu_free_c1_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 61:37]
|
||||
node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[el2_lsu_clkdomain.scala 63:52]
|
||||
node lsu_c1_d_clken = or(_T, io.clk_override) @[el2_lsu_clkdomain.scala 63:71]
|
||||
node _T_1 = or(io.lsu_pkt_d.valid, lsu_c1_d_clken_q) @[el2_lsu_clkdomain.scala 64:52]
|
||||
node lsu_c1_m_clken = or(_T_1, io.clk_override) @[el2_lsu_clkdomain.scala 64:71]
|
||||
node _T_2 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 65:52]
|
||||
node lsu_c1_r_clken = or(_T_2, io.clk_override) @[el2_lsu_clkdomain.scala 65:71]
|
||||
node _T_3 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 67:48]
|
||||
node lsu_c2_m_clken = or(_T_3, io.clk_override) @[el2_lsu_clkdomain.scala 67:67]
|
||||
node _T_4 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[el2_lsu_clkdomain.scala 68:48]
|
||||
node lsu_c2_r_clken = or(_T_4, io.clk_override) @[el2_lsu_clkdomain.scala 68:67]
|
||||
node _T_5 = and(lsu_c1_m_clken, io.lsu_pkt_d.store) @[el2_lsu_clkdomain.scala 70:50]
|
||||
node lsu_store_c1_m_clken = or(_T_5, io.clk_override) @[el2_lsu_clkdomain.scala 70:72]
|
||||
node _T_6 = and(lsu_c1_r_clken, io.lsu_pkt_m.store) @[el2_lsu_clkdomain.scala 71:50]
|
||||
node lsu_store_c1_r_clken = or(_T_6, io.clk_override) @[el2_lsu_clkdomain.scala 71:72]
|
||||
node _T_7 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[el2_lsu_clkdomain.scala 72:56]
|
||||
node _T_8 = or(_T_7, io.stbuf_reqvld_flushed_any) @[el2_lsu_clkdomain.scala 72:78]
|
||||
node lsu_stbuf_c1_clken = or(_T_8, io.clk_override) @[el2_lsu_clkdomain.scala 72:108]
|
||||
node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[el2_lsu_clkdomain.scala 73:50]
|
||||
node _T_9 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 74:62]
|
||||
node _T_10 = or(_T_9, io.clk_override) @[el2_lsu_clkdomain.scala 74:80]
|
||||
node lsu_bus_obuf_c1_clken = and(_T_10, io.lsu_bus_clk_en) @[el2_lsu_clkdomain.scala 74:99]
|
||||
node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 75:34]
|
||||
node _T_12 = or(_T_11, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 75:63]
|
||||
node _T_13 = or(_T_12, io.clk_override) @[el2_lsu_clkdomain.scala 75:81]
|
||||
node lsu_bus_buf_c1_clken = bits(_T_13, 0, 0) @[el2_lsu_clkdomain.scala 75:100]
|
||||
node _T_14 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[el2_lsu_clkdomain.scala 77:49]
|
||||
node _T_15 = or(_T_14, io.lsu_pkt_m.valid) @[el2_lsu_clkdomain.scala 77:70]
|
||||
node _T_16 = or(_T_15, io.lsu_pkt_r.valid) @[el2_lsu_clkdomain.scala 77:91]
|
||||
node _T_17 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:115]
|
||||
node _T_18 = or(_T_16, _T_17) @[el2_lsu_clkdomain.scala 77:113]
|
||||
node _T_19 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:146]
|
||||
node _T_20 = or(_T_18, _T_19) @[el2_lsu_clkdomain.scala 77:144]
|
||||
node lsu_free_c1_clken = or(_T_20, io.clk_override) @[el2_lsu_clkdomain.scala 77:170]
|
||||
node _T_21 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[el2_lsu_clkdomain.scala 78:51]
|
||||
node lsu_free_c2_clken = or(_T_21, io.clk_override) @[el2_lsu_clkdomain.scala 78:73]
|
||||
reg _T_22 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 81:61]
|
||||
_T_22 <= lsu_free_c1_clken @[el2_lsu_clkdomain.scala 81:61]
|
||||
lsu_free_c1_clken_q <= _T_22 @[el2_lsu_clkdomain.scala 81:27]
|
||||
reg _T_23 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 82:68]
|
||||
_T_23 <= lsu_c1_d_clken @[el2_lsu_clkdomain.scala 82:68]
|
||||
lsu_c1_d_clken_q <= _T_23 @[el2_lsu_clkdomain.scala 82:27]
|
||||
reg _T_24 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 83:68]
|
||||
_T_24 <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 83:68]
|
||||
lsu_c1_m_clken_q <= _T_24 @[el2_lsu_clkdomain.scala 83:27]
|
||||
reg _T_25 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 84:68]
|
||||
_T_25 <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 84:68]
|
||||
lsu_c1_r_clken_q <= _T_25 @[el2_lsu_clkdomain.scala 84:27]
|
||||
node _T_26 = bits(lsu_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 86:60]
|
||||
inst rvclkhdr of rvclkhdr @[beh_lib.scala 341:20]
|
||||
rvclkhdr.clock <= clock
|
||||
rvclkhdr.reset <= reset
|
||||
rvclkhdr.io.clk <= clock @[beh_lib.scala 342:15]
|
||||
rvclkhdr.io.en <= _T_26 @[beh_lib.scala 343:14]
|
||||
rvclkhdr.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
|
||||
io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[el2_lsu_clkdomain.scala 86:27]
|
||||
node _T_27 = bits(lsu_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 87:60]
|
||||
inst rvclkhdr_1 of rvclkhdr_1 @[beh_lib.scala 341:20]
|
||||
rvclkhdr_1.clock <= clock
|
||||
rvclkhdr_1.reset <= reset
|
||||
rvclkhdr_1.io.clk <= clock @[beh_lib.scala 342:15]
|
||||
rvclkhdr_1.io.en <= _T_27 @[beh_lib.scala 343:14]
|
||||
rvclkhdr_1.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
|
||||
io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[el2_lsu_clkdomain.scala 87:27]
|
||||
node _T_28 = bits(lsu_c2_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 88:60]
|
||||
inst rvclkhdr_2 of rvclkhdr_2 @[beh_lib.scala 341:20]
|
||||
rvclkhdr_2.clock <= clock
|
||||
rvclkhdr_2.reset <= reset
|
||||
rvclkhdr_2.io.clk <= clock @[beh_lib.scala 342:15]
|
||||
rvclkhdr_2.io.en <= _T_28 @[beh_lib.scala 343:14]
|
||||
rvclkhdr_2.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
|
||||
io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[el2_lsu_clkdomain.scala 88:27]
|
||||
node _T_29 = bits(lsu_c2_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 89:60]
|
||||
inst rvclkhdr_3 of rvclkhdr_3 @[beh_lib.scala 341:20]
|
||||
rvclkhdr_3.clock <= clock
|
||||
rvclkhdr_3.reset <= reset
|
||||
rvclkhdr_3.io.clk <= clock @[beh_lib.scala 342:15]
|
||||
rvclkhdr_3.io.en <= _T_29 @[beh_lib.scala 343:14]
|
||||
rvclkhdr_3.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
|
||||
io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[el2_lsu_clkdomain.scala 89:27]
|
||||
node _T_30 = bits(lsu_store_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 90:66]
|
||||
inst rvclkhdr_4 of rvclkhdr_4 @[beh_lib.scala 341:20]
|
||||
rvclkhdr_4.clock <= clock
|
||||
rvclkhdr_4.reset <= reset
|
||||
rvclkhdr_4.io.clk <= clock @[beh_lib.scala 342:15]
|
||||
rvclkhdr_4.io.en <= _T_30 @[beh_lib.scala 343:14]
|
||||
rvclkhdr_4.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
|
||||
io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[el2_lsu_clkdomain.scala 90:27]
|
||||
node _T_31 = bits(lsu_store_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 91:66]
|
||||
inst rvclkhdr_5 of rvclkhdr_5 @[beh_lib.scala 341:20]
|
||||
rvclkhdr_5.clock <= clock
|
||||
rvclkhdr_5.reset <= reset
|
||||
rvclkhdr_5.io.clk <= clock @[beh_lib.scala 342:15]
|
||||
rvclkhdr_5.io.en <= _T_31 @[beh_lib.scala 343:14]
|
||||
rvclkhdr_5.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
|
||||
io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[el2_lsu_clkdomain.scala 91:27]
|
||||
node _T_32 = bits(lsu_stbuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 92:64]
|
||||
inst rvclkhdr_6 of rvclkhdr_6 @[beh_lib.scala 341:20]
|
||||
rvclkhdr_6.clock <= clock
|
||||
rvclkhdr_6.reset <= reset
|
||||
rvclkhdr_6.io.clk <= clock @[beh_lib.scala 342:15]
|
||||
rvclkhdr_6.io.en <= _T_32 @[beh_lib.scala 343:14]
|
||||
rvclkhdr_6.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
|
||||
io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[el2_lsu_clkdomain.scala 92:27]
|
||||
node _T_33 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 93:67]
|
||||
inst rvclkhdr_7 of rvclkhdr_7 @[beh_lib.scala 341:20]
|
||||
rvclkhdr_7.clock <= clock
|
||||
rvclkhdr_7.reset <= reset
|
||||
rvclkhdr_7.io.clk <= clock @[beh_lib.scala 342:15]
|
||||
rvclkhdr_7.io.en <= _T_33 @[beh_lib.scala 343:14]
|
||||
rvclkhdr_7.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
|
||||
io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[el2_lsu_clkdomain.scala 93:27]
|
||||
node _T_34 = bits(lsu_bus_obuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 94:67]
|
||||
inst rvclkhdr_8 of rvclkhdr_8 @[beh_lib.scala 341:20]
|
||||
rvclkhdr_8.clock <= clock
|
||||
rvclkhdr_8.reset <= reset
|
||||
rvclkhdr_8.io.clk <= clock @[beh_lib.scala 342:15]
|
||||
rvclkhdr_8.io.en <= _T_34 @[beh_lib.scala 343:14]
|
||||
rvclkhdr_8.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
|
||||
io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[el2_lsu_clkdomain.scala 94:27]
|
||||
node _T_35 = bits(lsu_bus_buf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 95:66]
|
||||
inst rvclkhdr_9 of rvclkhdr_9 @[beh_lib.scala 341:20]
|
||||
rvclkhdr_9.clock <= clock
|
||||
rvclkhdr_9.reset <= reset
|
||||
rvclkhdr_9.io.clk <= clock @[beh_lib.scala 342:15]
|
||||
rvclkhdr_9.io.en <= _T_35 @[beh_lib.scala 343:14]
|
||||
rvclkhdr_9.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
|
||||
io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[el2_lsu_clkdomain.scala 95:27]
|
||||
node _T_36 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_clkdomain.scala 96:63]
|
||||
inst rvclkhdr_10 of rvclkhdr_10 @[beh_lib.scala 341:20]
|
||||
rvclkhdr_10.clock <= clock
|
||||
rvclkhdr_10.reset <= reset
|
||||
rvclkhdr_10.io.clk <= clock @[beh_lib.scala 342:15]
|
||||
rvclkhdr_10.io.en <= _T_36 @[beh_lib.scala 343:14]
|
||||
rvclkhdr_10.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
|
||||
io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[el2_lsu_clkdomain.scala 96:27]
|
||||
node _T_37 = bits(lsu_free_c2_clken, 0, 0) @[el2_lsu_clkdomain.scala 97:63]
|
||||
inst rvclkhdr_11 of rvclkhdr_11 @[beh_lib.scala 341:20]
|
||||
rvclkhdr_11.clock <= clock
|
||||
rvclkhdr_11.reset <= reset
|
||||
rvclkhdr_11.io.clk <= clock @[beh_lib.scala 342:15]
|
||||
rvclkhdr_11.io.en <= _T_37 @[beh_lib.scala 343:14]
|
||||
rvclkhdr_11.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
|
||||
io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[el2_lsu_clkdomain.scala 97:27]
|
||||
|
||||
|
|
|
|||
|
|
@ -4,20 +4,20 @@ module rvclkhdr(
|
|||
input io_en,
|
||||
input io_scan_mode
|
||||
);
|
||||
wire clkhdr_Q; // @[beh_lib.scala 330:26]
|
||||
wire clkhdr_CK; // @[beh_lib.scala 330:26]
|
||||
wire clkhdr_EN; // @[beh_lib.scala 330:26]
|
||||
wire clkhdr_SE; // @[beh_lib.scala 330:26]
|
||||
TEC_RV_ICG clkhdr ( // @[beh_lib.scala 330:26]
|
||||
wire clkhdr_Q; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_CK; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_EN; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_SE; // @[beh_lib.scala 332:24]
|
||||
TEC_RV_ICG clkhdr ( // @[beh_lib.scala 332:24]
|
||||
.Q(clkhdr_Q),
|
||||
.CK(clkhdr_CK),
|
||||
.EN(clkhdr_EN),
|
||||
.SE(clkhdr_SE)
|
||||
);
|
||||
assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 331:14]
|
||||
assign clkhdr_CK = io_clk; // @[beh_lib.scala 332:18]
|
||||
assign clkhdr_EN = io_en; // @[beh_lib.scala 333:18]
|
||||
assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 334:18]
|
||||
assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 333:12]
|
||||
assign clkhdr_CK = io_clk; // @[beh_lib.scala 334:16]
|
||||
assign clkhdr_EN = io_en; // @[beh_lib.scala 335:16]
|
||||
assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 336:16]
|
||||
endmodule
|
||||
module el2_lsu_clkdomain(
|
||||
input clock,
|
||||
|
|
@ -106,202 +106,201 @@ module el2_lsu_clkdomain(
|
|||
reg [31:0] _RAND_2;
|
||||
reg [31:0] _RAND_3;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire lsu_c1m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 88:35]
|
||||
wire lsu_c1m_cgc_io_clk; // @[el2_lsu_clkdomain.scala 88:35]
|
||||
wire lsu_c1m_cgc_io_en; // @[el2_lsu_clkdomain.scala 88:35]
|
||||
wire lsu_c1m_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 88:35]
|
||||
wire lsu_c1r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 89:35]
|
||||
wire lsu_c1r_cgc_io_clk; // @[el2_lsu_clkdomain.scala 89:35]
|
||||
wire lsu_c1r_cgc_io_en; // @[el2_lsu_clkdomain.scala 89:35]
|
||||
wire lsu_c1r_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 89:35]
|
||||
wire lsu_c2m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 90:35]
|
||||
wire lsu_c2m_cgc_io_clk; // @[el2_lsu_clkdomain.scala 90:35]
|
||||
wire lsu_c2m_cgc_io_en; // @[el2_lsu_clkdomain.scala 90:35]
|
||||
wire lsu_c2m_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 90:35]
|
||||
wire lsu_c2r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 91:35]
|
||||
wire lsu_c2r_cgc_io_clk; // @[el2_lsu_clkdomain.scala 91:35]
|
||||
wire lsu_c2r_cgc_io_en; // @[el2_lsu_clkdomain.scala 91:35]
|
||||
wire lsu_c2r_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 91:35]
|
||||
wire lsu_store_c1m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 92:35]
|
||||
wire lsu_store_c1m_cgc_io_clk; // @[el2_lsu_clkdomain.scala 92:35]
|
||||
wire lsu_store_c1m_cgc_io_en; // @[el2_lsu_clkdomain.scala 92:35]
|
||||
wire lsu_store_c1m_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 92:35]
|
||||
wire lsu_store_c1r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 93:35]
|
||||
wire lsu_store_c1r_cgc_io_clk; // @[el2_lsu_clkdomain.scala 93:35]
|
||||
wire lsu_store_c1r_cgc_io_en; // @[el2_lsu_clkdomain.scala 93:35]
|
||||
wire lsu_store_c1r_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 93:35]
|
||||
wire lsu_stbuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 94:35]
|
||||
wire lsu_stbuf_c1_cgc_io_clk; // @[el2_lsu_clkdomain.scala 94:35]
|
||||
wire lsu_stbuf_c1_cgc_io_en; // @[el2_lsu_clkdomain.scala 94:35]
|
||||
wire lsu_stbuf_c1_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 94:35]
|
||||
wire lsu_bus_ibuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 95:35]
|
||||
wire lsu_bus_ibuf_c1_cgc_io_clk; // @[el2_lsu_clkdomain.scala 95:35]
|
||||
wire lsu_bus_ibuf_c1_cgc_io_en; // @[el2_lsu_clkdomain.scala 95:35]
|
||||
wire lsu_bus_ibuf_c1_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 95:35]
|
||||
wire lsu_bus_obuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 96:35]
|
||||
wire lsu_bus_obuf_c1_cgc_io_clk; // @[el2_lsu_clkdomain.scala 96:35]
|
||||
wire lsu_bus_obuf_c1_cgc_io_en; // @[el2_lsu_clkdomain.scala 96:35]
|
||||
wire lsu_bus_obuf_c1_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 96:35]
|
||||
wire lsu_bus_buf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 97:35]
|
||||
wire lsu_bus_buf_c1_cgc_io_clk; // @[el2_lsu_clkdomain.scala 97:35]
|
||||
wire lsu_bus_buf_c1_cgc_io_en; // @[el2_lsu_clkdomain.scala 97:35]
|
||||
wire lsu_bus_buf_c1_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 97:35]
|
||||
wire lsu_busm_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 98:35]
|
||||
wire lsu_busm_cgc_io_clk; // @[el2_lsu_clkdomain.scala 98:35]
|
||||
wire lsu_busm_cgc_io_en; // @[el2_lsu_clkdomain.scala 98:35]
|
||||
wire lsu_busm_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 98:35]
|
||||
wire lsu_free_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 99:35]
|
||||
wire lsu_free_cgc_io_clk; // @[el2_lsu_clkdomain.scala 99:35]
|
||||
wire lsu_free_cgc_io_en; // @[el2_lsu_clkdomain.scala 99:35]
|
||||
wire lsu_free_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 99:35]
|
||||
wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[el2_lsu_clkdomain.scala 64:51]
|
||||
wire lsu_c1_d_clken = _T | io_clk_override; // @[el2_lsu_clkdomain.scala 64:70]
|
||||
reg lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 84:67]
|
||||
wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 65:51]
|
||||
wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 65:70]
|
||||
reg lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 85:67]
|
||||
wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 66:51]
|
||||
wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 66:70]
|
||||
wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 68:47]
|
||||
reg lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 86:67]
|
||||
wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 69:47]
|
||||
wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_store; // @[el2_lsu_clkdomain.scala 71:49]
|
||||
wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_store; // @[el2_lsu_clkdomain.scala 72:49]
|
||||
wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[el2_lsu_clkdomain.scala 73:55]
|
||||
wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[el2_lsu_clkdomain.scala 73:77]
|
||||
wire _T_9 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 75:61]
|
||||
wire _T_10 = _T_9 | io_clk_override; // @[el2_lsu_clkdomain.scala 75:79]
|
||||
wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[el2_lsu_clkdomain.scala 76:32]
|
||||
wire _T_12 = _T_11 | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 76:61]
|
||||
wire _T_13 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[el2_lsu_clkdomain.scala 78:48]
|
||||
wire _T_14 = _T_13 | io_lsu_pkt_m_valid; // @[el2_lsu_clkdomain.scala 78:69]
|
||||
wire _T_15 = _T_14 | io_lsu_pkt_r_valid; // @[el2_lsu_clkdomain.scala 78:90]
|
||||
wire _T_17 = _T_15 | _T_11; // @[el2_lsu_clkdomain.scala 78:112]
|
||||
wire _T_18 = ~io_lsu_stbuf_empty_any; // @[el2_lsu_clkdomain.scala 78:145]
|
||||
wire _T_19 = _T_17 | _T_18; // @[el2_lsu_clkdomain.scala 78:143]
|
||||
wire lsu_free_c1_clken = _T_19 | io_clk_override; // @[el2_lsu_clkdomain.scala 78:169]
|
||||
reg lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 82:60]
|
||||
wire _T_20 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 79:50]
|
||||
rvclkhdr lsu_c1m_cgc ( // @[el2_lsu_clkdomain.scala 88:35]
|
||||
.io_l1clk(lsu_c1m_cgc_io_l1clk),
|
||||
.io_clk(lsu_c1m_cgc_io_clk),
|
||||
.io_en(lsu_c1m_cgc_io_en),
|
||||
.io_scan_mode(lsu_c1m_cgc_io_scan_mode)
|
||||
wire rvclkhdr_io_l1clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_io_clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_io_en; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_1_io_clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_1_io_en; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_2_io_l1clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_2_io_clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_2_io_en; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_2_io_scan_mode; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_3_io_l1clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_3_io_clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_3_io_en; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_3_io_scan_mode; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_4_io_l1clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_4_io_clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_4_io_en; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_4_io_scan_mode; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_5_io_l1clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_5_io_clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_5_io_en; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_5_io_scan_mode; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_6_io_l1clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_6_io_clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_6_io_en; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_6_io_scan_mode; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_7_io_l1clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_7_io_clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_7_io_en; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_7_io_scan_mode; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_8_io_l1clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_8_io_clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_8_io_en; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_8_io_scan_mode; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_9_io_l1clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_9_io_clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_9_io_en; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_9_io_scan_mode; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_10_io_l1clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_10_io_clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_10_io_en; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_10_io_scan_mode; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_11_io_l1clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_11_io_clk; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_11_io_en; // @[beh_lib.scala 341:20]
|
||||
wire rvclkhdr_11_io_scan_mode; // @[beh_lib.scala 341:20]
|
||||
wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[el2_lsu_clkdomain.scala 63:52]
|
||||
reg lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 82:68]
|
||||
wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 64:52]
|
||||
wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 64:71]
|
||||
reg lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 83:68]
|
||||
wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 65:52]
|
||||
wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 65:71]
|
||||
wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 67:48]
|
||||
reg lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 84:68]
|
||||
wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 68:48]
|
||||
wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_store; // @[el2_lsu_clkdomain.scala 70:50]
|
||||
wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_store; // @[el2_lsu_clkdomain.scala 71:50]
|
||||
wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[el2_lsu_clkdomain.scala 72:56]
|
||||
wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[el2_lsu_clkdomain.scala 72:78]
|
||||
wire _T_9 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 74:62]
|
||||
wire _T_10 = _T_9 | io_clk_override; // @[el2_lsu_clkdomain.scala 74:80]
|
||||
wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[el2_lsu_clkdomain.scala 75:34]
|
||||
wire _T_12 = _T_11 | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 75:63]
|
||||
wire _T_14 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[el2_lsu_clkdomain.scala 77:49]
|
||||
wire _T_15 = _T_14 | io_lsu_pkt_m_valid; // @[el2_lsu_clkdomain.scala 77:70]
|
||||
wire _T_16 = _T_15 | io_lsu_pkt_r_valid; // @[el2_lsu_clkdomain.scala 77:91]
|
||||
wire _T_18 = _T_16 | _T_11; // @[el2_lsu_clkdomain.scala 77:113]
|
||||
wire _T_19 = ~io_lsu_stbuf_empty_any; // @[el2_lsu_clkdomain.scala 77:146]
|
||||
wire _T_20 = _T_18 | _T_19; // @[el2_lsu_clkdomain.scala 77:144]
|
||||
wire lsu_free_c1_clken = _T_20 | io_clk_override; // @[el2_lsu_clkdomain.scala 77:170]
|
||||
reg lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 81:61]
|
||||
wire _T_21 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 78:51]
|
||||
rvclkhdr rvclkhdr ( // @[beh_lib.scala 341:20]
|
||||
.io_l1clk(rvclkhdr_io_l1clk),
|
||||
.io_clk(rvclkhdr_io_clk),
|
||||
.io_en(rvclkhdr_io_en),
|
||||
.io_scan_mode(rvclkhdr_io_scan_mode)
|
||||
);
|
||||
rvclkhdr lsu_c1r_cgc ( // @[el2_lsu_clkdomain.scala 89:35]
|
||||
.io_l1clk(lsu_c1r_cgc_io_l1clk),
|
||||
.io_clk(lsu_c1r_cgc_io_clk),
|
||||
.io_en(lsu_c1r_cgc_io_en),
|
||||
.io_scan_mode(lsu_c1r_cgc_io_scan_mode)
|
||||
rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 341:20]
|
||||
.io_l1clk(rvclkhdr_1_io_l1clk),
|
||||
.io_clk(rvclkhdr_1_io_clk),
|
||||
.io_en(rvclkhdr_1_io_en),
|
||||
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
||||
);
|
||||
rvclkhdr lsu_c2m_cgc ( // @[el2_lsu_clkdomain.scala 90:35]
|
||||
.io_l1clk(lsu_c2m_cgc_io_l1clk),
|
||||
.io_clk(lsu_c2m_cgc_io_clk),
|
||||
.io_en(lsu_c2m_cgc_io_en),
|
||||
.io_scan_mode(lsu_c2m_cgc_io_scan_mode)
|
||||
rvclkhdr rvclkhdr_2 ( // @[beh_lib.scala 341:20]
|
||||
.io_l1clk(rvclkhdr_2_io_l1clk),
|
||||
.io_clk(rvclkhdr_2_io_clk),
|
||||
.io_en(rvclkhdr_2_io_en),
|
||||
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
||||
);
|
||||
rvclkhdr lsu_c2r_cgc ( // @[el2_lsu_clkdomain.scala 91:35]
|
||||
.io_l1clk(lsu_c2r_cgc_io_l1clk),
|
||||
.io_clk(lsu_c2r_cgc_io_clk),
|
||||
.io_en(lsu_c2r_cgc_io_en),
|
||||
.io_scan_mode(lsu_c2r_cgc_io_scan_mode)
|
||||
rvclkhdr rvclkhdr_3 ( // @[beh_lib.scala 341:20]
|
||||
.io_l1clk(rvclkhdr_3_io_l1clk),
|
||||
.io_clk(rvclkhdr_3_io_clk),
|
||||
.io_en(rvclkhdr_3_io_en),
|
||||
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
||||
);
|
||||
rvclkhdr lsu_store_c1m_cgc ( // @[el2_lsu_clkdomain.scala 92:35]
|
||||
.io_l1clk(lsu_store_c1m_cgc_io_l1clk),
|
||||
.io_clk(lsu_store_c1m_cgc_io_clk),
|
||||
.io_en(lsu_store_c1m_cgc_io_en),
|
||||
.io_scan_mode(lsu_store_c1m_cgc_io_scan_mode)
|
||||
rvclkhdr rvclkhdr_4 ( // @[beh_lib.scala 341:20]
|
||||
.io_l1clk(rvclkhdr_4_io_l1clk),
|
||||
.io_clk(rvclkhdr_4_io_clk),
|
||||
.io_en(rvclkhdr_4_io_en),
|
||||
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
||||
);
|
||||
rvclkhdr lsu_store_c1r_cgc ( // @[el2_lsu_clkdomain.scala 93:35]
|
||||
.io_l1clk(lsu_store_c1r_cgc_io_l1clk),
|
||||
.io_clk(lsu_store_c1r_cgc_io_clk),
|
||||
.io_en(lsu_store_c1r_cgc_io_en),
|
||||
.io_scan_mode(lsu_store_c1r_cgc_io_scan_mode)
|
||||
rvclkhdr rvclkhdr_5 ( // @[beh_lib.scala 341:20]
|
||||
.io_l1clk(rvclkhdr_5_io_l1clk),
|
||||
.io_clk(rvclkhdr_5_io_clk),
|
||||
.io_en(rvclkhdr_5_io_en),
|
||||
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
||||
);
|
||||
rvclkhdr lsu_stbuf_c1_cgc ( // @[el2_lsu_clkdomain.scala 94:35]
|
||||
.io_l1clk(lsu_stbuf_c1_cgc_io_l1clk),
|
||||
.io_clk(lsu_stbuf_c1_cgc_io_clk),
|
||||
.io_en(lsu_stbuf_c1_cgc_io_en),
|
||||
.io_scan_mode(lsu_stbuf_c1_cgc_io_scan_mode)
|
||||
rvclkhdr rvclkhdr_6 ( // @[beh_lib.scala 341:20]
|
||||
.io_l1clk(rvclkhdr_6_io_l1clk),
|
||||
.io_clk(rvclkhdr_6_io_clk),
|
||||
.io_en(rvclkhdr_6_io_en),
|
||||
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
||||
);
|
||||
rvclkhdr lsu_bus_ibuf_c1_cgc ( // @[el2_lsu_clkdomain.scala 95:35]
|
||||
.io_l1clk(lsu_bus_ibuf_c1_cgc_io_l1clk),
|
||||
.io_clk(lsu_bus_ibuf_c1_cgc_io_clk),
|
||||
.io_en(lsu_bus_ibuf_c1_cgc_io_en),
|
||||
.io_scan_mode(lsu_bus_ibuf_c1_cgc_io_scan_mode)
|
||||
rvclkhdr rvclkhdr_7 ( // @[beh_lib.scala 341:20]
|
||||
.io_l1clk(rvclkhdr_7_io_l1clk),
|
||||
.io_clk(rvclkhdr_7_io_clk),
|
||||
.io_en(rvclkhdr_7_io_en),
|
||||
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
||||
);
|
||||
rvclkhdr lsu_bus_obuf_c1_cgc ( // @[el2_lsu_clkdomain.scala 96:35]
|
||||
.io_l1clk(lsu_bus_obuf_c1_cgc_io_l1clk),
|
||||
.io_clk(lsu_bus_obuf_c1_cgc_io_clk),
|
||||
.io_en(lsu_bus_obuf_c1_cgc_io_en),
|
||||
.io_scan_mode(lsu_bus_obuf_c1_cgc_io_scan_mode)
|
||||
rvclkhdr rvclkhdr_8 ( // @[beh_lib.scala 341:20]
|
||||
.io_l1clk(rvclkhdr_8_io_l1clk),
|
||||
.io_clk(rvclkhdr_8_io_clk),
|
||||
.io_en(rvclkhdr_8_io_en),
|
||||
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
||||
);
|
||||
rvclkhdr lsu_bus_buf_c1_cgc ( // @[el2_lsu_clkdomain.scala 97:35]
|
||||
.io_l1clk(lsu_bus_buf_c1_cgc_io_l1clk),
|
||||
.io_clk(lsu_bus_buf_c1_cgc_io_clk),
|
||||
.io_en(lsu_bus_buf_c1_cgc_io_en),
|
||||
.io_scan_mode(lsu_bus_buf_c1_cgc_io_scan_mode)
|
||||
rvclkhdr rvclkhdr_9 ( // @[beh_lib.scala 341:20]
|
||||
.io_l1clk(rvclkhdr_9_io_l1clk),
|
||||
.io_clk(rvclkhdr_9_io_clk),
|
||||
.io_en(rvclkhdr_9_io_en),
|
||||
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
||||
);
|
||||
rvclkhdr lsu_busm_cgc ( // @[el2_lsu_clkdomain.scala 98:35]
|
||||
.io_l1clk(lsu_busm_cgc_io_l1clk),
|
||||
.io_clk(lsu_busm_cgc_io_clk),
|
||||
.io_en(lsu_busm_cgc_io_en),
|
||||
.io_scan_mode(lsu_busm_cgc_io_scan_mode)
|
||||
rvclkhdr rvclkhdr_10 ( // @[beh_lib.scala 341:20]
|
||||
.io_l1clk(rvclkhdr_10_io_l1clk),
|
||||
.io_clk(rvclkhdr_10_io_clk),
|
||||
.io_en(rvclkhdr_10_io_en),
|
||||
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
||||
);
|
||||
rvclkhdr lsu_free_cgc ( // @[el2_lsu_clkdomain.scala 99:35]
|
||||
.io_l1clk(lsu_free_cgc_io_l1clk),
|
||||
.io_clk(lsu_free_cgc_io_clk),
|
||||
.io_en(lsu_free_cgc_io_en),
|
||||
.io_scan_mode(lsu_free_cgc_io_scan_mode)
|
||||
rvclkhdr rvclkhdr_11 ( // @[beh_lib.scala 341:20]
|
||||
.io_l1clk(rvclkhdr_11_io_l1clk),
|
||||
.io_clk(rvclkhdr_11_io_clk),
|
||||
.io_en(rvclkhdr_11_io_en),
|
||||
.io_scan_mode(rvclkhdr_11_io_scan_mode)
|
||||
);
|
||||
assign io_lsu_c1_m_clk = lsu_c1m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 88:127]
|
||||
assign io_lsu_c1_r_clk = lsu_c1r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 89:127]
|
||||
assign io_lsu_c2_m_clk = lsu_c2m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 90:127]
|
||||
assign io_lsu_c2_r_clk = lsu_c2r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 91:127]
|
||||
assign io_lsu_store_c1_m_clk = lsu_store_c1m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 92:127]
|
||||
assign io_lsu_store_c1_r_clk = lsu_store_c1r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 93:127]
|
||||
assign io_lsu_stbuf_c1_clk = lsu_stbuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 94:127]
|
||||
assign io_lsu_bus_obuf_c1_clk = lsu_bus_obuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 96:127]
|
||||
assign io_lsu_bus_ibuf_c1_clk = lsu_bus_ibuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 95:127]
|
||||
assign io_lsu_bus_buf_c1_clk = lsu_bus_buf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 97:127]
|
||||
assign io_lsu_busm_clk = lsu_busm_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 98:127]
|
||||
assign io_lsu_free_c2_clk = lsu_free_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 99:127]
|
||||
assign lsu_c1m_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 101:30]
|
||||
assign lsu_c1m_cgc_io_en = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 88:77]
|
||||
assign lsu_c1m_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 101:75]
|
||||
assign lsu_c1r_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 102:30]
|
||||
assign lsu_c1r_cgc_io_en = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 89:77]
|
||||
assign lsu_c1r_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 102:75]
|
||||
assign lsu_c2m_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 103:30]
|
||||
assign lsu_c2m_cgc_io_en = _T_3 | io_clk_override; // @[el2_lsu_clkdomain.scala 90:77]
|
||||
assign lsu_c2m_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 103:75]
|
||||
assign lsu_c2r_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 104:30]
|
||||
assign lsu_c2r_cgc_io_en = _T_4 | io_clk_override; // @[el2_lsu_clkdomain.scala 91:77]
|
||||
assign lsu_c2r_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 104:75]
|
||||
assign lsu_store_c1m_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 105:30]
|
||||
assign lsu_store_c1m_cgc_io_en = _T_5 | io_clk_override; // @[el2_lsu_clkdomain.scala 92:77]
|
||||
assign lsu_store_c1m_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 105:75]
|
||||
assign lsu_store_c1r_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 106:30]
|
||||
assign lsu_store_c1r_cgc_io_en = _T_6 | io_clk_override; // @[el2_lsu_clkdomain.scala 93:77]
|
||||
assign lsu_store_c1r_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 106:75]
|
||||
assign lsu_stbuf_c1_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 107:30]
|
||||
assign lsu_stbuf_c1_cgc_io_en = _T_8 | io_clk_override; // @[el2_lsu_clkdomain.scala 94:77]
|
||||
assign lsu_stbuf_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 107:75]
|
||||
assign lsu_bus_ibuf_c1_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 108:30]
|
||||
assign lsu_bus_ibuf_c1_cgc_io_en = io_lsu_busreq_r | io_clk_override; // @[el2_lsu_clkdomain.scala 95:77]
|
||||
assign lsu_bus_ibuf_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 108:75]
|
||||
assign lsu_bus_obuf_c1_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 109:30]
|
||||
assign lsu_bus_obuf_c1_cgc_io_en = _T_10 & io_lsu_bus_clk_en; // @[el2_lsu_clkdomain.scala 96:77]
|
||||
assign lsu_bus_obuf_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 109:75]
|
||||
assign lsu_bus_buf_c1_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 110:30]
|
||||
assign lsu_bus_buf_c1_cgc_io_en = _T_12 | io_clk_override; // @[el2_lsu_clkdomain.scala 97:77]
|
||||
assign lsu_bus_buf_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 110:75]
|
||||
assign lsu_busm_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 111:30]
|
||||
assign lsu_busm_cgc_io_en = io_lsu_bus_clk_en; // @[el2_lsu_clkdomain.scala 98:77]
|
||||
assign lsu_busm_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 111:75]
|
||||
assign lsu_free_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 112:30]
|
||||
assign lsu_free_cgc_io_en = _T_20 | io_clk_override; // @[el2_lsu_clkdomain.scala 99:77]
|
||||
assign lsu_free_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 112:75]
|
||||
assign io_lsu_c1_m_clk = rvclkhdr_io_l1clk; // @[el2_lsu_clkdomain.scala 86:27]
|
||||
assign io_lsu_c1_r_clk = rvclkhdr_1_io_l1clk; // @[el2_lsu_clkdomain.scala 87:27]
|
||||
assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[el2_lsu_clkdomain.scala 88:27]
|
||||
assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[el2_lsu_clkdomain.scala 89:27]
|
||||
assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[el2_lsu_clkdomain.scala 90:27]
|
||||
assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[el2_lsu_clkdomain.scala 91:27]
|
||||
assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[el2_lsu_clkdomain.scala 92:27]
|
||||
assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[el2_lsu_clkdomain.scala 94:27]
|
||||
assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[el2_lsu_clkdomain.scala 93:27]
|
||||
assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[el2_lsu_clkdomain.scala 95:27]
|
||||
assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[el2_lsu_clkdomain.scala 96:27]
|
||||
assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[el2_lsu_clkdomain.scala 97:27]
|
||||
assign rvclkhdr_io_clk = clock; // @[beh_lib.scala 342:15]
|
||||
assign rvclkhdr_io_en = _T_1 | io_clk_override; // @[beh_lib.scala 343:14]
|
||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[beh_lib.scala 342:15]
|
||||
assign rvclkhdr_1_io_en = _T_2 | io_clk_override; // @[beh_lib.scala 343:14]
|
||||
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
|
||||
assign rvclkhdr_2_io_clk = clock; // @[beh_lib.scala 342:15]
|
||||
assign rvclkhdr_2_io_en = _T_3 | io_clk_override; // @[beh_lib.scala 343:14]
|
||||
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
|
||||
assign rvclkhdr_3_io_clk = clock; // @[beh_lib.scala 342:15]
|
||||
assign rvclkhdr_3_io_en = _T_4 | io_clk_override; // @[beh_lib.scala 343:14]
|
||||
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
|
||||
assign rvclkhdr_4_io_clk = clock; // @[beh_lib.scala 342:15]
|
||||
assign rvclkhdr_4_io_en = _T_5 | io_clk_override; // @[beh_lib.scala 343:14]
|
||||
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
|
||||
assign rvclkhdr_5_io_clk = clock; // @[beh_lib.scala 342:15]
|
||||
assign rvclkhdr_5_io_en = _T_6 | io_clk_override; // @[beh_lib.scala 343:14]
|
||||
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
|
||||
assign rvclkhdr_6_io_clk = clock; // @[beh_lib.scala 342:15]
|
||||
assign rvclkhdr_6_io_en = _T_8 | io_clk_override; // @[beh_lib.scala 343:14]
|
||||
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
|
||||
assign rvclkhdr_7_io_clk = clock; // @[beh_lib.scala 342:15]
|
||||
assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[beh_lib.scala 343:14]
|
||||
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
|
||||
assign rvclkhdr_8_io_clk = clock; // @[beh_lib.scala 342:15]
|
||||
assign rvclkhdr_8_io_en = _T_10 & io_lsu_bus_clk_en; // @[beh_lib.scala 343:14]
|
||||
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
|
||||
assign rvclkhdr_9_io_clk = clock; // @[beh_lib.scala 342:15]
|
||||
assign rvclkhdr_9_io_en = _T_12 | io_clk_override; // @[beh_lib.scala 343:14]
|
||||
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
|
||||
assign rvclkhdr_10_io_clk = clock; // @[beh_lib.scala 342:15]
|
||||
assign rvclkhdr_10_io_en = io_lsu_bus_clk_en; // @[beh_lib.scala 343:14]
|
||||
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
|
||||
assign rvclkhdr_11_io_clk = clock; // @[beh_lib.scala 342:15]
|
||||
assign rvclkhdr_11_io_en = _T_21 | io_clk_override; // @[beh_lib.scala 343:14]
|
||||
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -346,34 +345,50 @@ initial begin
|
|||
_RAND_3 = {1{`RANDOM}};
|
||||
lsu_free_c1_clken_q = _RAND_3[0:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
if (reset) begin
|
||||
lsu_c1_d_clken_q = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
lsu_c1_m_clken_q = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
lsu_c1_r_clken_q = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
lsu_free_c1_clken_q = 1'h0;
|
||||
end
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
`ifdef FIRRTL_AFTER_INITIAL
|
||||
`FIRRTL_AFTER_INITIAL
|
||||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge io_lsu_free_c2_clk) begin
|
||||
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
lsu_c1_d_clken_q <= 1'h0;
|
||||
end else begin
|
||||
lsu_c1_d_clken_q <= lsu_c1_d_clken;
|
||||
lsu_c1_d_clken_q <= _T | io_clk_override;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
lsu_c1_m_clken_q <= 1'h0;
|
||||
end else begin
|
||||
lsu_c1_m_clken_q <= lsu_c1_m_clken;
|
||||
lsu_c1_m_clken_q <= _T_1 | io_clk_override;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
lsu_c1_r_clken_q <= 1'h0;
|
||||
end else begin
|
||||
lsu_c1_r_clken_q <= lsu_c1_r_clken;
|
||||
lsu_c1_r_clken_q <= _T_2 | io_clk_override;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_clk) begin
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
lsu_free_c1_clken_q <= 1'h0;
|
||||
end else begin
|
||||
lsu_free_c1_clken_q <= lsu_free_c1_clken;
|
||||
lsu_free_c1_clken_q <= _T_20 | io_clk_override;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
2784
el2_lsu_dccm_ctl.fir
2784
el2_lsu_dccm_ctl.fir
File diff suppressed because it is too large
Load Diff
1265
el2_lsu_dccm_ctl.v
1265
el2_lsu_dccm_ctl.v
File diff suppressed because it is too large
Load Diff
|
|
@ -328,6 +328,11 @@
|
|||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"el2_lsu_ecc.TEC_RV_ICG",
|
||||
"resourceId":"/vsrc/TEC_RV_ICG.v"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
|
|
|
|||
3132
el2_lsu_ecc.fir
3132
el2_lsu_ecc.fir
File diff suppressed because it is too large
Load Diff
447
el2_lsu_ecc.v
447
el2_lsu_ecc.v
|
|
@ -1,3 +1,24 @@
|
|||
module rvclkhdr(
|
||||
output io_l1clk,
|
||||
input io_clk,
|
||||
input io_en,
|
||||
input io_scan_mode
|
||||
);
|
||||
wire clkhdr_Q; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_CK; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_EN; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_SE; // @[beh_lib.scala 332:24]
|
||||
TEC_RV_ICG clkhdr ( // @[beh_lib.scala 332:24]
|
||||
.Q(clkhdr_Q),
|
||||
.CK(clkhdr_CK),
|
||||
.EN(clkhdr_EN),
|
||||
.SE(clkhdr_SE)
|
||||
);
|
||||
assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 333:12]
|
||||
assign clkhdr_CK = io_clk; // @[beh_lib.scala 334:16]
|
||||
assign clkhdr_EN = io_en; // @[beh_lib.scala 335:16]
|
||||
assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 336:16]
|
||||
endmodule
|
||||
module el2_lsu_ecc(
|
||||
input clock,
|
||||
input reset,
|
||||
|
|
@ -80,34 +101,42 @@ module el2_lsu_ecc(
|
|||
reg [31:0] _RAND_6;
|
||||
reg [31:0] _RAND_7;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire _T_96 = ^io_dccm_rdata_hi_m; // @[el2_lib.scala 329:30]
|
||||
wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[el2_lib.scala 329:44]
|
||||
wire _T_98 = _T_96 ^ _T_97; // @[el2_lib.scala 329:35]
|
||||
wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[el2_lib.scala 329:78]
|
||||
wire _T_107 = ^_T_106; // @[el2_lib.scala 329:85]
|
||||
wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[el2_lib.scala 329:72]
|
||||
wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[el2_lib.scala 329:108]
|
||||
wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[el2_lib.scala 329:108]
|
||||
wire _T_124 = ^_T_123; // @[el2_lib.scala 329:115]
|
||||
wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[el2_lib.scala 329:102]
|
||||
wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[el2_lib.scala 329:138]
|
||||
wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[el2_lib.scala 329:138]
|
||||
wire _T_141 = ^_T_140; // @[el2_lib.scala 329:145]
|
||||
wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[el2_lib.scala 329:132]
|
||||
wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[el2_lib.scala 329:168]
|
||||
wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[el2_lib.scala 329:168]
|
||||
wire _T_161 = ^_T_160; // @[el2_lib.scala 329:175]
|
||||
wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[el2_lib.scala 329:162]
|
||||
wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 329:198]
|
||||
wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[el2_lib.scala 329:198]
|
||||
wire _T_181 = ^_T_180; // @[el2_lib.scala 329:205]
|
||||
wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[el2_lib.scala 329:192]
|
||||
wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 329:228]
|
||||
wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[el2_lib.scala 329:228]
|
||||
wire _T_201 = ^_T_200; // @[el2_lib.scala 329:235]
|
||||
wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[el2_lib.scala 329:222]
|
||||
wire rvclkhdr_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire _T_96 = ^io_dccm_rdata_hi_m; // @[el2_lib.scala 324:30]
|
||||
wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[el2_lib.scala 324:44]
|
||||
wire _T_98 = _T_96 ^ _T_97; // @[el2_lib.scala 324:35]
|
||||
wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[el2_lib.scala 324:76]
|
||||
wire _T_107 = ^_T_106; // @[el2_lib.scala 324:83]
|
||||
wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[el2_lib.scala 324:71]
|
||||
wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[el2_lib.scala 324:103]
|
||||
wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[el2_lib.scala 324:103]
|
||||
wire _T_124 = ^_T_123; // @[el2_lib.scala 324:110]
|
||||
wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[el2_lib.scala 324:98]
|
||||
wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[el2_lib.scala 324:130]
|
||||
wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[el2_lib.scala 324:130]
|
||||
wire _T_141 = ^_T_140; // @[el2_lib.scala 324:137]
|
||||
wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[el2_lib.scala 324:125]
|
||||
wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[el2_lib.scala 324:157]
|
||||
wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[el2_lib.scala 324:157]
|
||||
wire _T_161 = ^_T_160; // @[el2_lib.scala 324:164]
|
||||
wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[el2_lib.scala 324:152]
|
||||
wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 324:184]
|
||||
wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[el2_lib.scala 324:184]
|
||||
wire _T_181 = ^_T_180; // @[el2_lib.scala 324:191]
|
||||
wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[el2_lib.scala 324:179]
|
||||
wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 324:211]
|
||||
wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[el2_lib.scala 324:211]
|
||||
wire _T_201 = ^_T_200; // @[el2_lib.scala 324:218]
|
||||
wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[el2_lib.scala 324:206]
|
||||
wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58]
|
||||
wire _T_209 = _T_208 != 7'h0; // @[el2_lib.scala 330:44]
|
||||
wire _T_209 = _T_208 != 7'h0; // @[el2_lib.scala 325:44]
|
||||
wire _T_1155 = ~io_dec_tlu_core_ecc_disable; // @[el2_lsu_ecc.scala 107:70]
|
||||
wire _T_1162 = io_lsu_pkt_m_load | io_lsu_pkt_m_store; // @[el2_lsu_ecc.scala 125:60]
|
||||
wire _T_1163 = io_lsu_pkt_m_valid & _T_1162; // @[el2_lsu_ecc.scala 125:39]
|
||||
|
|
@ -117,197 +146,209 @@ module el2_lsu_ecc(
|
|||
wire _T_1168 = ldst_dual_m | io_lsu_pkt_m_dma; // @[el2_lsu_ecc.scala 127:48]
|
||||
wire _T_1169 = is_ldst_m & _T_1168; // @[el2_lsu_ecc.scala 127:33]
|
||||
wire is_ldst_hi_m = _T_1169 & _T_1155; // @[el2_lsu_ecc.scala 127:68]
|
||||
wire _T_210 = is_ldst_hi_m & _T_209; // @[el2_lib.scala 330:31]
|
||||
wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[el2_lib.scala 330:53]
|
||||
wire _T_215 = ~_T_208[6]; // @[el2_lib.scala 331:55]
|
||||
wire double_ecc_error_hi_any = _T_210 & _T_215; // @[el2_lib.scala 331:53]
|
||||
wire _T_218 = _T_208[5:0] == 6'h1; // @[el2_lib.scala 335:44]
|
||||
wire _T_220 = _T_208[5:0] == 6'h2; // @[el2_lib.scala 335:44]
|
||||
wire _T_222 = _T_208[5:0] == 6'h3; // @[el2_lib.scala 335:44]
|
||||
wire _T_224 = _T_208[5:0] == 6'h4; // @[el2_lib.scala 335:44]
|
||||
wire _T_226 = _T_208[5:0] == 6'h5; // @[el2_lib.scala 335:44]
|
||||
wire _T_228 = _T_208[5:0] == 6'h6; // @[el2_lib.scala 335:44]
|
||||
wire _T_230 = _T_208[5:0] == 6'h7; // @[el2_lib.scala 335:44]
|
||||
wire _T_232 = _T_208[5:0] == 6'h8; // @[el2_lib.scala 335:44]
|
||||
wire _T_234 = _T_208[5:0] == 6'h9; // @[el2_lib.scala 335:44]
|
||||
wire _T_236 = _T_208[5:0] == 6'ha; // @[el2_lib.scala 335:44]
|
||||
wire _T_238 = _T_208[5:0] == 6'hb; // @[el2_lib.scala 335:44]
|
||||
wire _T_240 = _T_208[5:0] == 6'hc; // @[el2_lib.scala 335:44]
|
||||
wire _T_242 = _T_208[5:0] == 6'hd; // @[el2_lib.scala 335:44]
|
||||
wire _T_244 = _T_208[5:0] == 6'he; // @[el2_lib.scala 335:44]
|
||||
wire _T_246 = _T_208[5:0] == 6'hf; // @[el2_lib.scala 335:44]
|
||||
wire _T_248 = _T_208[5:0] == 6'h10; // @[el2_lib.scala 335:44]
|
||||
wire _T_250 = _T_208[5:0] == 6'h11; // @[el2_lib.scala 335:44]
|
||||
wire _T_252 = _T_208[5:0] == 6'h12; // @[el2_lib.scala 335:44]
|
||||
wire _T_254 = _T_208[5:0] == 6'h13; // @[el2_lib.scala 335:44]
|
||||
wire _T_256 = _T_208[5:0] == 6'h14; // @[el2_lib.scala 335:44]
|
||||
wire _T_258 = _T_208[5:0] == 6'h15; // @[el2_lib.scala 335:44]
|
||||
wire _T_260 = _T_208[5:0] == 6'h16; // @[el2_lib.scala 335:44]
|
||||
wire _T_262 = _T_208[5:0] == 6'h17; // @[el2_lib.scala 335:44]
|
||||
wire _T_264 = _T_208[5:0] == 6'h18; // @[el2_lib.scala 335:44]
|
||||
wire _T_266 = _T_208[5:0] == 6'h19; // @[el2_lib.scala 335:44]
|
||||
wire _T_268 = _T_208[5:0] == 6'h1a; // @[el2_lib.scala 335:44]
|
||||
wire _T_270 = _T_208[5:0] == 6'h1b; // @[el2_lib.scala 335:44]
|
||||
wire _T_272 = _T_208[5:0] == 6'h1c; // @[el2_lib.scala 335:44]
|
||||
wire _T_274 = _T_208[5:0] == 6'h1d; // @[el2_lib.scala 335:44]
|
||||
wire _T_276 = _T_208[5:0] == 6'h1e; // @[el2_lib.scala 335:44]
|
||||
wire _T_278 = _T_208[5:0] == 6'h1f; // @[el2_lib.scala 335:44]
|
||||
wire _T_280 = _T_208[5:0] == 6'h20; // @[el2_lib.scala 335:44]
|
||||
wire _T_282 = _T_208[5:0] == 6'h21; // @[el2_lib.scala 335:44]
|
||||
wire _T_284 = _T_208[5:0] == 6'h22; // @[el2_lib.scala 335:44]
|
||||
wire _T_286 = _T_208[5:0] == 6'h23; // @[el2_lib.scala 335:44]
|
||||
wire _T_288 = _T_208[5:0] == 6'h24; // @[el2_lib.scala 335:44]
|
||||
wire _T_290 = _T_208[5:0] == 6'h25; // @[el2_lib.scala 335:44]
|
||||
wire _T_292 = _T_208[5:0] == 6'h26; // @[el2_lib.scala 335:44]
|
||||
wire _T_294 = _T_208[5:0] == 6'h27; // @[el2_lib.scala 335:44]
|
||||
wire _T_210 = is_ldst_hi_m & _T_209; // @[el2_lib.scala 325:32]
|
||||
wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[el2_lib.scala 325:53]
|
||||
wire _T_215 = ~_T_208[6]; // @[el2_lib.scala 326:55]
|
||||
wire double_ecc_error_hi_any = _T_210 & _T_215; // @[el2_lib.scala 326:53]
|
||||
wire _T_218 = _T_208[5:0] == 6'h1; // @[el2_lib.scala 330:41]
|
||||
wire _T_220 = _T_208[5:0] == 6'h2; // @[el2_lib.scala 330:41]
|
||||
wire _T_222 = _T_208[5:0] == 6'h3; // @[el2_lib.scala 330:41]
|
||||
wire _T_224 = _T_208[5:0] == 6'h4; // @[el2_lib.scala 330:41]
|
||||
wire _T_226 = _T_208[5:0] == 6'h5; // @[el2_lib.scala 330:41]
|
||||
wire _T_228 = _T_208[5:0] == 6'h6; // @[el2_lib.scala 330:41]
|
||||
wire _T_230 = _T_208[5:0] == 6'h7; // @[el2_lib.scala 330:41]
|
||||
wire _T_232 = _T_208[5:0] == 6'h8; // @[el2_lib.scala 330:41]
|
||||
wire _T_234 = _T_208[5:0] == 6'h9; // @[el2_lib.scala 330:41]
|
||||
wire _T_236 = _T_208[5:0] == 6'ha; // @[el2_lib.scala 330:41]
|
||||
wire _T_238 = _T_208[5:0] == 6'hb; // @[el2_lib.scala 330:41]
|
||||
wire _T_240 = _T_208[5:0] == 6'hc; // @[el2_lib.scala 330:41]
|
||||
wire _T_242 = _T_208[5:0] == 6'hd; // @[el2_lib.scala 330:41]
|
||||
wire _T_244 = _T_208[5:0] == 6'he; // @[el2_lib.scala 330:41]
|
||||
wire _T_246 = _T_208[5:0] == 6'hf; // @[el2_lib.scala 330:41]
|
||||
wire _T_248 = _T_208[5:0] == 6'h10; // @[el2_lib.scala 330:41]
|
||||
wire _T_250 = _T_208[5:0] == 6'h11; // @[el2_lib.scala 330:41]
|
||||
wire _T_252 = _T_208[5:0] == 6'h12; // @[el2_lib.scala 330:41]
|
||||
wire _T_254 = _T_208[5:0] == 6'h13; // @[el2_lib.scala 330:41]
|
||||
wire _T_256 = _T_208[5:0] == 6'h14; // @[el2_lib.scala 330:41]
|
||||
wire _T_258 = _T_208[5:0] == 6'h15; // @[el2_lib.scala 330:41]
|
||||
wire _T_260 = _T_208[5:0] == 6'h16; // @[el2_lib.scala 330:41]
|
||||
wire _T_262 = _T_208[5:0] == 6'h17; // @[el2_lib.scala 330:41]
|
||||
wire _T_264 = _T_208[5:0] == 6'h18; // @[el2_lib.scala 330:41]
|
||||
wire _T_266 = _T_208[5:0] == 6'h19; // @[el2_lib.scala 330:41]
|
||||
wire _T_268 = _T_208[5:0] == 6'h1a; // @[el2_lib.scala 330:41]
|
||||
wire _T_270 = _T_208[5:0] == 6'h1b; // @[el2_lib.scala 330:41]
|
||||
wire _T_272 = _T_208[5:0] == 6'h1c; // @[el2_lib.scala 330:41]
|
||||
wire _T_274 = _T_208[5:0] == 6'h1d; // @[el2_lib.scala 330:41]
|
||||
wire _T_276 = _T_208[5:0] == 6'h1e; // @[el2_lib.scala 330:41]
|
||||
wire _T_278 = _T_208[5:0] == 6'h1f; // @[el2_lib.scala 330:41]
|
||||
wire _T_280 = _T_208[5:0] == 6'h20; // @[el2_lib.scala 330:41]
|
||||
wire _T_282 = _T_208[5:0] == 6'h21; // @[el2_lib.scala 330:41]
|
||||
wire _T_284 = _T_208[5:0] == 6'h22; // @[el2_lib.scala 330:41]
|
||||
wire _T_286 = _T_208[5:0] == 6'h23; // @[el2_lib.scala 330:41]
|
||||
wire _T_288 = _T_208[5:0] == 6'h24; // @[el2_lib.scala 330:41]
|
||||
wire _T_290 = _T_208[5:0] == 6'h25; // @[el2_lib.scala 330:41]
|
||||
wire _T_292 = _T_208[5:0] == 6'h26; // @[el2_lib.scala 330:41]
|
||||
wire _T_294 = _T_208[5:0] == 6'h27; // @[el2_lib.scala 330:41]
|
||||
wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58]
|
||||
wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[el2_lib.scala 338:69]
|
||||
wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[el2_lib.scala 338:69]
|
||||
wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[el2_lib.scala 338:69]
|
||||
wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[el2_lib.scala 338:69]
|
||||
wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[el2_lib.scala 338:69]
|
||||
wire [38:0] _T_355 = _T_354 ^ _T_315; // @[el2_lib.scala 338:76]
|
||||
wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[el2_lib.scala 338:31]
|
||||
wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[el2_lib.scala 333:69]
|
||||
wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[el2_lib.scala 333:69]
|
||||
wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[el2_lib.scala 333:69]
|
||||
wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[el2_lib.scala 333:69]
|
||||
wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[el2_lib.scala 333:69]
|
||||
wire [38:0] _T_355 = _T_354 ^ _T_315; // @[el2_lib.scala 333:76]
|
||||
wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[el2_lib.scala 333:31]
|
||||
wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58]
|
||||
wire _T_474 = ^io_dccm_rdata_lo_m; // @[el2_lib.scala 329:30]
|
||||
wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[el2_lib.scala 329:44]
|
||||
wire _T_476 = _T_474 ^ _T_475; // @[el2_lib.scala 329:35]
|
||||
wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[el2_lib.scala 329:78]
|
||||
wire _T_485 = ^_T_484; // @[el2_lib.scala 329:85]
|
||||
wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[el2_lib.scala 329:72]
|
||||
wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[el2_lib.scala 329:108]
|
||||
wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[el2_lib.scala 329:108]
|
||||
wire _T_502 = ^_T_501; // @[el2_lib.scala 329:115]
|
||||
wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[el2_lib.scala 329:102]
|
||||
wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[el2_lib.scala 329:138]
|
||||
wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[el2_lib.scala 329:138]
|
||||
wire _T_519 = ^_T_518; // @[el2_lib.scala 329:145]
|
||||
wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[el2_lib.scala 329:132]
|
||||
wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[el2_lib.scala 329:168]
|
||||
wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[el2_lib.scala 329:168]
|
||||
wire _T_539 = ^_T_538; // @[el2_lib.scala 329:175]
|
||||
wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[el2_lib.scala 329:162]
|
||||
wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 329:198]
|
||||
wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[el2_lib.scala 329:198]
|
||||
wire _T_559 = ^_T_558; // @[el2_lib.scala 329:205]
|
||||
wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[el2_lib.scala 329:192]
|
||||
wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 329:228]
|
||||
wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[el2_lib.scala 329:228]
|
||||
wire _T_579 = ^_T_578; // @[el2_lib.scala 329:235]
|
||||
wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[el2_lib.scala 329:222]
|
||||
wire _T_474 = ^io_dccm_rdata_lo_m; // @[el2_lib.scala 324:30]
|
||||
wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[el2_lib.scala 324:44]
|
||||
wire _T_476 = _T_474 ^ _T_475; // @[el2_lib.scala 324:35]
|
||||
wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[el2_lib.scala 324:76]
|
||||
wire _T_485 = ^_T_484; // @[el2_lib.scala 324:83]
|
||||
wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[el2_lib.scala 324:71]
|
||||
wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[el2_lib.scala 324:103]
|
||||
wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[el2_lib.scala 324:103]
|
||||
wire _T_502 = ^_T_501; // @[el2_lib.scala 324:110]
|
||||
wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[el2_lib.scala 324:98]
|
||||
wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[el2_lib.scala 324:130]
|
||||
wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[el2_lib.scala 324:130]
|
||||
wire _T_519 = ^_T_518; // @[el2_lib.scala 324:137]
|
||||
wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[el2_lib.scala 324:125]
|
||||
wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[el2_lib.scala 324:157]
|
||||
wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[el2_lib.scala 324:157]
|
||||
wire _T_539 = ^_T_538; // @[el2_lib.scala 324:164]
|
||||
wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[el2_lib.scala 324:152]
|
||||
wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 324:184]
|
||||
wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[el2_lib.scala 324:184]
|
||||
wire _T_559 = ^_T_558; // @[el2_lib.scala 324:191]
|
||||
wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[el2_lib.scala 324:179]
|
||||
wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 324:211]
|
||||
wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[el2_lib.scala 324:211]
|
||||
wire _T_579 = ^_T_578; // @[el2_lib.scala 324:218]
|
||||
wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[el2_lib.scala 324:206]
|
||||
wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58]
|
||||
wire _T_587 = _T_586 != 7'h0; // @[el2_lib.scala 330:44]
|
||||
wire _T_587 = _T_586 != 7'h0; // @[el2_lib.scala 325:44]
|
||||
wire is_ldst_lo_m = is_ldst_m & _T_1155; // @[el2_lsu_ecc.scala 126:33]
|
||||
wire _T_588 = is_ldst_lo_m & _T_587; // @[el2_lib.scala 330:31]
|
||||
wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[el2_lib.scala 330:53]
|
||||
wire _T_593 = ~_T_586[6]; // @[el2_lib.scala 331:55]
|
||||
wire double_ecc_error_lo_any = _T_588 & _T_593; // @[el2_lib.scala 331:53]
|
||||
wire _T_596 = _T_586[5:0] == 6'h1; // @[el2_lib.scala 335:44]
|
||||
wire _T_598 = _T_586[5:0] == 6'h2; // @[el2_lib.scala 335:44]
|
||||
wire _T_600 = _T_586[5:0] == 6'h3; // @[el2_lib.scala 335:44]
|
||||
wire _T_602 = _T_586[5:0] == 6'h4; // @[el2_lib.scala 335:44]
|
||||
wire _T_604 = _T_586[5:0] == 6'h5; // @[el2_lib.scala 335:44]
|
||||
wire _T_606 = _T_586[5:0] == 6'h6; // @[el2_lib.scala 335:44]
|
||||
wire _T_608 = _T_586[5:0] == 6'h7; // @[el2_lib.scala 335:44]
|
||||
wire _T_610 = _T_586[5:0] == 6'h8; // @[el2_lib.scala 335:44]
|
||||
wire _T_612 = _T_586[5:0] == 6'h9; // @[el2_lib.scala 335:44]
|
||||
wire _T_614 = _T_586[5:0] == 6'ha; // @[el2_lib.scala 335:44]
|
||||
wire _T_616 = _T_586[5:0] == 6'hb; // @[el2_lib.scala 335:44]
|
||||
wire _T_618 = _T_586[5:0] == 6'hc; // @[el2_lib.scala 335:44]
|
||||
wire _T_620 = _T_586[5:0] == 6'hd; // @[el2_lib.scala 335:44]
|
||||
wire _T_622 = _T_586[5:0] == 6'he; // @[el2_lib.scala 335:44]
|
||||
wire _T_624 = _T_586[5:0] == 6'hf; // @[el2_lib.scala 335:44]
|
||||
wire _T_626 = _T_586[5:0] == 6'h10; // @[el2_lib.scala 335:44]
|
||||
wire _T_628 = _T_586[5:0] == 6'h11; // @[el2_lib.scala 335:44]
|
||||
wire _T_630 = _T_586[5:0] == 6'h12; // @[el2_lib.scala 335:44]
|
||||
wire _T_632 = _T_586[5:0] == 6'h13; // @[el2_lib.scala 335:44]
|
||||
wire _T_634 = _T_586[5:0] == 6'h14; // @[el2_lib.scala 335:44]
|
||||
wire _T_636 = _T_586[5:0] == 6'h15; // @[el2_lib.scala 335:44]
|
||||
wire _T_638 = _T_586[5:0] == 6'h16; // @[el2_lib.scala 335:44]
|
||||
wire _T_640 = _T_586[5:0] == 6'h17; // @[el2_lib.scala 335:44]
|
||||
wire _T_642 = _T_586[5:0] == 6'h18; // @[el2_lib.scala 335:44]
|
||||
wire _T_644 = _T_586[5:0] == 6'h19; // @[el2_lib.scala 335:44]
|
||||
wire _T_646 = _T_586[5:0] == 6'h1a; // @[el2_lib.scala 335:44]
|
||||
wire _T_648 = _T_586[5:0] == 6'h1b; // @[el2_lib.scala 335:44]
|
||||
wire _T_650 = _T_586[5:0] == 6'h1c; // @[el2_lib.scala 335:44]
|
||||
wire _T_652 = _T_586[5:0] == 6'h1d; // @[el2_lib.scala 335:44]
|
||||
wire _T_654 = _T_586[5:0] == 6'h1e; // @[el2_lib.scala 335:44]
|
||||
wire _T_656 = _T_586[5:0] == 6'h1f; // @[el2_lib.scala 335:44]
|
||||
wire _T_658 = _T_586[5:0] == 6'h20; // @[el2_lib.scala 335:44]
|
||||
wire _T_660 = _T_586[5:0] == 6'h21; // @[el2_lib.scala 335:44]
|
||||
wire _T_662 = _T_586[5:0] == 6'h22; // @[el2_lib.scala 335:44]
|
||||
wire _T_664 = _T_586[5:0] == 6'h23; // @[el2_lib.scala 335:44]
|
||||
wire _T_666 = _T_586[5:0] == 6'h24; // @[el2_lib.scala 335:44]
|
||||
wire _T_668 = _T_586[5:0] == 6'h25; // @[el2_lib.scala 335:44]
|
||||
wire _T_670 = _T_586[5:0] == 6'h26; // @[el2_lib.scala 335:44]
|
||||
wire _T_672 = _T_586[5:0] == 6'h27; // @[el2_lib.scala 335:44]
|
||||
wire _T_588 = is_ldst_lo_m & _T_587; // @[el2_lib.scala 325:32]
|
||||
wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[el2_lib.scala 325:53]
|
||||
wire _T_593 = ~_T_586[6]; // @[el2_lib.scala 326:55]
|
||||
wire double_ecc_error_lo_any = _T_588 & _T_593; // @[el2_lib.scala 326:53]
|
||||
wire _T_596 = _T_586[5:0] == 6'h1; // @[el2_lib.scala 330:41]
|
||||
wire _T_598 = _T_586[5:0] == 6'h2; // @[el2_lib.scala 330:41]
|
||||
wire _T_600 = _T_586[5:0] == 6'h3; // @[el2_lib.scala 330:41]
|
||||
wire _T_602 = _T_586[5:0] == 6'h4; // @[el2_lib.scala 330:41]
|
||||
wire _T_604 = _T_586[5:0] == 6'h5; // @[el2_lib.scala 330:41]
|
||||
wire _T_606 = _T_586[5:0] == 6'h6; // @[el2_lib.scala 330:41]
|
||||
wire _T_608 = _T_586[5:0] == 6'h7; // @[el2_lib.scala 330:41]
|
||||
wire _T_610 = _T_586[5:0] == 6'h8; // @[el2_lib.scala 330:41]
|
||||
wire _T_612 = _T_586[5:0] == 6'h9; // @[el2_lib.scala 330:41]
|
||||
wire _T_614 = _T_586[5:0] == 6'ha; // @[el2_lib.scala 330:41]
|
||||
wire _T_616 = _T_586[5:0] == 6'hb; // @[el2_lib.scala 330:41]
|
||||
wire _T_618 = _T_586[5:0] == 6'hc; // @[el2_lib.scala 330:41]
|
||||
wire _T_620 = _T_586[5:0] == 6'hd; // @[el2_lib.scala 330:41]
|
||||
wire _T_622 = _T_586[5:0] == 6'he; // @[el2_lib.scala 330:41]
|
||||
wire _T_624 = _T_586[5:0] == 6'hf; // @[el2_lib.scala 330:41]
|
||||
wire _T_626 = _T_586[5:0] == 6'h10; // @[el2_lib.scala 330:41]
|
||||
wire _T_628 = _T_586[5:0] == 6'h11; // @[el2_lib.scala 330:41]
|
||||
wire _T_630 = _T_586[5:0] == 6'h12; // @[el2_lib.scala 330:41]
|
||||
wire _T_632 = _T_586[5:0] == 6'h13; // @[el2_lib.scala 330:41]
|
||||
wire _T_634 = _T_586[5:0] == 6'h14; // @[el2_lib.scala 330:41]
|
||||
wire _T_636 = _T_586[5:0] == 6'h15; // @[el2_lib.scala 330:41]
|
||||
wire _T_638 = _T_586[5:0] == 6'h16; // @[el2_lib.scala 330:41]
|
||||
wire _T_640 = _T_586[5:0] == 6'h17; // @[el2_lib.scala 330:41]
|
||||
wire _T_642 = _T_586[5:0] == 6'h18; // @[el2_lib.scala 330:41]
|
||||
wire _T_644 = _T_586[5:0] == 6'h19; // @[el2_lib.scala 330:41]
|
||||
wire _T_646 = _T_586[5:0] == 6'h1a; // @[el2_lib.scala 330:41]
|
||||
wire _T_648 = _T_586[5:0] == 6'h1b; // @[el2_lib.scala 330:41]
|
||||
wire _T_650 = _T_586[5:0] == 6'h1c; // @[el2_lib.scala 330:41]
|
||||
wire _T_652 = _T_586[5:0] == 6'h1d; // @[el2_lib.scala 330:41]
|
||||
wire _T_654 = _T_586[5:0] == 6'h1e; // @[el2_lib.scala 330:41]
|
||||
wire _T_656 = _T_586[5:0] == 6'h1f; // @[el2_lib.scala 330:41]
|
||||
wire _T_658 = _T_586[5:0] == 6'h20; // @[el2_lib.scala 330:41]
|
||||
wire _T_660 = _T_586[5:0] == 6'h21; // @[el2_lib.scala 330:41]
|
||||
wire _T_662 = _T_586[5:0] == 6'h22; // @[el2_lib.scala 330:41]
|
||||
wire _T_664 = _T_586[5:0] == 6'h23; // @[el2_lib.scala 330:41]
|
||||
wire _T_666 = _T_586[5:0] == 6'h24; // @[el2_lib.scala 330:41]
|
||||
wire _T_668 = _T_586[5:0] == 6'h25; // @[el2_lib.scala 330:41]
|
||||
wire _T_670 = _T_586[5:0] == 6'h26; // @[el2_lib.scala 330:41]
|
||||
wire _T_672 = _T_586[5:0] == 6'h27; // @[el2_lib.scala 330:41]
|
||||
wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58]
|
||||
wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[el2_lib.scala 338:69]
|
||||
wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[el2_lib.scala 338:69]
|
||||
wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[el2_lib.scala 338:69]
|
||||
wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[el2_lib.scala 338:69]
|
||||
wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[el2_lib.scala 338:69]
|
||||
wire [38:0] _T_733 = _T_732 ^ _T_693; // @[el2_lib.scala 338:76]
|
||||
wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[el2_lib.scala 338:31]
|
||||
wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[el2_lib.scala 333:69]
|
||||
wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[el2_lib.scala 333:69]
|
||||
wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[el2_lib.scala 333:69]
|
||||
wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[el2_lib.scala 333:69]
|
||||
wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[el2_lib.scala 333:69]
|
||||
wire [38:0] _T_733 = _T_732 ^ _T_693; // @[el2_lib.scala 333:76]
|
||||
wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[el2_lib.scala 333:31]
|
||||
wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_1182 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[el2_lsu_ecc.scala 149:89]
|
||||
wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1182; // @[el2_lsu_ecc.scala 149:29]
|
||||
wire [5:0] _T_856 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[30],dccm_wdata_lo_any[29],dccm_wdata_lo_any[28],dccm_wdata_lo_any[27],dccm_wdata_lo_any[26]}; // @[el2_lib.scala 280:22]
|
||||
wire _T_857 = ^_T_856; // @[el2_lib.scala 280:29]
|
||||
wire [6:0] _T_863 = {dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],dccm_wdata_lo_any[15],dccm_wdata_lo_any[14],dccm_wdata_lo_any[13],dccm_wdata_lo_any[12],dccm_wdata_lo_any[11]}; // @[el2_lib.scala 280:40]
|
||||
wire [14:0] _T_871 = {dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[19],dccm_wdata_lo_any[18],_T_863}; // @[el2_lib.scala 280:40]
|
||||
wire _T_872 = ^_T_871; // @[el2_lib.scala 280:47]
|
||||
wire [6:0] _T_878 = {dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[8],dccm_wdata_lo_any[7],dccm_wdata_lo_any[6],dccm_wdata_lo_any[5],dccm_wdata_lo_any[4]}; // @[el2_lib.scala 280:58]
|
||||
wire [14:0] _T_886 = {dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[19],dccm_wdata_lo_any[18],_T_878}; // @[el2_lib.scala 280:58]
|
||||
wire _T_887 = ^_T_886; // @[el2_lib.scala 280:65]
|
||||
wire [8:0] _T_895 = {dccm_wdata_lo_any[15],dccm_wdata_lo_any[14],dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[8],dccm_wdata_lo_any[7],dccm_wdata_lo_any[3],dccm_wdata_lo_any[2],dccm_wdata_lo_any[1]}; // @[el2_lib.scala 280:76]
|
||||
wire [17:0] _T_904 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[30],dccm_wdata_lo_any[29],dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],_T_895}; // @[el2_lib.scala 280:76]
|
||||
wire _T_905 = ^_T_904; // @[el2_lib.scala 280:83]
|
||||
wire [8:0] _T_913 = {dccm_wdata_lo_any[13],dccm_wdata_lo_any[12],dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[6],dccm_wdata_lo_any[5],dccm_wdata_lo_any[3],dccm_wdata_lo_any[2],dccm_wdata_lo_any[0]}; // @[el2_lib.scala 280:94]
|
||||
wire [17:0] _T_922 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[28],dccm_wdata_lo_any[27],dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],_T_913}; // @[el2_lib.scala 280:94]
|
||||
wire _T_923 = ^_T_922; // @[el2_lib.scala 280:101]
|
||||
wire [8:0] _T_931 = {dccm_wdata_lo_any[13],dccm_wdata_lo_any[11],dccm_wdata_lo_any[10],dccm_wdata_lo_any[8],dccm_wdata_lo_any[6],dccm_wdata_lo_any[4],dccm_wdata_lo_any[3],dccm_wdata_lo_any[1],dccm_wdata_lo_any[0]}; // @[el2_lib.scala 280:112]
|
||||
wire [17:0] _T_940 = {dccm_wdata_lo_any[30],dccm_wdata_lo_any[28],dccm_wdata_lo_any[26],dccm_wdata_lo_any[25],dccm_wdata_lo_any[23],dccm_wdata_lo_any[21],dccm_wdata_lo_any[19],dccm_wdata_lo_any[17],dccm_wdata_lo_any[15],_T_931}; // @[el2_lib.scala 280:112]
|
||||
wire _T_941 = ^_T_940; // @[el2_lib.scala 280:119]
|
||||
wire [5:0] _T_856 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[30],dccm_wdata_lo_any[29],dccm_wdata_lo_any[28],dccm_wdata_lo_any[27],dccm_wdata_lo_any[26]}; // @[el2_lib.scala 287:22]
|
||||
wire _T_857 = ^_T_856; // @[el2_lib.scala 287:29]
|
||||
wire [6:0] _T_863 = {dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],dccm_wdata_lo_any[15],dccm_wdata_lo_any[14],dccm_wdata_lo_any[13],dccm_wdata_lo_any[12],dccm_wdata_lo_any[11]}; // @[el2_lib.scala 287:39]
|
||||
wire [14:0] _T_871 = {dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[19],dccm_wdata_lo_any[18],_T_863}; // @[el2_lib.scala 287:39]
|
||||
wire _T_872 = ^_T_871; // @[el2_lib.scala 287:46]
|
||||
wire [6:0] _T_878 = {dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[8],dccm_wdata_lo_any[7],dccm_wdata_lo_any[6],dccm_wdata_lo_any[5],dccm_wdata_lo_any[4]}; // @[el2_lib.scala 287:56]
|
||||
wire [14:0] _T_886 = {dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[19],dccm_wdata_lo_any[18],_T_878}; // @[el2_lib.scala 287:56]
|
||||
wire _T_887 = ^_T_886; // @[el2_lib.scala 287:63]
|
||||
wire [8:0] _T_895 = {dccm_wdata_lo_any[15],dccm_wdata_lo_any[14],dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[8],dccm_wdata_lo_any[7],dccm_wdata_lo_any[3],dccm_wdata_lo_any[2],dccm_wdata_lo_any[1]}; // @[el2_lib.scala 287:73]
|
||||
wire [17:0] _T_904 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[30],dccm_wdata_lo_any[29],dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],_T_895}; // @[el2_lib.scala 287:73]
|
||||
wire _T_905 = ^_T_904; // @[el2_lib.scala 287:80]
|
||||
wire [8:0] _T_913 = {dccm_wdata_lo_any[13],dccm_wdata_lo_any[12],dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[6],dccm_wdata_lo_any[5],dccm_wdata_lo_any[3],dccm_wdata_lo_any[2],dccm_wdata_lo_any[0]}; // @[el2_lib.scala 287:90]
|
||||
wire [17:0] _T_922 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[28],dccm_wdata_lo_any[27],dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],_T_913}; // @[el2_lib.scala 287:90]
|
||||
wire _T_923 = ^_T_922; // @[el2_lib.scala 287:97]
|
||||
wire [8:0] _T_931 = {dccm_wdata_lo_any[13],dccm_wdata_lo_any[11],dccm_wdata_lo_any[10],dccm_wdata_lo_any[8],dccm_wdata_lo_any[6],dccm_wdata_lo_any[4],dccm_wdata_lo_any[3],dccm_wdata_lo_any[1],dccm_wdata_lo_any[0]}; // @[el2_lib.scala 287:107]
|
||||
wire [17:0] _T_940 = {dccm_wdata_lo_any[30],dccm_wdata_lo_any[28],dccm_wdata_lo_any[26],dccm_wdata_lo_any[25],dccm_wdata_lo_any[23],dccm_wdata_lo_any[21],dccm_wdata_lo_any[19],dccm_wdata_lo_any[17],dccm_wdata_lo_any[15],_T_931}; // @[el2_lib.scala 287:107]
|
||||
wire _T_941 = ^_T_940; // @[el2_lib.scala 287:114]
|
||||
wire [5:0] _T_946 = {_T_857,_T_872,_T_887,_T_905,_T_923,_T_941}; // @[Cat.scala 29:58]
|
||||
wire _T_947 = ^dccm_wdata_lo_any; // @[el2_lib.scala 281:27]
|
||||
wire _T_948 = ^_T_946; // @[el2_lib.scala 281:37]
|
||||
wire _T_949 = _T_947 ^ _T_948; // @[el2_lib.scala 281:32]
|
||||
wire _T_947 = ^dccm_wdata_lo_any; // @[el2_lib.scala 288:27]
|
||||
wire _T_948 = ^_T_946; // @[el2_lib.scala 288:37]
|
||||
wire _T_949 = _T_947 ^ _T_948; // @[el2_lib.scala 288:32]
|
||||
wire [31:0] _T_1186 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : io_stbuf_data_any; // @[el2_lsu_ecc.scala 150:89]
|
||||
wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1186; // @[el2_lsu_ecc.scala 150:29]
|
||||
wire [5:0] _T_1050 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[30],dccm_wdata_hi_any[29],dccm_wdata_hi_any[28],dccm_wdata_hi_any[27],dccm_wdata_hi_any[26]}; // @[el2_lib.scala 280:22]
|
||||
wire _T_1051 = ^_T_1050; // @[el2_lib.scala 280:29]
|
||||
wire [6:0] _T_1057 = {dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],dccm_wdata_hi_any[15],dccm_wdata_hi_any[14],dccm_wdata_hi_any[13],dccm_wdata_hi_any[12],dccm_wdata_hi_any[11]}; // @[el2_lib.scala 280:40]
|
||||
wire [14:0] _T_1065 = {dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[19],dccm_wdata_hi_any[18],_T_1057}; // @[el2_lib.scala 280:40]
|
||||
wire _T_1066 = ^_T_1065; // @[el2_lib.scala 280:47]
|
||||
wire [6:0] _T_1072 = {dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[8],dccm_wdata_hi_any[7],dccm_wdata_hi_any[6],dccm_wdata_hi_any[5],dccm_wdata_hi_any[4]}; // @[el2_lib.scala 280:58]
|
||||
wire [14:0] _T_1080 = {dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[19],dccm_wdata_hi_any[18],_T_1072}; // @[el2_lib.scala 280:58]
|
||||
wire _T_1081 = ^_T_1080; // @[el2_lib.scala 280:65]
|
||||
wire [8:0] _T_1089 = {dccm_wdata_hi_any[15],dccm_wdata_hi_any[14],dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[8],dccm_wdata_hi_any[7],dccm_wdata_hi_any[3],dccm_wdata_hi_any[2],dccm_wdata_hi_any[1]}; // @[el2_lib.scala 280:76]
|
||||
wire [17:0] _T_1098 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[30],dccm_wdata_hi_any[29],dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],_T_1089}; // @[el2_lib.scala 280:76]
|
||||
wire _T_1099 = ^_T_1098; // @[el2_lib.scala 280:83]
|
||||
wire [8:0] _T_1107 = {dccm_wdata_hi_any[13],dccm_wdata_hi_any[12],dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[6],dccm_wdata_hi_any[5],dccm_wdata_hi_any[3],dccm_wdata_hi_any[2],dccm_wdata_hi_any[0]}; // @[el2_lib.scala 280:94]
|
||||
wire [17:0] _T_1116 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[28],dccm_wdata_hi_any[27],dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],_T_1107}; // @[el2_lib.scala 280:94]
|
||||
wire _T_1117 = ^_T_1116; // @[el2_lib.scala 280:101]
|
||||
wire [8:0] _T_1125 = {dccm_wdata_hi_any[13],dccm_wdata_hi_any[11],dccm_wdata_hi_any[10],dccm_wdata_hi_any[8],dccm_wdata_hi_any[6],dccm_wdata_hi_any[4],dccm_wdata_hi_any[3],dccm_wdata_hi_any[1],dccm_wdata_hi_any[0]}; // @[el2_lib.scala 280:112]
|
||||
wire [17:0] _T_1134 = {dccm_wdata_hi_any[30],dccm_wdata_hi_any[28],dccm_wdata_hi_any[26],dccm_wdata_hi_any[25],dccm_wdata_hi_any[23],dccm_wdata_hi_any[21],dccm_wdata_hi_any[19],dccm_wdata_hi_any[17],dccm_wdata_hi_any[15],_T_1125}; // @[el2_lib.scala 280:112]
|
||||
wire _T_1135 = ^_T_1134; // @[el2_lib.scala 280:119]
|
||||
wire [5:0] _T_1050 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[30],dccm_wdata_hi_any[29],dccm_wdata_hi_any[28],dccm_wdata_hi_any[27],dccm_wdata_hi_any[26]}; // @[el2_lib.scala 287:22]
|
||||
wire _T_1051 = ^_T_1050; // @[el2_lib.scala 287:29]
|
||||
wire [6:0] _T_1057 = {dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],dccm_wdata_hi_any[15],dccm_wdata_hi_any[14],dccm_wdata_hi_any[13],dccm_wdata_hi_any[12],dccm_wdata_hi_any[11]}; // @[el2_lib.scala 287:39]
|
||||
wire [14:0] _T_1065 = {dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[19],dccm_wdata_hi_any[18],_T_1057}; // @[el2_lib.scala 287:39]
|
||||
wire _T_1066 = ^_T_1065; // @[el2_lib.scala 287:46]
|
||||
wire [6:0] _T_1072 = {dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[8],dccm_wdata_hi_any[7],dccm_wdata_hi_any[6],dccm_wdata_hi_any[5],dccm_wdata_hi_any[4]}; // @[el2_lib.scala 287:56]
|
||||
wire [14:0] _T_1080 = {dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[19],dccm_wdata_hi_any[18],_T_1072}; // @[el2_lib.scala 287:56]
|
||||
wire _T_1081 = ^_T_1080; // @[el2_lib.scala 287:63]
|
||||
wire [8:0] _T_1089 = {dccm_wdata_hi_any[15],dccm_wdata_hi_any[14],dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[8],dccm_wdata_hi_any[7],dccm_wdata_hi_any[3],dccm_wdata_hi_any[2],dccm_wdata_hi_any[1]}; // @[el2_lib.scala 287:73]
|
||||
wire [17:0] _T_1098 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[30],dccm_wdata_hi_any[29],dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],_T_1089}; // @[el2_lib.scala 287:73]
|
||||
wire _T_1099 = ^_T_1098; // @[el2_lib.scala 287:80]
|
||||
wire [8:0] _T_1107 = {dccm_wdata_hi_any[13],dccm_wdata_hi_any[12],dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[6],dccm_wdata_hi_any[5],dccm_wdata_hi_any[3],dccm_wdata_hi_any[2],dccm_wdata_hi_any[0]}; // @[el2_lib.scala 287:90]
|
||||
wire [17:0] _T_1116 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[28],dccm_wdata_hi_any[27],dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],_T_1107}; // @[el2_lib.scala 287:90]
|
||||
wire _T_1117 = ^_T_1116; // @[el2_lib.scala 287:97]
|
||||
wire [8:0] _T_1125 = {dccm_wdata_hi_any[13],dccm_wdata_hi_any[11],dccm_wdata_hi_any[10],dccm_wdata_hi_any[8],dccm_wdata_hi_any[6],dccm_wdata_hi_any[4],dccm_wdata_hi_any[3],dccm_wdata_hi_any[1],dccm_wdata_hi_any[0]}; // @[el2_lib.scala 287:107]
|
||||
wire [17:0] _T_1134 = {dccm_wdata_hi_any[30],dccm_wdata_hi_any[28],dccm_wdata_hi_any[26],dccm_wdata_hi_any[25],dccm_wdata_hi_any[23],dccm_wdata_hi_any[21],dccm_wdata_hi_any[19],dccm_wdata_hi_any[17],dccm_wdata_hi_any[15],_T_1125}; // @[el2_lib.scala 287:107]
|
||||
wire _T_1135 = ^_T_1134; // @[el2_lib.scala 287:114]
|
||||
wire [5:0] _T_1140 = {_T_1051,_T_1066,_T_1081,_T_1099,_T_1117,_T_1135}; // @[Cat.scala 29:58]
|
||||
wire _T_1141 = ^dccm_wdata_hi_any; // @[el2_lib.scala 281:27]
|
||||
wire _T_1142 = ^_T_1140; // @[el2_lib.scala 281:37]
|
||||
wire _T_1143 = _T_1141 ^ _T_1142; // @[el2_lib.scala 281:32]
|
||||
wire _T_1141 = ^dccm_wdata_hi_any; // @[el2_lib.scala 288:27]
|
||||
wire _T_1142 = ^_T_1140; // @[el2_lib.scala 288:37]
|
||||
wire _T_1143 = _T_1141 ^ _T_1142; // @[el2_lib.scala 288:32]
|
||||
reg _T_1174; // @[el2_lsu_ecc.scala 141:72]
|
||||
reg _T_1175; // @[el2_lsu_ecc.scala 142:72]
|
||||
reg _T_1176; // @[el2_lsu_ecc.scala 143:72]
|
||||
reg _T_1177; // @[el2_lsu_ecc.scala 144:72]
|
||||
reg [31:0] _T_1178; // @[el2_lsu_ecc.scala 145:72]
|
||||
reg [31:0] _T_1179; // @[el2_lsu_ecc.scala 146:72]
|
||||
reg [31:0] _T_1188; // @[Reg.scala 27:20]
|
||||
reg [31:0] _T_1189; // @[Reg.scala 27:20]
|
||||
reg [31:0] _T_1188; // @[beh_lib.scala 358:14]
|
||||
reg [31:0] _T_1189; // @[beh_lib.scala 358:14]
|
||||
rvclkhdr rvclkhdr ( // @[beh_lib.scala 352:21]
|
||||
.io_l1clk(rvclkhdr_io_l1clk),
|
||||
.io_clk(rvclkhdr_io_clk),
|
||||
.io_en(rvclkhdr_io_en),
|
||||
.io_scan_mode(rvclkhdr_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 352:21]
|
||||
.io_l1clk(rvclkhdr_1_io_l1clk),
|
||||
.io_clk(rvclkhdr_1_io_clk),
|
||||
.io_en(rvclkhdr_1_io_en),
|
||||
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
||||
);
|
||||
assign io_sec_data_hi_r = _T_1178; // @[el2_lsu_ecc.scala 114:24 el2_lsu_ecc.scala 145:62]
|
||||
assign io_sec_data_lo_r = _T_1179; // @[el2_lsu_ecc.scala 117:27 el2_lsu_ecc.scala 146:62]
|
||||
assign io_sec_data_hi_m = {_T_364,_T_362}; // @[el2_lsu_ecc.scala 90:32 el2_lsu_ecc.scala 134:27]
|
||||
|
|
@ -325,6 +366,12 @@ module el2_lsu_ecc(
|
|||
assign io_lsu_double_ecc_error_r = _T_1175; // @[el2_lsu_ecc.scala 121:33 el2_lsu_ecc.scala 142:62]
|
||||
assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[el2_lsu_ecc.scala 92:30 el2_lsu_ecc.scala 138:33]
|
||||
assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[el2_lsu_ecc.scala 93:30 el2_lsu_ecc.scala 139:33]
|
||||
assign rvclkhdr_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -449,17 +496,17 @@ end // initial
|
|||
_T_1179 <= io_sec_data_lo_m;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_1188 <= 32'h0;
|
||||
end else if (io_ld_single_ecc_error_r) begin
|
||||
end else begin
|
||||
_T_1188 <= io_sec_data_hi_r;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_1189 <= 32'h0;
|
||||
end else if (io_ld_single_ecc_error_r) begin
|
||||
end else begin
|
||||
_T_1189 <= io_sec_data_lo_r;
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -31,33 +31,6 @@
|
|||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_dccm_d",
|
||||
"sources":[
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_store",
|
||||
|
|
@ -67,33 +40,6 @@
|
|||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_write"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_end_addr_d",
|
||||
"sources":[
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_store_data_bypass_d",
|
||||
|
|
@ -117,26 +63,6 @@
|
|||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_corr_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_addr_d",
|
||||
"sources":[
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_valid",
|
||||
|
|
@ -147,6 +73,23 @@
|
|||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_fast_int"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_store_data_m",
|
||||
"sources":[
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_picm_mask_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_store_data_bypass_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_pic_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
|
||||
|
|
@ -164,16 +107,16 @@
|
|||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
|
||||
|
|
@ -185,19 +128,35 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_store_data_m",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_addr_d",
|
||||
"sources":[
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_picm_mask_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_store_data_bypass_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_pic_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign"
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
|
||||
"sources":[
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign"
|
||||
]
|
||||
},
|
||||
{
|
||||
|
|
@ -222,15 +181,29 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_end_addr_d",
|
||||
"sources":[
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign"
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
|
||||
]
|
||||
},
|
||||
{
|
||||
|
|
@ -285,6 +258,33 @@
|
|||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_load"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_dccm_d",
|
||||
"sources":[
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word",
|
||||
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
|
|
|
|||
1721
el2_lsu_lsc_ctl.fir
1721
el2_lsu_lsc_ctl.fir
File diff suppressed because it is too large
Load Diff
1903
el2_lsu_lsc_ctl.v
1903
el2_lsu_lsc_ctl.v
File diff suppressed because it is too large
Load Diff
|
|
@ -116,6 +116,11 @@
|
|||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"el2_lsu_stbuf.TEC_RV_ICG",
|
||||
"resourceId":"/vsrc/TEC_RV_ICG.v"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
|
|
|
|||
|
|
@ -1,5 +1,197 @@
|
|||
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
|
||||
circuit el2_lsu_stbuf :
|
||||
extmodule TEC_RV_ICG :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = TEC_RV_ICG
|
||||
|
||||
|
||||
module rvclkhdr :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_1 :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = TEC_RV_ICG
|
||||
|
||||
|
||||
module rvclkhdr_1 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_2 :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = TEC_RV_ICG
|
||||
|
||||
|
||||
module rvclkhdr_2 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_3 :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = TEC_RV_ICG
|
||||
|
||||
|
||||
module rvclkhdr_3 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_3 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_4 :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = TEC_RV_ICG
|
||||
|
||||
|
||||
module rvclkhdr_4 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_4 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_5 :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = TEC_RV_ICG
|
||||
|
||||
|
||||
module rvclkhdr_5 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_5 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_6 :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = TEC_RV_ICG
|
||||
|
||||
|
||||
module rvclkhdr_6 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_6 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
extmodule TEC_RV_ICG_7 :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = TEC_RV_ICG
|
||||
|
||||
|
||||
module rvclkhdr_7 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_7 @[beh_lib.scala 332:24]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
|
||||
module el2_lsu_stbuf :
|
||||
input clock : Clock
|
||||
input reset : AsyncReset
|
||||
|
|
@ -831,61 +1023,93 @@ circuit el2_lsu_stbuf :
|
|||
stbuf_byteen[1] <= _T_644 @[el2_lsu_stbuf.scala 167:16]
|
||||
stbuf_byteen[2] <= _T_653 @[el2_lsu_stbuf.scala 167:16]
|
||||
stbuf_byteen[3] <= _T_662 @[el2_lsu_stbuf.scala 167:16]
|
||||
node _T_663 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 172:67]
|
||||
node _T_664 = bits(_T_663, 0, 0) @[el2_lsu_stbuf.scala 172:77]
|
||||
reg _T_665 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_664 : @[Reg.scala 28:19]
|
||||
_T_665 <= stbuf_addrin[0] @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_663 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 172:58]
|
||||
node _T_664 = bits(_T_663, 0, 0) @[el2_lsu_stbuf.scala 172:68]
|
||||
inst rvclkhdr of rvclkhdr @[beh_lib.scala 352:21]
|
||||
rvclkhdr.clock <= clock
|
||||
rvclkhdr.reset <= reset
|
||||
rvclkhdr.io.clk <= clock @[beh_lib.scala 354:16]
|
||||
rvclkhdr.io.en <= _T_664 @[beh_lib.scala 355:15]
|
||||
rvclkhdr.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22]
|
||||
reg _T_665 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14]
|
||||
_T_665 <= stbuf_addrin[0] @[beh_lib.scala 358:14]
|
||||
stbuf_addr[0] <= _T_665 @[el2_lsu_stbuf.scala 172:21]
|
||||
node _T_666 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 174:66]
|
||||
node _T_667 = bits(_T_666, 0, 0) @[el2_lsu_stbuf.scala 174:76]
|
||||
reg _T_668 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_667 : @[Reg.scala 28:19]
|
||||
_T_668 <= stbuf_datain[0] @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_666 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 174:57]
|
||||
node _T_667 = bits(_T_666, 0, 0) @[el2_lsu_stbuf.scala 174:67]
|
||||
inst rvclkhdr_1 of rvclkhdr_1 @[beh_lib.scala 352:21]
|
||||
rvclkhdr_1.clock <= clock
|
||||
rvclkhdr_1.reset <= reset
|
||||
rvclkhdr_1.io.clk <= clock @[beh_lib.scala 354:16]
|
||||
rvclkhdr_1.io.en <= _T_667 @[beh_lib.scala 355:15]
|
||||
rvclkhdr_1.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22]
|
||||
reg _T_668 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14]
|
||||
_T_668 <= stbuf_datain[0] @[beh_lib.scala 358:14]
|
||||
stbuf_data[0] <= _T_668 @[el2_lsu_stbuf.scala 174:20]
|
||||
node _T_669 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 172:67]
|
||||
node _T_670 = bits(_T_669, 0, 0) @[el2_lsu_stbuf.scala 172:77]
|
||||
reg _T_671 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_670 : @[Reg.scala 28:19]
|
||||
_T_671 <= stbuf_addrin[1] @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_669 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 172:58]
|
||||
node _T_670 = bits(_T_669, 0, 0) @[el2_lsu_stbuf.scala 172:68]
|
||||
inst rvclkhdr_2 of rvclkhdr_2 @[beh_lib.scala 352:21]
|
||||
rvclkhdr_2.clock <= clock
|
||||
rvclkhdr_2.reset <= reset
|
||||
rvclkhdr_2.io.clk <= clock @[beh_lib.scala 354:16]
|
||||
rvclkhdr_2.io.en <= _T_670 @[beh_lib.scala 355:15]
|
||||
rvclkhdr_2.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22]
|
||||
reg _T_671 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14]
|
||||
_T_671 <= stbuf_addrin[1] @[beh_lib.scala 358:14]
|
||||
stbuf_addr[1] <= _T_671 @[el2_lsu_stbuf.scala 172:21]
|
||||
node _T_672 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 174:66]
|
||||
node _T_673 = bits(_T_672, 0, 0) @[el2_lsu_stbuf.scala 174:76]
|
||||
reg _T_674 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_673 : @[Reg.scala 28:19]
|
||||
_T_674 <= stbuf_datain[1] @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_672 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 174:57]
|
||||
node _T_673 = bits(_T_672, 0, 0) @[el2_lsu_stbuf.scala 174:67]
|
||||
inst rvclkhdr_3 of rvclkhdr_3 @[beh_lib.scala 352:21]
|
||||
rvclkhdr_3.clock <= clock
|
||||
rvclkhdr_3.reset <= reset
|
||||
rvclkhdr_3.io.clk <= clock @[beh_lib.scala 354:16]
|
||||
rvclkhdr_3.io.en <= _T_673 @[beh_lib.scala 355:15]
|
||||
rvclkhdr_3.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22]
|
||||
reg _T_674 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14]
|
||||
_T_674 <= stbuf_datain[1] @[beh_lib.scala 358:14]
|
||||
stbuf_data[1] <= _T_674 @[el2_lsu_stbuf.scala 174:20]
|
||||
node _T_675 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 172:67]
|
||||
node _T_676 = bits(_T_675, 0, 0) @[el2_lsu_stbuf.scala 172:77]
|
||||
reg _T_677 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_676 : @[Reg.scala 28:19]
|
||||
_T_677 <= stbuf_addrin[2] @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_675 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 172:58]
|
||||
node _T_676 = bits(_T_675, 0, 0) @[el2_lsu_stbuf.scala 172:68]
|
||||
inst rvclkhdr_4 of rvclkhdr_4 @[beh_lib.scala 352:21]
|
||||
rvclkhdr_4.clock <= clock
|
||||
rvclkhdr_4.reset <= reset
|
||||
rvclkhdr_4.io.clk <= clock @[beh_lib.scala 354:16]
|
||||
rvclkhdr_4.io.en <= _T_676 @[beh_lib.scala 355:15]
|
||||
rvclkhdr_4.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22]
|
||||
reg _T_677 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14]
|
||||
_T_677 <= stbuf_addrin[2] @[beh_lib.scala 358:14]
|
||||
stbuf_addr[2] <= _T_677 @[el2_lsu_stbuf.scala 172:21]
|
||||
node _T_678 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 174:66]
|
||||
node _T_679 = bits(_T_678, 0, 0) @[el2_lsu_stbuf.scala 174:76]
|
||||
reg _T_680 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_679 : @[Reg.scala 28:19]
|
||||
_T_680 <= stbuf_datain[2] @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_678 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 174:57]
|
||||
node _T_679 = bits(_T_678, 0, 0) @[el2_lsu_stbuf.scala 174:67]
|
||||
inst rvclkhdr_5 of rvclkhdr_5 @[beh_lib.scala 352:21]
|
||||
rvclkhdr_5.clock <= clock
|
||||
rvclkhdr_5.reset <= reset
|
||||
rvclkhdr_5.io.clk <= clock @[beh_lib.scala 354:16]
|
||||
rvclkhdr_5.io.en <= _T_679 @[beh_lib.scala 355:15]
|
||||
rvclkhdr_5.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22]
|
||||
reg _T_680 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14]
|
||||
_T_680 <= stbuf_datain[2] @[beh_lib.scala 358:14]
|
||||
stbuf_data[2] <= _T_680 @[el2_lsu_stbuf.scala 174:20]
|
||||
node _T_681 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 172:67]
|
||||
node _T_682 = bits(_T_681, 0, 0) @[el2_lsu_stbuf.scala 172:77]
|
||||
reg _T_683 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_682 : @[Reg.scala 28:19]
|
||||
_T_683 <= stbuf_addrin[3] @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_681 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 172:58]
|
||||
node _T_682 = bits(_T_681, 0, 0) @[el2_lsu_stbuf.scala 172:68]
|
||||
inst rvclkhdr_6 of rvclkhdr_6 @[beh_lib.scala 352:21]
|
||||
rvclkhdr_6.clock <= clock
|
||||
rvclkhdr_6.reset <= reset
|
||||
rvclkhdr_6.io.clk <= clock @[beh_lib.scala 354:16]
|
||||
rvclkhdr_6.io.en <= _T_682 @[beh_lib.scala 355:15]
|
||||
rvclkhdr_6.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22]
|
||||
reg _T_683 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14]
|
||||
_T_683 <= stbuf_addrin[3] @[beh_lib.scala 358:14]
|
||||
stbuf_addr[3] <= _T_683 @[el2_lsu_stbuf.scala 172:21]
|
||||
node _T_684 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 174:66]
|
||||
node _T_685 = bits(_T_684, 0, 0) @[el2_lsu_stbuf.scala 174:76]
|
||||
reg _T_686 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_685 : @[Reg.scala 28:19]
|
||||
_T_686 <= stbuf_datain[3] @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_684 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 174:57]
|
||||
node _T_685 = bits(_T_684, 0, 0) @[el2_lsu_stbuf.scala 174:67]
|
||||
inst rvclkhdr_7 of rvclkhdr_7 @[beh_lib.scala 352:21]
|
||||
rvclkhdr_7.clock <= clock
|
||||
rvclkhdr_7.reset <= reset
|
||||
rvclkhdr_7.io.clk <= clock @[beh_lib.scala 354:16]
|
||||
rvclkhdr_7.io.en <= _T_685 @[beh_lib.scala 355:15]
|
||||
rvclkhdr_7.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22]
|
||||
reg _T_686 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14]
|
||||
_T_686 <= stbuf_datain[3] @[beh_lib.scala 358:14]
|
||||
stbuf_data[3] <= _T_686 @[el2_lsu_stbuf.scala 174:20]
|
||||
reg _T_687 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 176:53]
|
||||
_T_687 <= ldst_dual_d @[el2_lsu_stbuf.scala 176:53]
|
||||
|
|
|
|||
277
el2_lsu_stbuf.v
277
el2_lsu_stbuf.v
|
|
@ -1,3 +1,24 @@
|
|||
module rvclkhdr(
|
||||
output io_l1clk,
|
||||
input io_clk,
|
||||
input io_en,
|
||||
input io_scan_mode
|
||||
);
|
||||
wire clkhdr_Q; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_CK; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_EN; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_SE; // @[beh_lib.scala 332:24]
|
||||
TEC_RV_ICG clkhdr ( // @[beh_lib.scala 332:24]
|
||||
.Q(clkhdr_Q),
|
||||
.CK(clkhdr_CK),
|
||||
.EN(clkhdr_EN),
|
||||
.SE(clkhdr_SE)
|
||||
);
|
||||
assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 333:12]
|
||||
assign clkhdr_CK = io_clk; // @[beh_lib.scala 334:16]
|
||||
assign clkhdr_EN = io_en; // @[beh_lib.scala 335:16]
|
||||
assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 336:16]
|
||||
endmodule
|
||||
module el2_lsu_stbuf(
|
||||
input clock,
|
||||
input reset,
|
||||
|
|
@ -87,20 +108,52 @@ module el2_lsu_stbuf(
|
|||
reg [31:0] _RAND_22;
|
||||
reg [31:0] _RAND_23;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire rvclkhdr_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_2_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_2_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_2_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_2_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_3_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_3_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_3_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_3_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_4_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_4_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_4_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_4_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_5_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_5_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_5_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_5_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_6_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_6_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_6_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_6_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_7_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_7_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_7_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_7_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire [1:0] _T_5 = io_lsu_pkt_r_half ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_6 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [7:0] _T_7 = io_lsu_pkt_r_dword ? 8'hff : 8'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _GEN_18 = {{1'd0}, io_lsu_pkt_r_by}; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_8 = _GEN_18 | _T_5; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_19 = {{2'd0}, _T_8}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_9 = _GEN_19 | _T_6; // @[Mux.scala 27:72]
|
||||
wire [7:0] _GEN_20 = {{4'd0}, _T_9}; // @[Mux.scala 27:72]
|
||||
wire [7:0] ldst_byteen_r = _GEN_20 | _T_7; // @[Mux.scala 27:72]
|
||||
wire [1:0] _GEN_10 = {{1'd0}, io_lsu_pkt_r_by}; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_8 = _GEN_10 | _T_5; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_11 = {{2'd0}, _T_8}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_9 = _GEN_11 | _T_6; // @[Mux.scala 27:72]
|
||||
wire [7:0] _GEN_12 = {{4'd0}, _T_9}; // @[Mux.scala 27:72]
|
||||
wire [7:0] ldst_byteen_r = _GEN_12 | _T_7; // @[Mux.scala 27:72]
|
||||
wire ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[el2_lsu_stbuf.scala 118:40]
|
||||
reg ldst_dual_r; // @[el2_lsu_stbuf.scala 177:53]
|
||||
wire dual_stbuf_write_r = ldst_dual_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 119:41]
|
||||
wire [10:0] _GEN_21 = {{3'd0}, ldst_byteen_r}; // @[el2_lsu_stbuf.scala 121:40]
|
||||
wire [10:0] _T_14 = _GEN_21 << io_lsu_addr_r[1:0]; // @[el2_lsu_stbuf.scala 121:40]
|
||||
wire [10:0] _GEN_13 = {{3'd0}, ldst_byteen_r}; // @[el2_lsu_stbuf.scala 121:40]
|
||||
wire [10:0] _T_14 = _GEN_13 << io_lsu_addr_r[1:0]; // @[el2_lsu_stbuf.scala 121:40]
|
||||
wire [7:0] store_byteen_ext_r = _T_14[7:0]; // @[el2_lsu_stbuf.scala 121:23]
|
||||
wire [3:0] _T_17 = io_lsu_pkt_r_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] store_byteen_hi_r = store_byteen_ext_r[7:4] & _T_17; // @[el2_lsu_stbuf.scala 122:52]
|
||||
|
|
@ -110,7 +163,7 @@ module el2_lsu_stbuf(
|
|||
reg [1:0] WrPtr; // @[Reg.scala 27:20]
|
||||
wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[el2_lsu_stbuf.scala 126:27]
|
||||
wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[el2_lsu_stbuf.scala 127:27]
|
||||
reg [15:0] stbuf_addr_0; // @[Reg.scala 27:20]
|
||||
reg [15:0] stbuf_addr_0; // @[beh_lib.scala 358:14]
|
||||
wire _T_27 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120]
|
||||
reg _T_588; // @[el2_lsu_stbuf.scala 164:88]
|
||||
reg _T_580; // @[el2_lsu_stbuf.scala 164:88]
|
||||
|
|
@ -137,21 +190,21 @@ module el2_lsu_stbuf(
|
|||
wire [3:0] stbuf_reset = {_T_215,_T_211,_T_207,_T_203}; // @[Cat.scala 29:58]
|
||||
wire _T_34 = ~stbuf_reset[0]; // @[el2_lsu_stbuf.scala 131:218]
|
||||
wire _T_35 = _T_32 & _T_34; // @[el2_lsu_stbuf.scala 131:216]
|
||||
reg [15:0] stbuf_addr_1; // @[Reg.scala 27:20]
|
||||
reg [15:0] stbuf_addr_1; // @[beh_lib.scala 358:14]
|
||||
wire _T_38 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120]
|
||||
wire _T_40 = _T_38 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 131:179]
|
||||
wire _T_42 = ~stbuf_dma_kill[1]; // @[el2_lsu_stbuf.scala 131:197]
|
||||
wire _T_43 = _T_40 & _T_42; // @[el2_lsu_stbuf.scala 131:195]
|
||||
wire _T_45 = ~stbuf_reset[1]; // @[el2_lsu_stbuf.scala 131:218]
|
||||
wire _T_46 = _T_43 & _T_45; // @[el2_lsu_stbuf.scala 131:216]
|
||||
reg [15:0] stbuf_addr_2; // @[Reg.scala 27:20]
|
||||
reg [15:0] stbuf_addr_2; // @[beh_lib.scala 358:14]
|
||||
wire _T_49 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120]
|
||||
wire _T_51 = _T_49 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 131:179]
|
||||
wire _T_53 = ~stbuf_dma_kill[2]; // @[el2_lsu_stbuf.scala 131:197]
|
||||
wire _T_54 = _T_51 & _T_53; // @[el2_lsu_stbuf.scala 131:195]
|
||||
wire _T_56 = ~stbuf_reset[2]; // @[el2_lsu_stbuf.scala 131:218]
|
||||
wire _T_57 = _T_54 & _T_56; // @[el2_lsu_stbuf.scala 131:216]
|
||||
reg [15:0] stbuf_addr_3; // @[Reg.scala 27:20]
|
||||
reg [15:0] stbuf_addr_3; // @[beh_lib.scala 358:14]
|
||||
wire _T_60 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120]
|
||||
wire _T_62 = _T_60 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 131:179]
|
||||
wire _T_64 = ~stbuf_dma_kill[3]; // @[el2_lsu_stbuf.scala 131:197]
|
||||
|
|
@ -268,28 +321,28 @@ module el2_lsu_stbuf(
|
|||
wire [3:0] stbuf_byteenin_3 = sel_lo[3] ? _T_286 : _T_287; // @[el2_lsu_stbuf.scala 146:59]
|
||||
wire _T_291 = ~stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 148:68]
|
||||
wire _T_293 = _T_291 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 148:88]
|
||||
reg [31:0] stbuf_data_0; // @[Reg.scala 27:20]
|
||||
reg [31:0] stbuf_data_0; // @[beh_lib.scala 358:14]
|
||||
wire [7:0] _T_296 = _T_293 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 148:67]
|
||||
wire _T_300 = _T_291 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 149:31]
|
||||
wire [7:0] _T_303 = _T_300 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 149:10]
|
||||
wire [7:0] datain1_0 = sel_lo[0] ? _T_296 : _T_303; // @[el2_lsu_stbuf.scala 148:52]
|
||||
wire _T_307 = ~stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 148:68]
|
||||
wire _T_309 = _T_307 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 148:88]
|
||||
reg [31:0] stbuf_data_1; // @[Reg.scala 27:20]
|
||||
reg [31:0] stbuf_data_1; // @[beh_lib.scala 358:14]
|
||||
wire [7:0] _T_312 = _T_309 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 148:67]
|
||||
wire _T_316 = _T_307 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 149:31]
|
||||
wire [7:0] _T_319 = _T_316 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 149:10]
|
||||
wire [7:0] datain1_1 = sel_lo[1] ? _T_312 : _T_319; // @[el2_lsu_stbuf.scala 148:52]
|
||||
wire _T_323 = ~stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 148:68]
|
||||
wire _T_325 = _T_323 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 148:88]
|
||||
reg [31:0] stbuf_data_2; // @[Reg.scala 27:20]
|
||||
reg [31:0] stbuf_data_2; // @[beh_lib.scala 358:14]
|
||||
wire [7:0] _T_328 = _T_325 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 148:67]
|
||||
wire _T_332 = _T_323 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 149:31]
|
||||
wire [7:0] _T_335 = _T_332 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 149:10]
|
||||
wire [7:0] datain1_2 = sel_lo[2] ? _T_328 : _T_335; // @[el2_lsu_stbuf.scala 148:52]
|
||||
wire _T_339 = ~stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 148:68]
|
||||
wire _T_341 = _T_339 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 148:88]
|
||||
reg [31:0] stbuf_data_3; // @[Reg.scala 27:20]
|
||||
reg [31:0] stbuf_data_3; // @[beh_lib.scala 358:14]
|
||||
wire [7:0] _T_344 = _T_341 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 148:67]
|
||||
wire _T_348 = _T_339 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 149:31]
|
||||
wire [7:0] _T_351 = _T_348 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 149:10]
|
||||
|
|
@ -366,10 +419,14 @@ module el2_lsu_stbuf(
|
|||
wire _T_540 = _T_531 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 158:31]
|
||||
wire [7:0] _T_543 = _T_540 ? io_store_datafn_hi_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 158:10]
|
||||
wire [7:0] datain4_3 = sel_lo[3] ? _T_536 : _T_543; // @[el2_lsu_stbuf.scala 157:53]
|
||||
wire [31:0] stbuf_datain_0 = {datain4_0,datain3_0,datain2_0,datain1_0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] stbuf_datain_1 = {datain4_1,datain3_1,datain2_1,datain1_1}; // @[Cat.scala 29:58]
|
||||
wire [31:0] stbuf_datain_2 = {datain4_2,datain3_2,datain2_2,datain1_2}; // @[Cat.scala 29:58]
|
||||
wire [31:0] stbuf_datain_3 = {datain4_3,datain3_3,datain2_3,datain1_3}; // @[Cat.scala 29:58]
|
||||
wire [15:0] _T_545 = {datain2_0,datain1_0}; // @[Cat.scala 29:58]
|
||||
wire [15:0] _T_546 = {datain4_0,datain3_0}; // @[Cat.scala 29:58]
|
||||
wire [15:0] _T_548 = {datain2_1,datain1_1}; // @[Cat.scala 29:58]
|
||||
wire [15:0] _T_549 = {datain4_1,datain3_1}; // @[Cat.scala 29:58]
|
||||
wire [15:0] _T_551 = {datain2_2,datain1_2}; // @[Cat.scala 29:58]
|
||||
wire [15:0] _T_552 = {datain4_2,datain3_2}; // @[Cat.scala 29:58]
|
||||
wire [15:0] _T_554 = {datain2_3,datain1_3}; // @[Cat.scala 29:58]
|
||||
wire [15:0] _T_555 = {datain4_3,datain3_3}; // @[Cat.scala 29:58]
|
||||
wire _T_560 = stbuf_wr_en[0] | stbuf_vld[0]; // @[el2_lsu_stbuf.scala 164:92]
|
||||
wire _T_568 = stbuf_wr_en[1] | stbuf_vld[1]; // @[el2_lsu_stbuf.scala 164:92]
|
||||
wire _T_576 = stbuf_wr_en[2] | stbuf_vld[2]; // @[el2_lsu_stbuf.scala 164:92]
|
||||
|
|
@ -446,10 +503,10 @@ module el2_lsu_stbuf(
|
|||
wire _T_699 = _T_689[0] & _T_698; // @[el2_lsu_stbuf.scala 181:45]
|
||||
wire _T_700 = |stbuf_dma_kill_en; // @[el2_lsu_stbuf.scala 181:92]
|
||||
wire _T_701 = ~_T_700; // @[el2_lsu_stbuf.scala 181:72]
|
||||
wire [15:0] _GEN_9 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[el2_lsu_stbuf.scala 182:23]
|
||||
wire [15:0] _GEN_10 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_9; // @[el2_lsu_stbuf.scala 182:23]
|
||||
wire [31:0] _GEN_13 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[el2_lsu_stbuf.scala 183:23]
|
||||
wire [31:0] _GEN_14 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_13; // @[el2_lsu_stbuf.scala 183:23]
|
||||
wire [15:0] _GEN_1 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[el2_lsu_stbuf.scala 182:23]
|
||||
wire [15:0] _GEN_2 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_1; // @[el2_lsu_stbuf.scala 182:23]
|
||||
wire [31:0] _GEN_5 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[el2_lsu_stbuf.scala 183:23]
|
||||
wire [31:0] _GEN_6 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_5; // @[el2_lsu_stbuf.scala 183:23]
|
||||
wire _T_703 = ~dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 185:44]
|
||||
wire _T_704 = io_ldst_stbuf_reqvld_r & _T_703; // @[el2_lsu_stbuf.scala 185:42]
|
||||
wire _T_705 = store_coalesce_hi_r | store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 185:88]
|
||||
|
|
@ -478,12 +535,12 @@ module el2_lsu_stbuf(
|
|||
wire isdccmst_r = _T_738 & _T_739; // @[el2_lsu_stbuf.scala 196:81]
|
||||
wire [1:0] _T_740 = {1'h0,isdccmst_m}; // @[Cat.scala 29:58]
|
||||
wire _T_741 = isdccmst_m & ldst_dual_m; // @[el2_lsu_stbuf.scala 198:63]
|
||||
wire [2:0] _GEN_22 = {{1'd0}, _T_740}; // @[el2_lsu_stbuf.scala 198:48]
|
||||
wire [2:0] _T_742 = _GEN_22 << _T_741; // @[el2_lsu_stbuf.scala 198:48]
|
||||
wire [2:0] _GEN_14 = {{1'd0}, _T_740}; // @[el2_lsu_stbuf.scala 198:48]
|
||||
wire [2:0] _T_742 = _GEN_14 << _T_741; // @[el2_lsu_stbuf.scala 198:48]
|
||||
wire [1:0] _T_743 = {1'h0,isdccmst_r}; // @[Cat.scala 29:58]
|
||||
wire _T_744 = isdccmst_r & ldst_dual_r; // @[el2_lsu_stbuf.scala 199:63]
|
||||
wire [2:0] _GEN_23 = {{1'd0}, _T_743}; // @[el2_lsu_stbuf.scala 199:48]
|
||||
wire [2:0] _T_745 = _GEN_23 << _T_744; // @[el2_lsu_stbuf.scala 199:48]
|
||||
wire [2:0] _GEN_15 = {{1'd0}, _T_743}; // @[el2_lsu_stbuf.scala 199:48]
|
||||
wire [2:0] _T_745 = _GEN_15 << _T_744; // @[el2_lsu_stbuf.scala 199:48]
|
||||
wire [1:0] stbuf_specvld_m = _T_742[1:0]; // @[el2_lsu_stbuf.scala 198:20]
|
||||
wire [3:0] _T_746 = {2'h0,stbuf_specvld_m}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_748 = stbuf_numvld_any + _T_746; // @[el2_lsu_stbuf.scala 200:45]
|
||||
|
|
@ -670,10 +727,10 @@ module el2_lsu_stbuf(
|
|||
wire [7:0] _T_1179 = ld_byte_rhit_lo_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [7:0] _T_1181 = _T_1179 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 246:54]
|
||||
wire [7:0] _T_1184 = ld_byte_rhit_hi_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [23:0] _GEN_25 = {{16'd0}, _T_1184}; // @[el2_lsu_stbuf.scala 246:117]
|
||||
wire [23:0] _T_1186 = _GEN_25 & io_store_data_hi_r[31:8]; // @[el2_lsu_stbuf.scala 246:117]
|
||||
wire [23:0] _GEN_26 = {{16'd0}, _T_1181}; // @[el2_lsu_stbuf.scala 246:83]
|
||||
wire [23:0] fwdpipe4_lo = _GEN_26 | _T_1186; // @[el2_lsu_stbuf.scala 246:83]
|
||||
wire [23:0] _GEN_17 = {{16'd0}, _T_1184}; // @[el2_lsu_stbuf.scala 246:117]
|
||||
wire [23:0] _T_1186 = _GEN_17 & io_store_data_hi_r[31:8]; // @[el2_lsu_stbuf.scala 246:117]
|
||||
wire [23:0] _GEN_18 = {{16'd0}, _T_1181}; // @[el2_lsu_stbuf.scala 246:83]
|
||||
wire [23:0] fwdpipe4_lo = _GEN_18 | _T_1186; // @[el2_lsu_stbuf.scala 246:83]
|
||||
wire [47:0] _T_1189 = {fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo}; // @[Cat.scala 29:58]
|
||||
wire [7:0] _T_1192 = ld_byte_rhit_lo_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [7:0] _T_1194 = _T_1192 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 249:54]
|
||||
|
|
@ -693,10 +750,10 @@ module el2_lsu_stbuf(
|
|||
wire [7:0] _T_1222 = ld_byte_rhit_lo_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [7:0] _T_1224 = _T_1222 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 252:54]
|
||||
wire [7:0] _T_1227 = ld_byte_rhit_hi_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [23:0] _GEN_27 = {{16'd0}, _T_1227}; // @[el2_lsu_stbuf.scala 252:117]
|
||||
wire [23:0] _T_1229 = _GEN_27 & io_store_data_hi_r[31:8]; // @[el2_lsu_stbuf.scala 252:117]
|
||||
wire [23:0] _GEN_28 = {{16'd0}, _T_1224}; // @[el2_lsu_stbuf.scala 252:83]
|
||||
wire [23:0] fwdpipe4_hi = _GEN_28 | _T_1229; // @[el2_lsu_stbuf.scala 252:83]
|
||||
wire [23:0] _GEN_19 = {{16'd0}, _T_1227}; // @[el2_lsu_stbuf.scala 252:117]
|
||||
wire [23:0] _T_1229 = _GEN_19 & io_store_data_hi_r[31:8]; // @[el2_lsu_stbuf.scala 252:117]
|
||||
wire [23:0] _GEN_20 = {{16'd0}, _T_1224}; // @[el2_lsu_stbuf.scala 252:83]
|
||||
wire [23:0] fwdpipe4_hi = _GEN_20 | _T_1229; // @[el2_lsu_stbuf.scala 252:83]
|
||||
wire [47:0] _T_1232 = {fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi}; // @[Cat.scala 29:58]
|
||||
wire _T_1264 = ld_byte_rhit_hi[0] | stbuf_fwdbyteen_hi_pre_m_0; // @[el2_lsu_stbuf.scala 258:84]
|
||||
wire _T_1266 = ld_byte_rhit_hi[1] | stbuf_fwdbyteen_hi_pre_m_1; // @[el2_lsu_stbuf.scala 258:84]
|
||||
|
|
@ -722,10 +779,58 @@ module el2_lsu_stbuf(
|
|||
wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[el2_lsu_stbuf.scala 271:31]
|
||||
wire [15:0] _T_1312 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58]
|
||||
wire [15:0] _T_1313 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58]
|
||||
rvclkhdr rvclkhdr ( // @[beh_lib.scala 352:21]
|
||||
.io_l1clk(rvclkhdr_io_l1clk),
|
||||
.io_clk(rvclkhdr_io_clk),
|
||||
.io_en(rvclkhdr_io_en),
|
||||
.io_scan_mode(rvclkhdr_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 352:21]
|
||||
.io_l1clk(rvclkhdr_1_io_l1clk),
|
||||
.io_clk(rvclkhdr_1_io_clk),
|
||||
.io_en(rvclkhdr_1_io_en),
|
||||
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_2 ( // @[beh_lib.scala 352:21]
|
||||
.io_l1clk(rvclkhdr_2_io_l1clk),
|
||||
.io_clk(rvclkhdr_2_io_clk),
|
||||
.io_en(rvclkhdr_2_io_en),
|
||||
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_3 ( // @[beh_lib.scala 352:21]
|
||||
.io_l1clk(rvclkhdr_3_io_l1clk),
|
||||
.io_clk(rvclkhdr_3_io_clk),
|
||||
.io_en(rvclkhdr_3_io_en),
|
||||
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_4 ( // @[beh_lib.scala 352:21]
|
||||
.io_l1clk(rvclkhdr_4_io_l1clk),
|
||||
.io_clk(rvclkhdr_4_io_clk),
|
||||
.io_en(rvclkhdr_4_io_en),
|
||||
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_5 ( // @[beh_lib.scala 352:21]
|
||||
.io_l1clk(rvclkhdr_5_io_l1clk),
|
||||
.io_clk(rvclkhdr_5_io_clk),
|
||||
.io_en(rvclkhdr_5_io_en),
|
||||
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_6 ( // @[beh_lib.scala 352:21]
|
||||
.io_l1clk(rvclkhdr_6_io_l1clk),
|
||||
.io_clk(rvclkhdr_6_io_clk),
|
||||
.io_en(rvclkhdr_6_io_en),
|
||||
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_7 ( // @[beh_lib.scala 352:21]
|
||||
.io_l1clk(rvclkhdr_7_io_l1clk),
|
||||
.io_clk(rvclkhdr_7_io_clk),
|
||||
.io_en(rvclkhdr_7_io_en),
|
||||
.io_scan_mode(rvclkhdr_7_io_scan_mode)
|
||||
);
|
||||
assign io_stbuf_reqvld_any = _T_699 & _T_701; // @[el2_lsu_stbuf.scala 52:47 el2_lsu_stbuf.scala 181:25]
|
||||
assign io_stbuf_reqvld_flushed_any = _T_689[0] & _T_691[0]; // @[el2_lsu_stbuf.scala 53:36 el2_lsu_stbuf.scala 180:32]
|
||||
assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_10; // @[el2_lsu_stbuf.scala 54:35 el2_lsu_stbuf.scala 182:23]
|
||||
assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_14; // @[el2_lsu_stbuf.scala 55:35 el2_lsu_stbuf.scala 183:23]
|
||||
assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_2; // @[el2_lsu_stbuf.scala 54:35 el2_lsu_stbuf.scala 182:23]
|
||||
assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_6; // @[el2_lsu_stbuf.scala 55:35 el2_lsu_stbuf.scala 183:23]
|
||||
assign io_lsu_stbuf_full_any = _T_752 ? _T_754 : _T_755; // @[el2_lsu_stbuf.scala 56:43 el2_lsu_stbuf.scala 202:27]
|
||||
assign io_lsu_stbuf_empty_any = stbuf_numvld_any == 4'h0; // @[el2_lsu_stbuf.scala 57:43 el2_lsu_stbuf.scala 203:27]
|
||||
assign io_ldst_stbuf_reqvld_r = io_lsu_commit_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 58:43 el2_lsu_stbuf.scala 129:27]
|
||||
|
|
@ -733,6 +838,30 @@ module el2_lsu_stbuf(
|
|||
assign io_stbuf_fwddata_lo_m = {_T_1298,_T_1297}; // @[el2_lsu_stbuf.scala 60:43 el2_lsu_stbuf.scala 266:26]
|
||||
assign io_stbuf_fwdbyteen_hi_m = {_T_1272,_T_1264}; // @[el2_lsu_stbuf.scala 61:37 el2_lsu_stbuf.scala 258:28]
|
||||
assign io_stbuf_fwdbyteen_lo_m = {_T_1283,_T_1275}; // @[el2_lsu_stbuf.scala 62:37 el2_lsu_stbuf.scala 259:28]
|
||||
assign rvclkhdr_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
assign rvclkhdr_2_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
assign rvclkhdr_3_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
assign rvclkhdr_4_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
assign rvclkhdr_5_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
assign rvclkhdr_6_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
assign rvclkhdr_7_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -920,15 +1049,13 @@ end // initial
|
|||
end
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
stbuf_addr_0 <= 16'h0;
|
||||
end else if (stbuf_wr_en[0]) begin
|
||||
if (sel_lo[0]) begin
|
||||
stbuf_addr_0 <= io_lsu_addr_r[15:0];
|
||||
end else begin
|
||||
stbuf_addr_0 <= io_end_addr_r[15:0];
|
||||
end
|
||||
end else if (sel_lo[0]) begin
|
||||
stbuf_addr_0 <= io_lsu_addr_r[15:0];
|
||||
end else begin
|
||||
stbuf_addr_0 <= io_end_addr_r[15:0];
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
||||
|
|
@ -987,37 +1114,31 @@ end // initial
|
|||
_T_599 <= _T_595 & _T_34;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
stbuf_addr_1 <= 16'h0;
|
||||
end else if (stbuf_wr_en[1]) begin
|
||||
if (sel_lo[1]) begin
|
||||
stbuf_addr_1 <= io_lsu_addr_r[15:0];
|
||||
end else begin
|
||||
stbuf_addr_1 <= io_end_addr_r[15:0];
|
||||
end
|
||||
end else if (sel_lo[1]) begin
|
||||
stbuf_addr_1 <= io_lsu_addr_r[15:0];
|
||||
end else begin
|
||||
stbuf_addr_1 <= io_end_addr_r[15:0];
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
stbuf_addr_2 <= 16'h0;
|
||||
end else if (stbuf_wr_en[2]) begin
|
||||
if (sel_lo[2]) begin
|
||||
stbuf_addr_2 <= io_lsu_addr_r[15:0];
|
||||
end else begin
|
||||
stbuf_addr_2 <= io_end_addr_r[15:0];
|
||||
end
|
||||
end else if (sel_lo[2]) begin
|
||||
stbuf_addr_2 <= io_lsu_addr_r[15:0];
|
||||
end else begin
|
||||
stbuf_addr_2 <= io_end_addr_r[15:0];
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
stbuf_addr_3 <= 16'h0;
|
||||
end else if (stbuf_wr_en[3]) begin
|
||||
if (sel_lo[3]) begin
|
||||
stbuf_addr_3 <= io_lsu_addr_r[15:0];
|
||||
end else begin
|
||||
stbuf_addr_3 <= io_end_addr_r[15:0];
|
||||
end
|
||||
end else if (sel_lo[3]) begin
|
||||
stbuf_addr_3 <= io_lsu_addr_r[15:0];
|
||||
end else begin
|
||||
stbuf_addr_3 <= io_end_addr_r[15:0];
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
||||
|
|
@ -1048,32 +1169,32 @@ end // initial
|
|||
stbuf_byteen_3 <= _T_656 & _T_660;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
stbuf_data_0 <= 32'h0;
|
||||
end else if (stbuf_wr_en[0]) begin
|
||||
stbuf_data_0 <= stbuf_datain_0;
|
||||
end else begin
|
||||
stbuf_data_0 <= {_T_546,_T_545};
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
stbuf_data_1 <= 32'h0;
|
||||
end else if (stbuf_wr_en[1]) begin
|
||||
stbuf_data_1 <= stbuf_datain_1;
|
||||
end else begin
|
||||
stbuf_data_1 <= {_T_549,_T_548};
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
stbuf_data_2 <= 32'h0;
|
||||
end else if (stbuf_wr_en[2]) begin
|
||||
stbuf_data_2 <= stbuf_datain_2;
|
||||
end else begin
|
||||
stbuf_data_2 <= {_T_552,_T_551};
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
stbuf_data_3 <= 32'h0;
|
||||
end else if (stbuf_wr_en[3]) begin
|
||||
stbuf_data_3 <= stbuf_datain_3;
|
||||
end else begin
|
||||
stbuf_data_3 <= {_T_555,_T_554};
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||
|
|
|
|||
2454
el2_lsu_trigger.fir
2454
el2_lsu_trigger.fir
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Load Diff
1148
el2_lsu_trigger.v
1148
el2_lsu_trigger.v
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|
|
@ -1 +1 @@
|
|||
-1013773556
|
||||
-2044733690
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -1 +1 @@
|
|||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-structure-extractor\",\"revision\":\"2018.2.1+4-88400d3f\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea1.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-shell\",\"revision\":\"2018.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea1.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-compiler-indices\",\"revision\":\"0.1.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea1.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"}}
|
||||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-structure-extractor\",\"revision\":\"2018.2.1+4-88400d3f\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea2.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-shell\",\"revision\":\"2018.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea2.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-compiler-indices\",\"revision\":\"0.1.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea2.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"}}
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,37 @@
|
|||
package dmi
|
||||
import chisel3._
|
||||
import scala.collection._
|
||||
import chisel3.util._
|
||||
import include._
|
||||
import lib._
|
||||
|
||||
class dmi_jtag_to_core_sync extends Module with el2_lib with RequireAsyncReset {
|
||||
val io = IO(new Bundle{
|
||||
// JTAG signals
|
||||
val rd_en = Input(UInt(1.W))// 1 bit Read Enable from JTAG
|
||||
val wr_en = Input(UInt(1.W))// 1 bit Write enable from JTAG
|
||||
|
||||
// Processor Signals
|
||||
// val rst_n = Input(Bool()) // Core reset
|
||||
// val clk = Input(Bool()) // Core clock
|
||||
val reg_en = Output(UInt(1.W)) // 1 bit Write interface bit to Processor
|
||||
val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor
|
||||
})
|
||||
val c_rd_en =WireInit(0.U(1.W))
|
||||
val c_wr_en =WireInit(0.U(1.W))
|
||||
val rden =WireInit(0.U(3.W))
|
||||
val wren =WireInit(0.U(3.W))
|
||||
|
||||
// synchronizers
|
||||
rden := RegNext(Cat(rden(1,0),io.rd_en),0.U)
|
||||
wren := RegNext(Cat(wren(1,0),io.wr_en),0.U)
|
||||
c_rd_en := rden(1) & !rden(2)
|
||||
c_wr_en := wren(1) & !wren(2)
|
||||
// Outputs
|
||||
io.reg_en := c_wr_en | c_rd_en
|
||||
io.reg_wr_en := c_wr_en
|
||||
}
|
||||
object dmijtag_main extends App{
|
||||
println("Generate Verilog")
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new dmi_jtag_to_core_sync()))
|
||||
}
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
package dmi
|
||||
import chisel3._
|
||||
import scala.collection._
|
||||
import chisel3.util._
|
||||
import include._
|
||||
import lib._
|
||||
|
||||
class dmi_wrapper extends Module with el2_lib with RequireAsyncReset {
|
||||
val io = IO(new Bundle{
|
||||
// JTAG signals
|
||||
//val trst_n =Input(UInt(1.W)) // JTAG reset
|
||||
//val tck =Input(UInt(1.W)) // JTAG clock
|
||||
val tms =Input(UInt(1.W)) // Test mode select
|
||||
val tdi =Input(UInt(1.W)) // Test Data Input
|
||||
val tdo =Output(UInt(1.W)) // Test Data Output
|
||||
val tdoEnable =Output(UInt(1.W)) // Test Data Output enable
|
||||
|
||||
// Processor Signals
|
||||
// val core_rst_n =Input(UInt(1.W)) // Core reset
|
||||
// val core_clk =Input(UInt(1.W)) // Core clock
|
||||
val jtag_id = Input(UInt(32.W)) // JTAG ID
|
||||
val rd_data = Input(UInt(32.W)) // 32 bit Read data from Processor
|
||||
val reg_wr_data = Output(UInt(32.W)) // 32 bit Write data to Processor
|
||||
val reg_wr_addr = Output(UInt(7.W)) // 7 bit reg address to Processor
|
||||
val reg_en = Output(UInt(1.W)) // 1 bit Read enable to Processor
|
||||
val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor
|
||||
val dmi_hard_reset = Output(UInt(1.W))
|
||||
})
|
||||
//Wire Declaration
|
||||
val rd_en = WireInit(0.U(1.W))
|
||||
val wr_en = WireInit(0.U(1.W))
|
||||
val dmireset = WireInit(0.U(1.W))
|
||||
|
||||
//jtag_tap instantiation
|
||||
val i_jtag_tap = Module(new rvjtag_tap())
|
||||
//.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
|
||||
//.tck(tck), // dedicated JTAG TCK pad signal
|
||||
i_jtag_tap.io.tms := io.tms // dedicated JTAG TMS pad signal
|
||||
i_jtag_tap.io.tdi := io.tdi // dedicated JTAG TDI pad signal
|
||||
io.tdo := i_jtag_tap.io.tdo // dedicated JTAG TDO pad signal
|
||||
io.tdoEnable := i_jtag_tap.io.tdoEnable // enable for TDO pad
|
||||
io.reg_wr_data := i_jtag_tap.io.wr_data // 32 bit Write data
|
||||
io.reg_wr_addr := i_jtag_tap.io.wr_addr // 7 bit Write address
|
||||
rd_en := i_jtag_tap.io.rd_en // 1 bit read enable
|
||||
wr_en := i_jtag_tap.io.wr_en // 1 bit Write enable
|
||||
i_jtag_tap.io.rd_data := io.rd_data // 32 bit Read data
|
||||
i_jtag_tap.io.rd_status := 0.U(2.W)
|
||||
i_jtag_tap.io.idle := 0.U(3.W) // no need to wait to sample data
|
||||
i_jtag_tap.io.dmi_stat := 0.U(2.W) // no need to wait or error possible
|
||||
i_jtag_tap.io.version := 1.U(4.W) // debug spec 0.13 compliant
|
||||
i_jtag_tap.io.jtag_id := io.jtag_id
|
||||
io.dmi_hard_reset := i_jtag_tap.io.dmi_hard_reset
|
||||
dmireset := i_jtag_tap.io.dmi_reset
|
||||
|
||||
// dmi_jtag_to_core_sync instantiation
|
||||
val i_dmi_jtag_to_core_sync = Module(new dmi_jtag_to_core_sync())
|
||||
i_dmi_jtag_to_core_sync.io.wr_en := wr_en // 1 bit Write enable
|
||||
i_dmi_jtag_to_core_sync.io.rd_en := rd_en // 1 bit Read enable
|
||||
|
||||
io.reg_en :=i_dmi_jtag_to_core_sync.io.reg_en // 1 bit Write interface bit
|
||||
io.reg_wr_en := i_dmi_jtag_to_core_sync.io.reg_wr_en // 1 bit Write enable
|
||||
}
|
||||
object dmiwrapper_main extends App{
|
||||
println("Generate Verilog")
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new dmi_wrapper()))
|
||||
}
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
package dmi
|
||||
import chisel3._
|
||||
import scala.collection._
|
||||
import chisel3.util._
|
||||
import include._
|
||||
import lib._
|
||||
|
||||
class rvjtag_tap extends Module with el2_lib with RequireAsyncReset {
|
||||
val io = IO(new Bundle{
|
||||
val trst = Input(Bool())
|
||||
val tck = Input(Bool())
|
||||
val tms = Input(Bool())
|
||||
val tdi = Input(Bool())
|
||||
val dmi_reset = Input(Bool())
|
||||
val dmi_hard_reset = Input(Bool())
|
||||
val rd_status = Input(UInt(2.W))
|
||||
val dmi_stat = Input(UInt(2.W))
|
||||
val idle = Input(UInt(3.W))
|
||||
val version = Input(UInt(4.W))
|
||||
val jtag_id = Input(UInt(32.W))
|
||||
val rd_data = Input(UInt(32.W))
|
||||
|
||||
val tdo = Output(Bool())
|
||||
val tdoEnable = Output(Bool())
|
||||
val wr_en = Output(Bool())
|
||||
val rd_en = Output(Bool())
|
||||
val wr_data = Output(UInt(32.W))
|
||||
val wr_addr = Output(UInt(AWIDTH.W))
|
||||
})
|
||||
val AWIDTH = 7.U(6.W)
|
||||
val USER_DR_LENGTH = AWIDTH + 34
|
||||
val sr = RegInit(0.U(USER_DR_LENGTH.W))
|
||||
val nsr = RegInit(0.U(USER_DR_LENGTH.W))
|
||||
val dr = RegInit(0.U(USER_DR_LENGTH.W))
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
// Tap controller
|
||||
///////////////////////////////////////////////////////
|
||||
val state = RegInit(test_logic_reset_state)
|
||||
val nstate = RegInit(test_logic_reset_state)
|
||||
//logic[3:0] state, nstate;
|
||||
val ir = WireInit(0.U(5.W))
|
||||
val jtag_reset = WireInit(UInt(1.W))
|
||||
val shift_dr = WireInit(UInt(1.W))
|
||||
val pause_dr = WireInit(UInt(1.W))
|
||||
val update_dr = WireInit(UInt(1.W))
|
||||
val capture_dr = WireInit(UInt(1.W))
|
||||
val shift_ir = WireInit(UInt(1.W))
|
||||
val pause_ir = WireInit(UInt(1.W))
|
||||
val update_ir = WireInit(UInt(1.W))
|
||||
val capture_ir = WireInit(UInt(1.W))
|
||||
val dr_en = WireInit(UInt(2.W))
|
||||
val devid_sel = WireInit(UInt(1.W))
|
||||
val abits = WireInit(UInt(6.W))
|
||||
val abits = AWIDTH(5,0)
|
||||
|
||||
val test_logic_reset_state :: run_test_idle_state :: select_dr_scan_state :: capture_dr_state :: shift_dr_state :: exit1_dr_state :: pause_dr_state :: exit2_dr_state :: update_dr_state :: select_ir_scan_state :: capture_ir_state :: shift_ir_state :: exit1_ir_state :: pause_ir_state :: exit2_ir_state :: update_ir_state :: Nil = Enum(16)
|
||||
switch(state){
|
||||
is(test_logic_reset_state){ nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state)}
|
||||
is(run_test_idle_state){nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) }
|
||||
is(select_dr_scan_state){nstate := Mux(io.tms,select_ir_scan_state,capture_dr_state) }
|
||||
is(capture_dr_state){nstate := Mux(io.tms,exit1_dr_state,shift_dr_state) }
|
||||
is(shift_dr_state){nstate := Mux(io.tms,exit1_dr_state,shift_dr_state) }
|
||||
is(exit1_dr_state){nstate := Mux(io.tms,update_dr_state,pause_dr_state) }
|
||||
is(pause_dr_state){nstate := Mux(io.tms,exit2_dr_state,pause_dr_state) }
|
||||
is(exit2_dr_state){nstate := Mux(io.tms,update_dr_state,shift_dr_state) }
|
||||
is(update_dr_state){nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) }
|
||||
is(select_ir_scan_state){nstate := Mux(io.tms,test_logic_reset_state,capture_ir_state) }
|
||||
is(capture_ir_state){nstate := Mux(io.tms,exit1_ir_state,shift_i``r_state) }
|
||||
is(shift_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) }
|
||||
is(exit1_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) }
|
||||
is(pause_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) }
|
||||
is(exit2_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) }
|
||||
is(update_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) }
|
||||
}
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
|
||||
SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
|
||||
EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE;
|
||||
PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE;
|
||||
EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE;
|
||||
UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,271 @@
|
|||
//import chisel3._
|
||||
//import chisel3.util._
|
||||
//import include._
|
||||
//import lib._
|
||||
//import snapshot._
|
||||
//
|
||||
//class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib {
|
||||
// val io = IO (new Bundle {
|
||||
// val scan_mode = Input(Bool())
|
||||
// val free_clk = Input(Clock () )
|
||||
// val active_clk = Input(Clock () )
|
||||
// val clk_override = Input(Bool () )
|
||||
// val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W))
|
||||
// val picm_rdaddr = Input(UInt(32.W))
|
||||
// val picm_wraddr = Input(UInt(32.W))
|
||||
// val picm_wr_data = Input(UInt(32.W))
|
||||
// val picm_wren = Input(Bool())
|
||||
// val picm_rden = Input(Bool())
|
||||
// val picm_mken = Input(Bool())
|
||||
// val meicurpl = Input(UInt(4.W))
|
||||
// val meipt = Input(UInt(4.W))
|
||||
//
|
||||
// val mexintpend = Output(Bool())
|
||||
// val claimid = Output(UInt(8.W))
|
||||
// val pl = Output(UInt(4.W))
|
||||
// val picm_rd_data = Output(UInt(32.W))
|
||||
// val mhwakeup = Output(Bool())
|
||||
// val test = Output(UInt())
|
||||
// })
|
||||
//
|
||||
// io.mexintpend := 0.U
|
||||
// io.claimid := 0.U
|
||||
// io.pl := 0.U
|
||||
// io.picm_rd_data := 0.U
|
||||
// io.mhwakeup := 0.U
|
||||
//
|
||||
// val NUM_LEVELS = log2Ceil(PIC_TOTAL_INT_PLUS1)
|
||||
// val INTPRIORITY_BASE_ADDR = PIC_BASE_ADDR
|
||||
// val INTPEND_BASE_ADDR = PIC_BASE_ADDR + 0x00001000L
|
||||
// val INTENABLE_BASE_ADDR = PIC_BASE_ADDR + 0x00002000L
|
||||
// val EXT_INTR_PIC_CONFIG = PIC_BASE_ADDR + 0x00003000L
|
||||
// val EXT_INTR_GW_CONFIG = PIC_BASE_ADDR + 0x00004000L
|
||||
// val EXT_INTR_GW_CLEAR = PIC_BASE_ADDR + 0x00005000L
|
||||
//
|
||||
// val INTPEND_SIZE = PIC_TOTAL_INT_PLUS1 match {
|
||||
// case x if x < 32 => 32
|
||||
// case x if x < 64 => 64
|
||||
// case x if x < 128 => 128
|
||||
// case x if x < 256 => 256
|
||||
// case x if x < 512 => 512
|
||||
// case _ => 1024
|
||||
//
|
||||
// }
|
||||
//
|
||||
// val INT_GRPS = INTPEND_SIZE / 32
|
||||
// val INTPRIORITY_BITS = 4
|
||||
// val ID_BITS = 8
|
||||
// val GW_CONFIG = WireInit(UInt(PIC_TOTAL_INT_PLUS1.W), init=0.U)
|
||||
//
|
||||
// // val addr_intpend_base_match = WireInit(0.U(1.W))
|
||||
// // val raddr_config_pic_match = WireInit(0.U(1.W))
|
||||
// // val raddr_intenable_base_match = WireInit(0.U(1.W))
|
||||
//// val raddr_intpriority_base_match = WireInit(0.U(1.W))
|
||||
// // val raddr_config_gw_base_match = WireInit(0.U(1.W))
|
||||
// // val waddr_config_pic_match = WireInit(0.U(1.W))
|
||||
// // val waddr_intpriority_base_match = WireInit(0.U(1.W))
|
||||
// // val waddr_intenable_base_match = WireInit(0.U(1.W))
|
||||
// // val waddr_config_gw_base_match = WireInit(0.U(1.W))
|
||||
// // val addr_clear_gw_base_match = WireInit(0.U(1.W))
|
||||
//// val mexintpend_in = WireInit(0.U(1.W))
|
||||
// // val mhwakeup_in = WireInit(0.U(1.W))
|
||||
// // val intpend_reg_read = WireInit(0.U(1.W))
|
||||
// val picm_rd_data_in = WireInit(0.U(32.W))
|
||||
// val intpend_rd_out = WireInit(0.U(32.W))
|
||||
//// val intenable_rd_out = WireInit(0.U(1.W))
|
||||
// val intpriority_rd_out = WireInit(0.U (INTPRIORITY_BITS.W))
|
||||
// val gw_config_rd_out = WireInit(0.U(2.W))
|
||||
// val intpriority_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))
|
||||
// intpriority_reg := (0 until PIC_TOTAL_INT_PLUS1).map(i => 0.U)
|
||||
// // val intpriority_reg_inv = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))
|
||||
// // intpriority_reg_inv := (0 until PIC_TOTAL_INT_PLUS1).map(i => 0.U)
|
||||
// val intpriority_reg_we = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
|
||||
// val intpriority_reg_re = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
|
||||
// val gw_config_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(2.W)))
|
||||
// val intenable_reg = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
|
||||
// val intenable_reg_we = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
|
||||
// val intenable_reg_re = WireInit(Bool(), init = false.B)
|
||||
// val gw_config_reg_we = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
|
||||
// val gw_config_reg_re = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
|
||||
// val gw_clear_reg_we = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
|
||||
// //
|
||||
// val intpend_reg_extended = WireInit(0.U (INTPEND_SIZE.W))
|
||||
//// val maxint = WireInit(0.U (INTPRIORITY_BITS.W))
|
||||
// val selected_int_priority = WireInit(0.U (INTPRIORITY_BITS.W))
|
||||
//// val intpend_w_prior_en = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))
|
||||
//// val intpend_id = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(ID_BITS.W)))
|
||||
// //val intpend_rd_part_out = Wire(Vec(INT_GRPS,UInt(32.W)))
|
||||
// // val levelx_intpend_w_prior_en = Wire(Vec(NUM_LEVELS - NUM_LEVELS/2 ,Vec ((PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int])+1,UInt(INTPRIORITY_BITS.W))))
|
||||
//// val levelx_intpend_id = Wire(Vec(NUM_LEVELS - NUM_LEVELS/2 ,Vec ((PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int])+1,UInt(ID_BITS.W))))
|
||||
//// val l2_intpend_w_prior_en_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int],UInt(INTPRIORITY_BITS.W)))
|
||||
// // val l2_intpend_id_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int],UInt(ID_BITS.W)))
|
||||
// val config_reg = WireInit(0.U(1.W))
|
||||
//// val intpriord = WireInit(0.U(1.W))
|
||||
//// val config_reg_we = WireInit(0.U(1.W))
|
||||
//// val config_reg_re = WireInit(0.U(1.W))
|
||||
//// val config_reg_in = WireInit(0.U(1.W))
|
||||
// val prithresh_reg_write = WireInit(0.U(1.W))
|
||||
// val prithresh_reg_read = WireInit(0.U(1.W))
|
||||
// // val intpriority_reg_read = WireInit(0.U(1.W))
|
||||
// //val intenable_reg_read = WireInit(0.U(1.W))
|
||||
// //val gw_config_reg_read = WireInit(0.U(1.W))
|
||||
// val picm_wren_ff = WireInit(0.U(1.W))
|
||||
// val picm_rden_ff = WireInit(0.U(1.W))
|
||||
// val picm_raddr_ff = WireInit(0.U(32.W))
|
||||
// val picm_waddr_ff = WireInit(0.U(32.W))
|
||||
// val picm_wr_data_ff = WireInit(0.U(32.W))
|
||||
// val mask = WireInit(0.U(4.W))
|
||||
// val picm_mken_ff = WireInit(0.U(1.W))
|
||||
// val claimid_in = WireInit(0.U(ID_BITS.W))
|
||||
// val pl_in = WireInit(0.U(INTPRIORITY_BITS.W))
|
||||
// // val pl_in_q = WireInit(0.U(INTPRIORITY_BITS.W))
|
||||
// val extintsrc_req_sync = WireInit(0.U(PIC_TOTAL_INT_PLUS1.W))
|
||||
// val extintsrc_req_gw = WireInit(0.U(PIC_TOTAL_INT_PLUS1.W))
|
||||
// // val picm_bypass_ff = WireInit(0.U(1.W))
|
||||
//
|
||||
// // clocks
|
||||
// val pic_raddr_c1_clk = Wire(Clock())
|
||||
// val pic_data_c1_clk = Wire(Clock())
|
||||
// val pic_pri_c1_clk = Wire(Clock())
|
||||
// val pic_int_c1_clk = Wire(Clock())
|
||||
// val gw_config_c1_clk = Wire(Clock())
|
||||
//
|
||||
// withClock(pic_raddr_c1_clk) {picm_raddr_ff := RegNext(io.picm_rdaddr,0.U)}
|
||||
// withClock(pic_data_c1_clk) {picm_waddr_ff := RegNext (io.picm_wraddr,0.U)}
|
||||
// withClock(io.active_clk) {picm_wren_ff := RegNext(io.picm_wren,0.U)}
|
||||
// withClock(io.active_clk) {picm_rden_ff := RegNext(io.picm_rden,0.U)}
|
||||
// withClock(io.active_clk) {picm_mken_ff := RegNext(io.picm_mken,0.U)}
|
||||
// withClock(pic_data_c1_clk) {picm_wr_data_ff := RegNext(io.picm_wr_data,0.U)}
|
||||
//
|
||||
// val raddr_intenable_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (INTENABLE_BASE_ADDR >>(NUM_LEVELS+2)).asUInt//// (31,NUM_LEVELS+2)
|
||||
// val raddr_intpriority_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (INTPRIORITY_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
|
||||
// val raddr_config_gw_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CONFIG>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
|
||||
// val raddr_config_pic_match = picm_raddr_ff(31,0) === (EXT_INTR_PIC_CONFIG).asUInt //(31,0)
|
||||
// val addr_intpend_base_match = picm_raddr_ff(31,6) === (INTPEND_BASE_ADDR>>6).asUInt
|
||||
//
|
||||
// val waddr_config_pic_match = picm_waddr_ff(31,0) === (EXT_INTR_PIC_CONFIG).asUInt //(31,0)
|
||||
// val addr_clear_gw_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CLEAR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
|
||||
// val waddr_intpriority_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (INTPRIORITY_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
|
||||
// val waddr_intenable_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (INTENABLE_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
|
||||
// val waddr_config_gw_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CONFIG>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
|
||||
// val picm_bypass_ff = picm_rden_ff & picm_wren_ff & ( picm_raddr_ff === picm_waddr_ff)
|
||||
//
|
||||
// // ---- Clock gating section ------
|
||||
// // c1 clock enables
|
||||
// val pic_raddr_c1_clken = io.picm_mken | io.picm_rden | io.clk_override
|
||||
// val pic_data_c1_clken = io.picm_wren | io.clk_override
|
||||
// val pic_pri_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intpriority_base_match & picm_rden_ff) | io.clk_override
|
||||
// val pic_int_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intenable_base_match & picm_rden_ff) | io.clk_override
|
||||
// val gw_config_c1_clken = (waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff) | io.clk_override
|
||||
//
|
||||
// // C1 - 1 clock pulse for data
|
||||
// val pic_addr_c1_cgc = Module(new rvclkhdr)
|
||||
// pic_addr_c1_cgc.io.en := pic_raddr_c1_clken ; pic_raddr_c1_clk := pic_addr_c1_cgc.io.l1clk
|
||||
// pic_addr_c1_cgc.io.clk := clock ; pic_addr_c1_cgc.io.scan_mode := io.scan_mode
|
||||
//
|
||||
// val pic_data_c1_cgc = Module(new rvclkhdr)
|
||||
// pic_data_c1_cgc.io.en := pic_data_c1_clken ; pic_data_c1_clk := pic_data_c1_cgc.io.l1clk
|
||||
// pic_data_c1_cgc.io.clk := clock ; pic_data_c1_cgc.io.scan_mode := io.scan_mode
|
||||
//
|
||||
// val pic_pri_c1_cgc = Module(new rvclkhdr)
|
||||
// pic_pri_c1_cgc.io.en := pic_pri_c1_clken ; pic_pri_c1_clk := pic_pri_c1_cgc.io.l1clk
|
||||
// pic_pri_c1_cgc.io.clk := clock ; pic_pri_c1_cgc.io.scan_mode := io.scan_mode
|
||||
//
|
||||
// val pic_int_c1_cgc = Module(new rvclkhdr)
|
||||
// pic_int_c1_cgc.io.en := pic_int_c1_clken ; pic_int_c1_clk := pic_int_c1_cgc.io.l1clk
|
||||
// pic_int_c1_cgc.io.clk := clock ; pic_int_c1_cgc.io.scan_mode := io.scan_mode
|
||||
//
|
||||
// val gw_config_c1_cgc = Module(new rvclkhdr)
|
||||
// gw_config_c1_cgc.io.en := gw_config_c1_clken ; gw_config_c1_clk := gw_config_c1_cgc.io.l1clk
|
||||
// gw_config_c1_cgc.io.clk := clock ; gw_config_c1_cgc.io.scan_mode := io.scan_mode
|
||||
//
|
||||
// // ------ end clock gating section ------------------------
|
||||
//
|
||||
//
|
||||
// val sync_inst = Module(new rvsyncss(PIC_TOTAL_INT_PLUS1-1))
|
||||
// sync_inst.io.din := io.extintsrc_req>>1
|
||||
// extintsrc_req_sync := Cat(sync_inst.io.dout, io.extintsrc_req(0))
|
||||
// sync_inst.io.clk := io.free_clk
|
||||
//
|
||||
// io.test := extintsrc_req_sync
|
||||
// ///////////////////////////////////////////////////////////////////////
|
||||
// // Config Reg`
|
||||
// ///////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// val config_reg_we = waddr_config_pic_match & picm_wren_ff
|
||||
// val config_reg_re = raddr_config_pic_match & picm_rden_ff
|
||||
// val config_reg_in = picm_wr_data_ff(0)
|
||||
// withClock(io.free_clk){config_reg := RegEnable(config_reg_in,0.U,config_reg_we.asBool)}
|
||||
// val intpriord = config_reg
|
||||
//
|
||||
//// ///////////////////////////////////////////////////////////
|
||||
//// /// ClaimId Reg and Corresponding PL
|
||||
//// ///////////////////////////////////////////////////////////
|
||||
//// val pl_in_q = Mux(intpriord.asBool,~pl_in,pl_in).asUInt
|
||||
//// withClock(io.free_clk){io.claimid := RegNext(claimid_in,0.U)}
|
||||
//// withClock(io.free_clk){io.pl := RegNext(pl_in_q,0.U)}
|
||||
//// val meipt_inv = Mux(intpriord.asBool,!io.meipt,io.meipt)
|
||||
//// val meicurpl_inv = Mux(intpriord.asBool,!io.meicurpl,io.meicurpl)
|
||||
//// val mexintpend_in = ( selected_int_priority > meipt_inv) & ( selected_int_priority > meicurpl_inv)
|
||||
//// withClock(io.free_clk){io.mexintpend := RegNext(mexintpend_in,0.U)}
|
||||
//// val maxint = Mux(intpriord.asBool,0.U,15.U)
|
||||
//// val mhwakeup_in = pl_in_q === maxint
|
||||
//// withClock(io.free_clk){io.mhwakeup := RegNext(mhwakeup_in,0.U)}
|
||||
////
|
||||
//// //////////////////////////////////////////////////////////////////////////
|
||||
//// // Reads of register.
|
||||
//// // 1- intpending
|
||||
//// //////////////////////////////////////////////////////////////////////////
|
||||
//// val intpend_reg_read = addr_intpend_base_match & picm_rden_ff
|
||||
//// val intpriority_reg_read = raddr_intpriority_base_match & picm_rden_ff
|
||||
//// val intenable_reg_read = raddr_intenable_base_match & picm_rden_ff
|
||||
//// val gw_config_reg_read = raddr_config_gw_base_match & picm_rden_ff
|
||||
////
|
||||
////// val intpend_reg_extended = Cat(INTPEND_SIZE - PIC_TOTAL_INT_PLUS1 , extintsrc_req_gw)
|
||||
////// assign intpend_reg_extended[INTPEND_SIZE-1:0] = {{INTPEND_SIZE-pt.PIC_TOTAL_INT_PLUS1{1'b0}},extintsrc_req_gw[pt.PIC_TOTAL_INT_PLUS1-1:0]} ;
|
||||
////
|
||||
//// val intpend_rd_part_out = (0 until INT_GRPS).map (i=> Fill(32,intpend_reg_read & picm_raddr_ff(5,2) === i.asUInt) & intpend_reg_extended((32*i)+31,32*i)).reverse.reduce(Cat(_,_))
|
||||
//// intpend_rd_out := VecInit.tabulate(INT_GRPS)(i=>intpend_rd_part_out(i)).reverse.reduce (_|_)
|
||||
//// val intenable_rd_out = (0 until PIC_TOTAL_INT_PLUS1).map (i=> if (intenable_reg_re(i)) intenable_reg(i) else 0.U)
|
||||
//// val intpriority_rd_out = (0 until PIC_TOTAL_INT_PLUS1).map (i=> if (intpriority_reg_re(i)) intpriority_reg(i) else 0.U)
|
||||
//// val gw_config_rd_out = (0 until PIC_TOTAL_INT_PLUS1).map (i=> if (gw_config_reg_re(i)) gw_config_reg(i) else 0.U)
|
||||
//// //////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//// /*
|
||||
////
|
||||
//// for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
|
||||
//// if (intenable_reg_re[i]) begin
|
||||
//// intenable_rd_out = intenable_reg[i] ;
|
||||
//// end
|
||||
//// if (intpriority_reg_re[i]) begin
|
||||
//// intpriority_rd_out = intpriority_reg[i] ;
|
||||
//// end
|
||||
//// if (gw_config_reg_re[i]) begin
|
||||
//// gw_config_rd_out = gw_config_reg[i] ;
|
||||
//// end
|
||||
//// end
|
||||
//// end
|
||||
////
|
||||
////
|
||||
////
|
||||
//// always_comb begin : INTPEND_RD
|
||||
//// intpend_rd_out = '0 ;
|
||||
//// for (int i=0; i<INT_GRPS; i++) begin
|
||||
//// intpend_rd_out |= intpend_rd_part_out[i] ;
|
||||
//// end
|
||||
//// end
|
||||
////
|
||||
////
|
||||
////
|
||||
////
|
||||
////
|
||||
////
|
||||
////
|
||||
////
|
||||
////*/
|
||||
//// //////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//}
|
||||
//
|
||||
//object pic_main extends App{
|
||||
// println("Generate Verilog")
|
||||
// println((new chisel3.stage.ChiselStage).emitVerilog(new el2_pic_ctrl()))
|
||||
//}
|
||||
|
|
@ -17,10 +17,10 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
|
||||
val out = Output(UInt(32.W))
|
||||
val finish_dly = Output(UInt(1.W))
|
||||
// val out_s = Output(UInt(33.W))
|
||||
// val test = Output(UInt(6.W))
|
||||
// val out_s = Output(UInt(33.W))
|
||||
// val test = Output(UInt(6.W))
|
||||
})
|
||||
val exu_div_clk = Wire(Clock())
|
||||
// val exu_div_clk = Wire(Clock())
|
||||
val run_state = WireInit(0.U(1.W))
|
||||
val count = WireInit(0.U(6.W))
|
||||
val m_ff = WireInit(0.U(33.W))
|
||||
|
|
@ -44,9 +44,11 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
val finish_ff = WireInit(0.U(1.W))
|
||||
val smallnum_case_ff = WireInit(0.U(1.W))
|
||||
val smallnum_ff = WireInit(0.U(4.W))
|
||||
val smallnum_case = WireInit(0.U(1.W))
|
||||
val count_in = WireInit(0.U(6.W))
|
||||
val dividend_eff = WireInit(0.U(32.W))
|
||||
val a_shift = WireInit(0.U(33.W))
|
||||
// val scan_mode = WireInit(0.U(1.W))
|
||||
|
||||
io.out := 0.U
|
||||
io.finish_dly := 0.U
|
||||
|
|
@ -57,8 +59,9 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
// START - short circuit logic for small numbers {{
|
||||
// small number divides - any 4b / 4b is done in 1 cycle (divisor != 0)
|
||||
// smallnum case does not cover divide by 0
|
||||
val smallnum_case = ((q_ff(31,4) === 0.U(28.W)) & (m_ff(31,4) === 0.U(28.W)) & (m_ff =/= 0.U(32.W)) & !rem_ff & valid_x) |
|
||||
((q_ff === 0.U(32.W)) & (m_ff =/= 0.U(32.W)) & !rem_ff & valid_x)
|
||||
|
||||
smallnum_case := ((q_ff(31,4) === 0.U) & (m_ff(31,4) === 0.U) & (m_ff(31,0) =/= 0.U) & !rem_ff & valid_x) |
|
||||
((q_ff(31,0) === 0.U) & (m_ff(31,0) =/= 0.U) & !rem_ff & valid_x)
|
||||
|
||||
def pat(x : List[Int], y : List[Int]) = {
|
||||
val pat1 = (0 until x.size).map(i=> if(x(i)>=0) q_ff(x(i)) else !q_ff(x(i).abs)).reduce(_&_)
|
||||
|
|
@ -66,26 +69,26 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
pat1 & pat2
|
||||
}
|
||||
|
||||
val smallnum = Cat(
|
||||
pat(List(3),List(-3, -2, -1)),
|
||||
val smallnum = Cat(
|
||||
pat(List(3),List(-3, -2, -1)),
|
||||
|
||||
pat(List(3),List(-3, -2))& !m_ff(0) | pat(List(2),List(-3, -2, -1)) | pat(List(3, 2),List(-3, -2)),
|
||||
pat(List(3),List(-3, -2))& !m_ff(0) | pat(List(2),List(-3, -2, -1)) | pat(List(3, 2),List(-3, -2)),
|
||||
|
||||
pat(List(2),List(-3, -2))& !m_ff(0) | pat(List(1),List(-3, -2, -1)) | pat(List(3),List(-3, -1))& !m_ff(0) |
|
||||
pat(List(3, -2),List(-3, -2, 1, 0)) | pat(List(-3, 2, 1),List(-3, -2)) | pat(List(3, 2),List(-3))& !m_ff(0) |
|
||||
pat(List(3, 2),List(-3, 2, -1)) | pat(List(3, 1),List(-3,-1)) | pat(List(3, 2, 1),List(-3, 2)),
|
||||
pat(List(2),List(-3, -2))& !m_ff(0) | pat(List(1),List(-3, -2, -1)) | pat(List(3),List(-3, -1))& !m_ff(0) |
|
||||
pat(List(3, -2),List(-3, -2, 1, 0)) | pat(List(-3, 2, 1),List(-3, -2)) | pat(List(3, 2),List(-3))& !m_ff(0) |
|
||||
pat(List(3, 2),List(-3, 2, -1)) | pat(List(3, 1),List(-3,-1)) | pat(List(3, 2, 1),List(-3, 2)),
|
||||
|
||||
pat(List(2, 1, 0),List(-3, -1)) | pat(List(3, -2, 0),List(-3, 1, 0)) | pat(List(2),List(-3, -1))& !m_ff(0) |
|
||||
pat(List(1),List(-3, -2))& !m_ff(0) | pat(List(0),List(-3, -2, -1)) | pat(List(-3, 2, -1),List(-3, -2, 1, 0)) |
|
||||
pat(List(-3, 2, 1),List(-3))& !m_ff(0) | pat(List(3),List(-2, -1)) & !m_ff(0) | pat(List(3, -2),List(-3, 2, 1)) |
|
||||
pat(List(-3, 2, 1),List(-3, 2, -1)) | pat(List(-3, 2, 0),List(-3, -1)) | pat(List(3, -2, -1),List(-3, 2, 0)) |
|
||||
pat(List(-2, 1, 0),List(-3, -2)) | pat(List(3, 2),List(-1)) & !m_ff(0) | pat(List(-3, 2, 1, 0),List(-3, 2)) |
|
||||
pat(List(3, 2),List(3, -2)) | pat(List(3, 1),List(3,-2,-1)) | pat(List(3, 0),List(-2, -1)) |
|
||||
pat(List(3, -1),List(-3, 2, 1, 0)) | pat(List(3, 2, 1),List(3)) & !m_ff(0) | pat(List(3, 2, 1),List(3, -1)) |
|
||||
pat(List(3, 2, 0),List(3, -1)) | pat(List(3, -2, 1),List(-3, 1)) | pat(List(3, 1, 0),List(-2)) |
|
||||
pat(List(3, 2, 1, 0),List(3)) |pat(List(3, 1),List(-2)) & !m_ff(0)
|
||||
pat(List(2, 1, 0),List(-3, -1)) | pat(List(3, -2, 0),List(-3, 1, 0)) | pat(List(2),List(-3, -1))& !m_ff(0) |
|
||||
pat(List(1),List(-3, -2))& !m_ff(0) | pat(List(0),List(-3, -2, -1)) | pat(List(-3, 2, -1),List(-3, -2, 1, 0)) |
|
||||
pat(List(-3, 2, 1),List(-3))& !m_ff(0) | pat(List(3),List(-2, -1)) & !m_ff(0) | pat(List(3, -2),List(-3, 2, 1)) |
|
||||
pat(List(-3, 2, 1),List(-3, 2, -1)) | pat(List(-3, 2, 0),List(-3, -1)) | pat(List(3, -2, -1),List(-3, 2, 0)) |
|
||||
pat(List(-2, 1, 0),List(-3, -2)) | pat(List(3, 2),List(-1)) & !m_ff(0) | pat(List(-3, 2, 1, 0),List(-3, 2)) |
|
||||
pat(List(3, 2),List(3, -2)) | pat(List(3, 1),List(3,-2,-1)) | pat(List(3, 0),List(-2, -1)) |
|
||||
pat(List(3, -1),List(-3, 2, 1, 0)) | pat(List(3, 2, 1),List(3)) & !m_ff(0) | pat(List(3, 2, 1),List(3, -1)) |
|
||||
pat(List(3, 2, 0),List(3, -1)) | pat(List(3, -2, 1),List(-3, 1)) | pat(List(3, 1, 0),List(-2)) |
|
||||
pat(List(3, 2, 1, 0),List(3)) |pat(List(3, 1),List(-2)) & !m_ff(0)
|
||||
)
|
||||
//io.test := smallnum
|
||||
//io.test := smallnum
|
||||
// END - short circuit logic for small numbers }}
|
||||
|
||||
// *** Start Short Q *** {{
|
||||
|
|
@ -132,24 +135,24 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
( (a_cls(2,0) === "b000".U ) & (b_cls(2,1) === "b01".U ) ) |
|
||||
( (a_cls(2,0) === "b000".U ) & (b_cls(2,0) === "b001".U ) ) ,
|
||||
|
||||
( (a_cls(2) === "b1".U ) & (b_cls(2) === "b1".U ) ) | // Shift by 24
|
||||
( (a_cls(2) === "b1".U ) & (b_cls(2) === "b1".U ) ) | // Shift by 24
|
||||
( (a_cls(2,1) === "b01".U ) & (b_cls(2,1) === "b01".U ) ) |
|
||||
( (a_cls(2,0) === "b001".U ) & (b_cls(2,0) === "b001".U ) ) |
|
||||
( (a_cls(2,0) === "b000".U ) & (b_cls(2,0) === "b000".U ) ) ,
|
||||
|
||||
( (a_cls(2) === "b1".U ) & (b_cls(2,1) === "b01".U ) ) | // Shift by 16
|
||||
( (a_cls(2) === "b1".U ) & (b_cls(2,1) === "b01".U ) ) | // Shift by 16
|
||||
( (a_cls(2,1) === "b01".U ) & (b_cls(2,0) === "b001".U ) ) |
|
||||
( (a_cls(2,0) === "b001".U ) & (b_cls(2,0) === "b000".U ) ) ,
|
||||
|
||||
( (a_cls(2) === "b1".U ) & (b_cls(2,0) === "b001".U ) ) | // Shift by 8
|
||||
( (a_cls(2) === "b1".U ) & (b_cls(2,0) === "b001".U ) ) | // Shift by 8
|
||||
( (a_cls(2,1) === "b01".U ) & (b_cls(2,0) === "b000".U ) )
|
||||
|
||||
)
|
||||
val shortq_enable = valid_ff_x & (m_ff(31,0) =/= 0.U(32.W)) & (shortq_raw =/= 0.U(4.W))
|
||||
val shortq_shift = Fill(4,shortq_enable) & shortq_raw
|
||||
|
||||
withClock(exu_div_clk) {shortq_enable_ff := RegNext(shortq_enable,0.U)}
|
||||
withClock(exu_div_clk) {shortq_shift_xx := RegNext(shortq_shift,0.U)}
|
||||
// shortq_enable_ff := RegEnable(shortq_enable,0.U,div_clken.asBool)
|
||||
// shortq_shift_xx := RegEnable(shortq_shift,0.U,div_clken.asBool)
|
||||
|
||||
val shortq_shift_ff = Mux1H(Seq (
|
||||
shortq_shift_xx(3).asBool -> "b11111".U,
|
||||
|
|
@ -168,9 +171,10 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
io.finish_dly := finish_ff & !io.cancel
|
||||
val sign_eff = !io.dp.unsign & (io.divisor =/= 0.U(32.W))
|
||||
|
||||
|
||||
q_in := Mux1H(Seq(
|
||||
(!run_state).asBool -> Cat(0.U(1.W),io.dividend) ,
|
||||
(run_state & valid_ff_x | shortq_enable_ff).asBool -> (Cat(dividend_eff(31,0),!a_in(32)) << shortq_shift_ff) ,
|
||||
(run_state & (valid_ff_x | shortq_enable_ff)).asBool -> (Cat(dividend_eff(31,0),!a_in(32)) << shortq_shift_ff) ,
|
||||
(run_state & !(valid_ff_x | shortq_enable_ff)).asBool -> Cat(q_ff(31,0),!a_in(32))
|
||||
))
|
||||
val qff_enable = io.dp.valid | (run_state & !shortq_enable)
|
||||
|
|
@ -199,28 +203,32 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
rem_ff.asBool -> a_ff_eff ,
|
||||
(!smallnum_case_ff & !rem_ff).asBool -> q_ff_eff
|
||||
))
|
||||
val exu_div_cgc = Module(new rvclkhdr)
|
||||
exu_div_cgc.io.en := div_clken
|
||||
exu_div_clk := exu_div_cgc.io.l1clk
|
||||
exu_div_cgc.io.clk := clock
|
||||
exu_div_cgc.io.scan_mode := io.scan_mode
|
||||
|
||||
withClock(exu_div_clk){valid_ff_x := RegNext(io.dp.valid & !io.cancel,0.U)}
|
||||
withClock(exu_div_clk){finish_ff := RegNext(finish & !io.cancel,0.U)}
|
||||
withClock(exu_div_clk){run_state := RegNext(run_in,0.U)}
|
||||
withClock(exu_div_clk){count := RegNext(count_in,0.U)}
|
||||
withClock(exu_div_clk){dividend_neg_ff := RegEnable (io.dividend(31), 0.U, io.dp.valid.asBool)}
|
||||
withClock(exu_div_clk){divisor_neg_ff := RegEnable (io.divisor(31), 0.U, io.dp.valid.asBool)}
|
||||
withClock(exu_div_clk){sign_ff := RegEnable (sign_eff, 0.U, io.dp.valid.asBool)}
|
||||
withClock(exu_div_clk){rem_ff := RegEnable (io.dp.rem, 0.U, io.dp.valid.asBool)}
|
||||
withClock(exu_div_clk){smallnum_case_ff := RegNext(smallnum_case,0.U)}
|
||||
withClock(exu_div_clk){smallnum_ff := RegNext(smallnum,0.U)}
|
||||
q_ff := RegEnable (q_in, 0.U, qff_enable.asBool)
|
||||
a_ff := RegEnable (a_in, 0.U, aff_enable.asBool)
|
||||
m_ff := RegEnable (Cat(!io.dp.unsign & io.divisor(31), io.divisor), 0.U, io.dp.valid.asBool)
|
||||
val exu_div_cgc = rvclkhdr(clock,div_clken.asBool,io.scan_mode)
|
||||
|
||||
withClock(exu_div_cgc) {
|
||||
valid_ff_x := RegNext(io.dp.valid & !io.cancel, 0.U)
|
||||
finish_ff := RegNext(finish & !io.cancel, 0.U)
|
||||
run_state := RegNext(run_in, 0.U)
|
||||
count := RegNext(count_in, 0.U)
|
||||
dividend_neg_ff := RegEnable(io.dividend(31), 0.U, io.dp.valid.asBool)
|
||||
divisor_neg_ff := RegEnable(io.divisor(31), 0.U, io.dp.valid.asBool)
|
||||
sign_ff := RegEnable(sign_eff, 0.U, io.dp.valid.asBool)
|
||||
rem_ff := RegEnable(io.dp.rem, 0.U, io.dp.valid.asBool)
|
||||
smallnum_case_ff := RegNext(smallnum_case, 0.U)
|
||||
smallnum_ff := RegNext(smallnum, 0.U)
|
||||
shortq_enable_ff := RegNext(shortq_enable, 0.U)
|
||||
shortq_shift_xx := RegNext(shortq_shift, 0.U)
|
||||
}
|
||||
q_ff := rvdffe(q_in, qff_enable.asBool,clock,io.scan_mode)
|
||||
a_ff := rvdffe(a_in, aff_enable.asBool,clock,io.scan_mode)
|
||||
m_ff := rvdffe(Cat(!io.dp.unsign & io.divisor(31), io.divisor), io.dp.valid.asBool,clock,io.scan_mode)
|
||||
// q_ff := RegEnable (q_in, 0.U, qff_enable.asBool)
|
||||
// a_ff := RegEnable (a_in, 0.U, aff_enable.asBool)
|
||||
// m_ff := RegEnable (Cat(!io.dp.unsign & io.divisor(31), io.divisor), 0.U, io.dp.valid.asBool)
|
||||
|
||||
}
|
||||
object div_main extends App{
|
||||
println("Generate Verilog")
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_exu_div_ctl()))
|
||||
}
|
||||
}
|
||||
|
|
@ -5,6 +5,7 @@ import chisel3.util._
|
|||
import include._
|
||||
import lib._
|
||||
|
||||
|
||||
class el2_exu_mul_ctl extends Module with RequireAsyncReset with el2_lib {
|
||||
val io = IO(new Bundle{
|
||||
val scan_mode = Input(Bool())
|
||||
|
|
@ -16,6 +17,8 @@ class el2_exu_mul_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
|
||||
val rs1_ext_in = WireInit(SInt(33.W), 0.S)
|
||||
val rs2_ext_in = WireInit(SInt(33.W), 0.S)
|
||||
val rs1_x = WireInit(SInt(33.W), 0.S)
|
||||
val rs2_x = WireInit(SInt(33.W), 0.S)
|
||||
val prod_x = WireInit(SInt(66.W), 0.S)
|
||||
val low_x = WireInit(0.U(1.W))
|
||||
|
||||
|
|
@ -24,9 +27,15 @@ class el2_exu_mul_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
rs2_ext_in := Cat(io.mul_p.rs2_sign & io.rs2_in(31),io.rs2_in).asSInt
|
||||
|
||||
// --------------------------- Multiply ----------------------------------
|
||||
low_x := RegEnable (io.mul_p.low, 0.U, mul_x_enable.asBool)
|
||||
val rs1_x = RegEnable (rs1_ext_in, 0.S, mul_x_enable.asBool)
|
||||
val rs2_x = RegEnable (rs2_ext_in, 0.S, mul_x_enable.asBool)
|
||||
// val gated_clock = rvclkhdr(clock,mul_x_enable.asBool(),io.scan_mode)
|
||||
// withClock(gated_clock) {
|
||||
// low_x := RegNext(io.mul_p.low, 0.U)
|
||||
//rs1_x := RegNext(rs1_ext_in, 0.S)
|
||||
// rs2_x := RegNext(rs2_ext_in, 0.S)
|
||||
// }
|
||||
low_x := rvdffe (io.mul_p.low, mul_x_enable.asBool,clock,io.scan_mode)
|
||||
rs1_x := rvdffe(rs1_ext_in, mul_x_enable.asBool,clock,io.scan_mode)
|
||||
rs2_x := rvdffe (rs2_ext_in, mul_x_enable.asBool,clock,io.scan_mode)
|
||||
|
||||
prod_x := rs1_x * rs2_x
|
||||
io.result_x := Mux1H (Seq(!low_x.asBool -> prod_x(63,32), low_x.asBool -> prod_x(31,0)))
|
||||
|
|
@ -34,4 +43,4 @@ class el2_exu_mul_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
object mul_main extends App{
|
||||
println("Generate Verilog")
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_exu_mul_ctl()))
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -368,6 +368,16 @@ object rvdffe {
|
|||
RegNext(din,0.U.asTypeOf(din.cloneType))
|
||||
}
|
||||
}
|
||||
def apply(din: SInt, en: Bool, clk: Clock, scan_mode: Bool): Bits with Num[_ >: SInt with UInt <: Bits with Num[_ >: SInt with UInt]] = {
|
||||
val obj = Module(new rvclkhdr())
|
||||
val l1clk = obj.io.l1clk
|
||||
obj.io.clk := clk
|
||||
obj.io.en := en
|
||||
obj.io.scan_mode := scan_mode
|
||||
withClock(l1clk) {
|
||||
RegNext(din, 0.S)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -26,30 +26,30 @@ trait param {
|
|||
val BUILD_AXI4 = true
|
||||
val BUILD_AXI_NATIVE = true
|
||||
val BUS_PRTY_DEFAULT = 3
|
||||
val DATA_ACCESS_ADDR0 = 0x00000000 //.U(32.W)
|
||||
val DATA_ACCESS_ADDR1 = 0xC0000000 //.U(32.W)
|
||||
val DATA_ACCESS_ADDR2 = 0xA0000000 //.U(32.W)
|
||||
val DATA_ACCESS_ADDR3 = 0x80000000 //.U(32.W)
|
||||
val DATA_ACCESS_ADDR4 = 0x00000000 //.U(32.W)
|
||||
val DATA_ACCESS_ADDR5 = 0x00000000 //.U(32.W)
|
||||
val DATA_ACCESS_ADDR6 = 0x00000000 //.U(32.W)
|
||||
val DATA_ACCESS_ADDR7 = 0x00000000 //.U(32.W)
|
||||
val DATA_ACCESS_ENABLE0 = true //.U(1.W)
|
||||
val DATA_ACCESS_ENABLE1 = true //.U(1.W)
|
||||
val DATA_ACCESS_ENABLE2 = true //.U(1.W)
|
||||
val DATA_ACCESS_ENABLE3 = true //.U(1.W)
|
||||
val DATA_ACCESS_ENABLE4 = false //.U(1.W)
|
||||
val DATA_ACCESS_ENABLE5 = false //.U(1.W)
|
||||
val DATA_ACCESS_ENABLE6 = false //.U(1.W)
|
||||
val DATA_ACCESS_ENABLE7 = false //.U(1.W)
|
||||
val DATA_ACCESS_MASK0 = 0x7FFFFFFF //.U(32.W)
|
||||
val DATA_ACCESS_MASK1 = 0x3FFFFFFF //.U(32.W)
|
||||
val DATA_ACCESS_MASK2 = 0x1FFFFFFF //.U(32.W)
|
||||
val DATA_ACCESS_MASK3 = 0x0FFFFFFF //.U(32.W)
|
||||
val DATA_ACCESS_MASK4 = 0xFFFFFFFF //.U(32.W)
|
||||
val DATA_ACCESS_MASK5 = 0xFFFFFFFF //.U(32.W)
|
||||
val DATA_ACCESS_MASK6 = 0xFFFFFFFF //.U(32.W)
|
||||
val DATA_ACCESS_MASK7 = 0xFFFFFFFF //.U(32.W)
|
||||
val DATA_ACCESS_ADDR0 = "h00000000".U(32.W)
|
||||
val DATA_ACCESS_ADDR1 = "hC0000000".U(32.W)
|
||||
val DATA_ACCESS_ADDR2 = "hA0000000".U(32.W)
|
||||
val DATA_ACCESS_ADDR3 = "h80000000".U(32.W)
|
||||
val DATA_ACCESS_ADDR4 = "h00000000".U(32.W)
|
||||
val DATA_ACCESS_ADDR5 = "h00000000".U(32.W)
|
||||
val DATA_ACCESS_ADDR6 = "h00000000".U(32.W)
|
||||
val DATA_ACCESS_ADDR7 = "h00000000".U(32.W)
|
||||
val DATA_ACCESS_ENABLE0 = "h1".U(1.W)
|
||||
val DATA_ACCESS_ENABLE1 = "h1".U(1.W)
|
||||
val DATA_ACCESS_ENABLE2 = "h1".U(1.W)
|
||||
val DATA_ACCESS_ENABLE3 = "h1".U(1.W)
|
||||
val DATA_ACCESS_ENABLE4 = "h0".U(1.W)
|
||||
val DATA_ACCESS_ENABLE5 = "h0".U(1.W)
|
||||
val DATA_ACCESS_ENABLE6 = "h0".U(1.W)
|
||||
val DATA_ACCESS_ENABLE7 = "h0".U(1.W)
|
||||
val DATA_ACCESS_MASK0 = "h7FFFFFFF".U(32.W)
|
||||
val DATA_ACCESS_MASK1 = "h3FFFFFFF".U(32.W)
|
||||
val DATA_ACCESS_MASK2 = "h1FFFFFFF".U(32.W)
|
||||
val DATA_ACCESS_MASK3 = "h0FFFFFFF".U(32.W)
|
||||
val DATA_ACCESS_MASK4 = "hFFFFFFFF".U(32.W)
|
||||
val DATA_ACCESS_MASK5 = "hFFFFFFFF".U(32.W)
|
||||
val DATA_ACCESS_MASK6 = "hFFFFFFFF".U(32.W)
|
||||
val DATA_ACCESS_MASK7 = "hFFFFFFFF".U(32.W)
|
||||
val DCCM_BANK_BITS = 2 //.U(3.W)
|
||||
val DCCM_BITS = 16 //.U(5.W)
|
||||
val DCCM_BYTE_WIDTH = 4 //.U(3.W)
|
||||
|
|
@ -59,8 +59,8 @@ trait param {
|
|||
val DCCM_FDATA_WIDTH = 0x27 //.U(6.W)
|
||||
val DCCM_INDEX_BITS = 0xC //.U(4.W)
|
||||
val DCCM_NUM_BANKS = 0x04 //.U(5.W)
|
||||
val DCCM_REGION = 15 //.U(4.W)
|
||||
val DCCM_SADR = 0xF0040000
|
||||
val DCCM_REGION = 15
|
||||
val DCCM_SADR = "hF0040000".U(32.W)
|
||||
val DCCM_SIZE = 0x040
|
||||
val DCCM_WIDTH_BITS = 2 //.U(2.W)
|
||||
val DMA_BUF_DEPTH = 5 //.U(3.W)
|
||||
|
|
@ -103,7 +103,7 @@ trait param {
|
|||
val ICCM_INDEX_BITS = 0xC //.U(4.W)
|
||||
val ICCM_NUM_BANKS = 0x04 //.U(5.W)
|
||||
val ICCM_ONLY = 0x0 //.U(1.W)
|
||||
val ICCM_REGION = 0xE //.U(4.W)
|
||||
val ICCM_REGION = 0xE //.U(4.W)
|
||||
val ICCM_SADR = 0xEE000000L //.U(32.W)
|
||||
val ICCM_SIZE = 0x040 //.U(10.W)
|
||||
val IFU_BUS_ID = 0x1 //.U(1.W)
|
||||
|
|
@ -144,11 +144,11 @@ trait param {
|
|||
val LSU_STBUF_DEPTH = 0x4 //.U(4.W)
|
||||
val NO_ICCM_NO_ICACHE = 0x0 //.U(1.W)
|
||||
val PIC_2CYCLE = 0x0 //.U(1.W)
|
||||
val PIC_BASE_ADDR = 0xF00C0000 //.U(32.W)
|
||||
val PIC_BASE_ADDR = "hF00C0000".U(32.W)
|
||||
val PIC_BITS = 0x0F //.U(5.W)
|
||||
val PIC_INT_WORDS = 0x1 //.U(4.W)
|
||||
val PIC_REGION = 0xF //.U(4.W)
|
||||
val PIC_SIZE = 0x020 //.U(9.W)
|
||||
val PIC_REGION = 0xF
|
||||
val PIC_SIZE = 0x020//.U(9.W)
|
||||
val PIC_TOTAL_INT = 0x1F //.U(8.W)
|
||||
val PIC_TOTAL_INT_PLUS1 = 0x020 //.U(9.W)
|
||||
val RET_STACK_SIZE = 0x8 //.U(4.W)
|
||||
|
|
@ -199,6 +199,12 @@ trait el2_lib extends param{
|
|||
Cat(dout_upper,w1(11,0))
|
||||
}
|
||||
|
||||
def Encoder(dec_value:UInt) = {
|
||||
val enc_val = Cat(dec_value(4)| dec_value(5) | dec_value(6)|dec_value(7),
|
||||
dec_value(2)| dec_value(3) | dec_value(6)|dec_value(7),
|
||||
dec_value(1)| dec_value(3) | dec_value(5)|dec_value(7))
|
||||
enc_val }
|
||||
|
||||
|
||||
|
||||
def rvbradder(pc:UInt,offset:UInt) = { // lsb is not using in code
|
||||
|
|
@ -252,8 +258,6 @@ trait el2_lib extends param{
|
|||
in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt
|
||||
(in_range,in_region)
|
||||
}
|
||||
|
||||
|
||||
def rvecc_encode(din:UInt):UInt = {
|
||||
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
|
||||
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
|
||||
|
|
|
|||
|
|
@ -2,20 +2,12 @@ package lsu
|
|||
|
||||
import include._
|
||||
import lib._
|
||||
import snapshot._
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
|
||||
import chisel3.experimental.ChiselEnum
|
||||
import chisel3.experimental.{withClock, withReset, withClockAndReset}
|
||||
import chisel3.experimental.BundleLiterals._
|
||||
import chisel3.tester._
|
||||
import chisel3.tester.RawTester.test
|
||||
import chisel3.util.HasBlackBoxResource
|
||||
import chisel3.experimental.chiselName
|
||||
|
||||
@chiselName
|
||||
class el2_lsu_addrcheck extends Module with RequireAsyncReset
|
||||
class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib
|
||||
{val io = IO(new Bundle{
|
||||
val lsu_c2_m_clk = Input(Clock())
|
||||
|
||||
|
|
@ -38,126 +30,97 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset
|
|||
val fir_nondccm_access_error_d = Output(UInt(1.W))
|
||||
val scan_mode = Input(UInt(1.W))})
|
||||
|
||||
val start_addr_in_dccm_d = WireInit(0.U(1.W))
|
||||
val start_addr_in_dccm_region_d = WireInit(0.U(1.W))
|
||||
val end_addr_in_dccm_d = WireInit(0.U(1.W))
|
||||
val end_addr_in_dccm_region_d = WireInit(0.U(1.W))
|
||||
|
||||
//DCCM check
|
||||
// Start address check
|
||||
if(pt1.DCCM_ENABLE==1){ // Gen_dccm_enable
|
||||
val start_addr_dccm_rangecheck = Module(new rvrangecheck_ch(pt.DCCM_SADR,pt1.DCCM_SIZE))
|
||||
start_addr_dccm_rangecheck.io.addr := io.start_addr_d
|
||||
start_addr_in_dccm_d := start_addr_dccm_rangecheck.io.in_range
|
||||
start_addr_in_dccm_region_d := start_addr_dccm_rangecheck.io.in_region
|
||||
|
||||
// Gen_dccm_enable
|
||||
val (start_addr_in_dccm_d,start_addr_in_dccm_region_d) = if(DCCM_ENABLE) rvrangecheck_ch(io.start_addr_d,DCCM_SADR,DCCM_SIZE) else (0.U,0.U)
|
||||
// End address check
|
||||
val end_addr_dccm_rangecheck = Module(new rvrangecheck_ch(pt.DCCM_SADR,pt1.DCCM_SIZE))
|
||||
end_addr_dccm_rangecheck.io.addr := io.end_addr_d
|
||||
end_addr_in_dccm_d := end_addr_dccm_rangecheck.io.in_range
|
||||
end_addr_in_dccm_region_d := end_addr_dccm_rangecheck.io.in_region
|
||||
}
|
||||
else{ //Gen_dccm_disable
|
||||
start_addr_in_dccm_d := 0.U
|
||||
start_addr_in_dccm_region_d := 0.U
|
||||
end_addr_in_dccm_d := 0.U
|
||||
end_addr_in_dccm_region_d := 0.U
|
||||
}
|
||||
val (end_addr_in_dccm_d ,end_addr_in_dccm_region_d) = if(DCCM_ENABLE) rvrangecheck_ch(io.end_addr_d,DCCM_SADR,DCCM_SIZE) else (0.U,0.U)
|
||||
|
||||
val addr_in_iccm = WireInit(0.U(1.W))
|
||||
if(pt1.ICCM_ENABLE == 1){ //check_iccm
|
||||
addr_in_iccm := (io.start_addr_d(31,28) === pt.ICCM_REGION)
|
||||
if(ICCM_ENABLE ){ //check_iccm
|
||||
addr_in_iccm := (io.start_addr_d(31,28) === ICCM_REGION.U)
|
||||
}
|
||||
else{
|
||||
addr_in_iccm := 1.U
|
||||
}
|
||||
|
||||
|
||||
//PIC memory check
|
||||
//start address check
|
||||
val start_addr_pic_rangecheck = Module(new rvrangecheck_ch(pt.PIC_BASE_ADDR,pt1.PIC_SIZE))
|
||||
start_addr_pic_rangecheck.io.addr := io.start_addr_d(31,0)
|
||||
val start_addr_in_pic_d = start_addr_pic_rangecheck.io.in_range
|
||||
val start_addr_in_pic_region_d = start_addr_pic_rangecheck.io.in_region
|
||||
|
||||
val (start_addr_in_pic_d,start_addr_in_pic_region_d) = rvrangecheck_ch(io.start_addr_d(31,0),PIC_BASE_ADDR,PIC_SIZE)
|
||||
//End address check
|
||||
val end_addr_pic_rangecheck = Module(new rvrangecheck_ch(pt.PIC_BASE_ADDR,pt1.PIC_SIZE))
|
||||
end_addr_pic_rangecheck.io.addr := io.end_addr_d(31,0)
|
||||
val end_addr_in_pic_d = end_addr_pic_rangecheck.io.in_range
|
||||
val end_addr_in_pic_region_d = end_addr_pic_rangecheck.io.in_region
|
||||
val (end_addr_in_pic_d,end_addr_in_pic_region_d) = rvrangecheck_ch(io.end_addr_d(31,0),PIC_BASE_ADDR,PIC_SIZE)
|
||||
|
||||
val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d
|
||||
val base_reg_dccm_or_pic = (io.rs1_region_d(3,0) === pt.DCCM_REGION) | (io.rs1_region_d(3,0) === pt.PIC_REGION) //base region
|
||||
val base_reg_dccm_or_pic = (io.rs1_region_d(3,0) === DCCM_REGION.U) | (io.rs1_region_d(3,0) === PIC_REGION.U) //base region
|
||||
io.addr_in_dccm_d := (start_addr_in_dccm_d & end_addr_in_dccm_d)
|
||||
io.addr_in_pic_d := (start_addr_in_pic_d & end_addr_in_pic_d)
|
||||
|
||||
io.addr_external_d := ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d); //if start address does not belong to dccm/pic
|
||||
val csr_idx = Cat(io.start_addr_d(31,28),1.U)
|
||||
val is_sideeffects_d = io.dec_tlu_mrac_ff(csr_idx) & ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & io.lsu_pkt_d.valid & (io.lsu_pkt_d.store | io.lsu_pkt_d.load) //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
|
||||
val is_sideeffects_d = io.dec_tlu_mrac_ff(csr_idx) & !(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & io.lsu_pkt_d.valid & (io.lsu_pkt_d.store | io.lsu_pkt_d.load) //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
|
||||
val is_aligned_d = (io.lsu_pkt_d.word & (io.start_addr_d(1,0) === 0.U)) | (io.lsu_pkt_d.half & (io.start_addr_d(0) === 0.U)) | io.lsu_pkt_d.by
|
||||
|
||||
|
||||
val non_dccm_access_ok = (~(Cat(pt.DATA_ACCESS_ENABLE0,pt.DATA_ACCESS_ENABLE1,pt.DATA_ACCESS_ENABLE2,pt.DATA_ACCESS_ENABLE3,
|
||||
pt.DATA_ACCESS_ENABLE4,pt.DATA_ACCESS_ENABLE5,pt.DATA_ACCESS_ENABLE6,pt.DATA_ACCESS_ENABLE7)).orR) |
|
||||
(((pt.DATA_ACCESS_ENABLE0 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK0)) === (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0)) | //0111
|
||||
(pt.DATA_ACCESS_ENABLE1 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK1)) === (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1)) | //1111
|
||||
(pt.DATA_ACCESS_ENABLE2 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK2)) === (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2)) | //1011
|
||||
(pt.DATA_ACCESS_ENABLE3 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK3)) === (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3)) | //1000
|
||||
(pt.DATA_ACCESS_ENABLE4 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK4)) === (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4)) |
|
||||
(pt.DATA_ACCESS_ENABLE5 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK5)) === (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5)) |
|
||||
(pt.DATA_ACCESS_ENABLE6 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK6)) === (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6)) |
|
||||
(pt.DATA_ACCESS_ENABLE7 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK7)) === (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7)))
|
||||
val non_dccm_access_ok = (!(Cat(DATA_ACCESS_ENABLE0,DATA_ACCESS_ENABLE1,DATA_ACCESS_ENABLE2,DATA_ACCESS_ENABLE3,
|
||||
DATA_ACCESS_ENABLE4,DATA_ACCESS_ENABLE5,DATA_ACCESS_ENABLE6,DATA_ACCESS_ENABLE7)).orR) |
|
||||
(((DATA_ACCESS_ENABLE0 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK0)) === (DATA_ACCESS_ADDR0 | DATA_ACCESS_MASK0)) | //0111
|
||||
(DATA_ACCESS_ENABLE1 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK1)) === (DATA_ACCESS_ADDR1 | DATA_ACCESS_MASK1)) | //1111
|
||||
(DATA_ACCESS_ENABLE2 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK2)) === (DATA_ACCESS_ADDR2 | DATA_ACCESS_MASK2)) | //1011
|
||||
(DATA_ACCESS_ENABLE3 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK3)) === (DATA_ACCESS_ADDR3 | DATA_ACCESS_MASK3)) | //1000
|
||||
(DATA_ACCESS_ENABLE4 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK4)) === (DATA_ACCESS_ADDR4 | DATA_ACCESS_MASK4)) |
|
||||
(DATA_ACCESS_ENABLE5 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK5)) === (DATA_ACCESS_ADDR5 | DATA_ACCESS_MASK5)) |
|
||||
(DATA_ACCESS_ENABLE6 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK6)) === (DATA_ACCESS_ADDR6 | DATA_ACCESS_MASK6)) |
|
||||
(DATA_ACCESS_ENABLE7 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK7)) === (DATA_ACCESS_ADDR7 | DATA_ACCESS_MASK7)))
|
||||
&
|
||||
((pt.DATA_ACCESS_ENABLE0 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK0)) === (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0)) |
|
||||
(pt.DATA_ACCESS_ENABLE1 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK1)) === (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1)) |
|
||||
(pt.DATA_ACCESS_ENABLE2 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK2)) === (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2)) |
|
||||
(pt.DATA_ACCESS_ENABLE3 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK3)) === (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3)) |
|
||||
(pt.DATA_ACCESS_ENABLE4 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK4)) === (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4)) |
|
||||
(pt.DATA_ACCESS_ENABLE5 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK5)) === (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5)) |
|
||||
(pt.DATA_ACCESS_ENABLE6 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK6)) === (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6)) |
|
||||
(pt.DATA_ACCESS_ENABLE7 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK7)) === (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7))))
|
||||
((DATA_ACCESS_ENABLE0 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK0)) === (DATA_ACCESS_ADDR0 | DATA_ACCESS_MASK0)) |
|
||||
(DATA_ACCESS_ENABLE1 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK1)) === (DATA_ACCESS_ADDR1 | DATA_ACCESS_MASK1)) |
|
||||
(DATA_ACCESS_ENABLE2 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK2)) === (DATA_ACCESS_ADDR2 | DATA_ACCESS_MASK2)) |
|
||||
(DATA_ACCESS_ENABLE3 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK3)) === (DATA_ACCESS_ADDR3 | DATA_ACCESS_MASK3)) |
|
||||
(DATA_ACCESS_ENABLE4 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK4)) === (DATA_ACCESS_ADDR4 | DATA_ACCESS_MASK4)) |
|
||||
(DATA_ACCESS_ENABLE5 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK5)) === (DATA_ACCESS_ADDR5 | DATA_ACCESS_MASK5)) |
|
||||
(DATA_ACCESS_ENABLE6 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK6)) === (DATA_ACCESS_ADDR6 | DATA_ACCESS_MASK6)) |
|
||||
(DATA_ACCESS_ENABLE7 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK7)) === (DATA_ACCESS_ADDR7 | DATA_ACCESS_MASK7))))
|
||||
|
||||
val regpred_access_fault_d = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic)
|
||||
val picm_access_fault_d = (io.addr_in_pic_d & ((io.start_addr_d(1,0) =/= 0.U(2.W)) | ~io.lsu_pkt_d.word))
|
||||
val picm_access_fault_d = (io.addr_in_pic_d & ((io.start_addr_d(1,0) =/= 0.U(2.W)) | !io.lsu_pkt_d.word))
|
||||
|
||||
val unmapped_access_fault_d = WireInit(1.U(1.W))
|
||||
val mpu_access_fault_d = WireInit(1.U(1.W))
|
||||
if(pt1.DCCM_REGION == pt1.PIC_REGION){
|
||||
unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~(start_addr_in_dccm_d | start_addr_in_pic_d)) |
|
||||
if(DCCM_REGION == PIC_REGION){
|
||||
unmapped_access_fault_d := ((start_addr_in_dccm_region_d & !(start_addr_in_dccm_d | start_addr_in_pic_d)) |
|
||||
// 0. Addr in dccm/pic region but not in dccm/pic offset
|
||||
(end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d)) |
|
||||
(end_addr_in_dccm_region_d & !(end_addr_in_dccm_d | end_addr_in_pic_d)) |
|
||||
// 0. Addr in dccm/pic region but not in dccm/pic offset
|
||||
(start_addr_in_dccm_d & end_addr_in_pic_d) |
|
||||
// 0. DCCM -> PIC cross when DCCM/PIC in same region
|
||||
(start_addr_in_pic_d & end_addr_in_dccm_d))
|
||||
// 0. DCCM -> PIC cross when DCCM/PIC in same region
|
||||
mpu_access_fault_d := (~start_addr_in_dccm_region_d & ~non_dccm_access_ok)
|
||||
mpu_access_fault_d := (!start_addr_in_dccm_region_d & !non_dccm_access_ok)
|
||||
// 3. Address is not in a populated non-dccm region
|
||||
}
|
||||
|
||||
else{
|
||||
unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d) |
|
||||
(start_addr_in_pic_region_d & ~start_addr_in_pic_d) | (end_addr_in_pic_region_d & ~end_addr_in_pic_d))
|
||||
mpu_access_fault_d := (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);
|
||||
unmapped_access_fault_d := ((start_addr_in_dccm_region_d & !start_addr_in_dccm_d) | (end_addr_in_dccm_region_d & !end_addr_in_dccm_d) |
|
||||
(start_addr_in_pic_region_d & !start_addr_in_pic_d) | (end_addr_in_pic_region_d & !end_addr_in_pic_d))
|
||||
mpu_access_fault_d := (!start_addr_in_pic_region_d & !start_addr_in_dccm_region_d & !non_dccm_access_ok);
|
||||
// 3. Address is not in a populated non-dccm region
|
||||
}
|
||||
|
||||
//check width of access_fault_mscause_d
|
||||
io.access_fault_d := (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma
|
||||
io.access_fault_d := (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & io.lsu_pkt_d.valid & !io.lsu_pkt_d.dma
|
||||
val access_fault_mscause_d = Mux(unmapped_access_fault_d.asBool,2.U(4.W), Mux(mpu_access_fault_d.asBool,3.U(4.W), Mux(regpred_access_fault_d.asBool,5.U(4.W), Mux(picm_access_fault_d.asBool,6.U(4.W),0.U(4.W)))))
|
||||
val regcross_misaligned_fault_d = (io.start_addr_d(31,28) =/= io.end_addr_d(31,28))
|
||||
val sideeffect_misaligned_fault_d = (is_sideeffects_d & ~ is_aligned_d)
|
||||
io.misaligned_fault_d := (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & io.addr_external_d)) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma
|
||||
val sideeffect_misaligned_fault_d = (is_sideeffects_d & !is_aligned_d)
|
||||
io.misaligned_fault_d := (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & io.addr_external_d)) & io.lsu_pkt_d.valid & !io.lsu_pkt_d.dma
|
||||
val misaligned_fault_mscause_d = Mux(regcross_misaligned_fault_d,2.U(4.W),Mux(sideeffect_misaligned_fault_d.asBool,1.U(4.W),0.U(4.W)))
|
||||
io.exc_mscause_d := Mux(io.misaligned_fault_d.asBool, misaligned_fault_mscause_d(3,0), access_fault_mscause_d(3,0))
|
||||
io.fir_dccm_access_error_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d)|(end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
||||
io.fir_nondccm_access_error_d := ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
||||
io.fir_dccm_access_error_d := ((start_addr_in_dccm_region_d & !start_addr_in_dccm_d)|(end_addr_in_dccm_region_d & !end_addr_in_dccm_d)) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
||||
io.fir_nondccm_access_error_d := !(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
||||
|
||||
withClock(io.lsu_c2_m_clk){io.is_sideeffects_m := RegNext(is_sideeffects_d,0.U)} //TBD for clock and reset
|
||||
}
|
||||
//println(chisel3.Driver.emitVerilog(new el2_lsu_addrcheck))
|
||||
|
||||
object address_checker extends App{
|
||||
println("Generate Verilog")
|
||||
chisel3.Driver.execute(args, ()=> new el2_lsu_addrcheck)
|
||||
}
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_addrcheck()))
|
||||
}
|
||||
|
|
@ -8,17 +8,17 @@ import snapshot._
|
|||
import chisel3.experimental.{ChiselEnum, chiselName}
|
||||
import chisel3.util.ImplicitConversions.intToUInt
|
||||
|
||||
object el2_lsu_bus_buffer {
|
||||
object State extends ChiselEnum {
|
||||
val IDLE, WAIT, CMD, RESP, DONE_PARTIAL, DONE_WAIT, DONE = Value
|
||||
}
|
||||
}
|
||||
//object el2_lsu_bus_buffer {
|
||||
// object State extends ChiselEnum {
|
||||
// val IDLE, WAIT, CMD, RESP, DONE_PARTIAL, DONE_WAIT, DONE = Value
|
||||
// }
|
||||
//}
|
||||
|
||||
@chiselName
|
||||
class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
||||
class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib
|
||||
{
|
||||
import el2_lsu_bus_buffer.State
|
||||
import el2_lsu_bus_buffer.State._
|
||||
// import el2_lsu_bus_buffer.State
|
||||
// import el2_lsu_bus_buffer.State._
|
||||
|
||||
val io = IO (new Bundle {
|
||||
//val clk = Input(Clock()) //implicit
|
||||
|
|
@ -128,6 +128,8 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
val TIMER_MAX = TIMER - 1
|
||||
val TIMER_LOG2 = if (TIMER < 2) 1 else log2Ceil(TIMER)
|
||||
|
||||
val idle_C :: wait_C :: cmd_C :: resp_C :: done_partial_C :: done_wait_C :: done_C :: Nil = Enum(7)
|
||||
|
||||
val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U)
|
||||
val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U)
|
||||
val ld_addr_hitvec_lo = WireInit(UInt(4.W), init = 0.U)
|
||||
|
|
@ -160,9 +162,9 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
val lsu_nonblock_dual = WireInit(Bool(), init = false.B)
|
||||
val lsu_nonblock_load_data_ready = WireInit(Bool(), init = false.B)
|
||||
|
||||
val CmdPtr0Dec = Wire(Vec(DEPTH, Bool()))
|
||||
val CmdPtr1Dec = Wire(Vec(DEPTH, Bool()))
|
||||
val RspPtrDec = Wire(Vec(DEPTH, Bool()))
|
||||
val CmdPtr0Dec = Wire(Vec(DEPTH, Bool()))
|
||||
val CmdPtr1Dec = Wire(Vec(DEPTH, Bool()))
|
||||
val RspPtrDec = Wire(Vec(DEPTH, Bool()))
|
||||
val CmdPtr0 = WireInit(UInt(DEPTH_LOG2.W), init = 0.U)
|
||||
val CmdPtr1 = WireInit(UInt(DEPTH_LOG2.W), init = 0.U)
|
||||
val RspPtr = WireInit(UInt(DEPTH_LOG2.W), init = 0.U)
|
||||
|
|
@ -199,7 +201,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
val bus_rsp_rdata = WireInit(UInt(64.W), init = 0.U)
|
||||
|
||||
// Bus buffer signals
|
||||
val buf_state = Wire(Vec(DEPTH, State()))
|
||||
val buf_state = Wire(Vec(DEPTH, UInt(3.W)))
|
||||
val buf_sz = Wire(Vec(DEPTH, UInt(2.W)))
|
||||
val buf_addr = Wire(Vec(DEPTH, UInt(32.W)))
|
||||
val buf_byteen = Wire(Vec(DEPTH, UInt(4.W)))
|
||||
|
|
@ -220,7 +222,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
val buf_rspage = Wire(Vec(DEPTH, Vec(DEPTH, Bool())))
|
||||
val buf_rsp_pickage = Wire(Vec(DEPTH, Vec(DEPTH, Bool())))
|
||||
|
||||
val buf_nxtstate = Wire(Vec(DEPTH, State()))
|
||||
val buf_nxtstate = Wire(Vec(DEPTH, UInt(3.W)))
|
||||
val buf_rst = Wire(Vec(DEPTH, Bool()))
|
||||
val buf_state_en = Wire(Vec(DEPTH, Bool()))
|
||||
val buf_cmd_state_bus_en = Wire(Vec(DEPTH, Bool()))
|
||||
|
|
@ -349,10 +351,10 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
|
||||
///////////// Initialization of vectors//////////////////
|
||||
for (i <- 0 until DEPTH) {
|
||||
CmdPtr0Dec(i) := 0.U
|
||||
CmdPtr1Dec(i) := 0.U
|
||||
CmdPtr0Dec (i) := 0.U
|
||||
CmdPtr1Dec (i) := 0.U
|
||||
RspPtrDec(i) := 0.U
|
||||
buf_state(i) := IDLE
|
||||
buf_state(i) := idle_C
|
||||
buf_sz(i) := 0.U
|
||||
buf_addr(i) := 0.U
|
||||
buf_byteen(i) := 0.U
|
||||
|
|
@ -404,8 +406,8 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
ld_byte_ibuf_hit_lo := (0 until 4).map(i =>(ld_addr_ibuf_hit_lo & ibuf_byteen(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_byte_ibuf_hit_hi := (0 until 4).map(i =>(ld_addr_ibuf_hit_hi & ibuf_byteen(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
ld_addr_hitvec_lo := (0 until DEPTH).map(i =>((io.lsu_addr_m(31,2) === buf_addr(i)(31,2)) & buf_write(i) & (buf_state(i) =/= IDLE) & io.lsu_busreq_m).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_addr_hitvec_hi := (0 until DEPTH).map(i =>((io.end_addr_m(31,2) === buf_addr(i)(31,2)) & buf_write(i) & (buf_state(i) =/= IDLE) & io.lsu_busreq_m).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_addr_hitvec_lo := (0 until DEPTH).map(i =>((io.lsu_addr_m(31,2) === buf_addr(i)(31,2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_addr_hitvec_hi := (0 until DEPTH).map(i =>((io.end_addr_m(31,2) === buf_addr(i)(31,2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
io.ld_byte_hit_buf_lo := (0 until 4).map(i =>(ld_byte_ibuf_hit_lo(i) | ld_byte_hitvecfn_lo(i).orR).asUInt).reverse.reduce(Cat(_,_))
|
||||
io.ld_byte_hit_buf_hi := (0 until 4).map(i =>(ld_byte_ibuf_hit_lo(i) | ld_byte_hitvecfn_lo(i).orR).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
|
@ -440,12 +442,12 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
io.lsu_pkt_r.word.asBool -> (io.lsu_addr_r(1,0).asUInt === 0.U)
|
||||
))
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
ibuf_byp := (io.lsu_busreq_r & (io.lsu_pkt_r.load | io.no_word_merge_r) & ~ibuf_valid).asBool
|
||||
ibuf_wr_en := (io.lsu_busreq_r & io.lsu_commit_r & ~ibuf_byp).asBool
|
||||
ibuf_rst := ((ibuf_drain_vld & ~ibuf_wr_en) | io.dec_tlu_force_halt).asBool
|
||||
ibuf_force_drain := (io.lsu_busreq_m & ~io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.load | (ibuf_addr(31,2) =/= io.lsu_addr_m(31,2)))).asBool
|
||||
ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === (TIMER_MAX.asUInt(TIMER_LOG2.W)))) & ~(ibuf_merge_en & ibuf_merge_in)) |
|
||||
ibuf_byp | ibuf_force_drain | ibuf_sideeffect | ~ibuf_write | bus_coalescing_disable)
|
||||
ibuf_byp := (io.lsu_busreq_r & (io.lsu_pkt_r.load | io.no_word_merge_r) & !ibuf_valid).asBool
|
||||
ibuf_wr_en := (io.lsu_busreq_r & io.lsu_commit_r & !ibuf_byp).asBool
|
||||
ibuf_rst := ((ibuf_drain_vld & !ibuf_wr_en) | io.dec_tlu_force_halt).asBool
|
||||
ibuf_force_drain := (io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.load | (ibuf_addr(31,2) =/= io.lsu_addr_m(31,2)))).asBool
|
||||
ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === (TIMER_MAX.asUInt(TIMER_LOG2.W)))) & !(ibuf_merge_en & ibuf_merge_in)) |
|
||||
ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable)
|
||||
ibuf_tag_in := Mux((ibuf_merge_en & ibuf_merge_in), ibuf_tag(DEPTH_LOG2-1,0),Mux(io.ldst_dual_r,WrPtr1_r,WrPtr0_r))
|
||||
ibuf_dualtag_in := WrPtr0_r(DEPTH_LOG2-1,0)
|
||||
ibuf_sz_in := Cat(io.lsu_pkt_r.word,io.lsu_pkt_r.half)
|
||||
|
|
@ -459,7 +461,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
ibuf_merge_in := ~io.ldst_dual_r.asUInt()
|
||||
|
||||
withClock(io.lsu_free_c2_clk){
|
||||
ibuf_valid := RegEnable(~ibuf_rst ,init = false.B, (ibuf_wr_en|ibuf_rst).asBool())
|
||||
ibuf_valid := RegNext(Mux(ibuf_wr_en.asBool(),1.U ,ibuf_valid) & !ibuf_rst, false.B)
|
||||
ibuf_timer := RegNext(ibuf_timer_in ,init = 0.U)
|
||||
}
|
||||
withClock(io.lsu_bus_ibuf_c1_clk) {
|
||||
|
|
@ -483,7 +485,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
obuf_wr_wait := (buf_numvld_wrcmd_any(3,0) === 1.U(4.W)) & (buf_numvld_cmd_any(3,0) === 1.U(4.W)) & (obuf_wr_timer =/= (TIMER_MAX.asUInt(TIMER_LOG2.W))) &
|
||||
~bus_coalescing_disable & ~buf_nomerge(CmdPtr0) & ~buf_sideeffect(CmdPtr0) & ~obuf_force_wr_en
|
||||
obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & ~(io.is_sideeffects_r & bus_sideeffect_pend)) |
|
||||
((buf_state(CmdPtr0) === CMD) & found_cmdptr0 & ~buf_cmd_state_bus_en(CmdPtr0) & ~(buf_sideeffect(CmdPtr0) & bus_sideeffect_pend) &
|
||||
((buf_state(CmdPtr0) === cmd_C) & found_cmdptr0 & ~buf_cmd_state_bus_en(CmdPtr0) & ~(buf_sideeffect(CmdPtr0) & bus_sideeffect_pend) &
|
||||
(~(buf_dual(CmdPtr0) & buf_samedw(CmdPtr0) & ~buf_write(CmdPtr0)) | found_cmdptr1 | buf_nomerge(CmdPtr0) | obuf_force_wr_en))) &
|
||||
(bus_cmd_ready | ~obuf_valid | obuf_nosend) & ~obuf_wr_wait & ~lsu_bus_cntr_overflow & ~bus_addr_match_pending & io.lsu_bus_clk_en
|
||||
obuf_rst := ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & ~obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
|
||||
|
|
@ -504,7 +506,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
obuf_tag1_in := Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr0)
|
||||
obuf_rdrsp_tag_in := Mux((bus_cmd_sent & ~obuf_write), obuf_tag0(pt1.LSU_BUS_TAG-1,0), obuf_rdrsp_tag(pt1.LSU_BUS_TAG-1,0))
|
||||
|
||||
obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (buf_state(CmdPtr0) === CMD) & (buf_state(CmdPtr1) === CMD) &
|
||||
obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (buf_state(CmdPtr0) === cmd_C) & (buf_state(CmdPtr1) === cmd_C) &
|
||||
~buf_cmd_state_bus_en(CmdPtr0) & ~buf_sideeffect(CmdPtr0) &
|
||||
((buf_write(CmdPtr0) & buf_write(CmdPtr1) & (buf_addr(CmdPtr0)(31,3) === buf_addr(CmdPtr1)(31,3)) & ~bus_coalescing_disable & ~pt.BUILD_AXI_NATIVE) |
|
||||
(~buf_write(CmdPtr0) & buf_dual(CmdPtr0) & ~buf_dualhi(CmdPtr0) & buf_samedw(CmdPtr0)))) |
|
||||
|
|
@ -526,7 +528,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
obuf_wr_enQ := RegNext(obuf_wr_en , init = 0.U)
|
||||
}
|
||||
withClock(io.lsu_free_c2_clk){
|
||||
obuf_valid := RegEnable(~obuf_rst , init = 0.U, obuf_wr_en|obuf_rst)
|
||||
obuf_valid := RegNext(Mux(obuf_wr_en.asBool(),1.U ,obuf_valid) & !obuf_rst, false.B)
|
||||
obuf_nosend := RegEnable(obuf_nosend_in , init = 0.U, obuf_wr_en)
|
||||
}
|
||||
withClock(io.lsu_bus_obuf_c1_clk){
|
||||
|
|
@ -539,42 +541,49 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
obuf_tag1 := RegEnable(obuf_tag1_in , init = 0.U, obuf_wr_en)
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
WrPtr0_m := PriorityMux((0 until DEPTH).map(i =>(((buf_state(i) === IDLE) & ~((ibuf_valid & (ibuf_tag === i)) | (io.lsu_busreq_r & ((WrPtr0_r === i) | (io.ldst_dual_r & (WrPtr1_r === i)))))).asBool -> i.asUInt(DEPTH_LOG2.W))))
|
||||
WrPtr1_m := PriorityMux((0 until DEPTH).map(i =>(((buf_state(i) === IDLE) & ~((ibuf_valid & (ibuf_tag === i)) | (io.lsu_busreq_m & (WrPtr0_m === i)) | (io.lsu_busreq_r & (WrPtr0_r === i) | (io.ldst_dual_r & (WrPtr1_r === i))))).asBool -> i.asUInt(DEPTH_LOG2.W))))
|
||||
|
||||
for {
|
||||
i <- 0 until DEPTH
|
||||
j <- 0 until DEPTH
|
||||
}{
|
||||
CmdPtr0Dec(i) := ~(buf_age(i).asUInt.orR()) & (buf_state(i) === CMD) & ~buf_cmd_state_bus_en(i)
|
||||
CmdPtr1Dec(i) := ~((buf_age(i).asUInt.orR() & ~CmdPtr0Dec.asUInt)) & ~CmdPtr0Dec(i) & (buf_state(i) === CMD) & ~buf_cmd_state_bus_en(i)
|
||||
RspPtrDec(i) := ~(buf_rsp_pickage(i).asUInt.orR()) & (buf_state(i) === DONE_WAIT)
|
||||
// WrPtr0_m := PriorityMux((0 until DEPTH).map(i =>(((buf_state(i)===IDLE.U) & !((ibuf_valid & (ibuf_tag====i.U)) | (io.lsu_busreq_r & ((WrPtr0_r === i) | (io.ldst_dual_r & (WrPtr1_r === i)))))).asBool -> i.asUInt(DEPTH_LOG2.W))))
|
||||
val test_seq = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & ibuf_tag===i.U) |
|
||||
(io.lsu_busreq_r & ((WrPtr0_r===i.U) | (io.ldst_dual_r & (WrPtr1_r===i.U)))))).asBool() -> i.U)
|
||||
WrPtr0_m := MuxCase(0.U, test_seq)
|
||||
val test_seq2 = (0 until DEPTH).map(i=>((buf_state(i) === idle_C) & !((ibuf_valid & (ibuf_tag === i.U)) |
|
||||
(io.lsu_busreq_m & (WrPtr0_m === i.U)) | (io.lsu_busreq_r & (WrPtr0_r === i.U) |
|
||||
(io.ldst_dual_r & (WrPtr1_r === i.U))))).asBool -> i.U)
|
||||
WrPtr1_m := MuxCase(0.U, test_seq2)
|
||||
|
||||
buf_age_in(i)(j) := (((buf_state(i) === IDLE) & buf_state_en(i)) &
|
||||
(((buf_state(j) === WAIT) | ((buf_state(j) === CMD) & ~buf_cmd_state_bus_en(j))) |
|
||||
(ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (i === WrPtr0_r) & (j === ibuf_tag)) |
|
||||
(ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (i === WrPtr1_r) & (j === WrPtr0_r)))) | buf_age(i)(j)
|
||||
for {
|
||||
i <- 0 until DEPTH
|
||||
j <- 0 until DEPTH
|
||||
}{
|
||||
CmdPtr0Dec(i) := ~(buf_age(i).asUInt.orR()) & (buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i)
|
||||
CmdPtr1Dec(i) := ~((buf_age(i).asUInt & ~CmdPtr0Dec.asUInt).orR()) & ~CmdPtr0Dec(i) & (buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i)
|
||||
RspPtrDec(i) := ~(buf_rsp_pickage(i).asUInt.orR()) & (buf_state(i) === done_wait_C)
|
||||
|
||||
buf_age(i)(j) := buf_ageQ(i)(j) & ~((buf_state(j) === CMD) & buf_cmd_state_bus_en(j))
|
||||
buf_age_younger(i)(j) := Mux(i.asUInt(DEPTH_LOG2.W) === j.asUInt(DEPTH_LOG2.W), 0.U, (~buf_age(i)(j) & (buf_state(j) =/= IDLE)))
|
||||
buf_age_in(i)(j) := (((buf_state(i) === idle_C) & buf_state_en(i)) &
|
||||
(((buf_state(j) === wait_C) | ((buf_state(j) === cmd_C) & ~buf_cmd_state_bus_en(j))) |
|
||||
(ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (i === WrPtr0_r) & (j === ibuf_tag)) |
|
||||
(ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (i === WrPtr1_r) & (j === WrPtr0_r)))) | buf_age(i)(j)
|
||||
|
||||
buf_rspage_set(i)(j) := ((buf_state(i) === IDLE) & buf_state_en(i)) & (~((buf_state(j) === IDLE) | (buf_state(j) === DONE)) |
|
||||
(ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (i === WrPtr0_r) & (j === ibuf_tag)) |
|
||||
(ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (i === WrPtr1_r) & (j === WrPtr0_r)))
|
||||
buf_rspage_in(i)(j) := buf_rspage_set(i)(j) | buf_rspage(i)(j)
|
||||
buf_rspage(i)(j) := buf_rspageQ(i)(j) & ~((buf_state(j) === DONE) | (buf_state(j) === IDLE))
|
||||
buf_rsp_pickage(i)(j) := buf_rspageQ(i)(j) & (buf_state(j) === DONE_WAIT)
|
||||
}
|
||||
buf_age(i)(j) := buf_ageQ(i)(j) & ~((buf_state(j) === cmd_C) & buf_cmd_state_bus_en(j))
|
||||
buf_age_younger(i)(j) := Mux(i.asUInt(DEPTH_LOG2.W) === j.asUInt(DEPTH_LOG2.W), 0.U, (~buf_age(i)(j) & (buf_state(j) =/= idle_C)))
|
||||
|
||||
CmdPtr0 := PriorityEncoderOH(CmdPtr0Dec.asUInt)
|
||||
CmdPtr1 := PriorityEncoderOH(CmdPtr1Dec.asUInt)
|
||||
RspPtr := PriorityEncoderOH(RspPtrDec.asUInt)
|
||||
found_cmdptr0 := CmdPtr0Dec.reduce(_|_)
|
||||
found_cmdptr1 := CmdPtr1Dec.reduce(_|_)
|
||||
buf_rspage_set(i)(j) := ((buf_state(i) === idle_C) & buf_state_en(i)) & (~((buf_state(j) === idle_C) | (buf_state(j) === done_C)) |
|
||||
(ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (i === WrPtr0_r) & (j === ibuf_tag)) |
|
||||
(ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (i === WrPtr1_r) & (j === WrPtr0_r)))
|
||||
buf_rspage_in(i)(j) := buf_rspage_set(i)(j) | buf_rspage(i)(j)
|
||||
buf_rspage(i)(j) := buf_rspageQ(i)(j) & ~((buf_state(j) === done_C) | (buf_state(j) === idle_C))
|
||||
buf_rsp_pickage(i)(j) := buf_rspageQ(i)(j) & (buf_state(j) === done_wait_C)
|
||||
}
|
||||
|
||||
CmdPtr0 := PriorityEncoderOH(CmdPtr0Dec.asUInt)
|
||||
CmdPtr1 := PriorityEncoderOH(CmdPtr1Dec.asUInt)
|
||||
RspPtr := PriorityEncoderOH(RspPtrDec.asUInt)
|
||||
found_cmdptr0 := CmdPtr0Dec.reduce(_|_)
|
||||
found_cmdptr1 := CmdPtr1Dec.reduce(_|_)
|
||||
|
||||
////////////////////////// FSM ///////////////////////////////////////
|
||||
for (i <- 0 until DEPTH){
|
||||
buf_nxtstate(i) := IDLE
|
||||
buf_nxtstate(i) := idle_C
|
||||
buf_state_en(i) := 0.U
|
||||
buf_cmd_state_bus_en(i) := 0.U
|
||||
buf_resp_state_bus_en(i) := 0.U
|
||||
|
|
@ -603,33 +612,33 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
|
||||
// Buffer entry state machine
|
||||
switch (buf_state(i)){
|
||||
is (IDLE) {
|
||||
buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), CMD, WAIT)
|
||||
buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & ~ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag))
|
||||
is (idle_C) {
|
||||
buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C)
|
||||
buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag))
|
||||
buf_wr_en(i) := buf_state_en(i)
|
||||
buf_data_en(i) := buf_state_en(i)
|
||||
buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0))
|
||||
}
|
||||
is (WAIT) {
|
||||
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), IDLE, CMD)
|
||||
is (wait_C) {
|
||||
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C)
|
||||
buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt
|
||||
}
|
||||
is (CMD) {
|
||||
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), IDLE, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), DONE_WAIT, RESP))
|
||||
is (cmd_C) {
|
||||
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C))
|
||||
buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(pt1.LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(pt1.LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ
|
||||
buf_state_bus_en(i) := buf_cmd_state_bus_en(i)
|
||||
buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
|
||||
buf_ldfwd_in(i) := 1.U(1.W)
|
||||
buf_ldfwd_en(i) := buf_state_en(i) & ~buf_write(i) & obuf_nosend & ~io.dec_tlu_force_halt
|
||||
buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt
|
||||
buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(pt1.LSU_BUS_TAG - 2,0)).asUInt
|
||||
buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read
|
||||
buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error
|
||||
buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31,0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)))
|
||||
}
|
||||
is (RESP){
|
||||
buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & ~(pt.BUILD_AXI_NATIVE & bus_rsp_write_error))).asBool(), IDLE,
|
||||
Mux((buf_dual(i) & ~ buf_samedw(i) & ~ buf_write(i) &(buf_state(buf_dualtag(i)) =/= DONE_PARTIAL)), DONE_PARTIAL,
|
||||
Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & ~ buf_samedw(i) & ~ buf_write(i) & buf_ldfwd(buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === DONE_PARTIAL) & any_done_wait_state)), DONE_WAIT, DONE)))
|
||||
is (resp_C){
|
||||
buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & ~(pt.BUILD_AXI_NATIVE & bus_rsp_write_error))).asBool(), idle_C,
|
||||
Mux((buf_dual(i) & ~ buf_samedw(i) & ~ buf_write(i) &(buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C,
|
||||
Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & ~ buf_samedw(i) & ~ buf_write(i) & buf_ldfwd(buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C)))
|
||||
buf_resp_state_bus_en(i):= (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(pt1.LSU_BUS_TAG.W)))) |
|
||||
(bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(pt1.LSU_BUS_TAG.W))) |
|
||||
(buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) |
|
||||
|
|
@ -640,20 +649,20 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(pt1.LSU_BUS_TAG.W))) ) |
|
||||
(bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) |
|
||||
(bus_rsp_write_error & pt.BUILD_AXI_NATIVE & (bus_rsp_write_tag === i.asUInt(pt1.LSU_BUS_TAG.W))))
|
||||
buf_data_in(i) := Mux((buf_state_en(i) & ~buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0))
|
||||
buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0))
|
||||
}
|
||||
is (DONE_PARTIAL){ // Other part of dual load hasn't returned
|
||||
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), IDLE, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), DONE_WAIT, DONE))
|
||||
is (done_partial_C){ // Other part of dual load hasn't returned
|
||||
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C))
|
||||
buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) |
|
||||
(buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt())))
|
||||
buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
|
||||
}
|
||||
is (DONE_WAIT) { // WAIT state if there are multiple outstanding nb returns
|
||||
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), IDLE, DONE)
|
||||
is (done_wait_C) { // WAIT state if there are multiple outstanding nb returns
|
||||
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C)
|
||||
buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) |(buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt
|
||||
}
|
||||
is (DONE) {
|
||||
buf_nxtstate(i) := IDLE
|
||||
is (done_C) {
|
||||
buf_nxtstate(i) := idle_C
|
||||
buf_rst(i) := 1.U
|
||||
buf_state_en(i) := 1.U
|
||||
buf_ldfwd_in(i) := 0.U
|
||||
|
|
@ -664,7 +673,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
buf_byteen(i) := RegEnable(buf_byteen_in(i) , init = 0.U ,buf_wr_en(i))
|
||||
buf_data(i) := RegEnable(buf_data_in(i) , init = 0.U ,buf_data_en(i))
|
||||
withClock(io.lsu_bus_buf_c1_clk){
|
||||
buf_state(i) := RegEnable(buf_nxtstate(i) , init = IDLE ,buf_state_en(i))
|
||||
buf_state(i) := RegEnable(buf_nxtstate(i) , init = idle_C ,buf_state_en(i))
|
||||
buf_dualtag(i) := RegEnable(buf_dualtag_in(i) , init = 0.U ,buf_wr_en(i))
|
||||
buf_dual(i) := RegEnable(buf_dual_in(i) , init = 0.U ,buf_wr_en(i))
|
||||
buf_samedw(i) := RegEnable(buf_samedw_in(i) , init = 0.U ,buf_wr_en(i))
|
||||
|
|
@ -685,11 +694,11 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
buf_numvld_any := (io.lsu_busreq_m << io.ldst_dual_m) + (io.lsu_busreq_r << io.ldst_dual_r) + ibuf_valid +
|
||||
{for(i <- 0 until DEPTH) yield ( buf_state(i) =/= IDLE).asUInt }.reduce(_+_)
|
||||
buf_numvld_wrcmd_any := {for(i <- 0 until DEPTH) yield (( buf_state(i) === CMD) & ~buf_cmd_state_bus_en(i) & buf_write(i)).asUInt }.reduce(_+_)
|
||||
buf_numvld_cmd_any := {for(i <- 0 until DEPTH) yield (( buf_state(i) === CMD) & ~buf_cmd_state_bus_en(i)).asUInt }.reduce(_+_)
|
||||
buf_numvld_pend_any := {for(i <- 0 until DEPTH) yield (((buf_state(i) === CMD) & ~buf_cmd_state_bus_en(i)) | (buf_state(i) === WAIT)).asUInt }.reduce(_+_)
|
||||
any_done_wait_state := {for(i <- 0 until DEPTH) yield buf_state(i) === DONE_WAIT }.reduce(_|_)
|
||||
{for(i <- 0 until DEPTH) yield ( buf_state(i) =/= idle_C).asUInt }.reduce(_+_)
|
||||
buf_numvld_wrcmd_any := {for(i <- 0 until DEPTH) yield (( buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i) & buf_write(i)).asUInt }.reduce(_+_)
|
||||
buf_numvld_cmd_any := {for(i <- 0 until DEPTH) yield (( buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i)).asUInt }.reduce(_+_)
|
||||
buf_numvld_pend_any := {for(i <- 0 until DEPTH) yield (((buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i)) | (buf_state(i) === wait_C)).asUInt }.reduce(_+_)
|
||||
any_done_wait_state := {for(i <- 0 until DEPTH) yield buf_state(i) === done_wait_C }.reduce(_|_)
|
||||
|
||||
io.lsu_bus_buffer_pend_any := buf_numvld_pend_any =/= 0.U
|
||||
io.lsu_bus_buffer_full_any := Mux((io.ldst_dual_d & io.dec_lsu_valid_raw_d),buf_numvld_any(3,0) >= (DEPTH-1).asUInt(4.W), buf_numvld_any(3,0) === DEPTH.asUInt(4.W))
|
||||
|
|
@ -700,11 +709,11 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
io.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & ~io.lsu_commit_r
|
||||
io.lsu_nonblock_load_inv_tag_r := WrPtr0_r(DEPTH_LOG2-1,0)
|
||||
|
||||
lsu_nonblock_load_data_ready := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === DONE) -> ~(pt.BUILD_AXI_NATIVE & buf_write(i))))
|
||||
io.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === DONE & ~buf_write(i)) -> (buf_error(i))))
|
||||
io.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === DONE & (~buf_dual(i) | ~buf_dualhi(i)) & ~buf_write(i)) -> intToUInt(i)))
|
||||
lsu_nonblock_load_data_lo := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === DONE & ~buf_write(i) & (~buf_dual(i) | ~buf_dualhi(i))) -> buf_data(i)))
|
||||
lsu_nonblock_load_data_hi := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === DONE & ~buf_write(i) & ( buf_dual(i) & buf_dualhi(i))) -> buf_data(i)))
|
||||
lsu_nonblock_load_data_ready := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C) -> ~(pt.BUILD_AXI_NATIVE & buf_write(i))))
|
||||
io.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & ~buf_write(i)) -> (buf_error(i))))
|
||||
io.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & (~buf_dual(i) | ~buf_dualhi(i)) & ~buf_write(i)) -> intToUInt(i)))
|
||||
lsu_nonblock_load_data_lo := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & ~buf_write(i) & (~buf_dual(i) | ~buf_dualhi(i))) -> buf_data(i)))
|
||||
lsu_nonblock_load_data_hi := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & ~buf_write(i) & ( buf_dual(i) & buf_dualhi(i))) -> buf_data(i)))
|
||||
|
||||
lsu_nonblock_addr_offset := buf_addr(io.lsu_nonblock_load_data_tag)(1,0)
|
||||
lsu_nonblock_sz := buf_sz(io.lsu_nonblock_load_data_tag)(1,0)
|
||||
|
|
@ -719,8 +728,8 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
(~lsu_nonblock_unsign & lsu_nonblock_sz === 1.U) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)),lsu_nonblock_data_unalgn(15,0)),
|
||||
(lsu_nonblock_unsign & lsu_nonblock_sz === 2.U) -> lsu_nonblock_data_unalgn(31,0)
|
||||
))
|
||||
bus_sideeffect_pend := Mux(obuf_valid,obuf_sideeffect & io.dec_tlu_sideeffect_posted_disable,Mux1H((0 until DEPTH).map(i =>(buf_state(i) === RESP) -> (buf_sideeffect(i) & io.dec_tlu_sideeffect_posted_disable))))
|
||||
bus_addr_match_pending := Mux1H((0 until DEPTH).map(i =>(pt.BUILD_AXI_NATIVE & obuf_valid & (obuf_addr(31,3) === buf_addr(i)(31,3))).asBool -> ((buf_state(i) === RESP) & ~((obuf_tag0 === intToUInt(i)) | (obuf_merge & (obuf_tag1 === intToUInt(i)))))))
|
||||
bus_sideeffect_pend := Mux(obuf_valid,obuf_sideeffect & io.dec_tlu_sideeffect_posted_disable,Mux1H((0 until DEPTH).map(i =>(buf_state(i) === resp_C) -> (buf_sideeffect(i) & io.dec_tlu_sideeffect_posted_disable))))
|
||||
bus_addr_match_pending := Mux1H((0 until DEPTH).map(i =>(pt.BUILD_AXI_NATIVE & obuf_valid & (obuf_addr(31,3) === buf_addr(i)(31,3))).asBool -> ((buf_state(i) === resp_C) & ~((obuf_tag0 === intToUInt(i)) | (obuf_merge & (obuf_tag1 === intToUInt(i)))))))
|
||||
|
||||
bus_cmd_ready := Mux(obuf_write, Mux((obuf_cmd_done | obuf_data_done), Mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready), (io.lsu_axi_awready & io.lsu_axi_wready)), io.lsu_axi_arready)
|
||||
bus_wcmd_sent := io.lsu_axi_awvalid & io.lsu_axi_awready
|
||||
|
|
@ -737,7 +746,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
//////////////////////////////////////////////////////////////////////////////////
|
||||
lsu_axi_rdata_q := RegEnable(io.lsu_axi_rdata, init = 0.U, io.lsu_axi_rvalid&io.lsu_bus_clk_en)
|
||||
withClock(io.lsu_c2_r_clk){
|
||||
io.lsu_busreq_r := RegNext(RegNext((io.lsu_busreq_m & ~io.flush_r & ~io.ld_full_hit_m), init = 0.U), init = 0.U)
|
||||
io.lsu_busreq_r := RegNext((io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m), 0.U)
|
||||
WrPtr0_r := RegNext(WrPtr0_m, init = 0.U)
|
||||
WrPtr1_r := RegNext(WrPtr1_m, init = 0.U)
|
||||
lsu_nonblock_load_valid_r := RegNext(io.lsu_nonblock_load_valid_m, init = 0.U)
|
||||
|
|
@ -763,9 +772,9 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset
|
|||
io.ld_fwddata_buf_lo := 0.U
|
||||
io.ld_fwddata_buf_hi := 0.U
|
||||
|
||||
lsu_imprecise_error_store_tag := Mux1H((0 until DEPTH).map(i =>(((buf_state(i) === DONE) & buf_error(i) & buf_write(i)) -> intToUInt(i))))
|
||||
lsu_imprecise_error_store_tag := Mux1H((0 until DEPTH).map(i =>(((buf_state(i) === done_C) & buf_error(i) & buf_write(i)) -> intToUInt(i))))
|
||||
io.lsu_imprecise_error_load_any := io.lsu_nonblock_load_data_error & ~io.lsu_imprecise_error_store_any
|
||||
io.lsu_imprecise_error_store_any := {for(i <- 0 until DEPTH) yield io.lsu_bus_clk_en_q & (buf_state(i) === DONE) & buf_error(i) & buf_write(i)}.reduce(_|_)
|
||||
io.lsu_imprecise_error_store_any := {for(i <- 0 until DEPTH) yield io.lsu_bus_clk_en_q & (buf_state(i) === done_C) & buf_error(i) & buf_write(i)}.reduce(_|_)
|
||||
io.lsu_imprecise_error_addr_any := Mux(io.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.lsu_nonblock_load_data_tag))
|
||||
|
||||
bus_pend_trxnQ := 0.U(8.W)
|
||||
|
|
|
|||
|
|
@ -246,9 +246,9 @@ class el2_lsu_bus_intf extends Module with RequireAsyncReset{
|
|||
ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_r.word.asBool -> 15.U(4.W), io.lsu_pkt_r.half.asBool -> 3.U(4.W), io.lsu_pkt_r.by.asBool -> 1.U(4.W)))
|
||||
ldst_dual_d := io.lsu_addr_d(2) =/= io.end_addr_d(2)
|
||||
addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3))
|
||||
addr_match_word_lo_r_m := addr_match_dw_lo_r_m & ~(io.lsu_addr_r(2)^io.lsu_addr_m(2))
|
||||
no_word_merge_r := io.lsu_busreq_r & ~ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.load | ~addr_match_word_lo_r_m)
|
||||
no_dword_merge_r := io.lsu_busreq_r & ~ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.load | ~addr_match_dw_lo_r_m)
|
||||
addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2))
|
||||
no_word_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.load | !addr_match_word_lo_r_m)
|
||||
no_dword_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.load | !addr_match_dw_lo_r_m)
|
||||
ldst_byteen_ext_m := Cat(0.U(4.W),ldst_byteen_m(3,0)) << io.lsu_addr_m(1,0)
|
||||
ldst_byteen_ext_r := Cat(0.U(4.W),ldst_byteen_r(3,0)) << io.lsu_addr_r(1,0)
|
||||
store_data_ext_r := Cat(0.U(32.W),io.store_data_r(31,0)) << Cat(io.lsu_addr_r(1,0),0.U(3.W))
|
||||
|
|
@ -274,9 +274,9 @@ class el2_lsu_bus_intf extends Module with RequireAsyncReset{
|
|||
ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | ~ldst_byteen_lo_m(i))).asUInt).reduce(_&_)
|
||||
ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | ~ldst_byteen_hi_m(i))).asUInt).reduce(_&_)
|
||||
ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.load & ~io.is_sideeffects_m
|
||||
ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_)
|
||||
ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_)
|
||||
ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.load & !io.is_sideeffects_m
|
||||
ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0))
|
||||
io.bus_read_data_m := ld_fwddata_m(31,0)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,59 +1,56 @@
|
|||
|
||||
package lsu
|
||||
import chisel3._
|
||||
import chisel3.experimental.chiselName
|
||||
import chisel3.util._
|
||||
import lib._
|
||||
import include._
|
||||
import snapshot._
|
||||
|
||||
//noinspection ScalaStyle
|
||||
@chiselName
|
||||
class el2_lsu_clkdomain extends Module with RequireAsyncReset with el2_lib{
|
||||
val io = IO (new Bundle {
|
||||
/* Implicit
|
||||
val clk = Input(Clock()) // clock
|
||||
val rst_l = Input(1.W) // reset
|
||||
*/
|
||||
val free_clk = Input(Clock()) // clock
|
||||
// Inputs
|
||||
val clk_override = Input(Bool()) // chciken bit to turn off clock gating
|
||||
val addr_in_dccm_m = Input(Bool()) // address in dccm
|
||||
val dma_dccm_req = Input(Bool()) // dma is active
|
||||
val ldst_stbuf_reqvld_r = Input(Bool()) // allocating in to the store queue
|
||||
|
||||
val stbuf_reqvld_any = Input(Bool()) // stbuf is draining
|
||||
val stbuf_reqvld_flushed_any = Input(Bool()) // instruction going to stbuf is flushed
|
||||
val lsu_busreq_r = Input(Bool()) // busreq in r
|
||||
val lsu_bus_buffer_pend_any = Input(Bool()) // bus buffer has a pending bus entry
|
||||
val lsu_bus_buffer_empty_any = Input(Bool()) // external bus buffer is empty
|
||||
val lsu_stbuf_empty_any = Input(Bool()) // stbuf is empty
|
||||
val free_clk = Input(Clock()) // clock
|
||||
// Inputs
|
||||
val clk_override = Input(Bool()) // chciken bit to turn off clock gating
|
||||
val addr_in_dccm_m = Input(Bool()) // address in dccm
|
||||
val dma_dccm_req = Input(Bool()) // dma is active
|
||||
val ldst_stbuf_reqvld_r = Input(Bool()) // allocating in to the store queue
|
||||
|
||||
val lsu_bus_clk_en = Input(Bool()) // bus clock enable
|
||||
val stbuf_reqvld_any = Input(Bool()) // stbuf is draining
|
||||
val stbuf_reqvld_flushed_any = Input(Bool()) // instruction going to stbuf is flushed
|
||||
val lsu_busreq_r = Input(Bool()) // busreq in r
|
||||
val lsu_bus_buffer_pend_any = Input(Bool()) // bus buffer has a pending bus entry
|
||||
val lsu_bus_buffer_empty_any = Input(Bool()) // external bus buffer is empty
|
||||
val lsu_stbuf_empty_any = Input(Bool()) // stbuf is empty
|
||||
|
||||
val lsu_p = Input(new el2_lsu_pkt_t) // lsu packet in decode
|
||||
val lsu_pkt_d = Input(new el2_lsu_pkt_t) // lsu packet in d
|
||||
val lsu_pkt_m = Input(new el2_lsu_pkt_t) // lsu packet in m
|
||||
val lsu_pkt_r = Input(new el2_lsu_pkt_t) // lsu packet in r
|
||||
val lsu_bus_clk_en = Input(Bool()) // bus clock enable
|
||||
|
||||
// Outputs
|
||||
val lsu_c1_m_clk = Output(Clock()) // m pipe single pulse clock
|
||||
val lsu_c1_r_clk = Output(Clock()) // r pipe single pulse clock
|
||||
val lsu_p = Input(new el2_lsu_pkt_t) // lsu packet in decode
|
||||
val lsu_pkt_d = Input(new el2_lsu_pkt_t) // lsu packet in d
|
||||
val lsu_pkt_m = Input(new el2_lsu_pkt_t) // lsu packet in m
|
||||
val lsu_pkt_r = Input(new el2_lsu_pkt_t) // lsu packet in r
|
||||
|
||||
val lsu_c2_m_clk = Output(Clock()) // m pipe double pulse clock
|
||||
val lsu_c2_r_clk = Output(Clock()) // r pipe double pulse clock
|
||||
// Outputs
|
||||
val lsu_c1_m_clk = Output(Clock()) // m pipe single pulse clock
|
||||
val lsu_c1_r_clk = Output(Clock()) // r pipe single pulse clock
|
||||
|
||||
val lsu_store_c1_m_clk = Output(Clock()) // store in m
|
||||
val lsu_store_c1_r_clk = Output(Clock()) // store in r
|
||||
val lsu_c2_m_clk = Output(Clock()) // m pipe double pulse clock
|
||||
val lsu_c2_r_clk = Output(Clock()) // r pipe double pulse clock
|
||||
|
||||
val lsu_stbuf_c1_clk = Output(Clock())
|
||||
val lsu_bus_obuf_c1_clk = Output(Clock()) // ibuf clock
|
||||
val lsu_bus_ibuf_c1_clk = Output(Clock()) // ibuf clock
|
||||
val lsu_bus_buf_c1_clk = Output(Clock()) // ibuf clock
|
||||
val lsu_busm_clk = Output(Clock()) // bus clock
|
||||
val lsu_store_c1_m_clk = Output(Clock()) // store in m
|
||||
val lsu_store_c1_r_clk = Output(Clock()) // store in r
|
||||
|
||||
val lsu_free_c2_clk = Output(Clock())
|
||||
val lsu_stbuf_c1_clk = Output(Clock())
|
||||
val lsu_bus_obuf_c1_clk = Output(Clock()) // ibuf clock
|
||||
val lsu_bus_ibuf_c1_clk = Output(Clock()) // ibuf clock
|
||||
val lsu_bus_buf_c1_clk = Output(Clock()) // ibuf clock
|
||||
val lsu_busm_clk = Output(Clock()) // bus clock
|
||||
|
||||
val scan_mode = Input(Bool())
|
||||
})
|
||||
val lsu_free_c2_clk = Output(Clock())
|
||||
|
||||
val scan_mode = Input(Bool())
|
||||
})
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// Clock Enable Logic
|
||||
|
|
@ -62,6 +59,7 @@ class el2_lsu_clkdomain extends Module with RequireAsyncReset with el2_lib{
|
|||
val lsu_c1_m_clken_q = Wire(Bool())
|
||||
val lsu_c1_r_clken_q = Wire(Bool())
|
||||
val lsu_free_c1_clken_q = Wire(Bool())
|
||||
|
||||
val lsu_c1_d_clken = io.lsu_p.valid | io.dma_dccm_req | io.clk_override
|
||||
val lsu_c1_m_clken = io.lsu_pkt_d.valid | lsu_c1_d_clken_q | io.clk_override
|
||||
val lsu_c1_r_clken = io.lsu_pkt_m.valid | lsu_c1_m_clken_q | io.clk_override
|
||||
|
|
@ -74,44 +72,29 @@ class el2_lsu_clkdomain extends Module with RequireAsyncReset with el2_lib{
|
|||
val lsu_stbuf_c1_clken = io.ldst_stbuf_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override
|
||||
val lsu_bus_ibuf_c1_clken = io.lsu_busreq_r | io.clk_override
|
||||
val lsu_bus_obuf_c1_clken = (io.lsu_bus_buffer_pend_any | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en
|
||||
val lsu_bus_buf_c1_clken = ~io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.clk_override
|
||||
val lsu_bus_buf_c1_clken = (!io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.clk_override).asBool
|
||||
|
||||
val lsu_free_c1_clken = (io.lsu_p.valid | io.lsu_pkt_d.valid | io.lsu_pkt_m.valid | io.lsu_pkt_r.valid) | ~io.lsu_bus_buffer_empty_any | ~io.lsu_stbuf_empty_any | io.clk_override
|
||||
val lsu_free_c1_clken = (io.lsu_p.valid | io.lsu_pkt_d.valid | io.lsu_pkt_m.valid | io.lsu_pkt_r.valid) | !io.lsu_bus_buffer_empty_any | !io.lsu_stbuf_empty_any | io.clk_override
|
||||
val lsu_free_c2_clken = lsu_free_c1_clken | lsu_free_c1_clken_q | io.clk_override
|
||||
|
||||
|
||||
lsu_free_c1_clken_q := withClock(io.free_clk) {RegNext(lsu_free_c1_clken,0.U)}
|
||||
|
||||
lsu_c1_d_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_d_clken, 0.U)}
|
||||
lsu_c1_m_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_m_clken, 0.U)}
|
||||
lsu_c1_r_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_r_clken, 0.U)}
|
||||
|
||||
val lsu_c1m_cgc = Module(new rvclkhdr); lsu_c1m_cgc.io.en := lsu_c1_m_clken ; io.lsu_c1_m_clk := lsu_c1m_cgc.io.l1clk
|
||||
val lsu_c1r_cgc = Module(new rvclkhdr); lsu_c1r_cgc.io.en := lsu_c1_r_clken ; io.lsu_c1_r_clk := lsu_c1r_cgc.io.l1clk
|
||||
val lsu_c2m_cgc = Module(new rvclkhdr); lsu_c2m_cgc.io.en := lsu_c2_m_clken ; io.lsu_c2_m_clk := lsu_c2m_cgc.io.l1clk
|
||||
val lsu_c2r_cgc = Module(new rvclkhdr); lsu_c2r_cgc.io.en := lsu_c2_r_clken ; io.lsu_c2_r_clk := lsu_c2r_cgc.io.l1clk
|
||||
val lsu_store_c1m_cgc = Module(new rvclkhdr); lsu_store_c1m_cgc.io.en := lsu_store_c1_m_clken ; io.lsu_store_c1_m_clk := lsu_store_c1m_cgc.io.l1clk
|
||||
val lsu_store_c1r_cgc = Module(new rvclkhdr); lsu_store_c1r_cgc.io.en := lsu_store_c1_r_clken ; io.lsu_store_c1_r_clk := lsu_store_c1r_cgc.io.l1clk
|
||||
val lsu_stbuf_c1_cgc = Module(new rvclkhdr); lsu_stbuf_c1_cgc.io.en := lsu_stbuf_c1_clken ; io.lsu_stbuf_c1_clk := lsu_stbuf_c1_cgc.io.l1clk
|
||||
val lsu_bus_ibuf_c1_cgc = Module(new rvclkhdr); lsu_bus_ibuf_c1_cgc.io.en := lsu_bus_ibuf_c1_clken; io.lsu_bus_ibuf_c1_clk := lsu_bus_ibuf_c1_cgc.io.l1clk
|
||||
val lsu_bus_obuf_c1_cgc = Module(new rvclkhdr); lsu_bus_obuf_c1_cgc.io.en := lsu_bus_obuf_c1_clken; io.lsu_bus_obuf_c1_clk := lsu_bus_obuf_c1_cgc.io.l1clk
|
||||
val lsu_bus_buf_c1_cgc = Module(new rvclkhdr); lsu_bus_buf_c1_cgc.io.en := lsu_bus_buf_c1_clken ; io.lsu_bus_buf_c1_clk := lsu_bus_buf_c1_cgc.io.l1clk
|
||||
val lsu_busm_cgc = Module(new rvclkhdr); lsu_busm_cgc.io.en := io.lsu_bus_clk_en ; io.lsu_busm_clk := lsu_busm_cgc.io.l1clk
|
||||
val lsu_free_cgc = Module(new rvclkhdr); lsu_free_cgc.io.en := lsu_free_c2_clken ; io.lsu_free_c2_clk := lsu_free_cgc.io.l1clk
|
||||
|
||||
lsu_c1m_cgc.io.clk := clock; lsu_c1m_cgc.io.scan_mode := io.scan_mode
|
||||
lsu_c1r_cgc.io.clk := clock; lsu_c1r_cgc.io.scan_mode := io.scan_mode
|
||||
lsu_c2m_cgc.io.clk := clock; lsu_c2m_cgc.io.scan_mode := io.scan_mode
|
||||
lsu_c2r_cgc.io.clk := clock; lsu_c2r_cgc.io.scan_mode := io.scan_mode
|
||||
lsu_store_c1m_cgc.io.clk := clock; lsu_store_c1m_cgc.io.scan_mode := io.scan_mode
|
||||
lsu_store_c1r_cgc.io.clk := clock; lsu_store_c1r_cgc.io.scan_mode := io.scan_mode
|
||||
lsu_stbuf_c1_cgc.io.clk := clock; lsu_stbuf_c1_cgc.io.scan_mode := io.scan_mode
|
||||
lsu_bus_ibuf_c1_cgc.io.clk := clock; lsu_bus_ibuf_c1_cgc.io.scan_mode := io.scan_mode
|
||||
lsu_bus_obuf_c1_cgc.io.clk := clock; lsu_bus_obuf_c1_cgc.io.scan_mode := io.scan_mode
|
||||
lsu_bus_buf_c1_cgc.io.clk := clock; lsu_bus_buf_c1_cgc.io.scan_mode := io.scan_mode
|
||||
lsu_busm_cgc.io.clk := clock; lsu_busm_cgc.io.scan_mode := io.scan_mode
|
||||
lsu_free_cgc.io.clk := clock; lsu_free_cgc.io.scan_mode := io.scan_mode
|
||||
|
||||
io.lsu_c1_m_clk := rvclkhdr(clock,lsu_c1_m_clken.asBool,io.scan_mode)
|
||||
io.lsu_c1_r_clk := rvclkhdr(clock,lsu_c1_r_clken.asBool,io.scan_mode)
|
||||
io.lsu_c2_m_clk := rvclkhdr(clock,lsu_c2_m_clken.asBool,io.scan_mode)
|
||||
io.lsu_c2_r_clk := rvclkhdr(clock,lsu_c2_r_clken.asBool,io.scan_mode)
|
||||
io.lsu_store_c1_m_clk := rvclkhdr(clock,lsu_store_c1_m_clken.asBool,io.scan_mode)
|
||||
io.lsu_store_c1_r_clk := rvclkhdr(clock,lsu_store_c1_r_clken.asBool,io.scan_mode)
|
||||
io.lsu_stbuf_c1_clk := rvclkhdr(clock,lsu_stbuf_c1_clken.asBool,io.scan_mode)
|
||||
io.lsu_bus_ibuf_c1_clk := rvclkhdr(clock,lsu_bus_ibuf_c1_clken.asBool,io.scan_mode)
|
||||
io.lsu_bus_obuf_c1_clk := rvclkhdr(clock,lsu_bus_obuf_c1_clken.asBool,io.scan_mode)
|
||||
io.lsu_bus_buf_c1_clk := rvclkhdr(clock,lsu_bus_buf_c1_clken.asBool,io.scan_mode)
|
||||
io.lsu_busm_clk := rvclkhdr(clock,io.lsu_bus_clk_en.asBool,io.scan_mode)
|
||||
io.lsu_free_c2_clk := rvclkhdr(clock,lsu_free_c2_clken.asBool,io.scan_mode)
|
||||
|
||||
}
|
||||
object cgcmain extends App{
|
||||
|
|
|
|||
|
|
@ -1,21 +1,14 @@
|
|||
package lsu
|
||||
import include._
|
||||
import lib._
|
||||
import snapshot._
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
|
||||
import chisel3.experimental.ChiselEnum
|
||||
import chisel3.experimental.{withClock, withReset, withClockAndReset}
|
||||
import chisel3.experimental.BundleLiterals._
|
||||
import chisel3.tester._
|
||||
import chisel3.tester.RawTester.test
|
||||
import chisel3.util.HasBlackBoxResource
|
||||
|
||||
|
||||
|
||||
import chisel3.experimental.chiselName
|
||||
@chiselName
|
||||
class el2_lsu_dccm_ctl extends Module with RequireAsyncReset
|
||||
class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
|
||||
{
|
||||
val io = IO(new Bundle{
|
||||
//val rst_l = IO(Input(1.W)) //implicit
|
||||
|
|
@ -43,45 +36,45 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset
|
|||
|
||||
// lsu address down the pipe
|
||||
val lsu_addr_d = Input(UInt(32.W))//verify bits
|
||||
val lsu_addr_m = Input(UInt(pt1.DCCM_BITS.W))
|
||||
val lsu_addr_m = Input(UInt(DCCM_BITS.W))
|
||||
val lsu_addr_r = Input(UInt(32.W))
|
||||
|
||||
// lsu address down the pipe - needed to check unaligned
|
||||
val end_addr_d = Input(UInt(pt1.DCCM_BITS.W))
|
||||
val end_addr_m = Input(UInt(pt1.DCCM_BITS.W))
|
||||
val end_addr_r = Input(UInt(pt1.DCCM_BITS.W))
|
||||
val end_addr_d = Input(UInt(DCCM_BITS.W))
|
||||
val end_addr_m = Input(UInt(DCCM_BITS.W))
|
||||
val end_addr_r = Input(UInt(DCCM_BITS.W))
|
||||
|
||||
val stbuf_reqvld_any = Input(UInt(1.W))
|
||||
val stbuf_addr_any = Input(UInt(pt1.LSU_SB_BITS.W))
|
||||
val stbuf_data_any = Input(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val stbuf_ecc_any = Input(UInt(pt1.DCCM_ECC_WIDTH.W))
|
||||
val stbuf_fwddata_hi_m = Input(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val stbuf_fwddata_lo_m = Input(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val stbuf_fwdbyteen_lo_m = Input(UInt(pt1.DCCM_BYTE_WIDTH.W))
|
||||
val stbuf_fwdbyteen_hi_m = Input(UInt(pt1.DCCM_BYTE_WIDTH.W))
|
||||
val dccm_rdata_hi_r = Output(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val dccm_rdata_lo_r = Output(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val dccm_data_ecc_hi_r = Output(UInt(pt1.DCCM_ECC_WIDTH.W))
|
||||
val dccm_data_ecc_lo_r = Output(UInt(pt1.DCCM_ECC_WIDTH.W))
|
||||
val lsu_ld_data_r = Output(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val lsu_ld_data_corr_r = Output(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val stbuf_addr_any = Input(UInt(LSU_SB_BITS.W))
|
||||
val stbuf_data_any = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||
val stbuf_ecc_any = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||
val stbuf_fwddata_hi_m = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||
val stbuf_fwddata_lo_m = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||
val stbuf_fwdbyteen_lo_m = Input(UInt(DCCM_BYTE_WIDTH.W))
|
||||
val stbuf_fwdbyteen_hi_m = Input(UInt(DCCM_BYTE_WIDTH.W))
|
||||
val dccm_rdata_hi_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||
val dccm_rdata_lo_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||
val dccm_data_ecc_hi_r = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||
val dccm_data_ecc_lo_r = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||
val lsu_ld_data_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||
val lsu_ld_data_corr_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||
val lsu_double_ecc_error_r = Input(UInt(1.W))
|
||||
val single_ecc_error_hi_r = Input(UInt(1.W))
|
||||
val single_ecc_error_lo_r = Input(UInt(1.W))
|
||||
val sec_data_hi_r = Input(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val sec_data_lo_r = Input(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val sec_data_hi_r_ff = Input(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val sec_data_lo_r_ff = Input(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val sec_data_ecc_hi_r_ff = Input(UInt(pt1.DCCM_ECC_WIDTH.W))
|
||||
val sec_data_ecc_lo_r_ff = Input(UInt(pt1.DCCM_ECC_WIDTH.W))
|
||||
val dccm_rdata_hi_m = Output(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val dccm_rdata_lo_m = Output(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val dccm_data_ecc_hi_m = Output(UInt(pt1.DCCM_ECC_WIDTH.W))
|
||||
val dccm_data_ecc_lo_m = Output(UInt(pt1.DCCM_ECC_WIDTH.W))
|
||||
val lsu_ld_data_m = Output(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val sec_data_hi_r = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||
val sec_data_lo_r = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||
val sec_data_hi_r_ff = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||
val sec_data_lo_r_ff = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||
val sec_data_ecc_hi_r_ff = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||
val sec_data_ecc_lo_r_ff = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||
val dccm_rdata_hi_m = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||
val dccm_rdata_lo_m = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||
val dccm_data_ecc_hi_m = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||
val dccm_data_ecc_lo_m = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||
val lsu_ld_data_m = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||
val lsu_double_ecc_error_m = Input(UInt(1.W))
|
||||
val sec_data_hi_m = Input(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val sec_data_lo_m = Input(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val sec_data_hi_m = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||
val sec_data_lo_m = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||
val store_data_m = Input(UInt(32.W))
|
||||
val dma_dccm_wen = Input(UInt(1.W))
|
||||
val dma_pic_wen = Input(UInt(1.W))
|
||||
|
|
@ -90,12 +83,12 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset
|
|||
val dma_mem_wdata = Input(UInt(64.W))
|
||||
val dma_dccm_wdata_lo = Input(UInt(32.W))
|
||||
val dma_dccm_wdata_hi = Input(UInt(32.W))
|
||||
val dma_dccm_wdata_ecc_hi = Input(UInt(pt1.DCCM_ECC_WIDTH.W))
|
||||
val dma_dccm_wdata_ecc_lo = Input(UInt(pt1.DCCM_ECC_WIDTH.W))
|
||||
val store_data_hi_r = Output(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val store_data_lo_r = Output(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val store_datafn_hi_r = Output(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val store_datafn_lo_r = Output(UInt(pt1.DCCM_DATA_WIDTH.W))
|
||||
val dma_dccm_wdata_ecc_hi = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||
val dma_dccm_wdata_ecc_lo = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||
val store_data_hi_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||
val store_data_lo_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||
val store_datafn_hi_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||
val store_datafn_lo_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||
val store_data_r = Output(UInt(32.W))
|
||||
val ld_single_ecc_error_r = Output(UInt(1.W))
|
||||
val ld_single_ecc_error_r_ff = Output(UInt(1.W))
|
||||
|
|
@ -109,14 +102,14 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset
|
|||
val dccm_dma_rdata = Output(UInt(64.W))
|
||||
val dccm_wren = Output(UInt(1.W))
|
||||
val dccm_rden = Output(UInt(1.W))
|
||||
val dccm_wr_addr_lo = Output(UInt(pt1.DCCM_BITS.W))
|
||||
val dccm_wr_data_lo = Output(UInt(pt1.DCCM_FDATA_WIDTH.W))
|
||||
val dccm_rd_addr_lo = Output(UInt(pt1.DCCM_BITS.W))
|
||||
val dccm_rd_data_lo = Input(UInt(pt1.DCCM_FDATA_WIDTH.W))
|
||||
val dccm_wr_addr_hi = Output(UInt(pt1.DCCM_BITS.W))
|
||||
val dccm_wr_data_hi = Output(UInt(pt1.DCCM_FDATA_WIDTH.W))
|
||||
val dccm_rd_addr_hi = Output(UInt(pt1.DCCM_BITS.W))
|
||||
val dccm_rd_data_hi = Input(UInt(pt1.DCCM_FDATA_WIDTH.W))
|
||||
val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
|
||||
val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
|
||||
val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
|
||||
val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
|
||||
val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val picm_wren = Output(UInt(1.W))
|
||||
val picm_rden = Output(UInt(1.W))
|
||||
val picm_mken = Output(UInt(1.W))
|
||||
|
|
@ -143,7 +136,7 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset
|
|||
|
||||
|
||||
//Forwarding stbuf
|
||||
if (pt.LOAD_TO_USE_PLUS1 == 1){
|
||||
if (LOAD_TO_USE_PLUS1 == 1){
|
||||
io.dccm_dma_rvalid := io.lsu_pkt_r.valid & io.lsu_pkt_r.load & io.lsu_pkt_r.dma
|
||||
io.dccm_dma_ecc_error := io.lsu_double_ecc_error_r //from ecc
|
||||
io.dccm_dma_rdata := lsu_rdata_corr_r
|
||||
|
|
@ -183,31 +176,31 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset
|
|||
}
|
||||
|
||||
//Ecc error kill
|
||||
val kill_ecc_corr_lo_r = (((io.lsu_addr_d(pt1.DCCM_BITS-1,2) === io.lsu_addr_r(pt1.DCCM_BITS-1,2)).asUInt | (io.end_addr_d(pt1.DCCM_BITS-1,2) === io.lsu_addr_r(pt1.DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_d.valid & io.lsu_pkt_d.store & io.lsu_pkt_d.dma & io.addr_in_dccm_d) |
|
||||
(((io.lsu_addr_m(pt1.DCCM_BITS-1,2) === io.lsu_addr_r(pt1.DCCM_BITS-1,2)).asUInt | (io.end_addr_m(pt1.DCCM_BITS-1,2) === io.lsu_addr_r(pt1.DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.lsu_pkt_m.dma & io.addr_in_dccm_m)
|
||||
val kill_ecc_corr_lo_r = (((io.lsu_addr_d(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_d(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_d.valid & io.lsu_pkt_d.store & io.lsu_pkt_d.dma & io.addr_in_dccm_d) |
|
||||
(((io.lsu_addr_m(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_m(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.lsu_pkt_m.dma & io.addr_in_dccm_m)
|
||||
|
||||
val kill_ecc_corr_hi_r = (((io.lsu_addr_d(pt1.DCCM_BITS-1,2) === io.end_addr_r(pt1.DCCM_BITS-1,2)).asUInt | (io.end_addr_d(pt1.DCCM_BITS-1,2) === io.end_addr_r(pt1.DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_d.valid & io.lsu_pkt_d.store & io.lsu_pkt_d.dma & io.addr_in_dccm_d) |
|
||||
(((io.lsu_addr_m(pt1.DCCM_BITS-1,2) === io.end_addr_r(pt1.DCCM_BITS-1,2)).asUInt | (io.end_addr_m(pt1.DCCM_BITS-1,2) === io.end_addr_r(pt1.DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.lsu_pkt_m.dma & io.addr_in_dccm_m)
|
||||
val kill_ecc_corr_hi_r = (((io.lsu_addr_d(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_d(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_d.valid & io.lsu_pkt_d.store & io.lsu_pkt_d.dma & io.addr_in_dccm_d) |
|
||||
(((io.lsu_addr_m(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_m(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.lsu_pkt_m.dma & io.addr_in_dccm_m)
|
||||
|
||||
val ld_single_ecc_error_lo_r = io.lsu_pkt_r.load & io.single_ecc_error_lo_r & ~io.lsu_raw_fwd_lo_r
|
||||
val ld_single_ecc_error_hi_r = io.lsu_pkt_r.load & io.single_ecc_error_hi_r & ~io.lsu_raw_fwd_hi_r
|
||||
io.ld_single_ecc_error_r := (ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r) & ~io.lsu_double_ecc_error_r
|
||||
val ld_single_ecc_error_lo_r_ns = ld_single_ecc_error_lo_r & (io.lsu_commit_r | io.lsu_pkt_r.dma) & ~kill_ecc_corr_lo_r
|
||||
val ld_single_ecc_error_hi_r_ns = ld_single_ecc_error_hi_r & (io.lsu_commit_r | io.lsu_pkt_r.dma) & ~kill_ecc_corr_hi_r
|
||||
val ld_single_ecc_error_lo_r = io.lsu_pkt_r.load & io.single_ecc_error_lo_r & !io.lsu_raw_fwd_lo_r
|
||||
val ld_single_ecc_error_hi_r = io.lsu_pkt_r.load & io.single_ecc_error_hi_r & !io.lsu_raw_fwd_hi_r
|
||||
io.ld_single_ecc_error_r := (ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r) & !io.lsu_double_ecc_error_r
|
||||
val ld_single_ecc_error_lo_r_ns = ld_single_ecc_error_lo_r & (io.lsu_commit_r | io.lsu_pkt_r.dma) & !kill_ecc_corr_lo_r
|
||||
val ld_single_ecc_error_hi_r_ns = ld_single_ecc_error_hi_r & (io.lsu_commit_r | io.lsu_pkt_r.dma) & !kill_ecc_corr_hi_r
|
||||
|
||||
val lsu_double_ecc_error_r_ff = withClock(io.lsu_free_c2_clk){RegNext(io.lsu_double_ecc_error_r,0.U)}
|
||||
val ld_single_ecc_error_hi_r_ff = withClock(io.lsu_free_c2_clk){RegNext(ld_single_ecc_error_hi_r_ns,0.U)}
|
||||
val ld_single_ecc_error_lo_r_ff = withClock(io.lsu_free_c2_clk){RegNext(ld_single_ecc_error_lo_r_ns,0.U)}
|
||||
|
||||
val ld_sec_addr_hi_r_ff = rvdffe(io.end_addr_r(pt1.DCCM_BITS-1,0),io.ld_single_ecc_error_r.asBool,clock,io.scan_mode.asBool)
|
||||
val ld_sec_addr_lo_r_ff = rvdffe(io.lsu_addr_r(pt1.DCCM_BITS-1,0),io.ld_single_ecc_error_r.asBool,clock,io.scan_mode.asBool)
|
||||
val lsu_dccm_rden_d = io.lsu_pkt_d.valid & (io.lsu_pkt_d.load | (io.lsu_pkt_d.store & (~(io.lsu_pkt_d.word | io.lsu_pkt_d.dword) | (io.lsu_addr_d(1,0) =/= 0.U(2.W))))) & io.addr_in_dccm_d
|
||||
val ld_sec_addr_hi_r_ff = rvdffe(io.end_addr_r(DCCM_BITS-1,0),io.ld_single_ecc_error_r.asBool,clock,io.scan_mode.asBool)
|
||||
val ld_sec_addr_lo_r_ff = rvdffe(io.lsu_addr_r(DCCM_BITS-1,0),io.ld_single_ecc_error_r.asBool,clock,io.scan_mode.asBool)
|
||||
val lsu_dccm_rden_d = io.lsu_pkt_d.valid & (io.lsu_pkt_d.load | (io.lsu_pkt_d.store & (!(io.lsu_pkt_d.word | io.lsu_pkt_d.dword) | (io.lsu_addr_d(1,0) =/= 0.U(2.W))))) & io.addr_in_dccm_d
|
||||
val lsu_dccm_wren_d = io.dma_dccm_wen
|
||||
|
||||
io.ld_single_ecc_error_r_ff := (ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff) & ~lsu_double_ecc_error_r_ff
|
||||
io.lsu_stbuf_commit_any := io.stbuf_reqvld_any & (~(lsu_dccm_rden_d | lsu_dccm_wren_d | io.ld_single_ecc_error_r_ff) |
|
||||
(lsu_dccm_rden_d & ~((io.stbuf_addr_any(pt1.DCCM_WIDTH_BITS+pt1.DCCM_BANK_BITS-1,pt1.DCCM_WIDTH_BITS) === io.lsu_addr_d(pt1.DCCM_WIDTH_BITS+pt1.DCCM_BANK_BITS-1,pt1.DCCM_WIDTH_BITS)).asUInt |
|
||||
(io.stbuf_addr_any(pt1.DCCM_WIDTH_BITS+pt1.DCCM_BANK_BITS-1,pt1.DCCM_WIDTH_BITS) === io.end_addr_d(pt1.DCCM_WIDTH_BITS+pt1.DCCM_BANK_BITS-1,pt1.DCCM_WIDTH_BITS)).asUInt)))
|
||||
io.ld_single_ecc_error_r_ff := (ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff) & !lsu_double_ecc_error_r_ff
|
||||
io.lsu_stbuf_commit_any := io.stbuf_reqvld_any & (!(lsu_dccm_rden_d | lsu_dccm_wren_d | io.ld_single_ecc_error_r_ff) |
|
||||
(lsu_dccm_rden_d & !((io.stbuf_addr_any(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1,DCCM_WIDTH_BITS) === io.lsu_addr_d(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1,DCCM_WIDTH_BITS)).asUInt |
|
||||
(io.stbuf_addr_any(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1,DCCM_WIDTH_BITS) === io.end_addr_d(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1,DCCM_WIDTH_BITS)).asUInt)))
|
||||
|
||||
|
||||
//DCCM inputs
|
||||
|
|
@ -215,27 +208,27 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset
|
|||
io.dccm_rden := lsu_dccm_rden_d & io.addr_in_dccm_d
|
||||
|
||||
io.dccm_wr_addr_lo := Mux(io.ld_single_ecc_error_r_ff.asBool,
|
||||
Mux(ld_single_ecc_error_lo_r_ff===1.U,ld_sec_addr_lo_r_ff(pt1.DCCM_BITS-1,0),ld_sec_addr_hi_r_ff(pt1.DCCM_BITS-1,0)),
|
||||
Mux(lsu_dccm_wren_d.asBool,io.lsu_addr_d(pt1.DCCM_BITS-1,0),io.stbuf_addr_any(pt1.DCCM_BITS-1,0)))
|
||||
Mux(ld_single_ecc_error_lo_r_ff===1.U,ld_sec_addr_lo_r_ff(DCCM_BITS-1,0),ld_sec_addr_hi_r_ff(DCCM_BITS-1,0)),
|
||||
Mux(lsu_dccm_wren_d.asBool,io.lsu_addr_d(DCCM_BITS-1,0),io.stbuf_addr_any(DCCM_BITS-1,0)))
|
||||
|
||||
io.dccm_wr_addr_hi := Mux(io.ld_single_ecc_error_r_ff.asBool,
|
||||
Mux(ld_single_ecc_error_hi_r_ff===1.U, ld_sec_addr_hi_r_ff(pt1.DCCM_BITS-1,0), ld_sec_addr_lo_r_ff(pt1.DCCM_BITS-1,0)),
|
||||
Mux(lsu_dccm_wren_d.asBool, io.end_addr_d(pt1.DCCM_BITS-1,0),io.stbuf_addr_any(pt1.DCCM_BITS-1,0)))
|
||||
Mux(ld_single_ecc_error_hi_r_ff===1.U, ld_sec_addr_hi_r_ff(DCCM_BITS-1,0), ld_sec_addr_lo_r_ff(DCCM_BITS-1,0)),
|
||||
Mux(lsu_dccm_wren_d.asBool, io.end_addr_d(DCCM_BITS-1,0),io.stbuf_addr_any(DCCM_BITS-1,0)))
|
||||
|
||||
io.dccm_rd_addr_lo := io.lsu_addr_d(pt1.DCCM_BITS-1,0)
|
||||
io.dccm_rd_addr_hi := io.end_addr_d(pt1.DCCM_BITS-1,0)
|
||||
io.dccm_rd_addr_lo := io.lsu_addr_d(DCCM_BITS-1,0)
|
||||
io.dccm_rd_addr_hi := io.end_addr_d(DCCM_BITS-1,0)
|
||||
|
||||
io.dccm_wr_data_lo := Mux(io.ld_single_ecc_error_r_ff.asBool,
|
||||
Mux(ld_single_ecc_error_lo_r_ff===0.U,Cat(io.sec_data_ecc_lo_r_ff(pt1.DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(pt1.DCCM_DATA_WIDTH-1,0)) ,
|
||||
Cat(io.sec_data_ecc_hi_r_ff(pt1.DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(pt1.DCCM_DATA_WIDTH-1,0))) ,
|
||||
Mux(io.dma_dccm_wen.asBool,Cat(io.dma_dccm_wdata_ecc_lo(pt1.DCCM_ECC_WIDTH-1,0),io.dma_dccm_wdata_lo(pt1.DCCM_DATA_WIDTH-1,0)),
|
||||
Cat(io.stbuf_ecc_any(pt1.DCCM_ECC_WIDTH-1,0),io.stbuf_data_any(pt1.DCCM_DATA_WIDTH-1,0))))
|
||||
Mux(ld_single_ecc_error_lo_r_ff===0.U,Cat(io.sec_data_ecc_lo_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(DCCM_DATA_WIDTH-1,0)) ,
|
||||
Cat(io.sec_data_ecc_hi_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(DCCM_DATA_WIDTH-1,0))) ,
|
||||
Mux(io.dma_dccm_wen.asBool,Cat(io.dma_dccm_wdata_ecc_lo(DCCM_ECC_WIDTH-1,0),io.dma_dccm_wdata_lo(DCCM_DATA_WIDTH-1,0)),
|
||||
Cat(io.stbuf_ecc_any(DCCM_ECC_WIDTH-1,0),io.stbuf_data_any(DCCM_DATA_WIDTH-1,0))))
|
||||
|
||||
io.dccm_wr_data_hi := Mux(io.ld_single_ecc_error_r_ff.asBool,
|
||||
Mux(ld_single_ecc_error_hi_r_ff===0.U, Cat(io.sec_data_ecc_hi_r_ff(pt1.DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(pt1.DCCM_DATA_WIDTH-1,0)),
|
||||
Cat(io.sec_data_ecc_lo_r_ff(pt1.DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(pt1.DCCM_DATA_WIDTH-1,0))),
|
||||
Mux(io.dma_dccm_wen.asBool, Cat(io.dma_dccm_wdata_ecc_hi(pt1.DCCM_ECC_WIDTH-1,0),io.dma_dccm_wdata_hi(pt1.DCCM_DATA_WIDTH-1,0)),
|
||||
Cat(io.stbuf_ecc_any(pt1.DCCM_ECC_WIDTH-1,0),io.stbuf_data_any(pt1.DCCM_DATA_WIDTH-1,0))))
|
||||
Mux(ld_single_ecc_error_hi_r_ff===0.U, Cat(io.sec_data_ecc_hi_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(DCCM_DATA_WIDTH-1,0)),
|
||||
Cat(io.sec_data_ecc_lo_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(DCCM_DATA_WIDTH-1,0))),
|
||||
Mux(io.dma_dccm_wen.asBool, Cat(io.dma_dccm_wdata_ecc_hi(DCCM_ECC_WIDTH-1,0),io.dma_dccm_wdata_hi(DCCM_DATA_WIDTH-1,0)),
|
||||
Cat(io.stbuf_ecc_any(DCCM_ECC_WIDTH-1,0),io.stbuf_data_any(DCCM_DATA_WIDTH-1,0))))
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// DCCM outputs
|
||||
val store_byteen_m = (Fill(4,io.lsu_pkt_m.store)) & ((Fill(4,io.lsu_pkt_m.by) & 1.U(4.W)) |
|
||||
|
|
@ -251,11 +244,11 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset
|
|||
store_byteen_ext_r := store_byteen_r(3,0) << io.lsu_addr_r(1,0)
|
||||
|
||||
//LM: If store buffer addr matches with the address in the m-stage then there will be bypassed
|
||||
val dccm_wr_bypass_d_m_lo = (io.stbuf_addr_any(pt1.DCCM_BITS-1,2) === io.lsu_addr_m(pt1.DCCM_BITS-1,2)) & io.addr_in_dccm_m
|
||||
val dccm_wr_bypass_d_m_hi = (io.stbuf_addr_any(pt1.DCCM_BITS-1,2) === io.end_addr_m(pt1.DCCM_BITS-1,2)) & io.addr_in_dccm_m
|
||||
val dccm_wr_bypass_d_m_lo = (io.stbuf_addr_any(DCCM_BITS-1,2) === io.lsu_addr_m(DCCM_BITS-1,2)) & io.addr_in_dccm_m
|
||||
val dccm_wr_bypass_d_m_hi = (io.stbuf_addr_any(DCCM_BITS-1,2) === io.end_addr_m(DCCM_BITS-1,2)) & io.addr_in_dccm_m
|
||||
|
||||
val dccm_wr_bypass_d_r_lo = (io.stbuf_addr_any(pt1.DCCM_BITS-1,2) === io.lsu_addr_r(pt1.DCCM_BITS-1,2)) & io.addr_in_dccm_r
|
||||
val dccm_wr_bypass_d_r_hi = (io.stbuf_addr_any(pt1.DCCM_BITS-1,2) === io.end_addr_r(pt1.DCCM_BITS-1,2)) & io.addr_in_dccm_r
|
||||
val dccm_wr_bypass_d_r_lo = (io.stbuf_addr_any(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)) & io.addr_in_dccm_r
|
||||
val dccm_wr_bypass_d_r_hi = (io.stbuf_addr_any(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)) & io.addr_in_dccm_r
|
||||
|
||||
val dccm_wr_bypass_d_m_hi_Q = WireInit(0.U(1.W))
|
||||
val dccm_wr_bypass_d_m_lo_Q = WireInit(0.U(1.W))
|
||||
|
|
@ -268,7 +261,7 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset
|
|||
val store_data_hi_m = WireInit(0.U(32.W))
|
||||
val store_data_lo_m = WireInit(0.U(32.W))
|
||||
|
||||
if(pt.LOAD_TO_USE_PLUS1 == 1){
|
||||
if(LOAD_TO_USE_PLUS1 == 1){
|
||||
store_data_pre_r := Cat(Fill(32,0.U),io.store_data_r(31,0)) << 8.U*io.lsu_addr_r(1,0)
|
||||
store_data_pre_hi_r := store_data_pre_r(63,32)
|
||||
store_data_pre_lo_r := store_data_pre_r(31, 0)
|
||||
|
|
@ -289,24 +282,24 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset
|
|||
store_data_lo_m := store_data_pre_m(31, 0)
|
||||
io.store_data_lo_r := withClock(io.lsu_store_c1_r_clk){RegNext(Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_m(i).asBool, store_data_lo_m((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo).asBool, io.stbuf_data_any((8*i)+7,8*i),io.sec_data_lo_m((8*i)+7,8*i))))))),0.U)}
|
||||
io.store_data_hi_r := withClock(io.lsu_store_c1_r_clk){RegNext(Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_m(i+4).asBool,store_data_hi_m((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi).asBool, io.stbuf_data_any((8*i)+7,8*i),io.sec_data_hi_m((8*i)+7,8*i))))))),0.U)}
|
||||
io.store_datafn_lo_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo & ~store_byteen_ext_r(i)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_lo_r((8*i)+7,8*i))))))
|
||||
io.store_datafn_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo & ~store_byteen_ext_r(i)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_hi_r((8*i)+7,8*i))))))
|
||||
io.store_datafn_lo_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo & !store_byteen_ext_r(i)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_lo_r((8*i)+7,8*i))))))
|
||||
io.store_datafn_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo & !store_byteen_ext_r(i)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_hi_r((8*i)+7,8*i))))))
|
||||
io.store_data_r := (Cat(io.store_data_hi_r(31,0),io.store_data_lo_r(31,0)) >> 8.U*io.lsu_addr_r(1,0)) & Reverse(Cat(VecInit.tabulate(4)(i=> Fill(8,store_byteen_r(i)))))
|
||||
}
|
||||
io.dccm_rdata_lo_m := io.dccm_rd_data_lo(pt1.DCCM_DATA_WIDTH-1,0) //4 lines
|
||||
io.dccm_rdata_hi_m := io.dccm_rd_data_hi(pt1.DCCM_DATA_WIDTH-1,0)
|
||||
io.dccm_data_ecc_lo_m := io.dccm_rd_data_lo(pt1.DCCM_FDATA_WIDTH-1,pt1.DCCM_DATA_WIDTH)
|
||||
io.dccm_data_ecc_hi_m := io.dccm_rd_data_hi(pt1.DCCM_FDATA_WIDTH-1,pt1.DCCM_DATA_WIDTH)
|
||||
io.dccm_rdata_lo_m := io.dccm_rd_data_lo(DCCM_DATA_WIDTH-1,0) //4 lines
|
||||
io.dccm_rdata_hi_m := io.dccm_rd_data_hi(DCCM_DATA_WIDTH-1,0)
|
||||
io.dccm_data_ecc_lo_m := io.dccm_rd_data_lo(DCCM_FDATA_WIDTH-1,DCCM_DATA_WIDTH)
|
||||
io.dccm_data_ecc_hi_m := io.dccm_rd_data_hi(DCCM_FDATA_WIDTH-1,DCCM_DATA_WIDTH)
|
||||
|
||||
io.picm_wren := (io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.addr_in_pic_r & io.lsu_commit_r) | io.dma_pic_wen
|
||||
io.picm_rden := io.lsu_pkt_d.valid & io.lsu_pkt_d.load & io.addr_in_pic_d
|
||||
io.picm_mken := io.lsu_pkt_d.valid & io.lsu_pkt_d.store & io.addr_in_pic_d
|
||||
io.picm_rdaddr := pt.PIC_BASE_ADDR | Cat(Fill(32-pt1.PIC_BITS,0.U),io.lsu_addr_d(pt1.PIC_BITS-1,0))
|
||||
io.picm_wraddr := pt.PIC_BASE_ADDR | Cat(Fill(32-pt1.PIC_BITS,0.U),Mux(io.dma_pic_wen.asBool,io.dma_mem_addr(pt1.PIC_BITS-1,0),io.lsu_addr_r(pt1.PIC_BITS-1,0)))
|
||||
io.picm_rdaddr := PIC_BASE_ADDR | Cat(Fill(32-PIC_BITS,0.U),io.lsu_addr_d(PIC_BITS-1,0))
|
||||
io.picm_wraddr := PIC_BASE_ADDR | Cat(Fill(32-PIC_BITS,0.U),Mux(io.dma_pic_wen.asBool,io.dma_mem_addr(PIC_BITS-1,0),io.lsu_addr_r(PIC_BITS-1,0)))
|
||||
io.picm_mask_data_m := picm_rd_data_m(31,0)
|
||||
io.picm_wr_data := Mux(io.dma_pic_wen.asBool,io.dma_mem_wdata(31,0),io.store_datafn_lo_r(31,0))
|
||||
|
||||
if(pt1.DCCM_ENABLE == 1){
|
||||
if(DCCM_ENABLE){
|
||||
io.lsu_dccm_rden_m := withClock(io.lsu_c2_m_clk){RegNext(lsu_dccm_rden_d,0.U)}
|
||||
io.lsu_dccm_rden_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_dccm_rden_m,0.U)}
|
||||
}
|
||||
|
|
@ -314,54 +307,10 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset
|
|||
io.lsu_dccm_rden_m := 0.U
|
||||
io.lsu_dccm_rden_r := 0.U}
|
||||
|
||||
|
||||
//io.dccm_wr_addr_lo := 0.U
|
||||
//io.dccm_wr_addr_hi := 0.U
|
||||
//io.dccm_rd_addr_lo := 0.U
|
||||
//io.dccm_rd_addr_hi := 0.U
|
||||
//io.dccm_wr_data_lo := 0.U
|
||||
//io.dccm_wr_data_hi := 0.U
|
||||
|
||||
// io.dccm_rdata_hi_m := 0.U
|
||||
// io.dccm_rdata_lo_m := 0.U
|
||||
// io.dccm_data_ecc_hi_m := 0.U
|
||||
// io.dccm_data_ecc_lo_m := 0.U
|
||||
//io.lsu_ld_data_m := 0.U
|
||||
|
||||
//io.store_data_hi_r := 0.U
|
||||
//io.store_data_lo_r := 0.U
|
||||
//io.store_datafn_hi_r := 0.U
|
||||
//io.store_datafn_lo_r := 0.U
|
||||
// io.store_data_r := 0.U
|
||||
//io.ld_single_ecc_error_r := 0.U
|
||||
//io.ld_single_ecc_error_r_ff := 0.U
|
||||
//io.picm_mask_data_m := 0.U
|
||||
//io.lsu_stbuf_commit_any := 0.U
|
||||
// io.lsu_dccm_rden_m := 0.U
|
||||
// io.lsu_dccm_rden_r := 0.U
|
||||
//io.dccm_dma_rvalid := 0.U
|
||||
//io.dccm_dma_ecc_error := 0.U
|
||||
//io.dccm_dma_rtag := 0.U
|
||||
//io.dccm_dma_rdata := 0.U
|
||||
//io.dccm_wren := 0.U
|
||||
//io.dccm_rden := 0.U
|
||||
//io.dccm_wr_addr_lo := 0.U
|
||||
//io.dccm_wr_data_lo := 0.U
|
||||
//io.dccm_wr_addr_hi := 0.U
|
||||
//io.dccm_wr_data_hi := 0.U
|
||||
//io.dccm_rd_addr_hi := 0.U
|
||||
//io.dccm_rd_data_hi := 0.U
|
||||
//io.picm_wren := 0.U
|
||||
//io.picm_rden := 0.U
|
||||
//io.picm_mken := 0.U
|
||||
//io.picm_rdaddr := 0.U
|
||||
//io.picm_wraddr := 0.U
|
||||
//io.picm_wr_data := 0.U
|
||||
//io.picm_rd_data := 0.U
|
||||
}
|
||||
|
||||
object dccm_ctl extends App{
|
||||
println("Generate Verilog")
|
||||
chisel3.Driver.execute(args, ()=> new el2_lsu_dccm_ctl)
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_dccm_ctl()))
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -154,8 +154,8 @@ class el2_lsu_ecc extends Module with el2_lib with RequireAsyncReset {
|
|||
io.dma_dccm_wdata_ecc_hi := dccm_wdata_ecc_hi_any
|
||||
io.dma_dccm_wdata_ecc_lo := dccm_wdata_ecc_lo_any
|
||||
|
||||
io.sec_data_hi_r_ff := RegEnable(io.sec_data_hi_r, 0.U, io.ld_single_ecc_error_r)
|
||||
io.sec_data_lo_r_ff := RegEnable(io.sec_data_lo_r, 0.U, io.ld_single_ecc_error_r)
|
||||
io.sec_data_hi_r_ff := rvdffe(io.sec_data_hi_r, io.ld_single_ecc_error_r,clock,io.scan_mode)
|
||||
io.sec_data_lo_r_ff := rvdffe(io.sec_data_lo_r, io.ld_single_ecc_error_r,clock,io.scan_mode)
|
||||
|
||||
}
|
||||
object eccmain extends App{
|
||||
|
|
|
|||
|
|
@ -1,20 +1,13 @@
|
|||
package lsu
|
||||
import include._
|
||||
import lib._
|
||||
import snapshot._
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
|
||||
import chisel3.experimental.ChiselEnum
|
||||
import chisel3.experimental.{withClock, withReset, withClockAndReset}
|
||||
import chisel3.experimental.BundleLiterals._
|
||||
import chisel3.tester._
|
||||
import chisel3.tester.RawTester.test
|
||||
import chisel3.util.HasBlackBoxResource
|
||||
|
||||
|
||||
import chisel3.experimental.chiselName
|
||||
@chiselName
|
||||
class el2_lsu_lsc_ctl extends Module with RequireAsyncReset
|
||||
class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
|
||||
{
|
||||
val io = IO(new Bundle{
|
||||
//val rst_l = IO(Input(1.W)) //implicit
|
||||
|
|
@ -112,10 +105,7 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset
|
|||
val rs1_d = Mux(io.lsu_pkt_d.load_ldst_bypass_d.asBool,io.lsu_result_m,rs1_d_raw)
|
||||
|
||||
// generate the ls address
|
||||
val lsadder = Module(new rvlsadder())
|
||||
lsadder.io.rs1 := rs1_d
|
||||
lsadder.io.offset := offset_d
|
||||
val full_addr_d = lsadder.io.dout
|
||||
val full_addr_d = rvlsadder(rs1_d,offset_d)
|
||||
|
||||
val addr_offset_d = ((Fill(3,io.lsu_pkt_d.half)) & 1.U(3.W)) |
|
||||
((Fill(3,io.lsu_pkt_d.word)) & 3.U(3.W)) |
|
||||
|
|
@ -164,15 +154,15 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset
|
|||
fir_nondccm_access_error_m := withClock(io.lsu_c1_m_clk){RegNext(fir_nondccm_access_error_d,0.U)}
|
||||
|
||||
io.lsu_exc_m := access_fault_m | misaligned_fault_m
|
||||
io.lsu_single_ecc_error_incr := (io.lsu_single_ecc_error_r & ~io.lsu_double_ecc_error_r) & (io.lsu_commit_r | io.lsu_pkt_r.dma) & io.lsu_pkt_r.valid
|
||||
io.lsu_single_ecc_error_incr := (io.lsu_single_ecc_error_r & !io.lsu_double_ecc_error_r) & (io.lsu_commit_r | io.lsu_pkt_r.dma) & io.lsu_pkt_r.valid
|
||||
|
||||
if (pt1.LOAD_TO_USE_PLUS1 == 1){
|
||||
if (LOAD_TO_USE_PLUS1 == 1){
|
||||
// Generate exception packet
|
||||
io.lsu_error_pkt_r.exc_valid := (access_fault_r | misaligned_fault_r | io.lsu_double_ecc_error_r) & io.lsu_pkt_r.valid & ~io.lsu_pkt_r.dma & ~io.lsu_pkt_r.fast_int //TBD(lsu_pkt_r.fast_int)
|
||||
io.lsu_error_pkt_r.single_ecc_error := io.lsu_single_ecc_error_r & ~io.lsu_error_pkt_r.exc_valid & ~io.lsu_pkt_r.dma
|
||||
io.lsu_error_pkt_r.exc_valid := (access_fault_r | misaligned_fault_r | io.lsu_double_ecc_error_r) & io.lsu_pkt_r.valid & !io.lsu_pkt_r.dma & !io.lsu_pkt_r.fast_int //TBD(lsu_pkt_r.fast_int)
|
||||
io.lsu_error_pkt_r.single_ecc_error := io.lsu_single_ecc_error_r & !io.lsu_error_pkt_r.exc_valid & !io.lsu_pkt_r.dma
|
||||
io.lsu_error_pkt_r.inst_type := io.lsu_pkt_r.store
|
||||
io.lsu_error_pkt_r.exc_type := ~misaligned_fault_r
|
||||
io.lsu_error_pkt_r.mscause := Mux((io.lsu_double_ecc_error_r & ~misaligned_fault_r & ~access_fault_r).asBool,1.U(4.W), exc_mscause_r(3,0))
|
||||
io.lsu_error_pkt_r.mscause := Mux((io.lsu_double_ecc_error_r & !misaligned_fault_r & !access_fault_r).asBool,1.U(4.W), exc_mscause_r(3,0))
|
||||
io.lsu_error_pkt_r.addr := io.lsu_addr_r(31,0)//lsu_addr_d->lsu_full_addr
|
||||
io.lsu_fir_error := Mux(fir_nondccm_access_error_r.asBool,3.U(2.W), Mux(fir_dccm_access_error_r.asBool,2.U(2.W), Mux((io.lsu_pkt_r.fast_int & io.lsu_double_ecc_error_r).asBool,1.U(2.W),0.U(2.W))))
|
||||
|
||||
|
|
@ -186,11 +176,11 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset
|
|||
else //L2U_Plus1_0
|
||||
{
|
||||
// Generate exception packet
|
||||
lsu_error_pkt_m.exc_valid := (access_fault_m | misaligned_fault_m | io.lsu_double_ecc_error_m) & io.lsu_pkt_m.valid & ~io.lsu_pkt_m.dma & ~io.lsu_pkt_m.fast_int & ~io.flush_m_up //TBD(lsu_pkt_r.fast_int)
|
||||
lsu_error_pkt_m.single_ecc_error := io.lsu_single_ecc_error_m & ~lsu_error_pkt_m.exc_valid & ~io.lsu_pkt_m.dma
|
||||
lsu_error_pkt_m.exc_valid := (access_fault_m | misaligned_fault_m | io.lsu_double_ecc_error_m) & io.lsu_pkt_m.valid & !io.lsu_pkt_m.dma & !io.lsu_pkt_m.fast_int & !io.flush_m_up //TBD(lsu_pkt_r.fast_int)
|
||||
lsu_error_pkt_m.single_ecc_error := io.lsu_single_ecc_error_m & !lsu_error_pkt_m.exc_valid & !io.lsu_pkt_m.dma
|
||||
lsu_error_pkt_m.inst_type := io.lsu_pkt_m.store
|
||||
lsu_error_pkt_m.exc_type := ~misaligned_fault_m
|
||||
lsu_error_pkt_m.mscause := Mux(((io.lsu_double_ecc_error_m & ~misaligned_fault_m & ~access_fault_m)===1.U),1.U(4.W), exc_mscause_m(3,0))
|
||||
lsu_error_pkt_m.mscause := Mux(((io.lsu_double_ecc_error_m & !misaligned_fault_m & !access_fault_m)===1.U),1.U(4.W), exc_mscause_m(3,0))
|
||||
lsu_error_pkt_m.addr := io.lsu_addr_m(31,0)//lsu_addr_d->lsu_full_addr
|
||||
lsu_fir_error_m := Mux(fir_nondccm_access_error_m.asBool,3.U(2.W), Mux(fir_dccm_access_error_m.asBool,2.U(2.W), Mux((io.lsu_pkt_m.fast_int & io.lsu_double_ecc_error_m).asBool,1.U(2.W),0.U(2.W))))
|
||||
io.lsu_error_pkt_r := withClock(io.lsu_c2_r_clk){RegNext(lsu_error_pkt_m,0.U.asTypeOf(lsu_error_pkt_m.cloneType))}
|
||||
|
|
@ -218,9 +208,9 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset
|
|||
lsu_pkt_m_in := io.lsu_pkt_d
|
||||
lsu_pkt_r_in := io.lsu_pkt_m
|
||||
|
||||
io.lsu_pkt_d.valid := (io.lsu_p.valid & ~(io.flush_m_up & ~io.lsu_p.fast_int)) | io.dma_dccm_req
|
||||
lsu_pkt_m_in.valid := io.lsu_pkt_d.valid & ~(io.flush_m_up & ~io.lsu_pkt_d.dma)
|
||||
lsu_pkt_r_in.valid := io.lsu_pkt_m.valid & ~(io.flush_m_up & ~io.lsu_pkt_m.dma)
|
||||
io.lsu_pkt_d.valid := (io.lsu_p.valid & !(io.flush_m_up & !io.lsu_p.fast_int)) | io.dma_dccm_req
|
||||
lsu_pkt_m_in.valid := io.lsu_pkt_d.valid & !(io.flush_m_up & !io.lsu_pkt_d.dma)
|
||||
lsu_pkt_r_in.valid := io.lsu_pkt_m.valid & !(io.flush_m_up & !io.lsu_pkt_m.dma)
|
||||
|
||||
io.lsu_pkt_m := withClock(io.lsu_c1_m_clk){RegNext(lsu_pkt_m_in,0.U.asTypeOf(lsu_pkt_m_in.cloneType))}
|
||||
io.lsu_pkt_r := withClock(io.lsu_c1_r_clk){RegNext(lsu_pkt_r_in,0.U.asTypeOf(lsu_pkt_r_in.cloneType))}
|
||||
|
|
@ -236,36 +226,36 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset
|
|||
io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)}
|
||||
io.end_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d,0.U)}
|
||||
io.end_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m,0.U)}
|
||||
io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)}
|
||||
io.addr_in_dccm_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_dccm_m,0.U)}
|
||||
io.addr_in_pic_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_pic_d,0.U)}
|
||||
io.addr_in_pic_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_pic_m,0.U)}
|
||||
io.addr_external_m := withClock(io.lsu_c1_m_clk){RegNext(addr_external_d,0.U)}
|
||||
val addr_external_r = withClock(io.lsu_c1_r_clk){RegNext(io.addr_external_m,0.U)}
|
||||
val bus_read_data_r = withClock(io.lsu_c1_r_clk){RegNext(io.bus_read_data_m,0.U)}
|
||||
io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)}
|
||||
io.addr_in_dccm_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_dccm_m,0.U)}
|
||||
io.addr_in_pic_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_pic_d,0.U)}
|
||||
io.addr_in_pic_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_pic_m,0.U)}
|
||||
io.addr_external_m := withClock(io.lsu_c1_m_clk){RegNext(addr_external_d,0.U)}
|
||||
val addr_external_r = withClock(io.lsu_c1_r_clk){RegNext(io.addr_external_m,0.U)}
|
||||
val bus_read_data_r = withClock(io.lsu_c1_r_clk){RegNext(io.bus_read_data_m,0.U)}
|
||||
// Fast interrupt address
|
||||
io.lsu_fir_addr := io.lsu_ld_data_corr_r(31,1) //original (31,1) TBD
|
||||
// absence load/store all 0's
|
||||
io.lsu_addr_d := full_addr_d
|
||||
// Interrupt as a flush source allows the WB to occur
|
||||
io.lsu_commit_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.store | io.lsu_pkt_r.load) & ~io.flush_r & ~io.lsu_pkt_r.dma
|
||||
io.store_data_m := (io.picm_mask_data_m(31,0) | Fill(32,~io.addr_in_pic_m)) & Mux(io.lsu_pkt_m.store_data_bypass_m.asBool,io.lsu_result_m,store_data_pre_m)
|
||||
io.lsu_commit_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.store | io.lsu_pkt_r.load) & !io.flush_r & !io.lsu_pkt_r.dma
|
||||
io.store_data_m := (io.picm_mask_data_m(31,0) | Fill(32,!io.addr_in_pic_m)) & Mux(io.lsu_pkt_m.store_data_bypass_m.asBool,io.lsu_result_m,store_data_pre_m)
|
||||
|
||||
if (pt1.LOAD_TO_USE_PLUS1 == 1){
|
||||
if (LOAD_TO_USE_PLUS1 == 1){
|
||||
//bus_read_data_r coming from bus interface, lsu_ld_data_r -> coming from dccm_ctl
|
||||
lsu_ld_datafn_r := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_r)
|
||||
lsu_ld_datafn_corr_r := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_corr_r)
|
||||
// this is really R stage but don't want to make all the changes to support M,R buses
|
||||
io.lsu_result_m := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat(0.U(16.W),lsu_ld_datafn_r(15,0))) |
|
||||
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_r(7))) ,lsu_ld_datafn_r(7,0))) |
|
||||
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_r(15))) ,lsu_ld_datafn_r(15,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_r(7))) ,lsu_ld_datafn_r(7,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_r(15))) ,lsu_ld_datafn_r(15,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_r(31,0))
|
||||
// this signal is used for gpr update
|
||||
io.lsu_result_corr_r := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat(0.U(24.W),lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat(0.U(16.W),lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_corr_r(7))) ,lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_corr_r(15))) ,lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_corr_r(7))) ,lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_corr_r(15))) ,lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_corr_r(31,0))
|
||||
}
|
||||
|
||||
|
|
@ -274,19 +264,18 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset
|
|||
lsu_ld_datafn_corr_r := Mux(addr_external_r===1.U, bus_read_data_r,io.lsu_ld_data_corr_r)
|
||||
io.lsu_result_m := ((Fill(32,io.lsu_pkt_m.unsign & io.lsu_pkt_m.by)) & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) |
|
||||
((Fill(32,io.lsu_pkt_m.unsign & io.lsu_pkt_m.half)) & Cat(0.U(16.W),lsu_ld_datafn_m(15,0))) |
|
||||
((Fill(32,~io.lsu_pkt_m.unsign & io.lsu_pkt_m.by)) & Cat((Fill(24, lsu_ld_datafn_m(7))) ,lsu_ld_datafn_m(7,0))) |
|
||||
((Fill(32,~io.lsu_pkt_m.unsign & io.lsu_pkt_m.half)) & Cat((Fill(16,lsu_ld_datafn_m(15))) ,lsu_ld_datafn_m(15,0))) |
|
||||
((Fill(32,!io.lsu_pkt_m.unsign & io.lsu_pkt_m.by)) & Cat((Fill(24, lsu_ld_datafn_m(7))) ,lsu_ld_datafn_m(7,0))) |
|
||||
((Fill(32,!io.lsu_pkt_m.unsign & io.lsu_pkt_m.half)) & Cat((Fill(16,lsu_ld_datafn_m(15))) ,lsu_ld_datafn_m(15,0))) |
|
||||
((Fill(32,io.lsu_pkt_m.word)) & lsu_ld_datafn_m(31,0))
|
||||
io.lsu_result_corr_r := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat(0.U(24.W),lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat(0.U(16.W),lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_corr_r(7))) ,lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_corr_r(15))) ,lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_corr_r(7))) ,lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_corr_r(15))) ,lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_corr_r(31,0))
|
||||
}
|
||||
}
|
||||
|
||||
//println(chisel3.Driver.emitVerilog(new el2_lsu_lsc_ctl))
|
||||
object lsu_lsc_ctl extends App{
|
||||
println("Generate Verilog")
|
||||
chisel3.Driver.execute(args, ()=> new el2_lsu_lsc_ctl)
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_lsc_ctl()))
|
||||
}
|
||||
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Reference in New Issue