2020-10-22 17:52:47 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_lsu_lsc_ctl :
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module el2_lsu_addrcheck :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
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2020-11-23 17:53:08 +08:00
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node _T = bits(io.start_addr_d, 31, 28) @[el2_lib.scala 496:27]
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node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 496:49]
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wire start_addr_in_dccm_d : UInt<1> @[el2_lib.scala 497:26]
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node _T_1 = bits(io.start_addr_d, 31, 16) @[el2_lib.scala 501:24]
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node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[el2_lib.scala 501:39]
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start_addr_in_dccm_d <= _T_2 @[el2_lib.scala 501:16]
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node _T_3 = bits(io.end_addr_d, 31, 28) @[el2_lib.scala 496:27]
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node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[el2_lib.scala 496:49]
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wire end_addr_in_dccm_d : UInt<1> @[el2_lib.scala 497:26]
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node _T_4 = bits(io.end_addr_d, 31, 16) @[el2_lib.scala 501:24]
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node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[el2_lib.scala 501:39]
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end_addr_in_dccm_d <= _T_5 @[el2_lib.scala 501:16]
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2020-10-22 17:52:47 +08:00
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wire addr_in_iccm : UInt<1>
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addr_in_iccm <= UInt<1>("h00")
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2020-11-06 18:05:28 +08:00
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node _T_6 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 42:37]
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node _T_7 = eq(_T_6, UInt<4>("h0e")) @[el2_lsu_addrcheck.scala 42:45]
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addr_in_iccm <= _T_7 @[el2_lsu_addrcheck.scala 42:18]
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node _T_8 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 50:89]
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2020-11-23 17:53:08 +08:00
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node _T_9 = bits(_T_8, 31, 28) @[el2_lib.scala 496:27]
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node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[el2_lib.scala 496:49]
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wire start_addr_in_pic_d : UInt<1> @[el2_lib.scala 497:26]
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node _T_10 = bits(_T_8, 31, 15) @[el2_lib.scala 501:24]
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node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[el2_lib.scala 501:39]
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start_addr_in_pic_d <= _T_11 @[el2_lib.scala 501:16]
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2020-11-06 18:05:28 +08:00
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node _T_12 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 52:83]
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2020-11-23 17:53:08 +08:00
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node _T_13 = bits(_T_12, 31, 28) @[el2_lib.scala 496:27]
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node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[el2_lib.scala 496:49]
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wire end_addr_in_pic_d : UInt<1> @[el2_lib.scala 497:26]
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node _T_14 = bits(_T_12, 31, 15) @[el2_lib.scala 501:24]
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node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[el2_lib.scala 501:39]
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end_addr_in_pic_d <= _T_15 @[el2_lib.scala 501:16]
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2020-11-06 18:05:28 +08:00
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node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 54:60]
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node _T_16 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 55:48]
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node _T_17 = eq(_T_16, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 55:54]
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node _T_18 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 55:91]
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node _T_19 = eq(_T_18, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 55:97]
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node base_reg_dccm_or_pic = or(_T_17, _T_19) @[el2_lsu_addrcheck.scala 55:73]
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node _T_20 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 56:57]
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io.addr_in_dccm_d <= _T_20 @[el2_lsu_addrcheck.scala 56:32]
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node _T_21 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 57:56]
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io.addr_in_pic_d <= _T_21 @[el2_lsu_addrcheck.scala 57:32]
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node _T_22 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 59:63]
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node _T_23 = not(_T_22) @[el2_lsu_addrcheck.scala 59:33]
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io.addr_external_d <= _T_23 @[el2_lsu_addrcheck.scala 59:30]
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node _T_24 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 60:51]
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node csr_idx = cat(_T_24, UInt<1>("h01")) @[Cat.scala 29:58]
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node _T_25 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[el2_lsu_addrcheck.scala 61:50]
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node _T_26 = bits(_T_25, 0, 0) @[el2_lsu_addrcheck.scala 61:50]
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node _T_27 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 61:92]
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node _T_28 = or(_T_27, addr_in_iccm) @[el2_lsu_addrcheck.scala 61:121]
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node _T_29 = eq(_T_28, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 61:62]
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node _T_30 = and(_T_26, _T_29) @[el2_lsu_addrcheck.scala 61:60]
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node _T_31 = and(_T_30, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 61:137]
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node _T_32 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[el2_lsu_addrcheck.scala 61:180]
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node is_sideeffects_d = and(_T_31, _T_32) @[el2_lsu_addrcheck.scala 61:158]
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node _T_33 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 62:69]
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node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:75]
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node _T_35 = and(io.lsu_pkt_d.word, _T_34) @[el2_lsu_addrcheck.scala 62:51]
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node _T_36 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 62:124]
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node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:128]
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node _T_38 = and(io.lsu_pkt_d.half, _T_37) @[el2_lsu_addrcheck.scala 62:106]
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node _T_39 = or(_T_35, _T_38) @[el2_lsu_addrcheck.scala 62:85]
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node is_aligned_d = or(_T_39, io.lsu_pkt_d.by) @[el2_lsu_addrcheck.scala 62:138]
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node _T_40 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_42 = cat(_T_41, _T_40) @[Cat.scala 29:58]
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node _T_43 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
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node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
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node _T_45 = cat(_T_44, _T_43) @[Cat.scala 29:58]
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node _T_46 = cat(_T_45, _T_42) @[Cat.scala 29:58]
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2020-11-23 17:53:08 +08:00
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node _T_47 = orr(_T_46) @[el2_lsu_addrcheck.scala 66:99]
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2020-11-06 18:05:28 +08:00
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node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 65:33]
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2020-11-23 17:53:08 +08:00
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node _T_49 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 67:49]
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node _T_50 = or(_T_49, UInt<31>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:56]
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node _T_51 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:121]
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node _T_52 = eq(_T_50, _T_51) @[el2_lsu_addrcheck.scala 67:88]
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node _T_53 = and(UInt<1>("h01"), _T_52) @[el2_lsu_addrcheck.scala 67:30]
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node _T_54 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 68:49]
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node _T_55 = or(_T_54, UInt<30>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:56]
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node _T_56 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:121]
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node _T_57 = eq(_T_55, _T_56) @[el2_lsu_addrcheck.scala 68:88]
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node _T_58 = and(UInt<1>("h01"), _T_57) @[el2_lsu_addrcheck.scala 68:30]
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node _T_59 = or(_T_53, _T_58) @[el2_lsu_addrcheck.scala 67:153]
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node _T_60 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 69:49]
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node _T_61 = or(_T_60, UInt<29>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:56]
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node _T_62 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:121]
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node _T_63 = eq(_T_61, _T_62) @[el2_lsu_addrcheck.scala 69:88]
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node _T_64 = and(UInt<1>("h01"), _T_63) @[el2_lsu_addrcheck.scala 69:30]
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node _T_65 = or(_T_59, _T_64) @[el2_lsu_addrcheck.scala 68:153]
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node _T_66 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 70:49]
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node _T_67 = or(_T_66, UInt<28>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:56]
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node _T_68 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:121]
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node _T_69 = eq(_T_67, _T_68) @[el2_lsu_addrcheck.scala 70:88]
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node _T_70 = and(UInt<1>("h01"), _T_69) @[el2_lsu_addrcheck.scala 70:30]
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node _T_71 = or(_T_65, _T_70) @[el2_lsu_addrcheck.scala 69:153]
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node _T_72 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 71:49]
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node _T_73 = or(_T_72, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:56]
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node _T_74 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:121]
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node _T_75 = eq(_T_73, _T_74) @[el2_lsu_addrcheck.scala 71:88]
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node _T_76 = and(UInt<1>("h00"), _T_75) @[el2_lsu_addrcheck.scala 71:30]
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node _T_77 = or(_T_71, _T_76) @[el2_lsu_addrcheck.scala 70:153]
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node _T_78 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 72:49]
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node _T_79 = or(_T_78, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:56]
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node _T_80 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:121]
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node _T_81 = eq(_T_79, _T_80) @[el2_lsu_addrcheck.scala 72:88]
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node _T_82 = and(UInt<1>("h00"), _T_81) @[el2_lsu_addrcheck.scala 72:30]
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node _T_83 = or(_T_77, _T_82) @[el2_lsu_addrcheck.scala 71:153]
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node _T_84 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 73:49]
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node _T_85 = or(_T_84, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:56]
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node _T_86 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:121]
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node _T_87 = eq(_T_85, _T_86) @[el2_lsu_addrcheck.scala 73:88]
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node _T_88 = and(UInt<1>("h00"), _T_87) @[el2_lsu_addrcheck.scala 73:30]
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node _T_89 = or(_T_83, _T_88) @[el2_lsu_addrcheck.scala 72:153]
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node _T_90 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 74:49]
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node _T_91 = or(_T_90, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:56]
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node _T_92 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:121]
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node _T_93 = eq(_T_91, _T_92) @[el2_lsu_addrcheck.scala 74:88]
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node _T_94 = and(UInt<1>("h00"), _T_93) @[el2_lsu_addrcheck.scala 74:30]
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node _T_95 = or(_T_89, _T_94) @[el2_lsu_addrcheck.scala 73:153]
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node _T_96 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 76:48]
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node _T_97 = or(_T_96, UInt<31>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:57]
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node _T_98 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:122]
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node _T_99 = eq(_T_97, _T_98) @[el2_lsu_addrcheck.scala 76:89]
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node _T_100 = and(UInt<1>("h01"), _T_99) @[el2_lsu_addrcheck.scala 76:31]
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node _T_101 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 77:49]
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node _T_102 = or(_T_101, UInt<30>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:58]
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node _T_103 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:123]
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node _T_104 = eq(_T_102, _T_103) @[el2_lsu_addrcheck.scala 77:90]
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node _T_105 = and(UInt<1>("h01"), _T_104) @[el2_lsu_addrcheck.scala 77:32]
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node _T_106 = or(_T_100, _T_105) @[el2_lsu_addrcheck.scala 76:154]
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node _T_107 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 78:49]
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node _T_108 = or(_T_107, UInt<29>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:58]
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node _T_109 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:123]
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node _T_110 = eq(_T_108, _T_109) @[el2_lsu_addrcheck.scala 78:90]
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node _T_111 = and(UInt<1>("h01"), _T_110) @[el2_lsu_addrcheck.scala 78:32]
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node _T_112 = or(_T_106, _T_111) @[el2_lsu_addrcheck.scala 77:155]
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node _T_113 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 79:49]
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node _T_114 = or(_T_113, UInt<28>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:58]
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node _T_115 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:123]
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node _T_116 = eq(_T_114, _T_115) @[el2_lsu_addrcheck.scala 79:90]
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node _T_117 = and(UInt<1>("h01"), _T_116) @[el2_lsu_addrcheck.scala 79:32]
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node _T_118 = or(_T_112, _T_117) @[el2_lsu_addrcheck.scala 78:155]
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node _T_119 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 80:49]
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node _T_120 = or(_T_119, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:58]
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node _T_121 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:123]
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node _T_122 = eq(_T_120, _T_121) @[el2_lsu_addrcheck.scala 80:90]
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node _T_123 = and(UInt<1>("h00"), _T_122) @[el2_lsu_addrcheck.scala 80:32]
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node _T_124 = or(_T_118, _T_123) @[el2_lsu_addrcheck.scala 79:155]
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node _T_125 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 81:49]
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node _T_126 = or(_T_125, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:58]
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node _T_127 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:123]
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node _T_128 = eq(_T_126, _T_127) @[el2_lsu_addrcheck.scala 81:90]
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node _T_129 = and(UInt<1>("h00"), _T_128) @[el2_lsu_addrcheck.scala 81:32]
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node _T_130 = or(_T_124, _T_129) @[el2_lsu_addrcheck.scala 80:155]
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node _T_131 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 82:49]
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node _T_132 = or(_T_131, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:58]
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node _T_133 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:123]
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node _T_134 = eq(_T_132, _T_133) @[el2_lsu_addrcheck.scala 82:90]
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node _T_135 = and(UInt<1>("h00"), _T_134) @[el2_lsu_addrcheck.scala 82:32]
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node _T_136 = or(_T_130, _T_135) @[el2_lsu_addrcheck.scala 81:155]
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node _T_137 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 83:49]
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node _T_138 = or(_T_137, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:58]
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node _T_139 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:123]
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node _T_140 = eq(_T_138, _T_139) @[el2_lsu_addrcheck.scala 83:90]
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node _T_141 = and(UInt<1>("h00"), _T_140) @[el2_lsu_addrcheck.scala 83:32]
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node _T_142 = or(_T_136, _T_141) @[el2_lsu_addrcheck.scala 82:155]
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2020-11-06 18:05:28 +08:00
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node _T_143 = and(_T_95, _T_142) @[el2_lsu_addrcheck.scala 75:7]
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2020-11-23 17:53:08 +08:00
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node non_dccm_access_ok = or(_T_48, _T_143) @[el2_lsu_addrcheck.scala 66:104]
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2020-11-06 18:05:28 +08:00
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node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[el2_lsu_addrcheck.scala 85:57]
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node _T_144 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 86:70]
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node _T_145 = neq(_T_144, UInt<2>("h00")) @[el2_lsu_addrcheck.scala 86:76]
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node _T_146 = eq(io.lsu_pkt_d.word, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 86:92]
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node _T_147 = or(_T_145, _T_146) @[el2_lsu_addrcheck.scala 86:90]
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node picm_access_fault_d = and(io.addr_in_pic_d, _T_147) @[el2_lsu_addrcheck.scala 86:51]
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2020-10-22 17:52:47 +08:00
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wire unmapped_access_fault_d : UInt<1>
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unmapped_access_fault_d <= UInt<1>("h01")
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wire mpu_access_fault_d : UInt<1>
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mpu_access_fault_d <= UInt<1>("h01")
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2020-11-06 18:05:28 +08:00
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node _T_148 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[el2_lsu_addrcheck.scala 91:87]
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node _T_149 = eq(_T_148, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 91:64]
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node _T_150 = and(start_addr_in_dccm_region_d, _T_149) @[el2_lsu_addrcheck.scala 91:62]
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node _T_151 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 93:57]
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node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:36]
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node _T_153 = and(end_addr_in_dccm_region_d, _T_152) @[el2_lsu_addrcheck.scala 93:34]
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node _T_154 = or(_T_150, _T_153) @[el2_lsu_addrcheck.scala 91:112]
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node _T_155 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 95:29]
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node _T_156 = or(_T_154, _T_155) @[el2_lsu_addrcheck.scala 93:85]
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node _T_157 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 97:29]
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node _T_158 = or(_T_156, _T_157) @[el2_lsu_addrcheck.scala 95:85]
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unmapped_access_fault_d <= _T_158 @[el2_lsu_addrcheck.scala 91:29]
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node _T_159 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 99:33]
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node _T_160 = eq(non_dccm_access_ok, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 99:64]
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node _T_161 = and(_T_159, _T_160) @[el2_lsu_addrcheck.scala 99:62]
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mpu_access_fault_d <= _T_161 @[el2_lsu_addrcheck.scala 99:29]
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node _T_162 = or(unmapped_access_fault_d, mpu_access_fault_d) @[el2_lsu_addrcheck.scala 111:49]
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node _T_163 = or(_T_162, picm_access_fault_d) @[el2_lsu_addrcheck.scala 111:70]
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node _T_164 = or(_T_163, regpred_access_fault_d) @[el2_lsu_addrcheck.scala 111:92]
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node _T_165 = and(_T_164, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 111:118]
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node _T_166 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 111:141]
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node _T_167 = and(_T_165, _T_166) @[el2_lsu_addrcheck.scala 111:139]
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io.access_fault_d <= _T_167 @[el2_lsu_addrcheck.scala 111:21]
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node _T_168 = bits(unmapped_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:60]
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node _T_169 = bits(mpu_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:100]
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node _T_170 = bits(regpred_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:144]
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node _T_171 = bits(picm_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:185]
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node _T_172 = mux(_T_171, UInt<4>("h06"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 112:164]
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node _T_173 = mux(_T_170, UInt<4>("h05"), _T_172) @[el2_lsu_addrcheck.scala 112:120]
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node _T_174 = mux(_T_169, UInt<4>("h03"), _T_173) @[el2_lsu_addrcheck.scala 112:80]
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node access_fault_mscause_d = mux(_T_168, UInt<4>("h02"), _T_174) @[el2_lsu_addrcheck.scala 112:35]
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node _T_175 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 113:53]
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node _T_176 = bits(io.end_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 113:78]
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node regcross_misaligned_fault_d = neq(_T_175, _T_176) @[el2_lsu_addrcheck.scala 113:61]
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node _T_177 = eq(is_aligned_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 114:59]
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node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_177) @[el2_lsu_addrcheck.scala 114:57]
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node _T_178 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[el2_lsu_addrcheck.scala 115:90]
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node _T_179 = or(regcross_misaligned_fault_d, _T_178) @[el2_lsu_addrcheck.scala 115:57]
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node _T_180 = and(_T_179, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 115:113]
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node _T_181 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 115:136]
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node _T_182 = and(_T_180, _T_181) @[el2_lsu_addrcheck.scala 115:134]
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io.misaligned_fault_d <= _T_182 @[el2_lsu_addrcheck.scala 115:25]
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node _T_183 = bits(sideeffect_misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 116:111]
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node _T_184 = mux(_T_183, UInt<4>("h01"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 116:80]
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node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_184) @[el2_lsu_addrcheck.scala 116:39]
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node _T_185 = bits(io.misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 117:50]
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node _T_186 = bits(misaligned_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 117:84]
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node _T_187 = bits(access_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 117:113]
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node _T_188 = mux(_T_185, _T_186, _T_187) @[el2_lsu_addrcheck.scala 117:27]
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io.exc_mscause_d <= _T_188 @[el2_lsu_addrcheck.scala 117:21]
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node _T_189 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 118:66]
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node _T_190 = and(start_addr_in_dccm_region_d, _T_189) @[el2_lsu_addrcheck.scala 118:64]
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node _T_191 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 118:120]
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node _T_192 = and(end_addr_in_dccm_region_d, _T_191) @[el2_lsu_addrcheck.scala 118:118]
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node _T_193 = or(_T_190, _T_192) @[el2_lsu_addrcheck.scala 118:88]
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node _T_194 = and(_T_193, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 118:142]
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node _T_195 = and(_T_194, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 118:163]
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io.fir_dccm_access_error_d <= _T_195 @[el2_lsu_addrcheck.scala 118:31]
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node _T_196 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 119:66]
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node _T_197 = eq(_T_196, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 119:36]
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node _T_198 = and(_T_197, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 119:95]
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node _T_199 = and(_T_198, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 119:116]
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io.fir_nondccm_access_error_d <= _T_199 @[el2_lsu_addrcheck.scala 119:33]
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2020-11-23 17:53:08 +08:00
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reg _T_200 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 121:60]
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2020-11-06 18:05:28 +08:00
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_T_200 <= is_sideeffects_d @[el2_lsu_addrcheck.scala 121:60]
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io.is_sideeffects_m <= _T_200 @[el2_lsu_addrcheck.scala 121:50]
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2020-10-22 17:52:47 +08:00
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module el2_lsu_lsc_ctl :
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input clock : Clock
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input reset : AsyncReset
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2020-11-23 17:53:08 +08:00
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output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip scan_mode : UInt<1>}
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2020-11-06 18:05:28 +08:00
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wire dma_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 96:29]
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wire lsu_pkt_m_in : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 97:29]
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wire lsu_pkt_r_in : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 98:29]
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2020-11-23 17:53:08 +08:00
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wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 99:29]
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2020-11-06 18:05:28 +08:00
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node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 101:52]
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node lsu_rs1_d = mux(_T, io.exu_lsu_rs1_d, io.dma_mem_addr) @[el2_lsu_lsc_ctl.scala 101:28]
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node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 102:44]
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2020-10-22 17:52:47 +08:00
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node _T_2 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15]
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node _T_3 = mux(_T_2, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
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2020-11-06 18:05:28 +08:00
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node lsu_offset_d = and(_T_1, _T_3) @[el2_lsu_lsc_ctl.scala 102:51]
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node _T_4 = bits(io.lsu_pkt_d.load_ldst_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 105:61]
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node rs1_d = mux(_T_4, io.lsu_result_m, lsu_rs1_d) @[el2_lsu_lsc_ctl.scala 105:28]
|
2020-11-23 17:53:08 +08:00
|
|
|
node _T_5 = bits(rs1_d, 11, 0) @[el2_lib.scala 232:31]
|
2020-11-06 18:05:28 +08:00
|
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|
node _T_6 = cat(UInt<1>("h00"), _T_5) @[Cat.scala 29:58]
|
2020-11-23 17:53:08 +08:00
|
|
|
node _T_7 = bits(lsu_offset_d, 11, 0) @[el2_lib.scala 232:60]
|
2020-11-06 18:05:28 +08:00
|
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|
node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58]
|
2020-11-23 17:53:08 +08:00
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|
node _T_9 = add(_T_6, _T_8) @[el2_lib.scala 232:39]
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node _T_10 = tail(_T_9, 1) @[el2_lib.scala 232:39]
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node _T_11 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 233:41]
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node _T_12 = bits(_T_10, 12, 12) @[el2_lib.scala 233:50]
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node _T_13 = xor(_T_11, _T_12) @[el2_lib.scala 233:46]
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node _T_14 = not(_T_13) @[el2_lib.scala 233:33]
|
2020-11-06 18:05:28 +08:00
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node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15]
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node _T_16 = mux(_T_15, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
|
2020-11-23 17:53:08 +08:00
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|
node _T_17 = bits(rs1_d, 31, 12) @[el2_lib.scala 233:63]
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node _T_18 = and(_T_16, _T_17) @[el2_lib.scala 233:58]
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node _T_19 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 234:25]
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node _T_20 = not(_T_19) @[el2_lib.scala 234:18]
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node _T_21 = bits(_T_10, 12, 12) @[el2_lib.scala 234:34]
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node _T_22 = and(_T_20, _T_21) @[el2_lib.scala 234:30]
|
2020-11-06 18:05:28 +08:00
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node _T_23 = bits(_T_22, 0, 0) @[Bitwise.scala 72:15]
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node _T_24 = mux(_T_23, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
|
2020-11-23 17:53:08 +08:00
|
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node _T_25 = bits(rs1_d, 31, 12) @[el2_lib.scala 234:47]
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node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_lib.scala 234:54]
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node _T_27 = tail(_T_26, 1) @[el2_lib.scala 234:54]
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node _T_28 = and(_T_24, _T_27) @[el2_lib.scala 234:41]
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node _T_29 = or(_T_18, _T_28) @[el2_lib.scala 233:72]
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node _T_30 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 235:24]
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node _T_31 = bits(_T_10, 12, 12) @[el2_lib.scala 235:34]
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node _T_32 = not(_T_31) @[el2_lib.scala 235:31]
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node _T_33 = and(_T_30, _T_32) @[el2_lib.scala 235:29]
|
2020-11-06 18:05:28 +08:00
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node _T_34 = bits(_T_33, 0, 0) @[Bitwise.scala 72:15]
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node _T_35 = mux(_T_34, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
|
2020-11-23 17:53:08 +08:00
|
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|
node _T_36 = bits(rs1_d, 31, 12) @[el2_lib.scala 235:47]
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node _T_37 = sub(_T_36, UInt<1>("h01")) @[el2_lib.scala 235:54]
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node _T_38 = tail(_T_37, 1) @[el2_lib.scala 235:54]
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node _T_39 = and(_T_35, _T_38) @[el2_lib.scala 235:41]
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node _T_40 = or(_T_29, _T_39) @[el2_lib.scala 234:61]
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node _T_41 = bits(_T_10, 11, 0) @[el2_lib.scala 236:22]
|
2020-11-06 18:05:28 +08:00
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|
node full_addr_d = cat(_T_40, _T_41) @[Cat.scala 29:58]
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node _T_42 = bits(io.lsu_pkt_d.half, 0, 0) @[Bitwise.scala 72:15]
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node _T_43 = mux(_T_42, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
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node _T_44 = and(_T_43, UInt<3>("h01")) @[el2_lsu_lsc_ctl.scala 110:53]
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node _T_45 = bits(io.lsu_pkt_d.word, 0, 0) @[Bitwise.scala 72:15]
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node _T_46 = mux(_T_45, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
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node _T_47 = and(_T_46, UInt<3>("h03")) @[el2_lsu_lsc_ctl.scala 111:35]
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node _T_48 = or(_T_44, _T_47) @[el2_lsu_lsc_ctl.scala 110:65]
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node _T_49 = bits(io.lsu_pkt_d.dword, 0, 0) @[Bitwise.scala 72:15]
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node _T_50 = mux(_T_49, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
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node _T_51 = and(_T_50, UInt<3>("h07")) @[el2_lsu_lsc_ctl.scala 112:35]
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node addr_offset_d = or(_T_48, _T_51) @[el2_lsu_lsc_ctl.scala 111:47]
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node _T_52 = bits(lsu_offset_d, 11, 11) @[el2_lsu_lsc_ctl.scala 114:39]
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node _T_53 = bits(lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 114:52]
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node _T_54 = cat(_T_52, _T_53) @[Cat.scala 29:58]
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node _T_55 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
|
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|
node _T_56 = bits(addr_offset_d, 2, 0) @[el2_lsu_lsc_ctl.scala 114:91]
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|
node _T_57 = cat(_T_55, _T_56) @[Cat.scala 29:58]
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node _T_58 = add(_T_54, _T_57) @[el2_lsu_lsc_ctl.scala 114:60]
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|
node end_addr_offset_d = tail(_T_58, 1) @[el2_lsu_lsc_ctl.scala 114:60]
|
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|
node _T_59 = bits(rs1_d, 31, 0) @[el2_lsu_lsc_ctl.scala 115:32]
|
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|
node _T_60 = bits(end_addr_offset_d, 12, 12) @[el2_lsu_lsc_ctl.scala 115:70]
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|
node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15]
|
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node _T_62 = mux(_T_61, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
|
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|
node _T_63 = bits(end_addr_offset_d, 12, 0) @[el2_lsu_lsc_ctl.scala 115:93]
|
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node _T_64 = cat(_T_62, _T_63) @[Cat.scala 29:58]
|
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node _T_65 = add(_T_59, _T_64) @[el2_lsu_lsc_ctl.scala 115:39]
|
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|
node full_end_addr_d = tail(_T_65, 1) @[el2_lsu_lsc_ctl.scala 115:39]
|
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|
io.end_addr_d <= full_end_addr_d @[el2_lsu_lsc_ctl.scala 116:24]
|
|
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|
inst addrcheck of el2_lsu_addrcheck @[el2_lsu_lsc_ctl.scala 119:25]
|
2020-10-22 17:52:47 +08:00
|
|
|
addrcheck.clock <= clock
|
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|
addrcheck.reset <= reset
|
2020-11-06 18:05:28 +08:00
|
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|
addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[el2_lsu_lsc_ctl.scala 121:42]
|
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|
addrcheck.io.start_addr_d <= full_addr_d @[el2_lsu_lsc_ctl.scala 123:42]
|
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|
addrcheck.io.end_addr_d <= full_end_addr_d @[el2_lsu_lsc_ctl.scala 124:42]
|
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|
addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[el2_lsu_lsc_ctl.scala 125:42]
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addrcheck.io.lsu_pkt_d.store_data_bypass_m <= io.lsu_pkt_d.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 125:42]
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addrcheck.io.lsu_pkt_d.load_ldst_bypass_d <= io.lsu_pkt_d.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 125:42]
|
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addrcheck.io.lsu_pkt_d.store_data_bypass_d <= io.lsu_pkt_d.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 125:42]
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|
addrcheck.io.lsu_pkt_d.dma <= io.lsu_pkt_d.dma @[el2_lsu_lsc_ctl.scala 125:42]
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addrcheck.io.lsu_pkt_d.unsign <= io.lsu_pkt_d.unsign @[el2_lsu_lsc_ctl.scala 125:42]
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addrcheck.io.lsu_pkt_d.store <= io.lsu_pkt_d.store @[el2_lsu_lsc_ctl.scala 125:42]
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addrcheck.io.lsu_pkt_d.load <= io.lsu_pkt_d.load @[el2_lsu_lsc_ctl.scala 125:42]
|
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addrcheck.io.lsu_pkt_d.dword <= io.lsu_pkt_d.dword @[el2_lsu_lsc_ctl.scala 125:42]
|
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addrcheck.io.lsu_pkt_d.word <= io.lsu_pkt_d.word @[el2_lsu_lsc_ctl.scala 125:42]
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addrcheck.io.lsu_pkt_d.half <= io.lsu_pkt_d.half @[el2_lsu_lsc_ctl.scala 125:42]
|
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|
addrcheck.io.lsu_pkt_d.by <= io.lsu_pkt_d.by @[el2_lsu_lsc_ctl.scala 125:42]
|
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|
addrcheck.io.lsu_pkt_d.fast_int <= io.lsu_pkt_d.fast_int @[el2_lsu_lsc_ctl.scala 125:42]
|
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|
|
addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[el2_lsu_lsc_ctl.scala 126:42]
|
|
|
|
|
node _T_66 = bits(rs1_d, 31, 28) @[el2_lsu_lsc_ctl.scala 127:50]
|
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|
|
|
addrcheck.io.rs1_region_d <= _T_66 @[el2_lsu_lsc_ctl.scala 127:42]
|
|
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|
addrcheck.io.rs1_d <= rs1_d @[el2_lsu_lsc_ctl.scala 128:42]
|
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|
|
|
io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[el2_lsu_lsc_ctl.scala 129:42]
|
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|
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|
io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[el2_lsu_lsc_ctl.scala 130:42]
|
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|
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|
io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[el2_lsu_lsc_ctl.scala 131:42]
|
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|
|
|
addrcheck.io.scan_mode <= io.scan_mode @[el2_lsu_lsc_ctl.scala 138:42]
|
2020-10-22 17:52:47 +08:00
|
|
|
wire exc_mscause_r : UInt<4>
|
|
|
|
|
exc_mscause_r <= UInt<4>("h00")
|
|
|
|
|
wire fir_dccm_access_error_r : UInt<1>
|
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|
|
fir_dccm_access_error_r <= UInt<1>("h00")
|
|
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|
|
wire fir_nondccm_access_error_r : UInt<1>
|
|
|
|
|
fir_nondccm_access_error_r <= UInt<1>("h00")
|
2020-11-06 18:05:28 +08:00
|
|
|
wire access_fault_r : UInt<1>
|
|
|
|
|
access_fault_r <= UInt<1>("h00")
|
|
|
|
|
wire misaligned_fault_r : UInt<1>
|
|
|
|
|
misaligned_fault_r <= UInt<1>("h00")
|
2020-10-22 17:52:47 +08:00
|
|
|
wire lsu_fir_error_m : UInt<2>
|
|
|
|
|
lsu_fir_error_m <= UInt<2>("h00")
|
|
|
|
|
wire fir_dccm_access_error_m : UInt<1>
|
|
|
|
|
fir_dccm_access_error_m <= UInt<1>("h00")
|
|
|
|
|
wire fir_nondccm_access_error_m : UInt<1>
|
|
|
|
|
fir_nondccm_access_error_m <= UInt<1>("h00")
|
2020-11-06 18:05:28 +08:00
|
|
|
reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 150:75]
|
|
|
|
|
access_fault_m <= addrcheck.io.access_fault_d @[el2_lsu_lsc_ctl.scala 150:75]
|
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|
|
|
reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 151:75]
|
|
|
|
|
misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[el2_lsu_lsc_ctl.scala 151:75]
|
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|
|
|
reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 152:75]
|
|
|
|
|
exc_mscause_m <= addrcheck.io.exc_mscause_d @[el2_lsu_lsc_ctl.scala 152:75]
|
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|
|
|
reg _T_67 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 153:75]
|
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|
_T_67 <= addrcheck.io.fir_dccm_access_error_d @[el2_lsu_lsc_ctl.scala 153:75]
|
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|
|
|
fir_dccm_access_error_m <= _T_67 @[el2_lsu_lsc_ctl.scala 153:38]
|
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|
|
|
reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 154:75]
|
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|
_T_68 <= addrcheck.io.fir_nondccm_access_error_d @[el2_lsu_lsc_ctl.scala 154:75]
|
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|
|
|
fir_nondccm_access_error_m <= _T_68 @[el2_lsu_lsc_ctl.scala 154:38]
|
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|
|
|
node _T_69 = or(access_fault_m, misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 156:34]
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|
|
|
io.lsu_exc_m <= _T_69 @[el2_lsu_lsc_ctl.scala 156:16]
|
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|
node _T_70 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 157:64]
|
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|
node _T_71 = and(io.lsu_single_ecc_error_r, _T_70) @[el2_lsu_lsc_ctl.scala 157:62]
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|
node _T_72 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_lsc_ctl.scala 157:111]
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|
node _T_73 = and(_T_71, _T_72) @[el2_lsu_lsc_ctl.scala 157:92]
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|
node _T_74 = and(_T_73, io.lsu_pkt_r.valid) @[el2_lsu_lsc_ctl.scala 157:131]
|
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|
|
|
io.lsu_single_ecc_error_incr <= _T_74 @[el2_lsu_lsc_ctl.scala 157:32]
|
2020-11-23 17:53:08 +08:00
|
|
|
node _T_75 = or(access_fault_m, misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 179:46]
|
|
|
|
|
node _T_76 = or(_T_75, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 179:67]
|
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|
node _T_77 = and(_T_76, io.lsu_pkt_m.valid) @[el2_lsu_lsc_ctl.scala 179:96]
|
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|
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|
node _T_78 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:119]
|
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|
node _T_79 = and(_T_77, _T_78) @[el2_lsu_lsc_ctl.scala 179:117]
|
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|
|
|
node _T_80 = eq(io.lsu_pkt_m.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:139]
|
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|
node _T_81 = and(_T_79, _T_80) @[el2_lsu_lsc_ctl.scala 179:137]
|
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|
node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:164]
|
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|
node _T_83 = and(_T_81, _T_82) @[el2_lsu_lsc_ctl.scala 179:162]
|
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|
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|
lsu_error_pkt_m.valid <= _T_83 @[el2_lsu_lsc_ctl.scala 179:27]
|
|
|
|
|
node _T_84 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:75]
|
|
|
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|
node _T_85 = and(io.lsu_single_ecc_error_m, _T_84) @[el2_lsu_lsc_ctl.scala 180:73]
|
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|
node _T_86 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:101]
|
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|
|
|
node _T_87 = and(_T_85, _T_86) @[el2_lsu_lsc_ctl.scala 180:99]
|
|
|
|
|
lsu_error_pkt_m.bits.single_ecc_error <= _T_87 @[el2_lsu_lsc_ctl.scala 180:43]
|
|
|
|
|
lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.store @[el2_lsu_lsc_ctl.scala 181:43]
|
|
|
|
|
node _T_88 = not(misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 182:46]
|
|
|
|
|
lsu_error_pkt_m.bits.exc_type <= _T_88 @[el2_lsu_lsc_ctl.scala 182:43]
|
|
|
|
|
node _T_89 = eq(misaligned_fault_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 183:80]
|
|
|
|
|
node _T_90 = and(io.lsu_double_ecc_error_m, _T_89) @[el2_lsu_lsc_ctl.scala 183:78]
|
|
|
|
|
node _T_91 = eq(access_fault_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 183:102]
|
|
|
|
|
node _T_92 = and(_T_90, _T_91) @[el2_lsu_lsc_ctl.scala 183:100]
|
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|
|
|
node _T_93 = eq(_T_92, UInt<1>("h01")) @[el2_lsu_lsc_ctl.scala 183:118]
|
|
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|
|
node _T_94 = bits(exc_mscause_m, 3, 0) @[el2_lsu_lsc_ctl.scala 183:149]
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|
node _T_95 = mux(_T_93, UInt<4>("h01"), _T_94) @[el2_lsu_lsc_ctl.scala 183:49]
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|
lsu_error_pkt_m.bits.mscause <= _T_95 @[el2_lsu_lsc_ctl.scala 183:43]
|
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|
node _T_96 = bits(io.lsu_addr_m, 31, 0) @[el2_lsu_lsc_ctl.scala 184:59]
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|
lsu_error_pkt_m.bits.addr <= _T_96 @[el2_lsu_lsc_ctl.scala 184:43]
|
2020-11-06 18:05:28 +08:00
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|
node _T_97 = bits(fir_nondccm_access_error_m, 0, 0) @[el2_lsu_lsc_ctl.scala 185:72]
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|
node _T_98 = bits(fir_dccm_access_error_m, 0, 0) @[el2_lsu_lsc_ctl.scala 185:117]
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node _T_99 = and(io.lsu_pkt_m.fast_int, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 185:161]
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|
node _T_100 = bits(_T_99, 0, 0) @[el2_lsu_lsc_ctl.scala 185:190]
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|
node _T_101 = mux(_T_100, UInt<2>("h01"), UInt<2>("h00")) @[el2_lsu_lsc_ctl.scala 185:137]
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node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[el2_lsu_lsc_ctl.scala 185:92]
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node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[el2_lsu_lsc_ctl.scala 185:44]
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lsu_fir_error_m <= _T_103 @[el2_lsu_lsc_ctl.scala 185:38]
|
2020-11-23 17:53:08 +08:00
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wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 186:104]
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_T_104.bits.addr <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
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_T_104.bits.mscause <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
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_T_104.bits.exc_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
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_T_104.bits.inst_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
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_T_104.bits.single_ecc_error <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
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_T_104.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
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reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75]
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_T_105.bits.addr <= lsu_error_pkt_m.bits.addr @[el2_lsu_lsc_ctl.scala 186:75]
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_T_105.bits.mscause <= lsu_error_pkt_m.bits.mscause @[el2_lsu_lsc_ctl.scala 186:75]
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|
_T_105.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[el2_lsu_lsc_ctl.scala 186:75]
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|
_T_105.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[el2_lsu_lsc_ctl.scala 186:75]
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_T_105.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[el2_lsu_lsc_ctl.scala 186:75]
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_T_105.valid <= lsu_error_pkt_m.valid @[el2_lsu_lsc_ctl.scala 186:75]
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|
io.lsu_error_pkt_r.bits.addr <= _T_105.bits.addr @[el2_lsu_lsc_ctl.scala 186:38]
|
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|
io.lsu_error_pkt_r.bits.mscause <= _T_105.bits.mscause @[el2_lsu_lsc_ctl.scala 186:38]
|
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|
|
io.lsu_error_pkt_r.bits.exc_type <= _T_105.bits.exc_type @[el2_lsu_lsc_ctl.scala 186:38]
|
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|
|
io.lsu_error_pkt_r.bits.inst_type <= _T_105.bits.inst_type @[el2_lsu_lsc_ctl.scala 186:38]
|
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|
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_105.bits.single_ecc_error @[el2_lsu_lsc_ctl.scala 186:38]
|
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|
|
io.lsu_error_pkt_r.valid <= _T_105.valid @[el2_lsu_lsc_ctl.scala 186:38]
|
2020-11-06 18:05:28 +08:00
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|
|
reg _T_106 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 187:75]
|
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|
_T_106 <= lsu_fir_error_m @[el2_lsu_lsc_ctl.scala 187:75]
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|
|
io.lsu_fir_error <= _T_106 @[el2_lsu_lsc_ctl.scala 187:38]
|
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|
dma_pkt_d.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 189:22]
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|
|
dma_pkt_d.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 190:22]
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|
|
dma_pkt_d.valid <= io.dma_dccm_req @[el2_lsu_lsc_ctl.scala 191:22]
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|
|
dma_pkt_d.dma <= UInt<1>("h01") @[el2_lsu_lsc_ctl.scala 192:22]
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|
dma_pkt_d.store <= io.dma_mem_write @[el2_lsu_lsc_ctl.scala 193:22]
|
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|
node _T_107 = not(io.dma_mem_write) @[el2_lsu_lsc_ctl.scala 194:25]
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|
|
dma_pkt_d.load <= _T_107 @[el2_lsu_lsc_ctl.scala 194:22]
|
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|
|
node _T_108 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 195:39]
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|
|
node _T_109 = eq(_T_108, UInt<3>("h00")) @[el2_lsu_lsc_ctl.scala 195:45]
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|
|
dma_pkt_d.by <= _T_109 @[el2_lsu_lsc_ctl.scala 195:22]
|
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|
|
node _T_110 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 196:39]
|
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|
|
node _T_111 = eq(_T_110, UInt<3>("h01")) @[el2_lsu_lsc_ctl.scala 196:45]
|
|
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|
|
dma_pkt_d.half <= _T_111 @[el2_lsu_lsc_ctl.scala 196:22]
|
|
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|
|
node _T_112 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 197:39]
|
|
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|
|
node _T_113 = eq(_T_112, UInt<3>("h02")) @[el2_lsu_lsc_ctl.scala 197:45]
|
|
|
|
|
dma_pkt_d.word <= _T_113 @[el2_lsu_lsc_ctl.scala 197:22]
|
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|
|
node _T_114 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 198:39]
|
|
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|
|
node _T_115 = eq(_T_114, UInt<3>("h03")) @[el2_lsu_lsc_ctl.scala 198:45]
|
|
|
|
|
dma_pkt_d.dword <= _T_115 @[el2_lsu_lsc_ctl.scala 198:22]
|
|
|
|
|
dma_pkt_d.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 199:34]
|
|
|
|
|
dma_pkt_d.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 200:34]
|
|
|
|
|
dma_pkt_d.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 201:34]
|
2020-10-22 17:52:47 +08:00
|
|
|
wire lsu_ld_datafn_r : UInt<32>
|
|
|
|
|
lsu_ld_datafn_r <= UInt<32>("h00")
|
|
|
|
|
wire lsu_ld_datafn_corr_r : UInt<32>
|
|
|
|
|
lsu_ld_datafn_corr_r <= UInt<32>("h00")
|
|
|
|
|
wire lsu_ld_datafn_m : UInt<32>
|
|
|
|
|
lsu_ld_datafn_m <= UInt<32>("h00")
|
2020-11-06 18:05:28 +08:00
|
|
|
node _T_116 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 207:50]
|
|
|
|
|
node _T_117 = mux(_T_116, io.lsu_p, dma_pkt_d) @[el2_lsu_lsc_ctl.scala 207:26]
|
|
|
|
|
io.lsu_pkt_d.valid <= _T_117.valid @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
io.lsu_pkt_d.store_data_bypass_m <= _T_117.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
io.lsu_pkt_d.load_ldst_bypass_d <= _T_117.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
io.lsu_pkt_d.store_data_bypass_d <= _T_117.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
io.lsu_pkt_d.dma <= _T_117.dma @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
io.lsu_pkt_d.unsign <= _T_117.unsign @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
io.lsu_pkt_d.store <= _T_117.store @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
io.lsu_pkt_d.load <= _T_117.load @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
io.lsu_pkt_d.dword <= _T_117.dword @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
io.lsu_pkt_d.word <= _T_117.word @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
io.lsu_pkt_d.half <= _T_117.half @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
io.lsu_pkt_d.by <= _T_117.by @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
io.lsu_pkt_d.fast_int <= _T_117.fast_int @[el2_lsu_lsc_ctl.scala 207:20]
|
|
|
|
|
lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_m_in.store_data_bypass_m <= io.lsu_pkt_d.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_m_in.load_ldst_bypass_d <= io.lsu_pkt_d.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_m_in.store_data_bypass_d <= io.lsu_pkt_d.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_m_in.dma <= io.lsu_pkt_d.dma @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_m_in.unsign <= io.lsu_pkt_d.unsign @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_m_in.store <= io.lsu_pkt_d.store @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_m_in.load <= io.lsu_pkt_d.load @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_m_in.dword <= io.lsu_pkt_d.dword @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_m_in.word <= io.lsu_pkt_d.word @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_m_in.half <= io.lsu_pkt_d.half @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_m_in.by <= io.lsu_pkt_d.by @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_m_in.fast_int <= io.lsu_pkt_d.fast_int @[el2_lsu_lsc_ctl.scala 208:20]
|
|
|
|
|
lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
lsu_pkt_r_in.store_data_bypass_m <= io.lsu_pkt_m.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
lsu_pkt_r_in.load_ldst_bypass_d <= io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
lsu_pkt_r_in.store_data_bypass_d <= io.lsu_pkt_m.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
lsu_pkt_r_in.dma <= io.lsu_pkt_m.dma @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
lsu_pkt_r_in.unsign <= io.lsu_pkt_m.unsign @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
lsu_pkt_r_in.store <= io.lsu_pkt_m.store @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
lsu_pkt_r_in.load <= io.lsu_pkt_m.load @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
lsu_pkt_r_in.dword <= io.lsu_pkt_m.dword @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
lsu_pkt_r_in.word <= io.lsu_pkt_m.word @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
lsu_pkt_r_in.half <= io.lsu_pkt_m.half @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
lsu_pkt_r_in.by <= io.lsu_pkt_m.by @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
lsu_pkt_r_in.fast_int <= io.lsu_pkt_m.fast_int @[el2_lsu_lsc_ctl.scala 209:20]
|
|
|
|
|
node _T_118 = eq(io.lsu_p.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 211:64]
|
|
|
|
|
node _T_119 = and(io.flush_m_up, _T_118) @[el2_lsu_lsc_ctl.scala 211:61]
|
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|
|
node _T_120 = eq(_T_119, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 211:45]
|
|
|
|
|
node _T_121 = and(io.lsu_p.valid, _T_120) @[el2_lsu_lsc_ctl.scala 211:43]
|
|
|
|
|
node _T_122 = or(_T_121, io.dma_dccm_req) @[el2_lsu_lsc_ctl.scala 211:85]
|
|
|
|
|
io.lsu_pkt_d.valid <= _T_122 @[el2_lsu_lsc_ctl.scala 211:24]
|
|
|
|
|
node _T_123 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 212:68]
|
|
|
|
|
node _T_124 = and(io.flush_m_up, _T_123) @[el2_lsu_lsc_ctl.scala 212:65]
|
|
|
|
|
node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 212:49]
|
|
|
|
|
node _T_126 = and(io.lsu_pkt_d.valid, _T_125) @[el2_lsu_lsc_ctl.scala 212:47]
|
|
|
|
|
lsu_pkt_m_in.valid <= _T_126 @[el2_lsu_lsc_ctl.scala 212:24]
|
|
|
|
|
node _T_127 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 213:68]
|
|
|
|
|
node _T_128 = and(io.flush_m_up, _T_127) @[el2_lsu_lsc_ctl.scala 213:65]
|
|
|
|
|
node _T_129 = eq(_T_128, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 213:49]
|
|
|
|
|
node _T_130 = and(io.lsu_pkt_m.valid, _T_129) @[el2_lsu_lsc_ctl.scala 213:47]
|
|
|
|
|
lsu_pkt_r_in.valid <= _T_130 @[el2_lsu_lsc_ctl.scala 213:24]
|
|
|
|
|
wire _T_131 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.dma <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.store <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.load <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.dword <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.word <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.half <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.by <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
_T_131.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
|
|
|
|
|
reg _T_132 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, io.lsu_c1_m_clk with : (reset => (reset, _T_131)) @[el2_lsu_lsc_ctl.scala 215:65]
|
|
|
|
|
_T_132.valid <= lsu_pkt_m_in.valid @[el2_lsu_lsc_ctl.scala 215:65]
|
|
|
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|
_T_132.store_data_bypass_m <= lsu_pkt_m_in.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 215:65]
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_T_132.load_ldst_bypass_d <= lsu_pkt_m_in.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 215:65]
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_T_132.store_data_bypass_d <= lsu_pkt_m_in.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 215:65]
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_T_132.dma <= lsu_pkt_m_in.dma @[el2_lsu_lsc_ctl.scala 215:65]
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_T_132.unsign <= lsu_pkt_m_in.unsign @[el2_lsu_lsc_ctl.scala 215:65]
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_T_132.store <= lsu_pkt_m_in.store @[el2_lsu_lsc_ctl.scala 215:65]
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_T_132.load <= lsu_pkt_m_in.load @[el2_lsu_lsc_ctl.scala 215:65]
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_T_132.dword <= lsu_pkt_m_in.dword @[el2_lsu_lsc_ctl.scala 215:65]
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_T_132.word <= lsu_pkt_m_in.word @[el2_lsu_lsc_ctl.scala 215:65]
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_T_132.half <= lsu_pkt_m_in.half @[el2_lsu_lsc_ctl.scala 215:65]
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_T_132.by <= lsu_pkt_m_in.by @[el2_lsu_lsc_ctl.scala 215:65]
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_T_132.fast_int <= lsu_pkt_m_in.fast_int @[el2_lsu_lsc_ctl.scala 215:65]
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io.lsu_pkt_m.valid <= _T_132.valid @[el2_lsu_lsc_ctl.scala 215:28]
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io.lsu_pkt_m.store_data_bypass_m <= _T_132.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 215:28]
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io.lsu_pkt_m.load_ldst_bypass_d <= _T_132.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 215:28]
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io.lsu_pkt_m.store_data_bypass_d <= _T_132.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 215:28]
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io.lsu_pkt_m.dma <= _T_132.dma @[el2_lsu_lsc_ctl.scala 215:28]
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io.lsu_pkt_m.unsign <= _T_132.unsign @[el2_lsu_lsc_ctl.scala 215:28]
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io.lsu_pkt_m.store <= _T_132.store @[el2_lsu_lsc_ctl.scala 215:28]
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io.lsu_pkt_m.load <= _T_132.load @[el2_lsu_lsc_ctl.scala 215:28]
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io.lsu_pkt_m.dword <= _T_132.dword @[el2_lsu_lsc_ctl.scala 215:28]
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io.lsu_pkt_m.word <= _T_132.word @[el2_lsu_lsc_ctl.scala 215:28]
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io.lsu_pkt_m.half <= _T_132.half @[el2_lsu_lsc_ctl.scala 215:28]
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io.lsu_pkt_m.by <= _T_132.by @[el2_lsu_lsc_ctl.scala 215:28]
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io.lsu_pkt_m.fast_int <= _T_132.fast_int @[el2_lsu_lsc_ctl.scala 215:28]
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wire _T_133 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.dma <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.store <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.load <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.dword <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.word <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.half <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.by <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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_T_133.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
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reg _T_134 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, io.lsu_c1_r_clk with : (reset => (reset, _T_133)) @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.valid <= lsu_pkt_r_in.valid @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.store_data_bypass_m <= lsu_pkt_r_in.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.load_ldst_bypass_d <= lsu_pkt_r_in.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.store_data_bypass_d <= lsu_pkt_r_in.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.dma <= lsu_pkt_r_in.dma @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.unsign <= lsu_pkt_r_in.unsign @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.store <= lsu_pkt_r_in.store @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.load <= lsu_pkt_r_in.load @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.dword <= lsu_pkt_r_in.dword @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.word <= lsu_pkt_r_in.word @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.half <= lsu_pkt_r_in.half @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.by <= lsu_pkt_r_in.by @[el2_lsu_lsc_ctl.scala 216:65]
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_T_134.fast_int <= lsu_pkt_r_in.fast_int @[el2_lsu_lsc_ctl.scala 216:65]
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io.lsu_pkt_r.valid <= _T_134.valid @[el2_lsu_lsc_ctl.scala 216:28]
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io.lsu_pkt_r.store_data_bypass_m <= _T_134.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 216:28]
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io.lsu_pkt_r.load_ldst_bypass_d <= _T_134.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 216:28]
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io.lsu_pkt_r.store_data_bypass_d <= _T_134.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 216:28]
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io.lsu_pkt_r.dma <= _T_134.dma @[el2_lsu_lsc_ctl.scala 216:28]
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io.lsu_pkt_r.unsign <= _T_134.unsign @[el2_lsu_lsc_ctl.scala 216:28]
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io.lsu_pkt_r.store <= _T_134.store @[el2_lsu_lsc_ctl.scala 216:28]
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io.lsu_pkt_r.load <= _T_134.load @[el2_lsu_lsc_ctl.scala 216:28]
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io.lsu_pkt_r.dword <= _T_134.dword @[el2_lsu_lsc_ctl.scala 216:28]
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io.lsu_pkt_r.word <= _T_134.word @[el2_lsu_lsc_ctl.scala 216:28]
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io.lsu_pkt_r.half <= _T_134.half @[el2_lsu_lsc_ctl.scala 216:28]
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io.lsu_pkt_r.by <= _T_134.by @[el2_lsu_lsc_ctl.scala 216:28]
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io.lsu_pkt_r.fast_int <= _T_134.fast_int @[el2_lsu_lsc_ctl.scala 216:28]
|
2020-11-23 17:53:08 +08:00
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reg _T_135 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 217:65]
|
2020-11-06 18:05:28 +08:00
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_T_135 <= lsu_pkt_m_in.valid @[el2_lsu_lsc_ctl.scala 217:65]
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io.lsu_pkt_m.valid <= _T_135 @[el2_lsu_lsc_ctl.scala 217:28]
|
2020-11-23 17:53:08 +08:00
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reg _T_136 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 218:65]
|
2020-11-06 18:05:28 +08:00
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_T_136 <= lsu_pkt_r_in.valid @[el2_lsu_lsc_ctl.scala 218:65]
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io.lsu_pkt_r.valid <= _T_136 @[el2_lsu_lsc_ctl.scala 218:28]
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node _T_137 = bits(io.dma_mem_wdata, 63, 0) @[el2_lsu_lsc_ctl.scala 220:47]
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node _T_138 = bits(io.dma_mem_addr, 2, 0) @[el2_lsu_lsc_ctl.scala 220:76]
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node _T_139 = cat(_T_138, UInt<3>("h00")) @[Cat.scala 29:58]
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node dma_mem_wdata_shifted = dshr(_T_137, _T_139) @[el2_lsu_lsc_ctl.scala 220:54]
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node _T_140 = bits(io.dma_dccm_req, 0, 0) @[el2_lsu_lsc_ctl.scala 221:51]
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node _T_141 = bits(dma_mem_wdata_shifted, 31, 0) @[el2_lsu_lsc_ctl.scala 221:79]
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node _T_142 = bits(io.exu_lsu_rs2_d, 31, 0) @[el2_lsu_lsc_ctl.scala 221:102]
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node store_data_d = mux(_T_140, _T_141, _T_142) @[el2_lsu_lsc_ctl.scala 221:34]
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node _T_143 = bits(io.lsu_pkt_d.store_data_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 222:68]
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node _T_144 = bits(io.lsu_result_m, 31, 0) @[el2_lsu_lsc_ctl.scala 222:90]
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node _T_145 = bits(store_data_d, 31, 0) @[el2_lsu_lsc_ctl.scala 222:109]
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node store_data_m_in = mux(_T_143, _T_144, _T_145) @[el2_lsu_lsc_ctl.scala 222:34]
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reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 224:72]
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|
store_data_pre_m <= store_data_m_in @[el2_lsu_lsc_ctl.scala 224:72]
|
2020-11-23 17:53:08 +08:00
|
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|
reg _T_146 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 225:62]
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|
_T_146 <= io.lsu_addr_d @[el2_lsu_lsc_ctl.scala 225:62]
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|
io.lsu_addr_m <= _T_146 @[el2_lsu_lsc_ctl.scala 225:24]
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|
reg _T_147 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 226:62]
|
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|
_T_147 <= io.lsu_addr_m @[el2_lsu_lsc_ctl.scala 226:62]
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|
|
io.lsu_addr_r <= _T_147 @[el2_lsu_lsc_ctl.scala 226:24]
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|
reg _T_148 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 227:62]
|
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|
_T_148 <= io.end_addr_d @[el2_lsu_lsc_ctl.scala 227:62]
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|
io.end_addr_m <= _T_148 @[el2_lsu_lsc_ctl.scala 227:24]
|
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|
reg _T_149 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 228:62]
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|
_T_149 <= io.end_addr_m @[el2_lsu_lsc_ctl.scala 228:62]
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|
io.end_addr_r <= _T_149 @[el2_lsu_lsc_ctl.scala 228:24]
|
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|
reg _T_150 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 229:62]
|
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|
_T_150 <= io.addr_in_dccm_d @[el2_lsu_lsc_ctl.scala 229:62]
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|
|
io.addr_in_dccm_m <= _T_150 @[el2_lsu_lsc_ctl.scala 229:24]
|
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|
reg _T_151 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 230:62]
|
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|
|
_T_151 <= io.addr_in_dccm_m @[el2_lsu_lsc_ctl.scala 230:62]
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|
|
io.addr_in_dccm_r <= _T_151 @[el2_lsu_lsc_ctl.scala 230:24]
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|
|
reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 231:62]
|
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|
_T_152 <= io.addr_in_pic_d @[el2_lsu_lsc_ctl.scala 231:62]
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|
|
io.addr_in_pic_m <= _T_152 @[el2_lsu_lsc_ctl.scala 231:24]
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|
|
reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 232:62]
|
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|
_T_153 <= io.addr_in_pic_m @[el2_lsu_lsc_ctl.scala 232:62]
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|
|
io.addr_in_pic_r <= _T_153 @[el2_lsu_lsc_ctl.scala 232:24]
|
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|
|
reg _T_154 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 233:62]
|
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|
_T_154 <= addrcheck.io.addr_external_d @[el2_lsu_lsc_ctl.scala 233:62]
|
|
|
|
|
io.addr_external_m <= _T_154 @[el2_lsu_lsc_ctl.scala 233:24]
|
2020-11-06 18:05:28 +08:00
|
|
|
reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 234:66]
|
|
|
|
|
addr_external_r <= io.addr_external_m @[el2_lsu_lsc_ctl.scala 234:66]
|
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|
|
reg bus_read_data_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 235:66]
|
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|
|
bus_read_data_r <= io.bus_read_data_m @[el2_lsu_lsc_ctl.scala 235:66]
|
|
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|
|
node _T_155 = bits(io.lsu_ld_data_corr_r, 31, 1) @[el2_lsu_lsc_ctl.scala 237:52]
|
|
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|
|
io.lsu_fir_addr <= _T_155 @[el2_lsu_lsc_ctl.scala 237:28]
|
|
|
|
|
io.lsu_addr_d <= full_addr_d @[el2_lsu_lsc_ctl.scala 239:28]
|
|
|
|
|
node _T_156 = or(io.lsu_pkt_r.store, io.lsu_pkt_r.load) @[el2_lsu_lsc_ctl.scala 241:63]
|
|
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|
|
node _T_157 = and(io.lsu_pkt_r.valid, _T_156) @[el2_lsu_lsc_ctl.scala 241:41]
|
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|
node _T_158 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 241:86]
|
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|
|
node _T_159 = and(_T_157, _T_158) @[el2_lsu_lsc_ctl.scala 241:84]
|
|
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|
node _T_160 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 241:100]
|
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|
|
node _T_161 = and(_T_159, _T_160) @[el2_lsu_lsc_ctl.scala 241:98]
|
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|
|
io.lsu_commit_r <= _T_161 @[el2_lsu_lsc_ctl.scala 241:19]
|
|
|
|
|
node _T_162 = bits(io.picm_mask_data_m, 31, 0) @[el2_lsu_lsc_ctl.scala 242:52]
|
|
|
|
|
node _T_163 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 242:69]
|
|
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|
|
node _T_164 = bits(_T_163, 0, 0) @[Bitwise.scala 72:15]
|
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|
|
node _T_165 = mux(_T_164, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
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|
|
node _T_166 = or(_T_162, _T_165) @[el2_lsu_lsc_ctl.scala 242:59]
|
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|
|
node _T_167 = bits(io.lsu_pkt_m.store_data_bypass_m, 0, 0) @[el2_lsu_lsc_ctl.scala 242:128]
|
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|
|
node _T_168 = mux(_T_167, io.lsu_result_m, store_data_pre_m) @[el2_lsu_lsc_ctl.scala 242:94]
|
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|
node _T_169 = and(_T_166, _T_168) @[el2_lsu_lsc_ctl.scala 242:89]
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|
io.store_data_m <= _T_169 @[el2_lsu_lsc_ctl.scala 242:29]
|
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|
node _T_170 = bits(io.addr_external_m, 0, 0) @[el2_lsu_lsc_ctl.scala 263:53]
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|
|
node _T_171 = mux(_T_170, io.bus_read_data_m, io.lsu_ld_data_m) @[el2_lsu_lsc_ctl.scala 263:33]
|
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lsu_ld_datafn_m <= _T_171 @[el2_lsu_lsc_ctl.scala 263:27]
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node _T_172 = eq(addr_external_r, UInt<1>("h01")) @[el2_lsu_lsc_ctl.scala 264:49]
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node _T_173 = mux(_T_172, bus_read_data_r, io.lsu_ld_data_corr_r) @[el2_lsu_lsc_ctl.scala 264:33]
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lsu_ld_datafn_corr_r <= _T_173 @[el2_lsu_lsc_ctl.scala 264:27]
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node _T_174 = and(io.lsu_pkt_m.unsign, io.lsu_pkt_m.by) @[el2_lsu_lsc_ctl.scala 265:61]
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node _T_175 = bits(_T_174, 0, 0) @[Bitwise.scala 72:15]
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node _T_176 = mux(_T_175, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
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node _T_177 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 265:115]
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node _T_178 = cat(UInt<24>("h00"), _T_177) @[Cat.scala 29:58]
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node _T_179 = and(_T_176, _T_178) @[el2_lsu_lsc_ctl.scala 265:84]
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node _T_180 = and(io.lsu_pkt_m.unsign, io.lsu_pkt_m.half) @[el2_lsu_lsc_ctl.scala 266:38]
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node _T_181 = bits(_T_180, 0, 0) @[Bitwise.scala 72:15]
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node _T_182 = mux(_T_181, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
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node _T_183 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 266:92]
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node _T_184 = cat(UInt<16>("h00"), _T_183) @[Cat.scala 29:58]
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node _T_185 = and(_T_182, _T_184) @[el2_lsu_lsc_ctl.scala 266:61]
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node _T_186 = or(_T_179, _T_185) @[el2_lsu_lsc_ctl.scala 265:123]
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node _T_187 = eq(io.lsu_pkt_m.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 267:17]
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node _T_188 = and(_T_187, io.lsu_pkt_m.by) @[el2_lsu_lsc_ctl.scala 267:38]
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node _T_189 = bits(_T_188, 0, 0) @[Bitwise.scala 72:15]
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node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
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node _T_191 = bits(lsu_ld_datafn_m, 7, 7) @[el2_lsu_lsc_ctl.scala 267:92]
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node _T_192 = bits(_T_191, 0, 0) @[Bitwise.scala 72:15]
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node _T_193 = mux(_T_192, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
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node _T_194 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 267:115]
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node _T_195 = cat(_T_193, _T_194) @[Cat.scala 29:58]
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node _T_196 = and(_T_190, _T_195) @[el2_lsu_lsc_ctl.scala 267:61]
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node _T_197 = or(_T_186, _T_196) @[el2_lsu_lsc_ctl.scala 266:104]
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node _T_198 = eq(io.lsu_pkt_m.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 268:17]
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node _T_199 = and(_T_198, io.lsu_pkt_m.half) @[el2_lsu_lsc_ctl.scala 268:38]
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node _T_200 = bits(_T_199, 0, 0) @[Bitwise.scala 72:15]
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node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
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node _T_202 = bits(lsu_ld_datafn_m, 15, 15) @[el2_lsu_lsc_ctl.scala 268:91]
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node _T_203 = bits(_T_202, 0, 0) @[Bitwise.scala 72:15]
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node _T_204 = mux(_T_203, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
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node _T_205 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 268:115]
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node _T_206 = cat(_T_204, _T_205) @[Cat.scala 29:58]
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node _T_207 = and(_T_201, _T_206) @[el2_lsu_lsc_ctl.scala 268:61]
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node _T_208 = or(_T_197, _T_207) @[el2_lsu_lsc_ctl.scala 267:124]
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node _T_209 = bits(io.lsu_pkt_m.word, 0, 0) @[Bitwise.scala 72:15]
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node _T_210 = mux(_T_209, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
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node _T_211 = bits(lsu_ld_datafn_m, 31, 0) @[el2_lsu_lsc_ctl.scala 269:55]
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node _T_212 = and(_T_210, _T_211) @[el2_lsu_lsc_ctl.scala 269:38]
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node _T_213 = or(_T_208, _T_212) @[el2_lsu_lsc_ctl.scala 268:124]
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io.lsu_result_m <= _T_213 @[el2_lsu_lsc_ctl.scala 265:27]
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node _T_214 = and(io.lsu_pkt_r.unsign, io.lsu_pkt_r.by) @[el2_lsu_lsc_ctl.scala 270:61]
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node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 72:15]
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node _T_216 = mux(_T_215, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
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node _T_217 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 270:120]
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node _T_218 = cat(UInt<24>("h00"), _T_217) @[Cat.scala 29:58]
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node _T_219 = and(_T_216, _T_218) @[el2_lsu_lsc_ctl.scala 270:84]
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node _T_220 = and(io.lsu_pkt_r.unsign, io.lsu_pkt_r.half) @[el2_lsu_lsc_ctl.scala 271:38]
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node _T_221 = bits(_T_220, 0, 0) @[Bitwise.scala 72:15]
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node _T_222 = mux(_T_221, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
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node _T_223 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 271:97]
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node _T_224 = cat(UInt<16>("h00"), _T_223) @[Cat.scala 29:58]
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node _T_225 = and(_T_222, _T_224) @[el2_lsu_lsc_ctl.scala 271:61]
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node _T_226 = or(_T_219, _T_225) @[el2_lsu_lsc_ctl.scala 270:128]
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node _T_227 = eq(io.lsu_pkt_r.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 272:17]
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node _T_228 = and(_T_227, io.lsu_pkt_r.by) @[el2_lsu_lsc_ctl.scala 272:38]
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node _T_229 = bits(_T_228, 0, 0) @[Bitwise.scala 72:15]
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node _T_230 = mux(_T_229, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
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node _T_231 = bits(lsu_ld_datafn_corr_r, 7, 7) @[el2_lsu_lsc_ctl.scala 272:97]
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node _T_232 = bits(_T_231, 0, 0) @[Bitwise.scala 72:15]
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node _T_233 = mux(_T_232, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
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node _T_234 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 272:125]
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node _T_235 = cat(_T_233, _T_234) @[Cat.scala 29:58]
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node _T_236 = and(_T_230, _T_235) @[el2_lsu_lsc_ctl.scala 272:61]
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node _T_237 = or(_T_226, _T_236) @[el2_lsu_lsc_ctl.scala 271:109]
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node _T_238 = eq(io.lsu_pkt_r.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 273:17]
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node _T_239 = and(_T_238, io.lsu_pkt_r.half) @[el2_lsu_lsc_ctl.scala 273:38]
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node _T_240 = bits(_T_239, 0, 0) @[Bitwise.scala 72:15]
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node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
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node _T_242 = bits(lsu_ld_datafn_corr_r, 15, 15) @[el2_lsu_lsc_ctl.scala 273:96]
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node _T_243 = bits(_T_242, 0, 0) @[Bitwise.scala 72:15]
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node _T_244 = mux(_T_243, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
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node _T_245 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 273:125]
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node _T_246 = cat(_T_244, _T_245) @[Cat.scala 29:58]
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node _T_247 = and(_T_241, _T_246) @[el2_lsu_lsc_ctl.scala 273:61]
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node _T_248 = or(_T_237, _T_247) @[el2_lsu_lsc_ctl.scala 272:134]
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node _T_249 = bits(io.lsu_pkt_r.word, 0, 0) @[Bitwise.scala 72:15]
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node _T_250 = mux(_T_249, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
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node _T_251 = bits(lsu_ld_datafn_corr_r, 31, 0) @[el2_lsu_lsc_ctl.scala 274:60]
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node _T_252 = and(_T_250, _T_251) @[el2_lsu_lsc_ctl.scala 274:38]
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node _T_253 = or(_T_248, _T_252) @[el2_lsu_lsc_ctl.scala 273:134]
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io.lsu_result_corr_r <= _T_253 @[el2_lsu_lsc_ctl.scala 270:27]
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2020-10-22 17:52:47 +08:00
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