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DMA Updated

This commit is contained in:
waleed-lm 2020-12-11 10:09:38 +05:00
parent 23ecf60a50
commit 0f1f134851
93 changed files with 14792 additions and 14640 deletions
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86
dbg.fir
View File

@ -144,6 +144,54 @@ circuit dbg :
clkhdr.EN <= io.en @[lib.scala 321:18] clkhdr.EN <= io.en @[lib.scala 321:18]
clkhdr.SE <= io.scan_mode @[lib.scala 322:18] clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
extmodule gated_latch_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_6 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_6 @[lib.scala 318:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 319:14]
clkhdr.CK <= io.clk @[lib.scala 320:18]
clkhdr.EN <= io.en @[lib.scala 321:18]
clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
extmodule gated_latch_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_7 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_7 @[lib.scala 318:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 319:14]
clkhdr.CK <= io.clk @[lib.scala 320:18]
clkhdr.EN <= io.en @[lib.scala 321:18]
clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
module dbg : module dbg :
input clock : Clock input clock : Clock
input reset : AsyncReset input reset : AsyncReset
@ -640,10 +688,14 @@ circuit dbg :
node command_din = cat(_T_300, _T_298) @[Cat.scala 29:58] node command_din = cat(_T_300, _T_298) @[Cat.scala 29:58]
node _T_301 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 237:32] node _T_301 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 237:32]
node _T_302 = asAsyncReset(_T_301) @[dbg.scala 237:59] node _T_302 = asAsyncReset(_T_301) @[dbg.scala 237:59]
reg command_reg : UInt, clock with : (reset => (_T_302, UInt<1>("h00"))) @[Reg.scala 27:20] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 352:23]
when command_wren : @[Reg.scala 28:19] rvclkhdr_5.clock <= clock
command_reg <= command_din @[Reg.scala 28:23] rvclkhdr_5.reset <= _T_302
skip @[Reg.scala 28:19] rvclkhdr_5.io.clk <= clock @[lib.scala 354:18]
rvclkhdr_5.io.en <= command_wren @[lib.scala 355:17]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_302, UInt<1>("h00"))) @[lib.scala 358:16]
command_reg <= command_din @[lib.scala 358:16]
node _T_303 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 241:39] node _T_303 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 241:39]
node _T_304 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 241:77] node _T_304 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 241:77]
node _T_305 = and(_T_303, _T_304) @[dbg.scala 241:58] node _T_305 = and(_T_303, _T_304) @[dbg.scala 241:58]
@ -664,10 +716,14 @@ circuit dbg :
node data0_din = or(_T_313, _T_316) @[dbg.scala 245:64] node data0_din = or(_T_313, _T_316) @[dbg.scala 245:64]
node _T_317 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 246:30] node _T_317 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 246:30]
node _T_318 = asAsyncReset(_T_317) @[dbg.scala 246:57] node _T_318 = asAsyncReset(_T_317) @[dbg.scala 246:57]
reg data0_reg : UInt, clock with : (reset => (_T_318, UInt<1>("h00"))) @[Reg.scala 27:20] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 352:23]
when data0_reg_wren : @[Reg.scala 28:19] rvclkhdr_6.clock <= clock
data0_reg <= data0_din @[Reg.scala 28:23] rvclkhdr_6.reset <= _T_318
skip @[Reg.scala 28:19] rvclkhdr_6.io.clk <= clock @[lib.scala 354:18]
rvclkhdr_6.io.en <= data0_reg_wren @[lib.scala 355:17]
rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (_T_318, UInt<1>("h00"))) @[lib.scala 358:16]
data0_reg <= data0_din @[lib.scala 358:16]
node _T_319 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 250:39] node _T_319 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 250:39]
node _T_320 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 250:77] node _T_320 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 250:77]
node _T_321 = and(_T_319, _T_320) @[dbg.scala 250:58] node _T_321 = and(_T_319, _T_320) @[dbg.scala 250:58]
@ -678,13 +734,13 @@ circuit dbg :
node data1_din = and(_T_324, io.dmi_reg_wdata) @[dbg.scala 251:44] node data1_din = and(_T_324, io.dmi_reg_wdata) @[dbg.scala 251:44]
node _T_325 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 252:27] node _T_325 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 252:27]
node _T_326 = asAsyncReset(_T_325) @[dbg.scala 252:54] node _T_326 = asAsyncReset(_T_325) @[dbg.scala 252:54]
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 352:23] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 352:23]
rvclkhdr_5.clock <= clock rvclkhdr_7.clock <= clock
rvclkhdr_5.reset <= _T_326 rvclkhdr_7.reset <= _T_326
rvclkhdr_5.io.clk <= clock @[lib.scala 354:18] rvclkhdr_7.io.clk <= clock @[lib.scala 354:18]
rvclkhdr_5.io.en <= data1_reg_wren @[lib.scala 355:17] rvclkhdr_7.io.en <= data1_reg_wren @[lib.scala 355:17]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
reg _T_327 : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_326, UInt<1>("h00"))) @[lib.scala 358:16] reg _T_327 : UInt, rvclkhdr_7.io.l1clk with : (reset => (_T_326, UInt<1>("h00"))) @[lib.scala 358:16]
_T_327 <= data1_din @[lib.scala 358:16] _T_327 <= data1_din @[lib.scala 358:16]
data1_reg <= _T_327 @[dbg.scala 252:13] data1_reg <= _T_327 @[dbg.scala 252:13]
wire dbg_nxtstate : UInt<3> wire dbg_nxtstate : UInt<3>

203
dbg.v
View File

@ -344,29 +344,36 @@ module dbg(
wire [20:0] _T_289 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58] wire [20:0] _T_289 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58]
wire _T_294 = dbg_state == 3'h2; // @[dbg.scala 235:100] wire _T_294 = dbg_state == 3'h2; // @[dbg.scala 235:100]
wire command_wren = _T_235 & _T_294; // @[dbg.scala 235:87] wire command_wren = _T_235 & _T_294; // @[dbg.scala 235:87]
wire [31:0] command_din = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20],3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] wire [19:0] _T_298 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58]
reg [31:0] command_reg; // @[Reg.scala 27:20] wire [11:0] _T_300 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58]
wire rvclkhdr_5_io_l1clk; // @[lib.scala 352:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 352:23]
wire rvclkhdr_5_io_en; // @[lib.scala 352:23]
wire rvclkhdr_5_io_scan_mode; // @[lib.scala 352:23]
reg [31:0] command_reg; // @[lib.scala 358:16]
wire _T_305 = _T_87 & _T_217; // @[dbg.scala 241:58] wire _T_305 = _T_87 & _T_217; // @[dbg.scala 241:58]
wire data0_reg_wren0 = _T_305 & _T_294; // @[dbg.scala 241:89] wire data0_reg_wren0 = _T_305 & _T_294; // @[dbg.scala 241:89]
wire _T_307 = dbg_state == 3'h4; // @[dbg.scala 242:59] wire _T_307 = dbg_state == 3'h4; // @[dbg.scala 242:59]
wire _T_308 = io_core_dbg_cmd_done & _T_307; // @[dbg.scala 242:46] wire _T_308 = io_core_dbg_cmd_done & _T_307; // @[dbg.scala 242:46]
wire _T_310 = ~command_reg[16]; // @[dbg.scala 242:83] wire _T_310 = ~command_reg[16]; // @[dbg.scala 242:83]
wire data0_reg_wren1 = _T_308 & _T_310; // @[dbg.scala 242:81] wire data0_reg_wren1 = _T_308 & _T_310; // @[dbg.scala 242:81]
wire data0_reg_wren = data0_reg_wren0 | data0_reg_wren1; // @[dbg.scala 244:40]
wire [31:0] _T_312 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_312 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_313 = _T_312 & io_dmi_reg_wdata; // @[dbg.scala 245:45] wire [31:0] _T_313 = _T_312 & io_dmi_reg_wdata; // @[dbg.scala 245:45]
wire [31:0] _T_315 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_315 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_316 = _T_315 & io_core_dbg_rddata; // @[dbg.scala 245:92] wire [31:0] _T_316 = _T_315 & io_core_dbg_rddata; // @[dbg.scala 245:92]
wire [31:0] data0_din = _T_313 | _T_316; // @[dbg.scala 245:64] wire rvclkhdr_6_io_l1clk; // @[lib.scala 352:23]
reg [31:0] data0_reg; // @[Reg.scala 27:20] wire rvclkhdr_6_io_clk; // @[lib.scala 352:23]
wire rvclkhdr_6_io_en; // @[lib.scala 352:23]
wire rvclkhdr_6_io_scan_mode; // @[lib.scala 352:23]
reg [31:0] data0_reg; // @[lib.scala 358:16]
wire _T_320 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 250:77] wire _T_320 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 250:77]
wire _T_321 = _T_87 & _T_320; // @[dbg.scala 250:58] wire _T_321 = _T_87 & _T_320; // @[dbg.scala 250:58]
wire data1_reg_wren = _T_321 & _T_294; // @[dbg.scala 250:89] wire data1_reg_wren = _T_321 & _T_294; // @[dbg.scala 250:89]
wire [31:0] _T_324 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_324 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire rvclkhdr_5_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_7_io_l1clk; // @[lib.scala 352:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 352:23] wire rvclkhdr_7_io_clk; // @[lib.scala 352:23]
wire rvclkhdr_5_io_en; // @[lib.scala 352:23] wire rvclkhdr_7_io_en; // @[lib.scala 352:23]
wire rvclkhdr_5_io_scan_mode; // @[lib.scala 352:23] wire rvclkhdr_7_io_scan_mode; // @[lib.scala 352:23]
reg [31:0] _T_327; // @[lib.scala 358:16] reg [31:0] _T_327; // @[lib.scala 358:16]
wire [2:0] dbg_nxtstate; wire [2:0] dbg_nxtstate;
wire _T_328 = 3'h0 == dbg_state; // @[Conditional.scala 37:30] wire _T_328 = 3'h0 == dbg_state; // @[Conditional.scala 37:30]
@ -414,30 +421,30 @@ module dbg(
wire _T_424 = 3'h5 == dbg_state; // @[Conditional.scala 37:30] wire _T_424 = 3'h5 == dbg_state; // @[Conditional.scala 37:30]
wire _T_433 = 3'h6 == dbg_state; // @[Conditional.scala 37:30] wire _T_433 = 3'h6 == dbg_state; // @[Conditional.scala 37:30]
wire _T_436 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 304:40] wire _T_436 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 304:40]
wire _GEN_13 = _T_433 & _T_436; // @[Conditional.scala 39:67] wire _GEN_11 = _T_433 & _T_436; // @[Conditional.scala 39:67]
wire _GEN_14 = _T_433 & _T_356; // @[Conditional.scala 39:67] wire _GEN_12 = _T_433 & _T_356; // @[Conditional.scala 39:67]
wire [2:0] _GEN_15 = _T_424 ? _T_348 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_13 = _T_424 ? _T_348 : 3'h0; // @[Conditional.scala 39:67]
wire _GEN_16 = _T_424 | _GEN_13; // @[Conditional.scala 39:67] wire _GEN_14 = _T_424 | _GEN_11; // @[Conditional.scala 39:67]
wire _GEN_17 = _T_424 & dbg_state_en; // @[Conditional.scala 39:67] wire _GEN_15 = _T_424 & dbg_state_en; // @[Conditional.scala 39:67]
wire _GEN_19 = _T_424 ? _T_356 : _GEN_14; // @[Conditional.scala 39:67] wire _GEN_17 = _T_424 ? _T_356 : _GEN_12; // @[Conditional.scala 39:67]
wire [2:0] _GEN_20 = _T_413 ? _T_415 : _GEN_15; // @[Conditional.scala 39:67] wire [2:0] _GEN_18 = _T_413 ? _T_415 : _GEN_13; // @[Conditional.scala 39:67]
wire _GEN_21 = _T_413 ? _T_417 : _GEN_16; // @[Conditional.scala 39:67] wire _GEN_19 = _T_413 ? _T_417 : _GEN_14; // @[Conditional.scala 39:67]
wire _GEN_22 = _T_413 ? _T_356 : _GEN_19; // @[Conditional.scala 39:67] wire _GEN_20 = _T_413 ? _T_356 : _GEN_17; // @[Conditional.scala 39:67]
wire _GEN_23 = _T_413 ? 1'h0 : _GEN_17; // @[Conditional.scala 39:67] wire _GEN_21 = _T_413 ? 1'h0 : _GEN_15; // @[Conditional.scala 39:67]
wire [2:0] _GEN_25 = _T_396 ? _T_401 : _GEN_20; // @[Conditional.scala 39:67] wire [2:0] _GEN_23 = _T_396 ? _T_401 : _GEN_18; // @[Conditional.scala 39:67]
wire _GEN_26 = _T_396 ? _T_406 : _GEN_21; // @[Conditional.scala 39:67] wire _GEN_24 = _T_396 ? _T_406 : _GEN_19; // @[Conditional.scala 39:67]
wire _GEN_27 = _T_396 ? _T_356 : _GEN_22; // @[Conditional.scala 39:67] wire _GEN_25 = _T_396 ? _T_356 : _GEN_20; // @[Conditional.scala 39:67]
wire _GEN_28 = _T_396 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67] wire _GEN_26 = _T_396 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
wire [2:0] _GEN_30 = _T_358 ? _T_370 : _GEN_25; // @[Conditional.scala 39:67] wire [2:0] _GEN_28 = _T_358 ? _T_370 : _GEN_23; // @[Conditional.scala 39:67]
wire _GEN_31 = _T_358 ? _T_384 : _GEN_26; // @[Conditional.scala 39:67] wire _GEN_29 = _T_358 ? _T_384 : _GEN_24; // @[Conditional.scala 39:67]
wire _GEN_32 = _T_358 ? _T_386 : _GEN_28; // @[Conditional.scala 39:67] wire _GEN_30 = _T_358 ? _T_386 : _GEN_26; // @[Conditional.scala 39:67]
wire _GEN_34 = _T_358 & _T_388; // @[Conditional.scala 39:67] wire _GEN_32 = _T_358 & _T_388; // @[Conditional.scala 39:67]
wire _GEN_35 = _T_358 ? _T_356 : _GEN_27; // @[Conditional.scala 39:67] wire _GEN_33 = _T_358 ? _T_356 : _GEN_25; // @[Conditional.scala 39:67]
wire [2:0] _GEN_36 = _T_346 ? _T_348 : _GEN_30; // @[Conditional.scala 39:67] wire [2:0] _GEN_34 = _T_346 ? _T_348 : _GEN_28; // @[Conditional.scala 39:67]
wire _GEN_37 = _T_346 ? _T_351 : _GEN_31; // @[Conditional.scala 39:67] wire _GEN_35 = _T_346 ? _T_351 : _GEN_29; // @[Conditional.scala 39:67]
wire _GEN_38 = _T_346 ? _T_356 : _GEN_35; // @[Conditional.scala 39:67] wire _GEN_36 = _T_346 ? _T_356 : _GEN_33; // @[Conditional.scala 39:67]
wire _GEN_37 = _T_346 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67]
wire _GEN_39 = _T_346 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] wire _GEN_39 = _T_346 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
wire _GEN_41 = _T_346 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67]
wire [31:0] _T_445 = _T_217 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_445 = _T_217 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_446 = _T_445 & data0_reg; // @[dbg.scala 308:71] wire [31:0] _T_446 = _T_445 & data0_reg; // @[dbg.scala 308:71]
wire [31:0] _T_449 = _T_320 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_449 = _T_320 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
@ -489,8 +496,8 @@ module dbg(
wire _T_540 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 346:65] wire _T_540 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 346:65]
wire _T_541 = sbcs_wren & _T_540; // @[dbg.scala 346:38] wire _T_541 = sbcs_wren & _T_540; // @[dbg.scala 346:38]
wire _T_543 = io_dmi_reg_wdata[14:12] == 3'h0; // @[dbg.scala 347:27] wire _T_543 = io_dmi_reg_wdata[14:12] == 3'h0; // @[dbg.scala 347:27]
wire [2:0] _GEN_118 = {{2'd0}, _T_543}; // @[dbg.scala 347:53] wire [2:0] _GEN_116 = {{2'd0}, _T_543}; // @[dbg.scala 347:53]
wire [2:0] _T_545 = _GEN_118 & sbcs_reg[14:12]; // @[dbg.scala 347:53] wire [2:0] _T_545 = _GEN_116 & sbcs_reg[14:12]; // @[dbg.scala 347:53]
wire _T_546 = 4'h1 == sb_state; // @[Conditional.scala 37:30] wire _T_546 = 4'h1 == sb_state; // @[Conditional.scala 37:30]
wire _T_547 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 350:41] wire _T_547 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 350:41]
wire _T_549 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 351:40] wire _T_549 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 351:40]
@ -512,39 +519,39 @@ module dbg(
wire _T_575 = 4'h8 == sb_state; // @[Conditional.scala 37:30] wire _T_575 = 4'h8 == sb_state; // @[Conditional.scala 37:30]
wire _T_576 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 385:39] wire _T_576 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 385:39]
wire _T_578 = 4'h9 == sb_state; // @[Conditional.scala 37:30] wire _T_578 = 4'h9 == sb_state; // @[Conditional.scala 37:30]
wire _GEN_53 = _T_578 & sbcs_reg[16]; // @[Conditional.scala 39:67] wire _GEN_51 = _T_578 & sbcs_reg[16]; // @[Conditional.scala 39:67]
wire _GEN_55 = _T_575 ? _T_576 : _T_578; // @[Conditional.scala 39:67] wire _GEN_53 = _T_575 ? _T_576 : _T_578; // @[Conditional.scala 39:67]
wire _GEN_56 = _T_575 & _T_574; // @[Conditional.scala 39:67] wire _GEN_54 = _T_575 & _T_574; // @[Conditional.scala 39:67]
wire _GEN_58 = _T_575 ? 1'h0 : _T_578; // @[Conditional.scala 39:67] wire _GEN_56 = _T_575 ? 1'h0 : _T_578; // @[Conditional.scala 39:67]
wire _GEN_60 = _T_575 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] wire _GEN_58 = _T_575 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67]
wire _GEN_62 = _T_572 ? _T_573 : _GEN_55; // @[Conditional.scala 39:67] wire _GEN_60 = _T_572 ? _T_573 : _GEN_53; // @[Conditional.scala 39:67]
wire _GEN_63 = _T_572 ? _T_574 : _GEN_56; // @[Conditional.scala 39:67] wire _GEN_61 = _T_572 ? _T_574 : _GEN_54; // @[Conditional.scala 39:67]
wire _GEN_63 = _T_572 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67]
wire _GEN_65 = _T_572 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67] wire _GEN_65 = _T_572 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67]
wire _GEN_67 = _T_572 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] wire _GEN_67 = _T_570 ? _T_571 : _GEN_60; // @[Conditional.scala 39:67]
wire _GEN_69 = _T_570 ? _T_571 : _GEN_62; // @[Conditional.scala 39:67] wire _GEN_68 = _T_570 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67]
wire _GEN_70 = _T_570 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] wire _GEN_70 = _T_570 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
wire _GEN_72 = _T_570 ? 1'h0 : _GEN_65; // @[Conditional.scala 39:67] wire _GEN_72 = _T_570 ? 1'h0 : _GEN_65; // @[Conditional.scala 39:67]
wire _GEN_74 = _T_570 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67] wire _GEN_74 = _T_568 ? _T_569 : _GEN_67; // @[Conditional.scala 39:67]
wire _GEN_76 = _T_568 ? _T_569 : _GEN_69; // @[Conditional.scala 39:67] wire _GEN_75 = _T_568 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67]
wire _GEN_77 = _T_568 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] wire _GEN_77 = _T_568 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67]
wire _GEN_79 = _T_568 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] wire _GEN_79 = _T_568 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
wire _GEN_81 = _T_568 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] wire _GEN_81 = _T_562 ? _T_567 : _GEN_74; // @[Conditional.scala 39:67]
wire _GEN_83 = _T_562 ? _T_567 : _GEN_76; // @[Conditional.scala 39:67] wire _GEN_82 = _T_562 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67]
wire _GEN_84 = _T_562 ? 1'h0 : _GEN_77; // @[Conditional.scala 39:67] wire _GEN_84 = _T_562 ? 1'h0 : _GEN_77; // @[Conditional.scala 39:67]
wire _GEN_86 = _T_562 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] wire _GEN_86 = _T_562 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
wire _GEN_88 = _T_562 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] wire _GEN_88 = _T_560 ? _T_561 : _GEN_81; // @[Conditional.scala 39:67]
wire _GEN_90 = _T_560 ? _T_561 : _GEN_83; // @[Conditional.scala 39:67] wire _GEN_89 = _T_560 ? 1'h0 : _GEN_82; // @[Conditional.scala 39:67]
wire _GEN_91 = _T_560 ? 1'h0 : _GEN_84; // @[Conditional.scala 39:67] wire _GEN_91 = _T_560 ? 1'h0 : _GEN_84; // @[Conditional.scala 39:67]
wire _GEN_93 = _T_560 ? 1'h0 : _GEN_86; // @[Conditional.scala 39:67] wire _GEN_93 = _T_560 ? 1'h0 : _GEN_86; // @[Conditional.scala 39:67]
wire _GEN_95 = _T_560 ? 1'h0 : _GEN_88; // @[Conditional.scala 39:67] wire _GEN_95 = _T_553 ? _T_550 : _GEN_88; // @[Conditional.scala 39:67]
wire _GEN_97 = _T_553 ? _T_550 : _GEN_90; // @[Conditional.scala 39:67] wire _GEN_96 = _T_553 ? _T_547 : _GEN_89; // @[Conditional.scala 39:67]
wire _GEN_98 = _T_553 ? _T_547 : _GEN_91; // @[Conditional.scala 39:67] wire _GEN_98 = _T_553 ? 1'h0 : _GEN_91; // @[Conditional.scala 39:67]
wire _GEN_100 = _T_553 ? 1'h0 : _GEN_93; // @[Conditional.scala 39:67] wire _GEN_100 = _T_553 ? 1'h0 : _GEN_93; // @[Conditional.scala 39:67]
wire _GEN_102 = _T_553 ? 1'h0 : _GEN_95; // @[Conditional.scala 39:67] wire _GEN_102 = _T_546 ? _T_550 : _GEN_95; // @[Conditional.scala 39:67]
wire _GEN_104 = _T_546 ? _T_550 : _GEN_97; // @[Conditional.scala 39:67] wire _GEN_103 = _T_546 ? _T_547 : _GEN_96; // @[Conditional.scala 39:67]
wire _GEN_105 = _T_546 ? _T_547 : _GEN_98; // @[Conditional.scala 39:67] wire _GEN_105 = _T_546 ? 1'h0 : _GEN_98; // @[Conditional.scala 39:67]
wire _GEN_107 = _T_546 ? 1'h0 : _GEN_100; // @[Conditional.scala 39:67] wire _GEN_107 = _T_546 ? 1'h0 : _GEN_100; // @[Conditional.scala 39:67]
wire _GEN_109 = _T_546 ? 1'h0 : _GEN_102; // @[Conditional.scala 39:67]
reg [3:0] _T_582; // @[Reg.scala 27:20] reg [3:0] _T_582; // @[Reg.scala 27:20]
wire _T_589 = |io_sb_axi_r_bits_resp; // @[dbg.scala 406:69] wire _T_589 = |io_sb_axi_r_bits_resp; // @[dbg.scala 406:69]
wire _T_590 = sb_bus_rsp_read & _T_589; // @[dbg.scala 406:39] wire _T_590 = sb_bus_rsp_read & _T_589; // @[dbg.scala 406:39]
@ -569,37 +576,37 @@ module dbg(
wire [63:0] _T_638 = _T_634 & _T_637; // @[dbg.scala 420:119] wire [63:0] _T_638 = _T_634 & _T_637; // @[dbg.scala 420:119]
wire [7:0] _T_643 = _T_66 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_643 = _T_66 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [14:0] _T_645 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 422:82] wire [14:0] _T_645 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 422:82]
wire [14:0] _GEN_119 = {{7'd0}, _T_643}; // @[dbg.scala 422:67] wire [14:0] _GEN_117 = {{7'd0}, _T_643}; // @[dbg.scala 422:67]
wire [14:0] _T_646 = _GEN_119 & _T_645; // @[dbg.scala 422:67] wire [14:0] _T_646 = _GEN_117 & _T_645; // @[dbg.scala 422:67]
wire [7:0] _T_650 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_650 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_652 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] wire [2:0] _T_652 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58]
wire [14:0] _T_653 = 15'h3 << _T_652; // @[dbg.scala 423:59] wire [14:0] _T_653 = 15'h3 << _T_652; // @[dbg.scala 423:59]
wire [14:0] _GEN_120 = {{7'd0}, _T_650}; // @[dbg.scala 423:44] wire [14:0] _GEN_118 = {{7'd0}, _T_650}; // @[dbg.scala 423:44]
wire [14:0] _T_654 = _GEN_120 & _T_653; // @[dbg.scala 423:44] wire [14:0] _T_654 = _GEN_118 & _T_653; // @[dbg.scala 423:44]
wire [14:0] _T_655 = _T_646 | _T_654; // @[dbg.scala 422:107] wire [14:0] _T_655 = _T_646 | _T_654; // @[dbg.scala 422:107]
wire [7:0] _T_659 = _T_55 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_659 = _T_55 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_661 = {sbaddress0_reg[2],1'h0}; // @[Cat.scala 29:58] wire [1:0] _T_661 = {sbaddress0_reg[2],1'h0}; // @[Cat.scala 29:58]
wire [10:0] _T_662 = 11'hf << _T_661; // @[dbg.scala 424:59] wire [10:0] _T_662 = 11'hf << _T_661; // @[dbg.scala 424:59]
wire [10:0] _GEN_121 = {{3'd0}, _T_659}; // @[dbg.scala 424:44] wire [10:0] _GEN_119 = {{3'd0}, _T_659}; // @[dbg.scala 424:44]
wire [10:0] _T_663 = _GEN_121 & _T_662; // @[dbg.scala 424:44] wire [10:0] _T_663 = _GEN_119 & _T_662; // @[dbg.scala 424:44]
wire [14:0] _GEN_122 = {{4'd0}, _T_663}; // @[dbg.scala 423:97] wire [14:0] _GEN_120 = {{4'd0}, _T_663}; // @[dbg.scala 423:97]
wire [14:0] _T_664 = _T_655 | _GEN_122; // @[dbg.scala 423:97] wire [14:0] _T_664 = _T_655 | _GEN_120; // @[dbg.scala 423:97]
wire [7:0] _T_668 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_668 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [14:0] _GEN_123 = {{7'd0}, _T_668}; // @[dbg.scala 424:95] wire [14:0] _GEN_121 = {{7'd0}, _T_668}; // @[dbg.scala 424:95]
wire [14:0] _T_670 = _T_664 | _GEN_123; // @[dbg.scala 424:95] wire [14:0] _T_670 = _T_664 | _GEN_121; // @[dbg.scala 424:95]
wire [3:0] _GEN_124 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99] wire [3:0] _GEN_122 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99]
wire [6:0] _T_681 = 4'h8 * _GEN_124; // @[dbg.scala 441:99] wire [6:0] _T_681 = 4'h8 * _GEN_122; // @[dbg.scala 441:99]
wire [63:0] _T_682 = io_sb_axi_r_bits_data >> _T_681; // @[dbg.scala 441:92] wire [63:0] _T_682 = io_sb_axi_r_bits_data >> _T_681; // @[dbg.scala 441:92]
wire [63:0] _T_683 = _T_682 & 64'hff; // @[dbg.scala 441:123] wire [63:0] _T_683 = _T_682 & 64'hff; // @[dbg.scala 441:123]
wire [63:0] _T_684 = _T_608 & _T_683; // @[dbg.scala 441:59] wire [63:0] _T_684 = _T_608 & _T_683; // @[dbg.scala 441:59]
wire [4:0] _GEN_125 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86] wire [4:0] _GEN_123 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86]
wire [6:0] _T_691 = 5'h10 * _GEN_125; // @[dbg.scala 442:86] wire [6:0] _T_691 = 5'h10 * _GEN_123; // @[dbg.scala 442:86]
wire [63:0] _T_692 = io_sb_axi_r_bits_data >> _T_691; // @[dbg.scala 442:78] wire [63:0] _T_692 = io_sb_axi_r_bits_data >> _T_691; // @[dbg.scala 442:78]
wire [63:0] _T_693 = _T_692 & 64'hffff; // @[dbg.scala 442:110] wire [63:0] _T_693 = _T_692 & 64'hffff; // @[dbg.scala 442:110]
wire [63:0] _T_694 = _T_617 & _T_693; // @[dbg.scala 442:45] wire [63:0] _T_694 = _T_617 & _T_693; // @[dbg.scala 442:45]
wire [63:0] _T_695 = _T_684 | _T_694; // @[dbg.scala 441:140] wire [63:0] _T_695 = _T_684 | _T_694; // @[dbg.scala 441:140]
wire [5:0] _GEN_126 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86] wire [5:0] _GEN_124 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86]
wire [6:0] _T_702 = 6'h20 * _GEN_126; // @[dbg.scala 443:86] wire [6:0] _T_702 = 6'h20 * _GEN_124; // @[dbg.scala 443:86]
wire [63:0] _T_703 = io_sb_axi_r_bits_data >> _T_702; // @[dbg.scala 443:78] wire [63:0] _T_703 = io_sb_axi_r_bits_data >> _T_702; // @[dbg.scala 443:78]
wire [63:0] _T_704 = _T_703 & 64'hffffffff; // @[dbg.scala 443:107] wire [63:0] _T_704 = _T_703 & 64'hffffffff; // @[dbg.scala 443:107]
wire [63:0] _T_705 = _T_626 & _T_704; // @[dbg.scala 443:45] wire [63:0] _T_705 = _T_626 & _T_704; // @[dbg.scala 443:45]
@ -641,10 +648,22 @@ module dbg(
.io_en(rvclkhdr_5_io_en), .io_en(rvclkhdr_5_io_en),
.io_scan_mode(rvclkhdr_5_io_scan_mode) .io_scan_mode(rvclkhdr_5_io_scan_mode)
); );
rvclkhdr rvclkhdr_6 ( // @[lib.scala 352:23]
.io_l1clk(rvclkhdr_6_io_l1clk),
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en),
.io_scan_mode(rvclkhdr_6_io_scan_mode)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 352:23]
.io_l1clk(rvclkhdr_7_io_l1clk),
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en),
.io_scan_mode(rvclkhdr_7_io_scan_mode)
);
assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 329:19] assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 329:19]
assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[dbg.scala 100:21] assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[dbg.scala 100:21]
assign io_dbg_halt_req = _T_328 ? _T_344 : _GEN_38; // @[dbg.scala 261:19 dbg.scala 267:23 dbg.scala 272:23 dbg.scala 283:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 300:23 dbg.scala 305:23] assign io_dbg_halt_req = _T_328 ? _T_344 : _GEN_36; // @[dbg.scala 261:19 dbg.scala 267:23 dbg.scala 272:23 dbg.scala 283:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 300:23 dbg.scala 305:23]
assign io_dbg_resume_req = _T_328 ? 1'h0 : _GEN_41; // @[dbg.scala 262:21 dbg.scala 282:25] assign io_dbg_resume_req = _T_328 ? 1'h0 : _GEN_39; // @[dbg.scala 262:21 dbg.scala 282:25]
assign io_dmi_reg_rdata = _T_502; // @[dbg.scala 320:20] assign io_dmi_reg_rdata = _T_502; // @[dbg.scala 320:20]
assign io_sb_axi_aw_valid = _T_595 | _T_596; // @[dbg.scala 407:22] assign io_sb_axi_aw_valid = _T_595 | _T_596; // @[dbg.scala 407:22]
assign io_sb_axi_aw_bits_id = 1'h0; // @[dbg.scala 409:24] assign io_sb_axi_aw_bits_id = 1'h0; // @[dbg.scala 409:24]
@ -686,22 +705,22 @@ module dbg(
assign io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[dbg.scala 448:39] assign io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[dbg.scala 448:39]
assign io_dbg_dma_io_dbg_dma_bubble = _T_515 | _T_307; // @[dbg.scala 330:32] assign io_dbg_dma_io_dbg_dma_bubble = _T_515 | _T_307; // @[dbg.scala 330:32]
assign dbg_state = _T_499; // @[dbg.scala 315:13] assign dbg_state = _T_499; // @[dbg.scala 315:13]
assign dbg_state_en = _T_328 ? _T_340 : _GEN_37; // @[dbg.scala 258:16 dbg.scala 266:20 dbg.scala 271:20 dbg.scala 278:20 dbg.scala 287:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 304:20] assign dbg_state_en = _T_328 ? _T_340 : _GEN_35; // @[dbg.scala 258:16 dbg.scala 266:20 dbg.scala 271:20 dbg.scala 278:20 dbg.scala 287:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 304:20]
assign sb_state = _T_582; // @[dbg.scala 397:12] assign sb_state = _T_582; // @[dbg.scala 397:12]
assign sb_state_en = _T_535 ? _T_538 : _GEN_104; // @[dbg.scala 343:19 dbg.scala 351:19 dbg.scala 357:19 dbg.scala 363:19 dbg.scala 367:19 dbg.scala 371:19 dbg.scala 375:19 dbg.scala 379:19 dbg.scala 385:19 dbg.scala 391:19] assign sb_state_en = _T_535 ? _T_538 : _GEN_102; // @[dbg.scala 343:19 dbg.scala 351:19 dbg.scala 357:19 dbg.scala 363:19 dbg.scala 367:19 dbg.scala 371:19 dbg.scala 375:19 dbg.scala 379:19 dbg.scala 385:19 dbg.scala 391:19]
assign dmcontrol_reg = {_T_157,_T_155}; // @[dbg.scala 178:17] assign dmcontrol_reg = {_T_157,_T_155}; // @[dbg.scala 178:17]
assign sbaddress0_reg = _T_128; // @[dbg.scala 159:18] assign sbaddress0_reg = _T_128; // @[dbg.scala 159:18]
assign sbcs_sbbusy_wren = _T_535 ? sb_state_en : _GEN_107; // @[dbg.scala 335:20 dbg.scala 344:24 dbg.scala 392:24] assign sbcs_sbbusy_wren = _T_535 ? sb_state_en : _GEN_105; // @[dbg.scala 335:20 dbg.scala 344:24 dbg.scala 392:24]
assign sbcs_sberror_wren = _T_535 ? _T_541 : _GEN_105; // @[dbg.scala 337:21 dbg.scala 346:25 dbg.scala 352:25 dbg.scala 358:25 dbg.scala 380:25 dbg.scala 386:25] assign sbcs_sberror_wren = _T_535 ? _T_541 : _GEN_103; // @[dbg.scala 337:21 dbg.scala 346:25 dbg.scala 352:25 dbg.scala 358:25 dbg.scala 380:25 dbg.scala 386:25]
assign sb_bus_rdata = _T_706 | _T_712; // @[dbg.scala 441:16] assign sb_bus_rdata = _T_706 | _T_712; // @[dbg.scala 441:16]
assign sbaddress0_reg_wren1 = _T_535 ? 1'h0 : _GEN_109; // @[dbg.scala 339:24 dbg.scala 394:28] assign sbaddress0_reg_wren1 = _T_535 ? 1'h0 : _GEN_107; // @[dbg.scala 339:24 dbg.scala 394:28]
assign dmstatus_reg = {_T_177,_T_173}; // @[dbg.scala 184:16] assign dmstatus_reg = {_T_177,_T_173}; // @[dbg.scala 184:16]
assign dmstatus_havereset = _T_210; // @[dbg.scala 201:22] assign dmstatus_havereset = _T_210; // @[dbg.scala 201:22]
assign dmstatus_resumeack = _T_201; // @[dbg.scala 193:22] assign dmstatus_resumeack = _T_201; // @[dbg.scala 193:22]
assign dmstatus_unavail = dmcontrol_reg[1] | _T_194; // @[dbg.scala 191:20] assign dmstatus_unavail = dmcontrol_reg[1] | _T_194; // @[dbg.scala 191:20]
assign dmstatus_running = ~_T_197; // @[dbg.scala 192:20] assign dmstatus_running = ~_T_197; // @[dbg.scala 192:20]
assign dmstatus_halted = _T_206; // @[dbg.scala 197:19] assign dmstatus_halted = _T_206; // @[dbg.scala 197:19]
assign abstractcs_busy_wren = _T_328 ? 1'h0 : _GEN_39; // @[dbg.scala 259:24 dbg.scala 280:28 dbg.scala 298:28] assign abstractcs_busy_wren = _T_328 ? 1'h0 : _GEN_37; // @[dbg.scala 259:24 dbg.scala 280:28 dbg.scala 298:28]
assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 401:19] assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 401:19]
assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 402:25] assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 402:25]
assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 403:25] assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 403:25]
@ -728,9 +747,15 @@ module dbg(
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
assign abstractcs_reg = {_T_289,_T_287}; // @[dbg.scala 233:18] assign abstractcs_reg = {_T_289,_T_287}; // @[dbg.scala 233:18]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_5_io_clk = clock; // @[lib.scala 354:18]
assign rvclkhdr_5_io_en = _T_321 & _T_294; // @[lib.scala 355:17] assign rvclkhdr_5_io_en = _T_235 & _T_294; // @[lib.scala 355:17]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
assign dbg_nxtstate = _T_328 ? _T_331 : _GEN_36; // @[dbg.scala 257:16 dbg.scala 265:20 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 286:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 303:20] assign rvclkhdr_6_io_clk = clock; // @[lib.scala 354:18]
assign rvclkhdr_6_io_en = data0_reg_wren0 | data0_reg_wren1; // @[lib.scala 355:17]
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 354:18]
assign rvclkhdr_7_io_en = _T_321 & _T_294; // @[lib.scala 355:17]
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
assign dbg_nxtstate = _T_328 ? _T_331 : _GEN_34; // @[dbg.scala 257:16 dbg.scala 265:20 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 286:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 303:20]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE `define RANDOMIZE
`endif `endif
@ -1029,21 +1054,21 @@ end // initial
abs_temp_10_8 <= _T_276 | _T_281; abs_temp_10_8 <= _T_276 | _T_281;
end end
end end
always @(posedge clock or posedge _T_30) begin always @(posedge rvclkhdr_5_io_l1clk or posedge _T_30) begin
if (_T_30) begin if (_T_30) begin
command_reg <= 32'h0; command_reg <= 32'h0;
end else if (command_wren) begin end else begin
command_reg <= command_din; command_reg <= {_T_300,_T_298};
end end
end end
always @(posedge clock or posedge _T_30) begin always @(posedge rvclkhdr_6_io_l1clk or posedge _T_30) begin
if (_T_30) begin if (_T_30) begin
data0_reg <= 32'h0; data0_reg <= 32'h0;
end else if (data0_reg_wren) begin end else begin
data0_reg <= data0_din; data0_reg <= _T_313 | _T_316;
end end
end end
always @(posedge rvclkhdr_5_io_l1clk or posedge _T_30) begin always @(posedge rvclkhdr_7_io_l1clk or posedge _T_30) begin
if (_T_30) begin if (_T_30) begin
_T_327 <= 32'h0; _T_327 <= 32'h0;
end else begin end else begin

664
dma_ctrl.fir
View File

@ -1830,7 +1830,7 @@ circuit dma_ctrl :
node _T_987 = add(num_fifo_vld_tmp, num_fifo_vld_tmp2) @[dma_ctrl.scala 295:45] node _T_987 = add(num_fifo_vld_tmp, num_fifo_vld_tmp2) @[dma_ctrl.scala 295:45]
node _T_988 = tail(_T_987, 1) @[dma_ctrl.scala 295:45] node _T_988 = tail(_T_987, 1) @[dma_ctrl.scala 295:45]
num_fifo_vld <= _T_988 @[dma_ctrl.scala 295:25] num_fifo_vld <= _T_988 @[dma_ctrl.scala 295:25]
node fifo_full_spec = geq(num_fifo_vld_tmp2, UInt<3>("h05")) @[dma_ctrl.scala 297:46] node fifo_full_spec = geq(num_fifo_vld, UInt<3>("h05")) @[dma_ctrl.scala 297:41]
node _T_989 = or(fifo_full, dbg_dma_bubble_bus) @[dma_ctrl.scala 299:39] node _T_989 = or(fifo_full, dbg_dma_bubble_bus) @[dma_ctrl.scala 299:39]
node dma_fifo_ready = not(_T_989) @[dma_ctrl.scala 299:27] node dma_fifo_ready = not(_T_989) @[dma_ctrl.scala 299:27]
node _T_990 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 303:38] node _T_990 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 303:38]
@ -1903,230 +1903,250 @@ circuit dma_ctrl :
node _T_1056 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 313:26] node _T_1056 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 313:26]
node _T_1057 = eq(_T_1056, UInt<2>("h03")) @[dma_ctrl.scala 313:32] node _T_1057 = eq(_T_1056, UInt<2>("h03")) @[dma_ctrl.scala 313:32]
node _T_1058 = bits(dma_mem_byteen, 6, 3) @[dma_ctrl.scala 313:59] node _T_1058 = bits(dma_mem_byteen, 6, 3) @[dma_ctrl.scala 313:59]
node _T_1059 = mux(_T_1048, _T_1049, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1059 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 314:26]
node _T_1060 = mux(_T_1051, _T_1052, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1060 = eq(_T_1059, UInt<3>("h04")) @[dma_ctrl.scala 314:32]
node _T_1061 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1061 = bits(dma_mem_byteen, 7, 4) @[dma_ctrl.scala 314:59]
node _T_1062 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1062 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 315:26]
node _T_1063 = or(_T_1059, _T_1060) @[Mux.scala 27:72] node _T_1063 = eq(_T_1062, UInt<3>("h05")) @[dma_ctrl.scala 315:32]
node _T_1064 = or(_T_1063, _T_1061) @[Mux.scala 27:72] node _T_1064 = bits(dma_mem_byteen, 7, 5) @[dma_ctrl.scala 315:59]
node _T_1065 = or(_T_1064, _T_1062) @[Mux.scala 27:72] node _T_1065 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 316:26]
wire _T_1066 : UInt<4> @[Mux.scala 27:72] node _T_1066 = eq(_T_1065, UInt<3>("h06")) @[dma_ctrl.scala 316:32]
_T_1066 <= _T_1065 @[Mux.scala 27:72] node _T_1067 = bits(dma_mem_byteen, 7, 6) @[dma_ctrl.scala 316:59]
node _T_1067 = neq(_T_1066, UInt<4>("h0f")) @[dma_ctrl.scala 313:68] node _T_1068 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 317:26]
node _T_1068 = and(_T_1046, _T_1067) @[dma_ctrl.scala 310:78] node _T_1069 = eq(_T_1068, UInt<3>("h07")) @[dma_ctrl.scala 317:32]
node _T_1069 = or(_T_1043, _T_1068) @[dma_ctrl.scala 309:145] node _T_1070 = bits(dma_mem_byteen, 7, 7) @[dma_ctrl.scala 317:59]
node _T_1070 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 314:62] node _T_1071 = mux(_T_1048, _T_1049, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1071 = eq(_T_1070, UInt<2>("h03")) @[dma_ctrl.scala 314:69] node _T_1072 = mux(_T_1051, _T_1052, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1072 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1071) @[dma_ctrl.scala 314:45] node _T_1073 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1073 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 314:97] node _T_1074 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1074 = eq(_T_1073, UInt<4>("h0f")) @[dma_ctrl.scala 314:103] node _T_1075 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1075 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 314:133] node _T_1076 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1076 = eq(_T_1075, UInt<8>("h0f0")) @[dma_ctrl.scala 314:139] node _T_1077 = mux(_T_1066, _T_1067, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1077 = or(_T_1074, _T_1076) @[dma_ctrl.scala 314:116] node _T_1078 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1078 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 314:169] node _T_1079 = or(_T_1071, _T_1072) @[Mux.scala 27:72]
node _T_1079 = eq(_T_1078, UInt<8>("h0ff")) @[dma_ctrl.scala 314:175] node _T_1080 = or(_T_1079, _T_1073) @[Mux.scala 27:72]
node _T_1080 = or(_T_1077, _T_1079) @[dma_ctrl.scala 314:152] node _T_1081 = or(_T_1080, _T_1074) @[Mux.scala 27:72]
node _T_1081 = eq(_T_1080, UInt<1>("h00")) @[dma_ctrl.scala 314:80] node _T_1082 = or(_T_1081, _T_1075) @[Mux.scala 27:72]
node _T_1082 = and(_T_1072, _T_1081) @[dma_ctrl.scala 314:78] node _T_1083 = or(_T_1082, _T_1076) @[Mux.scala 27:72]
node _T_1083 = or(_T_1069, _T_1082) @[dma_ctrl.scala 313:79] node _T_1084 = or(_T_1083, _T_1077) @[Mux.scala 27:72]
node _T_1084 = and(_T_1010, _T_1083) @[dma_ctrl.scala 304:87] node _T_1085 = or(_T_1084, _T_1078) @[Mux.scala 27:72]
dma_alignment_error <= _T_1084 @[dma_ctrl.scala 304:25] wire _T_1086 : UInt<4> @[Mux.scala 27:72]
node _T_1085 = and(fifo_empty, dbg_dma_bubble_bus) @[dma_ctrl.scala 319:50] _T_1086 <= _T_1085 @[Mux.scala 27:72]
io.dbg_dma_io.dma_dbg_ready <= _T_1085 @[dma_ctrl.scala 319:36] node _T_1087 = neq(_T_1086, UInt<4>("h0f")) @[dma_ctrl.scala 317:66]
node _T_1086 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 320:39] node _T_1088 = and(_T_1046, _T_1087) @[dma_ctrl.scala 310:78]
node _T_1087 = bits(_T_1086, 0, 0) @[dma_ctrl.scala 320:39] node _T_1089 = or(_T_1043, _T_1088) @[dma_ctrl.scala 309:145]
node _T_1088 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 320:58] node _T_1090 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 318:62]
node _T_1089 = bits(_T_1088, 0, 0) @[dma_ctrl.scala 320:58] node _T_1091 = eq(_T_1090, UInt<2>("h03")) @[dma_ctrl.scala 318:69]
node _T_1090 = and(_T_1087, _T_1089) @[dma_ctrl.scala 320:48] node _T_1092 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1091) @[dma_ctrl.scala 318:45]
node _T_1091 = dshr(fifo_done, RspPtr) @[dma_ctrl.scala 320:78] node _T_1093 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 318:97]
node _T_1092 = bits(_T_1091, 0, 0) @[dma_ctrl.scala 320:78] node _T_1094 = eq(_T_1093, UInt<4>("h0f")) @[dma_ctrl.scala 318:103]
node _T_1093 = and(_T_1090, _T_1092) @[dma_ctrl.scala 320:67] node _T_1095 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 318:133]
io.dma_dbg_cmd_done <= _T_1093 @[dma_ctrl.scala 320:25] node _T_1096 = eq(_T_1095, UInt<8>("h0f0")) @[dma_ctrl.scala 318:139]
node _T_1094 = bits(fifo_addr[RspPtr], 2, 2) @[dma_ctrl.scala 321:49] node _T_1097 = or(_T_1094, _T_1096) @[dma_ctrl.scala 318:116]
node _T_1095 = bits(fifo_data[RspPtr], 63, 32) @[dma_ctrl.scala 321:71] node _T_1098 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 318:169]
node _T_1096 = bits(fifo_data[RspPtr], 31, 0) @[dma_ctrl.scala 321:98] node _T_1099 = eq(_T_1098, UInt<8>("h0ff")) @[dma_ctrl.scala 318:175]
node _T_1097 = mux(_T_1094, _T_1095, _T_1096) @[dma_ctrl.scala 321:31] node _T_1100 = or(_T_1097, _T_1099) @[dma_ctrl.scala 318:152]
io.dma_dbg_rddata <= _T_1097 @[dma_ctrl.scala 321:25] node _T_1101 = eq(_T_1100, UInt<1>("h00")) @[dma_ctrl.scala 318:80]
node _T_1098 = orr(fifo_error[RspPtr]) @[dma_ctrl.scala 322:47] node _T_1102 = and(_T_1092, _T_1101) @[dma_ctrl.scala 318:78]
io.dma_dbg_cmd_fail <= _T_1098 @[dma_ctrl.scala 322:25] node _T_1103 = or(_T_1089, _T_1102) @[dma_ctrl.scala 317:79]
node _T_1099 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 324:38] node _T_1104 = and(_T_1010, _T_1103) @[dma_ctrl.scala 304:87]
node _T_1100 = bits(_T_1099, 0, 0) @[dma_ctrl.scala 324:38] dma_alignment_error <= _T_1104 @[dma_ctrl.scala 304:25]
node _T_1101 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 324:58] node _T_1105 = and(fifo_empty, dbg_dma_bubble_bus) @[dma_ctrl.scala 323:50]
node _T_1102 = bits(_T_1101, 0, 0) @[dma_ctrl.scala 324:58] io.dbg_dma_io.dma_dbg_ready <= _T_1105 @[dma_ctrl.scala 323:36]
node _T_1103 = eq(_T_1102, UInt<1>("h00")) @[dma_ctrl.scala 324:48] node _T_1106 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 324:39]
node _T_1104 = and(_T_1100, _T_1103) @[dma_ctrl.scala 324:46] node _T_1107 = bits(_T_1106, 0, 0) @[dma_ctrl.scala 324:39]
node _T_1105 = dshr(fifo_dbg, RdPtr) @[dma_ctrl.scala 324:76] node _T_1108 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 324:58]
node _T_1106 = bits(_T_1105, 0, 0) @[dma_ctrl.scala 324:76] node _T_1109 = bits(_T_1108, 0, 0) @[dma_ctrl.scala 324:58]
node _T_1107 = and(_T_1104, _T_1106) @[dma_ctrl.scala 324:66] node _T_1110 = and(_T_1107, _T_1109) @[dma_ctrl.scala 324:48]
node _T_1108 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[dma_ctrl.scala 324:111] node _T_1111 = dshr(fifo_done, RspPtr) @[dma_ctrl.scala 324:78]
node _T_1109 = or(_T_1108, dma_mem_addr_in_pic) @[dma_ctrl.scala 324:134] node _T_1112 = bits(_T_1111, 0, 0) @[dma_ctrl.scala 324:78]
node _T_1110 = not(_T_1109) @[dma_ctrl.scala 324:88] node _T_1113 = and(_T_1110, _T_1112) @[dma_ctrl.scala 324:67]
node _T_1111 = bits(_T_1110, 0, 0) @[dma_ctrl.scala 324:164] io.dma_dbg_cmd_done <= _T_1113 @[dma_ctrl.scala 324:25]
node _T_1112 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 324:184] node _T_1114 = bits(fifo_addr[RspPtr], 2, 2) @[dma_ctrl.scala 325:49]
node _T_1113 = neq(_T_1112, UInt<2>("h02")) @[dma_ctrl.scala 324:191] node _T_1115 = bits(fifo_data[RspPtr], 63, 32) @[dma_ctrl.scala 325:71]
node _T_1114 = or(_T_1111, _T_1113) @[dma_ctrl.scala 324:167] node _T_1116 = bits(fifo_data[RspPtr], 31, 0) @[dma_ctrl.scala 325:98]
node _T_1115 = and(_T_1107, _T_1114) @[dma_ctrl.scala 324:84] node _T_1117 = mux(_T_1114, _T_1115, _T_1116) @[dma_ctrl.scala 325:31]
dma_dbg_cmd_error <= _T_1115 @[dma_ctrl.scala 324:25] io.dma_dbg_rddata <= _T_1117 @[dma_ctrl.scala 325:25]
node _T_1116 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 328:80] node _T_1118 = orr(fifo_error[RspPtr]) @[dma_ctrl.scala 326:47]
node _T_1117 = and(dma_mem_req, _T_1116) @[dma_ctrl.scala 328:56] io.dma_dbg_cmd_fail <= _T_1118 @[dma_ctrl.scala 326:25]
node _T_1118 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 328:121] node _T_1119 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 328:38]
node _T_1119 = and(_T_1117, _T_1118) @[dma_ctrl.scala 328:103] node _T_1120 = bits(_T_1119, 0, 0) @[dma_ctrl.scala 328:38]
io.dec_dma.tlu_dma.dma_dccm_stall_any <= _T_1119 @[dma_ctrl.scala 328:41] node _T_1121 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 328:58]
node _T_1120 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 329:56] node _T_1122 = bits(_T_1121, 0, 0) @[dma_ctrl.scala 328:58]
node _T_1121 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 329:97] node _T_1123 = eq(_T_1122, UInt<1>("h00")) @[dma_ctrl.scala 328:48]
node _T_1122 = and(_T_1120, _T_1121) @[dma_ctrl.scala 329:79] node _T_1124 = and(_T_1120, _T_1123) @[dma_ctrl.scala 328:46]
io.ifu_dma.dma_ifc.dma_iccm_stall_any <= _T_1122 @[dma_ctrl.scala 329:41] node _T_1125 = dshr(fifo_dbg, RdPtr) @[dma_ctrl.scala 328:76]
io.dec_dma.tlu_dma.dma_iccm_stall_any <= io.ifu_dma.dma_ifc.dma_iccm_stall_any @[dma_ctrl.scala 330:41] node _T_1126 = bits(_T_1125, 0, 0) @[dma_ctrl.scala 328:76]
io.dec_dma.dctl_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dma_ctrl.scala 331:42] node _T_1127 = and(_T_1124, _T_1126) @[dma_ctrl.scala 328:66]
node _T_1123 = orr(fifo_valid) @[dma_ctrl.scala 334:30] node _T_1128 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[dma_ctrl.scala 328:111]
node _T_1124 = not(_T_1123) @[dma_ctrl.scala 334:17] node _T_1129 = or(_T_1128, dma_mem_addr_in_pic) @[dma_ctrl.scala 328:134]
fifo_empty <= _T_1124 @[dma_ctrl.scala 334:14] node _T_1130 = not(_T_1129) @[dma_ctrl.scala 328:88]
dma_nack_count_csr <= io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[dma_ctrl.scala 338:22] node _T_1131 = bits(_T_1130, 0, 0) @[dma_ctrl.scala 328:164]
node _T_1125 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 339:45] node _T_1132 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 328:184]
node _T_1126 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 339:115] node _T_1133 = neq(_T_1132, UInt<2>("h02")) @[dma_ctrl.scala 328:191]
node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[dma_ctrl.scala 339:77] node _T_1134 = or(_T_1131, _T_1133) @[dma_ctrl.scala 328:167]
node _T_1128 = bits(_T_1127, 0, 0) @[Bitwise.scala 72:15] node _T_1135 = and(_T_1127, _T_1134) @[dma_ctrl.scala 328:84]
node _T_1129 = mux(_T_1128, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] dma_dbg_cmd_error <= _T_1135 @[dma_ctrl.scala 328:25]
node _T_1130 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 339:171] node _T_1136 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 332:80]
node _T_1131 = and(_T_1129, _T_1130) @[dma_ctrl.scala 339:155] node _T_1137 = and(dma_mem_req, _T_1136) @[dma_ctrl.scala 332:56]
node _T_1132 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 339:196] node _T_1138 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 332:121]
node _T_1133 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 339:243] node _T_1139 = and(_T_1137, _T_1138) @[dma_ctrl.scala 332:103]
node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dma_ctrl.scala 339:205] io.dec_dma.tlu_dma.dma_dccm_stall_any <= _T_1139 @[dma_ctrl.scala 332:41]
node _T_1135 = and(_T_1132, _T_1134) @[dma_ctrl.scala 339:203] node _T_1140 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 333:56]
node _T_1136 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 339:298] node _T_1141 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 333:97]
node _T_1137 = add(_T_1136, UInt<1>("h01")) @[dma_ctrl.scala 339:304] node _T_1142 = and(_T_1140, _T_1141) @[dma_ctrl.scala 333:79]
node _T_1138 = tail(_T_1137, 1) @[dma_ctrl.scala 339:304] io.ifu_dma.dma_ifc.dma_iccm_stall_any <= _T_1142 @[dma_ctrl.scala 333:41]
node _T_1139 = mux(_T_1135, _T_1138, UInt<1>("h00")) @[dma_ctrl.scala 339:182] io.dec_dma.tlu_dma.dma_iccm_stall_any <= io.ifu_dma.dma_ifc.dma_iccm_stall_any @[dma_ctrl.scala 334:41]
node dma_nack_count_d = mux(_T_1125, _T_1131, _T_1139) @[dma_ctrl.scala 339:29] io.dec_dma.dctl_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dma_ctrl.scala 335:42]
node _T_1140 = bits(dma_nack_count_d, 2, 0) @[dma_ctrl.scala 342:31] node _T_1143 = orr(fifo_valid) @[dma_ctrl.scala 338:30]
node _T_1141 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 342:55] node _T_1144 = not(_T_1143) @[dma_ctrl.scala 338:17]
reg _T_1142 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] fifo_empty <= _T_1144 @[dma_ctrl.scala 338:14]
when _T_1141 : @[Reg.scala 28:19] dma_nack_count_csr <= io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[dma_ctrl.scala 342:22]
_T_1142 <= _T_1140 @[Reg.scala 28:23] node _T_1145 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 343:45]
node _T_1146 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 343:115]
node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dma_ctrl.scala 343:77]
node _T_1148 = bits(_T_1147, 0, 0) @[Bitwise.scala 72:15]
node _T_1149 = mux(_T_1148, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_1150 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 343:171]
node _T_1151 = and(_T_1149, _T_1150) @[dma_ctrl.scala 343:155]
node _T_1152 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 343:196]
node _T_1153 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 343:243]
node _T_1154 = eq(_T_1153, UInt<1>("h00")) @[dma_ctrl.scala 343:205]
node _T_1155 = and(_T_1152, _T_1154) @[dma_ctrl.scala 343:203]
node _T_1156 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 343:298]
node _T_1157 = add(_T_1156, UInt<1>("h01")) @[dma_ctrl.scala 343:304]
node _T_1158 = tail(_T_1157, 1) @[dma_ctrl.scala 343:304]
node _T_1159 = mux(_T_1155, _T_1158, UInt<1>("h00")) @[dma_ctrl.scala 343:182]
node dma_nack_count_d = mux(_T_1145, _T_1151, _T_1159) @[dma_ctrl.scala 343:29]
node _T_1160 = bits(dma_nack_count_d, 2, 0) @[dma_ctrl.scala 346:31]
node _T_1161 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 346:55]
reg _T_1162 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1161 : @[Reg.scala 28:19]
_T_1162 <= _T_1160 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
dma_nack_count <= _T_1142 @[dma_ctrl.scala 341:22] dma_nack_count <= _T_1162 @[dma_ctrl.scala 345:22]
node _T_1143 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 347:33] node _T_1163 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 351:33]
node _T_1144 = bits(_T_1143, 0, 0) @[dma_ctrl.scala 347:33] node _T_1164 = bits(_T_1163, 0, 0) @[dma_ctrl.scala 351:33]
node _T_1145 = dshr(fifo_rpend, RdPtr) @[dma_ctrl.scala 347:54] node _T_1165 = dshr(fifo_rpend, RdPtr) @[dma_ctrl.scala 351:54]
node _T_1146 = bits(_T_1145, 0, 0) @[dma_ctrl.scala 347:54] node _T_1166 = bits(_T_1165, 0, 0) @[dma_ctrl.scala 351:54]
node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dma_ctrl.scala 347:43] node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dma_ctrl.scala 351:43]
node _T_1148 = and(_T_1144, _T_1147) @[dma_ctrl.scala 347:41] node _T_1168 = and(_T_1164, _T_1167) @[dma_ctrl.scala 351:41]
node _T_1149 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 347:74] node _T_1169 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 351:74]
node _T_1150 = bits(_T_1149, 0, 0) @[dma_ctrl.scala 347:74] node _T_1170 = bits(_T_1169, 0, 0) @[dma_ctrl.scala 351:74]
node _T_1151 = eq(_T_1150, UInt<1>("h00")) @[dma_ctrl.scala 347:64] node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[dma_ctrl.scala 351:64]
node _T_1152 = and(_T_1148, _T_1151) @[dma_ctrl.scala 347:62] node _T_1172 = and(_T_1168, _T_1171) @[dma_ctrl.scala 351:62]
node _T_1153 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 347:104] node _T_1173 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 351:104]
node _T_1154 = or(_T_1153, dma_dbg_cmd_error) @[dma_ctrl.scala 347:126] node _T_1174 = or(_T_1173, dma_dbg_cmd_error) @[dma_ctrl.scala 351:126]
node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[dma_ctrl.scala 347:84] node _T_1175 = eq(_T_1174, UInt<1>("h00")) @[dma_ctrl.scala 351:84]
node _T_1156 = and(_T_1152, _T_1155) @[dma_ctrl.scala 347:82] node _T_1176 = and(_T_1172, _T_1175) @[dma_ctrl.scala 351:82]
dma_mem_req <= _T_1156 @[dma_ctrl.scala 347:20] dma_mem_req <= _T_1176 @[dma_ctrl.scala 351:20]
node _T_1157 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 348:79] node _T_1177 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 352:79]
node _T_1158 = and(dma_mem_req, _T_1157) @[dma_ctrl.scala 348:55] node _T_1178 = and(dma_mem_req, _T_1177) @[dma_ctrl.scala 352:55]
node _T_1159 = and(_T_1158, io.lsu_dma.dccm_ready) @[dma_ctrl.scala 348:102] node _T_1179 = and(_T_1178, io.lsu_dma.dccm_ready) @[dma_ctrl.scala 352:102]
io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= _T_1159 @[dma_ctrl.scala 348:40] io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= _T_1179 @[dma_ctrl.scala 352:40]
node _T_1160 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 349:55] node _T_1180 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 353:55]
node _T_1161 = and(_T_1160, io.iccm_ready) @[dma_ctrl.scala 349:78] node _T_1181 = and(_T_1180, io.iccm_ready) @[dma_ctrl.scala 353:78]
io.ifu_dma.dma_mem_ctl.dma_iccm_req <= _T_1161 @[dma_ctrl.scala 349:40] io.ifu_dma.dma_mem_ctl.dma_iccm_req <= _T_1181 @[dma_ctrl.scala 353:40]
io.lsu_dma.dma_mem_tag <= RdPtr @[dma_ctrl.scala 350:28] io.lsu_dma.dma_mem_tag <= RdPtr @[dma_ctrl.scala 354:28]
dma_mem_addr_int <= fifo_addr[RdPtr] @[dma_ctrl.scala 351:20] dma_mem_addr_int <= fifo_addr[RdPtr] @[dma_ctrl.scala 355:20]
dma_mem_sz_int <= fifo_sz[RdPtr] @[dma_ctrl.scala 352:20] dma_mem_sz_int <= fifo_sz[RdPtr] @[dma_ctrl.scala 356:20]
node _T_1162 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 353:101] node _T_1182 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 357:101]
node _T_1163 = eq(_T_1162, UInt<8>("h0f0")) @[dma_ctrl.scala 353:107] node _T_1183 = eq(_T_1182, UInt<8>("h0f0")) @[dma_ctrl.scala 357:107]
node _T_1164 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1163) @[dma_ctrl.scala 353:84] node _T_1184 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1183) @[dma_ctrl.scala 357:84]
node _T_1165 = bits(dma_mem_addr_int, 31, 3) @[dma_ctrl.scala 353:141] node _T_1185 = bits(dma_mem_addr_int, 31, 3) @[dma_ctrl.scala 357:141]
node _T_1166 = bits(dma_mem_addr_int, 1, 0) @[dma_ctrl.scala 353:171] node _T_1186 = bits(dma_mem_addr_int, 1, 0) @[dma_ctrl.scala 357:171]
node _T_1167 = cat(_T_1165, UInt<1>("h01")) @[Cat.scala 29:58] node _T_1187 = cat(_T_1185, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_1168 = cat(_T_1167, _T_1166) @[Cat.scala 29:58] node _T_1188 = cat(_T_1187, _T_1186) @[Cat.scala 29:58]
node _T_1169 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 353:196] node _T_1189 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 357:196]
node _T_1170 = mux(_T_1164, _T_1168, _T_1169) @[dma_ctrl.scala 353:46] node _T_1190 = mux(_T_1184, _T_1188, _T_1189) @[dma_ctrl.scala 357:46]
io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= _T_1170 @[dma_ctrl.scala 353:40] io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= _T_1190 @[dma_ctrl.scala 357:40]
node _T_1171 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 354:102] node _T_1191 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 358:102]
node _T_1172 = eq(_T_1171, UInt<4>("h0f")) @[dma_ctrl.scala 354:108] node _T_1192 = eq(_T_1191, UInt<4>("h0f")) @[dma_ctrl.scala 358:108]
node _T_1173 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 354:138] node _T_1193 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 358:138]
node _T_1174 = eq(_T_1173, UInt<8>("h0f0")) @[dma_ctrl.scala 354:144] node _T_1194 = eq(_T_1193, UInt<8>("h0f0")) @[dma_ctrl.scala 358:144]
node _T_1175 = or(_T_1172, _T_1174) @[dma_ctrl.scala 354:121] node _T_1195 = or(_T_1192, _T_1194) @[dma_ctrl.scala 358:121]
node _T_1176 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1175) @[dma_ctrl.scala 354:84] node _T_1196 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1195) @[dma_ctrl.scala 358:84]
node _T_1177 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 354:178] node _T_1197 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 358:178]
node _T_1178 = mux(_T_1176, UInt<2>("h02"), _T_1177) @[dma_ctrl.scala 354:46] node _T_1198 = mux(_T_1196, UInt<2>("h02"), _T_1197) @[dma_ctrl.scala 358:46]
io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= _T_1178 @[dma_ctrl.scala 354:40] io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= _T_1198 @[dma_ctrl.scala 358:40]
dma_mem_byteen <= fifo_byteen[RdPtr] @[dma_ctrl.scala 355:20] dma_mem_byteen <= fifo_byteen[RdPtr] @[dma_ctrl.scala 359:20]
node _T_1179 = dshr(fifo_write, RdPtr) @[dma_ctrl.scala 356:53] node _T_1199 = dshr(fifo_write, RdPtr) @[dma_ctrl.scala 360:53]
node _T_1180 = bits(_T_1179, 0, 0) @[dma_ctrl.scala 356:53] node _T_1200 = bits(_T_1199, 0, 0) @[dma_ctrl.scala 360:53]
io.lsu_dma.dma_lsc_ctl.dma_mem_write <= _T_1180 @[dma_ctrl.scala 356:40] io.lsu_dma.dma_lsc_ctl.dma_mem_write <= _T_1200 @[dma_ctrl.scala 360:40]
io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= fifo_data[RdPtr] @[dma_ctrl.scala 357:40] io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= fifo_data[RdPtr] @[dma_ctrl.scala 361:40]
node _T_1181 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 361:83] node _T_1201 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 365:83]
node _T_1182 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, _T_1181) @[dma_ctrl.scala 361:81] node _T_1202 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, _T_1201) @[dma_ctrl.scala 365:81]
io.dec_dma.tlu_dma.dma_pmu_dccm_read <= _T_1182 @[dma_ctrl.scala 361:42] io.dec_dma.tlu_dma.dma_pmu_dccm_read <= _T_1202 @[dma_ctrl.scala 365:42]
node _T_1183 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 362:81] node _T_1203 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 366:81]
io.dec_dma.tlu_dma.dma_pmu_dccm_write <= _T_1183 @[dma_ctrl.scala 362:42] io.dec_dma.tlu_dma.dma_pmu_dccm_write <= _T_1203 @[dma_ctrl.scala 366:42]
node _T_1184 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 363:82] node _T_1204 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 367:82]
node _T_1185 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 363:123] node _T_1205 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 367:123]
node _T_1186 = and(_T_1184, _T_1185) @[dma_ctrl.scala 363:121] node _T_1206 = and(_T_1204, _T_1205) @[dma_ctrl.scala 367:121]
io.dec_dma.tlu_dma.dma_pmu_any_read <= _T_1186 @[dma_ctrl.scala 363:42] io.dec_dma.tlu_dma.dma_pmu_any_read <= _T_1206 @[dma_ctrl.scala 367:42]
node _T_1187 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 364:82] node _T_1207 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 368:82]
node _T_1188 = and(_T_1187, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 364:121] node _T_1208 = and(_T_1207, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 368:121]
io.dec_dma.tlu_dma.dma_pmu_any_write <= _T_1188 @[dma_ctrl.scala 364:42] io.dec_dma.tlu_dma.dma_pmu_any_write <= _T_1208 @[dma_ctrl.scala 368:42]
reg _T_1189 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 369:12] reg _T_1209 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 373:12]
_T_1189 <= fifo_full_spec @[dma_ctrl.scala 369:12] _T_1209 <= fifo_full_spec @[dma_ctrl.scala 373:12]
fifo_full <= _T_1189 @[dma_ctrl.scala 368:22] fifo_full <= _T_1209 @[dma_ctrl.scala 372:22]
reg _T_1190 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 373:12] reg _T_1210 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 377:12]
_T_1190 <= io.dbg_dma_io.dbg_dma_bubble @[dma_ctrl.scala 373:12] _T_1210 <= io.dbg_dma_io.dbg_dma_bubble @[dma_ctrl.scala 377:12]
dbg_dma_bubble_bus <= _T_1190 @[dma_ctrl.scala 372:22] dbg_dma_bubble_bus <= _T_1210 @[dma_ctrl.scala 376:22]
reg _T_1191 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 377:12] reg _T_1211 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 381:12]
_T_1191 <= io.dma_dbg_cmd_done @[dma_ctrl.scala 377:12] _T_1211 <= io.dma_dbg_cmd_done @[dma_ctrl.scala 381:12]
dma_dbg_cmd_done_q <= _T_1191 @[dma_ctrl.scala 376:22] dma_dbg_cmd_done_q <= _T_1211 @[dma_ctrl.scala 380:22]
node _T_1192 = and(bus_cmd_valid, io.dma_bus_clk_en) @[dma_ctrl.scala 382:44] node _T_1212 = and(bus_cmd_valid, io.dma_bus_clk_en) @[dma_ctrl.scala 386:44]
node _T_1193 = or(_T_1192, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 382:65] node _T_1213 = or(_T_1212, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 386:65]
node dma_buffer_c1_clken = or(_T_1193, io.clk_override) @[dma_ctrl.scala 382:99] node dma_buffer_c1_clken = or(_T_1213, io.clk_override) @[dma_ctrl.scala 386:99]
node _T_1194 = or(bus_cmd_valid, bus_rsp_valid) @[dma_ctrl.scala 383:44] node _T_1214 = or(bus_cmd_valid, bus_rsp_valid) @[dma_ctrl.scala 387:44]
node _T_1195 = or(_T_1194, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 383:60] node _T_1215 = or(_T_1214, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 387:60]
node _T_1196 = or(_T_1195, io.dma_dbg_cmd_done) @[dma_ctrl.scala 383:94] node _T_1216 = or(_T_1215, io.dma_dbg_cmd_done) @[dma_ctrl.scala 387:94]
node _T_1197 = or(_T_1196, dma_dbg_cmd_done_q) @[dma_ctrl.scala 383:116] node _T_1217 = or(_T_1216, dma_dbg_cmd_done_q) @[dma_ctrl.scala 387:116]
node _T_1198 = orr(fifo_valid) @[dma_ctrl.scala 383:151] node _T_1218 = orr(fifo_valid) @[dma_ctrl.scala 387:151]
node _T_1199 = or(_T_1197, _T_1198) @[dma_ctrl.scala 383:137] node _T_1219 = or(_T_1217, _T_1218) @[dma_ctrl.scala 387:137]
node dma_free_clken = or(_T_1199, io.clk_override) @[dma_ctrl.scala 383:156] node dma_free_clken = or(_T_1219, io.clk_override) @[dma_ctrl.scala 387:156]
inst dma_buffer_c1cgc of rvclkhdr_10 @[dma_ctrl.scala 385:32] inst dma_buffer_c1cgc of rvclkhdr_10 @[dma_ctrl.scala 389:32]
dma_buffer_c1cgc.clock <= clock dma_buffer_c1cgc.clock <= clock
dma_buffer_c1cgc.reset <= reset dma_buffer_c1cgc.reset <= reset
dma_buffer_c1cgc.io.en <= dma_buffer_c1_clken @[dma_ctrl.scala 386:33] dma_buffer_c1cgc.io.en <= dma_buffer_c1_clken @[dma_ctrl.scala 390:33]
dma_buffer_c1cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 387:33] dma_buffer_c1cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 391:33]
dma_buffer_c1cgc.io.clk <= clock @[dma_ctrl.scala 388:33] dma_buffer_c1cgc.io.clk <= clock @[dma_ctrl.scala 392:33]
dma_buffer_c1_clk <= dma_buffer_c1cgc.io.l1clk @[dma_ctrl.scala 389:33] dma_buffer_c1_clk <= dma_buffer_c1cgc.io.l1clk @[dma_ctrl.scala 393:33]
inst dma_free_cgc of rvclkhdr_11 @[dma_ctrl.scala 391:28] inst dma_free_cgc of rvclkhdr_11 @[dma_ctrl.scala 395:28]
dma_free_cgc.clock <= clock dma_free_cgc.clock <= clock
dma_free_cgc.reset <= reset dma_free_cgc.reset <= reset
dma_free_cgc.io.en <= dma_free_clken @[dma_ctrl.scala 392:29] dma_free_cgc.io.en <= dma_free_clken @[dma_ctrl.scala 396:29]
dma_free_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 393:29] dma_free_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 397:29]
dma_free_cgc.io.clk <= clock @[dma_ctrl.scala 394:29] dma_free_cgc.io.clk <= clock @[dma_ctrl.scala 398:29]
dma_free_clk <= dma_free_cgc.io.l1clk @[dma_ctrl.scala 395:29] dma_free_clk <= dma_free_cgc.io.l1clk @[dma_ctrl.scala 399:29]
inst dma_bus_cgc of rvclkhdr_12 @[dma_ctrl.scala 397:27] inst dma_bus_cgc of rvclkhdr_12 @[dma_ctrl.scala 401:27]
dma_bus_cgc.clock <= clock dma_bus_cgc.clock <= clock
dma_bus_cgc.reset <= reset dma_bus_cgc.reset <= reset
dma_bus_cgc.io.en <= io.dma_bus_clk_en @[dma_ctrl.scala 398:28] dma_bus_cgc.io.en <= io.dma_bus_clk_en @[dma_ctrl.scala 402:28]
dma_bus_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 399:28] dma_bus_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 403:28]
dma_bus_cgc.io.clk <= clock @[dma_ctrl.scala 400:28] dma_bus_cgc.io.clk <= clock @[dma_ctrl.scala 404:28]
dma_bus_clk <= dma_bus_cgc.io.l1clk @[dma_ctrl.scala 401:28] dma_bus_clk <= dma_bus_cgc.io.l1clk @[dma_ctrl.scala 405:28]
node wrbuf_en = and(io.dma_axi.aw.valid, io.dma_axi.aw.ready) @[dma_ctrl.scala 405:47] node wrbuf_en = and(io.dma_axi.aw.valid, io.dma_axi.aw.ready) @[dma_ctrl.scala 409:47]
node wrbuf_data_en = and(io.dma_axi.w.valid, io.dma_axi.w.ready) @[dma_ctrl.scala 406:46] node wrbuf_data_en = and(io.dma_axi.w.valid, io.dma_axi.w.ready) @[dma_ctrl.scala 410:46]
node wrbuf_cmd_sent = and(axi_mstr_prty_en, bus_cmd_write) @[dma_ctrl.scala 407:40] node wrbuf_cmd_sent = and(axi_mstr_prty_en, bus_cmd_write) @[dma_ctrl.scala 411:40]
node _T_1200 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 408:42] node _T_1220 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 412:42]
node _T_1201 = eq(wrbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 408:51] node _T_1221 = eq(wrbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 412:51]
node wrbuf_rst = and(_T_1200, _T_1201) @[dma_ctrl.scala 408:49] node wrbuf_rst = and(_T_1220, _T_1221) @[dma_ctrl.scala 412:49]
node _T_1202 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 409:42] node _T_1222 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 413:42]
node _T_1203 = eq(wrbuf_data_en, UInt<1>("h00")) @[dma_ctrl.scala 409:51] node _T_1223 = eq(wrbuf_data_en, UInt<1>("h00")) @[dma_ctrl.scala 413:51]
node wrbuf_data_rst = and(_T_1202, _T_1203) @[dma_ctrl.scala 409:49] node wrbuf_data_rst = and(_T_1222, _T_1223) @[dma_ctrl.scala 413:49]
node _T_1204 = mux(wrbuf_en, UInt<1>("h01"), wrbuf_vld) @[dma_ctrl.scala 411:63] node _T_1224 = mux(wrbuf_en, UInt<1>("h01"), wrbuf_vld) @[dma_ctrl.scala 415:63]
node _T_1205 = eq(wrbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 411:92] node _T_1225 = eq(wrbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 415:92]
node _T_1206 = and(_T_1204, _T_1205) @[dma_ctrl.scala 411:90] node _T_1226 = and(_T_1224, _T_1225) @[dma_ctrl.scala 415:90]
reg _T_1207 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 411:59] reg _T_1227 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 415:59]
_T_1207 <= _T_1206 @[dma_ctrl.scala 411:59] _T_1227 <= _T_1226 @[dma_ctrl.scala 415:59]
wrbuf_vld <= _T_1207 @[dma_ctrl.scala 411:25] wrbuf_vld <= _T_1227 @[dma_ctrl.scala 415:25]
node _T_1208 = mux(wrbuf_data_en, UInt<1>("h01"), wrbuf_data_vld) @[dma_ctrl.scala 413:63] node _T_1228 = mux(wrbuf_data_en, UInt<1>("h01"), wrbuf_data_vld) @[dma_ctrl.scala 417:63]
node _T_1209 = eq(wrbuf_data_rst, UInt<1>("h00")) @[dma_ctrl.scala 413:102] node _T_1229 = eq(wrbuf_data_rst, UInt<1>("h00")) @[dma_ctrl.scala 417:102]
node _T_1210 = and(_T_1208, _T_1209) @[dma_ctrl.scala 413:100] node _T_1230 = and(_T_1228, _T_1229) @[dma_ctrl.scala 417:100]
reg _T_1211 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 413:59] reg _T_1231 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 417:59]
_T_1211 <= _T_1210 @[dma_ctrl.scala 413:59] _T_1231 <= _T_1230 @[dma_ctrl.scala 417:59]
wrbuf_data_vld <= _T_1211 @[dma_ctrl.scala 413:25] wrbuf_data_vld <= _T_1231 @[dma_ctrl.scala 417:25]
reg wrbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg wrbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when wrbuf_en : @[Reg.scala 28:19] when wrbuf_en : @[Reg.scala 28:19]
wrbuf_tag <= io.dma_axi.aw.bits.id @[Reg.scala 28:23] wrbuf_tag <= io.dma_axi.aw.bits.id @[Reg.scala 28:23]
@ -2135,21 +2155,21 @@ circuit dma_ctrl :
when wrbuf_en : @[Reg.scala 28:19] when wrbuf_en : @[Reg.scala 28:19]
wrbuf_sz <= io.dma_axi.aw.bits.size @[Reg.scala 28:23] wrbuf_sz <= io.dma_axi.aw.bits.size @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_1212 = and(wrbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 423:68] node _T_1232 = and(wrbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 427:68]
inst rvclkhdr_10 of rvclkhdr_13 @[lib.scala 352:23] inst rvclkhdr_10 of rvclkhdr_13 @[lib.scala 352:23]
rvclkhdr_10.clock <= clock rvclkhdr_10.clock <= clock
rvclkhdr_10.reset <= reset rvclkhdr_10.reset <= reset
rvclkhdr_10.io.clk <= clock @[lib.scala 354:18] rvclkhdr_10.io.clk <= clock @[lib.scala 354:18]
rvclkhdr_10.io.en <= _T_1212 @[lib.scala 355:17] rvclkhdr_10.io.en <= _T_1232 @[lib.scala 355:17]
rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 356:24] rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
reg wrbuf_addr : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] reg wrbuf_addr : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
wrbuf_addr <= io.dma_axi.aw.bits.addr @[lib.scala 358:16] wrbuf_addr <= io.dma_axi.aw.bits.addr @[lib.scala 358:16]
node _T_1213 = and(wrbuf_data_en, io.dma_bus_clk_en) @[dma_ctrl.scala 425:72] node _T_1233 = and(wrbuf_data_en, io.dma_bus_clk_en) @[dma_ctrl.scala 429:72]
inst rvclkhdr_11 of rvclkhdr_14 @[lib.scala 352:23] inst rvclkhdr_11 of rvclkhdr_14 @[lib.scala 352:23]
rvclkhdr_11.clock <= clock rvclkhdr_11.clock <= clock
rvclkhdr_11.reset <= reset rvclkhdr_11.reset <= reset
rvclkhdr_11.io.clk <= clock @[lib.scala 354:18] rvclkhdr_11.io.clk <= clock @[lib.scala 354:18]
rvclkhdr_11.io.en <= _T_1213 @[lib.scala 355:17] rvclkhdr_11.io.en <= _T_1233 @[lib.scala 355:17]
rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 356:24] rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
reg wrbuf_data : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] reg wrbuf_data : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
wrbuf_data <= io.dma_axi.w.bits.data @[lib.scala 358:16] wrbuf_data <= io.dma_axi.w.bits.data @[lib.scala 358:16]
@ -2157,18 +2177,18 @@ circuit dma_ctrl :
when wrbuf_data_en : @[Reg.scala 28:19] when wrbuf_data_en : @[Reg.scala 28:19]
wrbuf_byteen <= io.dma_axi.w.bits.strb @[Reg.scala 28:23] wrbuf_byteen <= io.dma_axi.w.bits.strb @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node rdbuf_en = and(io.dma_axi.ar.valid, io.dma_axi.ar.ready) @[dma_ctrl.scala 433:59] node rdbuf_en = and(io.dma_axi.ar.valid, io.dma_axi.ar.ready) @[dma_ctrl.scala 437:59]
node _T_1214 = eq(bus_cmd_write, UInt<1>("h00")) @[dma_ctrl.scala 434:44] node _T_1234 = eq(bus_cmd_write, UInt<1>("h00")) @[dma_ctrl.scala 438:44]
node rdbuf_cmd_sent = and(axi_mstr_prty_en, _T_1214) @[dma_ctrl.scala 434:42] node rdbuf_cmd_sent = and(axi_mstr_prty_en, _T_1234) @[dma_ctrl.scala 438:42]
node _T_1215 = bits(rdbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 435:54] node _T_1235 = bits(rdbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 439:54]
node _T_1216 = eq(rdbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 435:63] node _T_1236 = eq(rdbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 439:63]
node rdbuf_rst = and(_T_1215, _T_1216) @[dma_ctrl.scala 435:61] node rdbuf_rst = and(_T_1235, _T_1236) @[dma_ctrl.scala 439:61]
node _T_1217 = mux(rdbuf_en, UInt<1>("h01"), rdbuf_vld) @[dma_ctrl.scala 437:51] node _T_1237 = mux(rdbuf_en, UInt<1>("h01"), rdbuf_vld) @[dma_ctrl.scala 441:51]
node _T_1218 = eq(rdbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 437:80] node _T_1238 = eq(rdbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 441:80]
node _T_1219 = and(_T_1217, _T_1218) @[dma_ctrl.scala 437:78] node _T_1239 = and(_T_1237, _T_1238) @[dma_ctrl.scala 441:78]
reg _T_1220 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 437:47] reg _T_1240 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 441:47]
_T_1220 <= _T_1219 @[dma_ctrl.scala 437:47] _T_1240 <= _T_1239 @[dma_ctrl.scala 441:47]
rdbuf_vld <= _T_1220 @[dma_ctrl.scala 437:13] rdbuf_vld <= _T_1240 @[dma_ctrl.scala 441:13]
reg rdbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg rdbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when rdbuf_en : @[Reg.scala 28:19] when rdbuf_en : @[Reg.scala 28:19]
rdbuf_tag <= io.dma_axi.ar.bits.id @[Reg.scala 28:23] rdbuf_tag <= io.dma_axi.ar.bits.id @[Reg.scala 28:23]
@ -2177,100 +2197,100 @@ circuit dma_ctrl :
when rdbuf_en : @[Reg.scala 28:19] when rdbuf_en : @[Reg.scala 28:19]
rdbuf_sz <= io.dma_axi.ar.bits.size @[Reg.scala 28:23] rdbuf_sz <= io.dma_axi.ar.bits.size @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_1221 = and(rdbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 447:61] node _T_1241 = and(rdbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 451:61]
inst rvclkhdr_12 of rvclkhdr_15 @[lib.scala 352:23] inst rvclkhdr_12 of rvclkhdr_15 @[lib.scala 352:23]
rvclkhdr_12.clock <= clock rvclkhdr_12.clock <= clock
rvclkhdr_12.reset <= reset rvclkhdr_12.reset <= reset
rvclkhdr_12.io.clk <= clock @[lib.scala 354:18] rvclkhdr_12.io.clk <= clock @[lib.scala 354:18]
rvclkhdr_12.io.en <= _T_1221 @[lib.scala 355:17] rvclkhdr_12.io.en <= _T_1241 @[lib.scala 355:17]
rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 356:24] rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
reg rdbuf_addr : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] reg rdbuf_addr : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
rdbuf_addr <= io.dma_axi.ar.bits.addr @[lib.scala 358:16] rdbuf_addr <= io.dma_axi.ar.bits.addr @[lib.scala 358:16]
node _T_1222 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 449:44] node _T_1242 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 453:44]
node _T_1223 = and(wrbuf_vld, _T_1222) @[dma_ctrl.scala 449:42] node _T_1243 = and(wrbuf_vld, _T_1242) @[dma_ctrl.scala 453:42]
node _T_1224 = not(_T_1223) @[dma_ctrl.scala 449:30] node _T_1244 = not(_T_1243) @[dma_ctrl.scala 453:30]
io.dma_axi.aw.ready <= _T_1224 @[dma_ctrl.scala 449:27] io.dma_axi.aw.ready <= _T_1244 @[dma_ctrl.scala 453:27]
node _T_1225 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 450:49] node _T_1245 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 454:49]
node _T_1226 = and(wrbuf_data_vld, _T_1225) @[dma_ctrl.scala 450:47] node _T_1246 = and(wrbuf_data_vld, _T_1245) @[dma_ctrl.scala 454:47]
node _T_1227 = not(_T_1226) @[dma_ctrl.scala 450:30] node _T_1247 = not(_T_1246) @[dma_ctrl.scala 454:30]
io.dma_axi.w.ready <= _T_1227 @[dma_ctrl.scala 450:27] io.dma_axi.w.ready <= _T_1247 @[dma_ctrl.scala 454:27]
node _T_1228 = eq(rdbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 451:44] node _T_1248 = eq(rdbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 455:44]
node _T_1229 = and(rdbuf_vld, _T_1228) @[dma_ctrl.scala 451:42] node _T_1249 = and(rdbuf_vld, _T_1248) @[dma_ctrl.scala 455:42]
node _T_1230 = not(_T_1229) @[dma_ctrl.scala 451:30] node _T_1250 = not(_T_1249) @[dma_ctrl.scala 455:30]
io.dma_axi.ar.ready <= _T_1230 @[dma_ctrl.scala 451:27] io.dma_axi.ar.ready <= _T_1250 @[dma_ctrl.scala 455:27]
node _T_1231 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 455:51] node _T_1251 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 459:51]
node _T_1232 = or(_T_1231, rdbuf_vld) @[dma_ctrl.scala 455:69] node _T_1252 = or(_T_1251, rdbuf_vld) @[dma_ctrl.scala 459:69]
bus_cmd_valid <= _T_1232 @[dma_ctrl.scala 455:37] bus_cmd_valid <= _T_1252 @[dma_ctrl.scala 459:37]
node _T_1233 = and(bus_cmd_valid, dma_fifo_ready) @[dma_ctrl.scala 456:54] node _T_1253 = and(bus_cmd_valid, dma_fifo_ready) @[dma_ctrl.scala 460:54]
axi_mstr_prty_en <= _T_1233 @[dma_ctrl.scala 456:37] axi_mstr_prty_en <= _T_1253 @[dma_ctrl.scala 460:37]
bus_cmd_write <= axi_mstr_sel @[dma_ctrl.scala 457:37] bus_cmd_write <= axi_mstr_sel @[dma_ctrl.scala 461:37]
bus_cmd_posted_write <= UInt<1>("h00") @[dma_ctrl.scala 458:25] bus_cmd_posted_write <= UInt<1>("h00") @[dma_ctrl.scala 462:25]
node _T_1234 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 459:57] node _T_1254 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 463:57]
node _T_1235 = mux(_T_1234, wrbuf_addr, rdbuf_addr) @[dma_ctrl.scala 459:43] node _T_1255 = mux(_T_1254, wrbuf_addr, rdbuf_addr) @[dma_ctrl.scala 463:43]
bus_cmd_addr <= _T_1235 @[dma_ctrl.scala 459:37] bus_cmd_addr <= _T_1255 @[dma_ctrl.scala 463:37]
node _T_1236 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 460:59] node _T_1256 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 464:59]
node _T_1237 = mux(_T_1236, wrbuf_sz, rdbuf_sz) @[dma_ctrl.scala 460:45] node _T_1257 = mux(_T_1256, wrbuf_sz, rdbuf_sz) @[dma_ctrl.scala 464:45]
bus_cmd_sz <= _T_1237 @[dma_ctrl.scala 460:39] bus_cmd_sz <= _T_1257 @[dma_ctrl.scala 464:39]
bus_cmd_wdata <= wrbuf_data @[dma_ctrl.scala 461:37] bus_cmd_wdata <= wrbuf_data @[dma_ctrl.scala 465:37]
bus_cmd_byteen <= wrbuf_byteen @[dma_ctrl.scala 462:37] bus_cmd_byteen <= wrbuf_byteen @[dma_ctrl.scala 466:37]
node _T_1238 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 463:57] node _T_1258 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 467:57]
node _T_1239 = mux(_T_1238, wrbuf_tag, rdbuf_tag) @[dma_ctrl.scala 463:43] node _T_1259 = mux(_T_1258, wrbuf_tag, rdbuf_tag) @[dma_ctrl.scala 467:43]
bus_cmd_tag <= _T_1239 @[dma_ctrl.scala 463:37] bus_cmd_tag <= _T_1259 @[dma_ctrl.scala 467:37]
bus_cmd_mid <= UInt<1>("h00") @[dma_ctrl.scala 464:37] bus_cmd_mid <= UInt<1>("h00") @[dma_ctrl.scala 468:37]
bus_cmd_prty <= UInt<1>("h00") @[dma_ctrl.scala 465:37] bus_cmd_prty <= UInt<1>("h00") @[dma_ctrl.scala 469:37]
node _T_1240 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 469:43] node _T_1260 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 473:43]
node _T_1241 = and(_T_1240, rdbuf_vld) @[dma_ctrl.scala 469:60] node _T_1261 = and(_T_1260, rdbuf_vld) @[dma_ctrl.scala 473:60]
node _T_1242 = eq(_T_1241, UInt<1>("h01")) @[dma_ctrl.scala 469:73] node _T_1262 = eq(_T_1261, UInt<1>("h01")) @[dma_ctrl.scala 473:73]
node _T_1243 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 469:111] node _T_1263 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 473:111]
node _T_1244 = mux(_T_1242, axi_mstr_priority, _T_1243) @[dma_ctrl.scala 469:31] node _T_1264 = mux(_T_1262, axi_mstr_priority, _T_1263) @[dma_ctrl.scala 473:31]
axi_mstr_sel <= _T_1244 @[dma_ctrl.scala 469:25] axi_mstr_sel <= _T_1264 @[dma_ctrl.scala 473:25]
node axi_mstr_prty_in = not(axi_mstr_priority) @[dma_ctrl.scala 470:27] node axi_mstr_prty_in = not(axi_mstr_priority) @[dma_ctrl.scala 474:27]
node _T_1245 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 474:55] node _T_1265 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 478:55]
reg _T_1246 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1266 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1245 : @[Reg.scala 28:19] when _T_1265 : @[Reg.scala 28:19]
_T_1246 <= axi_mstr_prty_in @[Reg.scala 28:23] _T_1266 <= axi_mstr_prty_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
axi_mstr_priority <= _T_1246 @[dma_ctrl.scala 473:27] axi_mstr_priority <= _T_1266 @[dma_ctrl.scala 477:27]
node _T_1247 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 477:39] node _T_1267 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 481:39]
node _T_1248 = bits(_T_1247, 0, 0) @[dma_ctrl.scala 477:39] node _T_1268 = bits(_T_1267, 0, 0) @[dma_ctrl.scala 481:39]
node _T_1249 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 477:59] node _T_1269 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 481:59]
node _T_1250 = bits(_T_1249, 0, 0) @[dma_ctrl.scala 477:59] node _T_1270 = bits(_T_1269, 0, 0) @[dma_ctrl.scala 481:59]
node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[dma_ctrl.scala 477:50] node _T_1271 = eq(_T_1270, UInt<1>("h00")) @[dma_ctrl.scala 481:50]
node _T_1252 = and(_T_1248, _T_1251) @[dma_ctrl.scala 477:48] node _T_1272 = and(_T_1268, _T_1271) @[dma_ctrl.scala 481:48]
node _T_1253 = dshr(fifo_done_bus, RspPtr) @[dma_ctrl.scala 477:83] node _T_1273 = dshr(fifo_done_bus, RspPtr) @[dma_ctrl.scala 481:83]
node _T_1254 = bits(_T_1253, 0, 0) @[dma_ctrl.scala 477:83] node _T_1274 = bits(_T_1273, 0, 0) @[dma_ctrl.scala 481:83]
node axi_rsp_valid = and(_T_1252, _T_1254) @[dma_ctrl.scala 477:68] node axi_rsp_valid = and(_T_1272, _T_1274) @[dma_ctrl.scala 481:68]
node _T_1255 = dshr(fifo_write, RspPtr) @[dma_ctrl.scala 479:39] node _T_1275 = dshr(fifo_write, RspPtr) @[dma_ctrl.scala 483:39]
node axi_rsp_write = bits(_T_1255, 0, 0) @[dma_ctrl.scala 479:39] node axi_rsp_write = bits(_T_1275, 0, 0) @[dma_ctrl.scala 483:39]
node _T_1256 = bits(fifo_error[RspPtr], 0, 0) @[dma_ctrl.scala 480:51] node _T_1276 = bits(fifo_error[RspPtr], 0, 0) @[dma_ctrl.scala 484:51]
node _T_1257 = bits(fifo_error[RspPtr], 1, 1) @[dma_ctrl.scala 480:83] node _T_1277 = bits(fifo_error[RspPtr], 1, 1) @[dma_ctrl.scala 484:83]
node _T_1258 = mux(_T_1257, UInt<2>("h03"), UInt<1>("h00")) @[dma_ctrl.scala 480:64] node _T_1278 = mux(_T_1277, UInt<2>("h03"), UInt<1>("h00")) @[dma_ctrl.scala 484:64]
node axi_rsp_error = mux(_T_1256, UInt<2>("h02"), _T_1258) @[dma_ctrl.scala 480:32] node axi_rsp_error = mux(_T_1276, UInt<2>("h02"), _T_1278) @[dma_ctrl.scala 484:32]
node _T_1259 = and(axi_rsp_valid, axi_rsp_write) @[dma_ctrl.scala 486:44] node _T_1279 = and(axi_rsp_valid, axi_rsp_write) @[dma_ctrl.scala 490:44]
io.dma_axi.b.valid <= _T_1259 @[dma_ctrl.scala 486:27] io.dma_axi.b.valid <= _T_1279 @[dma_ctrl.scala 490:27]
node _T_1260 = bits(axi_rsp_error, 1, 0) @[dma_ctrl.scala 487:57] node _T_1280 = bits(axi_rsp_error, 1, 0) @[dma_ctrl.scala 491:57]
io.dma_axi.b.bits.resp <= _T_1260 @[dma_ctrl.scala 487:41] io.dma_axi.b.bits.resp <= _T_1280 @[dma_ctrl.scala 491:41]
io.dma_axi.b.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 488:33] io.dma_axi.b.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 492:33]
node _T_1261 = eq(axi_rsp_write, UInt<1>("h00")) @[dma_ctrl.scala 490:46] node _T_1281 = eq(axi_rsp_write, UInt<1>("h00")) @[dma_ctrl.scala 494:46]
node _T_1262 = and(axi_rsp_valid, _T_1261) @[dma_ctrl.scala 490:44] node _T_1282 = and(axi_rsp_valid, _T_1281) @[dma_ctrl.scala 494:44]
io.dma_axi.r.valid <= _T_1262 @[dma_ctrl.scala 490:27] io.dma_axi.r.valid <= _T_1282 @[dma_ctrl.scala 494:27]
io.dma_axi.r.bits.resp <= axi_rsp_error @[dma_ctrl.scala 491:41] io.dma_axi.r.bits.resp <= axi_rsp_error @[dma_ctrl.scala 495:41]
node _T_1263 = bits(fifo_data[RspPtr], 63, 0) @[dma_ctrl.scala 492:59] node _T_1283 = bits(fifo_data[RspPtr], 63, 0) @[dma_ctrl.scala 496:59]
io.dma_axi.r.bits.data <= _T_1263 @[dma_ctrl.scala 492:43] io.dma_axi.r.bits.data <= _T_1283 @[dma_ctrl.scala 496:43]
io.dma_axi.r.bits.last <= UInt<1>("h01") @[dma_ctrl.scala 493:41] io.dma_axi.r.bits.last <= UInt<1>("h01") @[dma_ctrl.scala 497:41]
io.dma_axi.r.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 494:37] io.dma_axi.r.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 498:37]
bus_posted_write_done <= UInt<1>("h00") @[dma_ctrl.scala 496:25] bus_posted_write_done <= UInt<1>("h00") @[dma_ctrl.scala 500:25]
node _T_1264 = or(io.dma_axi.b.valid, io.dma_axi.r.valid) @[dma_ctrl.scala 497:60] node _T_1284 = or(io.dma_axi.b.valid, io.dma_axi.r.valid) @[dma_ctrl.scala 501:60]
bus_rsp_valid <= _T_1264 @[dma_ctrl.scala 497:37] bus_rsp_valid <= _T_1284 @[dma_ctrl.scala 501:37]
node _T_1265 = and(io.dma_axi.b.valid, io.dma_axi.b.ready) @[dma_ctrl.scala 498:61] node _T_1285 = and(io.dma_axi.b.valid, io.dma_axi.b.ready) @[dma_ctrl.scala 502:61]
node _T_1266 = and(io.dma_axi.r.valid, io.dma_axi.r.ready) @[dma_ctrl.scala 498:105] node _T_1286 = and(io.dma_axi.r.valid, io.dma_axi.r.ready) @[dma_ctrl.scala 502:105]
node _T_1267 = or(_T_1265, _T_1266) @[dma_ctrl.scala 498:83] node _T_1287 = or(_T_1285, _T_1286) @[dma_ctrl.scala 502:83]
bus_rsp_sent <= _T_1267 @[dma_ctrl.scala 498:37] bus_rsp_sent <= _T_1287 @[dma_ctrl.scala 502:37]
io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 499:40] io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 503:40]
io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 500:41] io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 504:41]
io.ifu_dma.dma_mem_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[dma_ctrl.scala 501:37] io.ifu_dma.dma_mem_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[dma_ctrl.scala 505:37]
io.ifu_dma.dma_mem_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 502:39] io.ifu_dma.dma_mem_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 506:39]
io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 503:40] io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 507:40]
io.ifu_dma.dma_mem_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[dma_ctrl.scala 504:40] io.ifu_dma.dma_mem_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[dma_ctrl.scala 508:40]
io.ifu_dma.dma_mem_ctl.dma_mem_tag <= io.lsu_dma.dma_mem_tag @[dma_ctrl.scala 505:38] io.ifu_dma.dma_mem_ctl.dma_mem_tag <= io.lsu_dma.dma_mem_tag @[dma_ctrl.scala 509:38]

455
dma_ctrl.v
View File

@ -231,18 +231,18 @@ module dma_ctrl(
wire rvclkhdr_9_io_clk; // @[lib.scala 352:23] wire rvclkhdr_9_io_clk; // @[lib.scala 352:23]
wire rvclkhdr_9_io_en; // @[lib.scala 352:23] wire rvclkhdr_9_io_en; // @[lib.scala 352:23]
wire rvclkhdr_9_io_scan_mode; // @[lib.scala 352:23] wire rvclkhdr_9_io_scan_mode; // @[lib.scala 352:23]
wire dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 385:32] wire dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 389:32]
wire dma_buffer_c1cgc_io_clk; // @[dma_ctrl.scala 385:32] wire dma_buffer_c1cgc_io_clk; // @[dma_ctrl.scala 389:32]
wire dma_buffer_c1cgc_io_en; // @[dma_ctrl.scala 385:32] wire dma_buffer_c1cgc_io_en; // @[dma_ctrl.scala 389:32]
wire dma_buffer_c1cgc_io_scan_mode; // @[dma_ctrl.scala 385:32] wire dma_buffer_c1cgc_io_scan_mode; // @[dma_ctrl.scala 389:32]
wire dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 391:28] wire dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 395:28]
wire dma_free_cgc_io_clk; // @[dma_ctrl.scala 391:28] wire dma_free_cgc_io_clk; // @[dma_ctrl.scala 395:28]
wire dma_free_cgc_io_en; // @[dma_ctrl.scala 391:28] wire dma_free_cgc_io_en; // @[dma_ctrl.scala 395:28]
wire dma_free_cgc_io_scan_mode; // @[dma_ctrl.scala 391:28] wire dma_free_cgc_io_scan_mode; // @[dma_ctrl.scala 395:28]
wire dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 397:27] wire dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 401:27]
wire dma_bus_cgc_io_clk; // @[dma_ctrl.scala 397:27] wire dma_bus_cgc_io_clk; // @[dma_ctrl.scala 401:27]
wire dma_bus_cgc_io_en; // @[dma_ctrl.scala 397:27] wire dma_bus_cgc_io_en; // @[dma_ctrl.scala 401:27]
wire dma_bus_cgc_io_scan_mode; // @[dma_ctrl.scala 397:27] wire dma_bus_cgc_io_scan_mode; // @[dma_ctrl.scala 401:27]
wire rvclkhdr_10_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_10_io_l1clk; // @[lib.scala 352:23]
wire rvclkhdr_10_io_clk; // @[lib.scala 352:23] wire rvclkhdr_10_io_clk; // @[lib.scala 352:23]
wire rvclkhdr_10_io_en; // @[lib.scala 352:23] wire rvclkhdr_10_io_en; // @[lib.scala 352:23]
@ -255,31 +255,31 @@ module dma_ctrl(
wire rvclkhdr_12_io_clk; // @[lib.scala 352:23] wire rvclkhdr_12_io_clk; // @[lib.scala 352:23]
wire rvclkhdr_12_io_en; // @[lib.scala 352:23] wire rvclkhdr_12_io_en; // @[lib.scala 352:23]
wire rvclkhdr_12_io_scan_mode; // @[lib.scala 352:23] wire rvclkhdr_12_io_scan_mode; // @[lib.scala 352:23]
wire dma_free_clk = dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 168:26 dma_ctrl.scala 395:29] wire dma_free_clk = dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 168:26 dma_ctrl.scala 399:29]
reg [2:0] RdPtr; // @[Reg.scala 27:20] reg [2:0] RdPtr; // @[Reg.scala 27:20]
reg [31:0] fifo_addr_4; // @[lib.scala 358:16] reg [31:0] fifo_addr_4; // @[lib.scala 358:16]
reg [31:0] fifo_addr_3; // @[lib.scala 358:16] reg [31:0] fifo_addr_3; // @[lib.scala 358:16]
reg [31:0] fifo_addr_2; // @[lib.scala 358:16] reg [31:0] fifo_addr_2; // @[lib.scala 358:16]
reg [31:0] fifo_addr_1; // @[lib.scala 358:16] reg [31:0] fifo_addr_1; // @[lib.scala 358:16]
reg [31:0] fifo_addr_0; // @[lib.scala 358:16] reg [31:0] fifo_addr_0; // @[lib.scala 358:16]
wire [31:0] _GEN_60 = 3'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 351:20] wire [31:0] _GEN_60 = 3'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 355:20]
wire [31:0] _GEN_61 = 3'h2 == RdPtr ? fifo_addr_2 : _GEN_60; // @[dma_ctrl.scala 351:20] wire [31:0] _GEN_61 = 3'h2 == RdPtr ? fifo_addr_2 : _GEN_60; // @[dma_ctrl.scala 355:20]
wire [31:0] _GEN_62 = 3'h3 == RdPtr ? fifo_addr_3 : _GEN_61; // @[dma_ctrl.scala 351:20] wire [31:0] _GEN_62 = 3'h3 == RdPtr ? fifo_addr_3 : _GEN_61; // @[dma_ctrl.scala 355:20]
wire [31:0] dma_mem_addr_int = 3'h4 == RdPtr ? fifo_addr_4 : _GEN_62; // @[dma_ctrl.scala 351:20] wire [31:0] dma_mem_addr_int = 3'h4 == RdPtr ? fifo_addr_4 : _GEN_62; // @[dma_ctrl.scala 355:20]
wire dma_mem_addr_in_dccm = dma_mem_addr_int[31:16] == 16'hf004; // @[lib.scala 345:39] wire dma_mem_addr_in_dccm = dma_mem_addr_int[31:16] == 16'hf004; // @[lib.scala 345:39]
wire dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[lib.scala 345:39] wire dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[lib.scala 345:39]
wire dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[lib.scala 345:39] wire dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[lib.scala 345:39]
wire dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 401:28] wire dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 405:28]
reg wrbuf_vld; // @[dma_ctrl.scala 411:59] reg wrbuf_vld; // @[dma_ctrl.scala 415:59]
reg wrbuf_data_vld; // @[dma_ctrl.scala 413:59] reg wrbuf_data_vld; // @[dma_ctrl.scala 417:59]
wire _T_1240 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 469:43] wire _T_1260 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 473:43]
reg rdbuf_vld; // @[dma_ctrl.scala 437:47] reg rdbuf_vld; // @[dma_ctrl.scala 441:47]
wire _T_1241 = _T_1240 & rdbuf_vld; // @[dma_ctrl.scala 469:60] wire _T_1261 = _T_1260 & rdbuf_vld; // @[dma_ctrl.scala 473:60]
reg axi_mstr_priority; // @[Reg.scala 27:20] reg axi_mstr_priority; // @[Reg.scala 27:20]
wire axi_mstr_sel = _T_1241 ? axi_mstr_priority : _T_1240; // @[dma_ctrl.scala 469:31] wire axi_mstr_sel = _T_1261 ? axi_mstr_priority : _T_1260; // @[dma_ctrl.scala 473:31]
reg [31:0] wrbuf_addr; // @[lib.scala 358:16] reg [31:0] wrbuf_addr; // @[lib.scala 358:16]
reg [31:0] rdbuf_addr; // @[lib.scala 358:16] reg [31:0] rdbuf_addr; // @[lib.scala 358:16]
wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 459:43] wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 463:43]
wire [2:0] _GEN_90 = {{2'd0}, io_dbg_dma_dbg_ib_dbg_cmd_addr[2]}; // @[dma_ctrl.scala 195:91] wire [2:0] _GEN_90 = {{2'd0}, io_dbg_dma_dbg_ib_dbg_cmd_addr[2]}; // @[dma_ctrl.scala 195:91]
wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[dma_ctrl.scala 195:91] wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[dma_ctrl.scala 195:91]
wire [18:0] _T_18 = 19'hf << _T_17; // @[dma_ctrl.scala 195:83] wire [18:0] _T_18 = 19'hf << _T_17; // @[dma_ctrl.scala 195:83]
@ -288,15 +288,15 @@ module dma_ctrl(
wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58] wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58]
reg [2:0] wrbuf_sz; // @[Reg.scala 27:20] reg [2:0] wrbuf_sz; // @[Reg.scala 27:20]
reg [2:0] rdbuf_sz; // @[Reg.scala 27:20] reg [2:0] rdbuf_sz; // @[Reg.scala 27:20]
wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 460:45] wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 464:45]
wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[dma_ctrl.scala 197:33] wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[dma_ctrl.scala 197:33]
wire fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dma_dbg_ib_dbg_cmd_write : axi_mstr_sel; // @[dma_ctrl.scala 199:33] wire fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dma_dbg_ib_dbg_cmd_write : axi_mstr_sel; // @[dma_ctrl.scala 199:33]
wire bus_cmd_valid = _T_1240 | rdbuf_vld; // @[dma_ctrl.scala 455:69] wire bus_cmd_valid = _T_1260 | rdbuf_vld; // @[dma_ctrl.scala 459:69]
reg fifo_full; // @[dma_ctrl.scala 369:12] reg fifo_full; // @[dma_ctrl.scala 373:12]
reg dbg_dma_bubble_bus; // @[dma_ctrl.scala 373:12] reg dbg_dma_bubble_bus; // @[dma_ctrl.scala 377:12]
wire _T_989 = fifo_full | dbg_dma_bubble_bus; // @[dma_ctrl.scala 299:39] wire _T_989 = fifo_full | dbg_dma_bubble_bus; // @[dma_ctrl.scala 299:39]
wire dma_fifo_ready = ~_T_989; // @[dma_ctrl.scala 299:27] wire dma_fifo_ready = ~_T_989; // @[dma_ctrl.scala 299:27]
wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 456:54] wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 460:54]
wire _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 206:80] wire _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 206:80]
wire _T_31 = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_type[1]; // @[dma_ctrl.scala 206:136] wire _T_31 = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_type[1]; // @[dma_ctrl.scala 206:136]
wire _T_32 = _T_28 | _T_31; // @[dma_ctrl.scala 206:101] wire _T_32 = _T_28 | _T_31; // @[dma_ctrl.scala 206:101]
@ -333,7 +333,7 @@ module dma_ctrl(
wire [4:0] _T_992 = fifo_done >> RdPtr; // @[dma_ctrl.scala 303:58] wire [4:0] _T_992 = fifo_done >> RdPtr; // @[dma_ctrl.scala 303:58]
wire _T_994 = ~_T_992[0]; // @[dma_ctrl.scala 303:48] wire _T_994 = ~_T_992[0]; // @[dma_ctrl.scala 303:48]
wire _T_995 = _T_990[0] & _T_994; // @[dma_ctrl.scala 303:46] wire _T_995 = _T_990[0] & _T_994; // @[dma_ctrl.scala 303:46]
wire dma_buffer_c1_clk = dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 172:31 dma_ctrl.scala 389:33] wire dma_buffer_c1_clk = dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 172:31 dma_ctrl.scala 393:33]
reg _T_886; // @[Reg.scala 27:20] reg _T_886; // @[Reg.scala 27:20]
reg _T_884; // @[Reg.scala 27:20] reg _T_884; // @[Reg.scala 27:20]
reg _T_882; // @[Reg.scala 27:20] reg _T_882; // @[Reg.scala 27:20]
@ -353,10 +353,10 @@ module dma_ctrl(
reg [2:0] fifo_sz_2; // @[Reg.scala 27:20] reg [2:0] fifo_sz_2; // @[Reg.scala 27:20]
reg [2:0] fifo_sz_1; // @[Reg.scala 27:20] reg [2:0] fifo_sz_1; // @[Reg.scala 27:20]
reg [2:0] fifo_sz_0; // @[Reg.scala 27:20] reg [2:0] fifo_sz_0; // @[Reg.scala 27:20]
wire [2:0] _GEN_65 = 3'h1 == RdPtr ? fifo_sz_1 : fifo_sz_0; // @[dma_ctrl.scala 352:20] wire [2:0] _GEN_65 = 3'h1 == RdPtr ? fifo_sz_1 : fifo_sz_0; // @[dma_ctrl.scala 356:20]
wire [2:0] _GEN_66 = 3'h2 == RdPtr ? fifo_sz_2 : _GEN_65; // @[dma_ctrl.scala 352:20] wire [2:0] _GEN_66 = 3'h2 == RdPtr ? fifo_sz_2 : _GEN_65; // @[dma_ctrl.scala 356:20]
wire [2:0] _GEN_67 = 3'h3 == RdPtr ? fifo_sz_3 : _GEN_66; // @[dma_ctrl.scala 352:20] wire [2:0] _GEN_67 = 3'h3 == RdPtr ? fifo_sz_3 : _GEN_66; // @[dma_ctrl.scala 356:20]
wire [2:0] dma_mem_sz_int = 3'h4 == RdPtr ? fifo_sz_4 : _GEN_67; // @[dma_ctrl.scala 352:20] wire [2:0] dma_mem_sz_int = 3'h4 == RdPtr ? fifo_sz_4 : _GEN_67; // @[dma_ctrl.scala 356:20]
wire _T_1012 = dma_mem_sz_int == 3'h1; // @[dma_ctrl.scala 305:28] wire _T_1012 = dma_mem_sz_int == 3'h1; // @[dma_ctrl.scala 305:28]
wire _T_1014 = _T_1012 & dma_mem_addr_int[0]; // @[dma_ctrl.scala 305:37] wire _T_1014 = _T_1012 & dma_mem_addr_int[0]; // @[dma_ctrl.scala 305:37]
wire _T_1016 = dma_mem_sz_int == 3'h2; // @[dma_ctrl.scala 306:29] wire _T_1016 = dma_mem_sz_int == 3'h2; // @[dma_ctrl.scala 306:29]
@ -383,33 +383,48 @@ module dma_ctrl(
reg [7:0] fifo_byteen_2; // @[Reg.scala 27:20] reg [7:0] fifo_byteen_2; // @[Reg.scala 27:20]
reg [7:0] fifo_byteen_1; // @[Reg.scala 27:20] reg [7:0] fifo_byteen_1; // @[Reg.scala 27:20]
reg [7:0] fifo_byteen_0; // @[Reg.scala 27:20] reg [7:0] fifo_byteen_0; // @[Reg.scala 27:20]
wire [7:0] _GEN_70 = 3'h1 == RdPtr ? fifo_byteen_1 : fifo_byteen_0; // @[dma_ctrl.scala 355:20] wire [7:0] _GEN_70 = 3'h1 == RdPtr ? fifo_byteen_1 : fifo_byteen_0; // @[dma_ctrl.scala 359:20]
wire [7:0] _GEN_71 = 3'h2 == RdPtr ? fifo_byteen_2 : _GEN_70; // @[dma_ctrl.scala 355:20] wire [7:0] _GEN_71 = 3'h2 == RdPtr ? fifo_byteen_2 : _GEN_70; // @[dma_ctrl.scala 359:20]
wire [7:0] _GEN_72 = 3'h3 == RdPtr ? fifo_byteen_3 : _GEN_71; // @[dma_ctrl.scala 355:20] wire [7:0] _GEN_72 = 3'h3 == RdPtr ? fifo_byteen_3 : _GEN_71; // @[dma_ctrl.scala 359:20]
wire [7:0] dma_mem_byteen = 3'h4 == RdPtr ? fifo_byteen_4 : _GEN_72; // @[dma_ctrl.scala 355:20] wire [7:0] dma_mem_byteen = 3'h4 == RdPtr ? fifo_byteen_4 : _GEN_72; // @[dma_ctrl.scala 359:20]
wire [3:0] _T_1059 = _T_1048 ? dma_mem_byteen[3:0] : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1071 = _T_1048 ? dma_mem_byteen[3:0] : 4'h0; // @[Mux.scala 27:72]
wire _T_1051 = dma_mem_addr_int[2:0] == 3'h1; // @[dma_ctrl.scala 311:32] wire _T_1051 = dma_mem_addr_int[2:0] == 3'h1; // @[dma_ctrl.scala 311:32]
wire [3:0] _T_1060 = _T_1051 ? dma_mem_byteen[4:1] : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1072 = _T_1051 ? dma_mem_byteen[4:1] : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_1063 = _T_1059 | _T_1060; // @[Mux.scala 27:72] wire [3:0] _T_1079 = _T_1071 | _T_1072; // @[Mux.scala 27:72]
wire _T_1054 = dma_mem_addr_int[2:0] == 3'h2; // @[dma_ctrl.scala 312:32] wire _T_1054 = dma_mem_addr_int[2:0] == 3'h2; // @[dma_ctrl.scala 312:32]
wire [3:0] _T_1061 = _T_1054 ? dma_mem_byteen[5:2] : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1073 = _T_1054 ? dma_mem_byteen[5:2] : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_1064 = _T_1063 | _T_1061; // @[Mux.scala 27:72] wire [3:0] _T_1080 = _T_1079 | _T_1073; // @[Mux.scala 27:72]
wire _T_1057 = dma_mem_addr_int[2:0] == 3'h3; // @[dma_ctrl.scala 313:32] wire _T_1057 = dma_mem_addr_int[2:0] == 3'h3; // @[dma_ctrl.scala 313:32]
wire [3:0] _T_1062 = _T_1057 ? dma_mem_byteen[6:3] : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1074 = _T_1057 ? dma_mem_byteen[6:3] : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_1065 = _T_1064 | _T_1062; // @[Mux.scala 27:72] wire [3:0] _T_1081 = _T_1080 | _T_1074; // @[Mux.scala 27:72]
wire _T_1067 = _T_1065 != 4'hf; // @[dma_ctrl.scala 313:68] wire _T_1060 = dma_mem_addr_int[2:0] == 3'h4; // @[dma_ctrl.scala 314:32]
wire _T_1068 = _T_1046 & _T_1067; // @[dma_ctrl.scala 310:78] wire [3:0] _T_1075 = _T_1060 ? dma_mem_byteen[7:4] : 4'h0; // @[Mux.scala 27:72]
wire _T_1069 = _T_1043 | _T_1068; // @[dma_ctrl.scala 309:145] wire [3:0] _T_1082 = _T_1081 | _T_1075; // @[Mux.scala 27:72]
wire _T_1072 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1022; // @[dma_ctrl.scala 314:45] wire _T_1063 = dma_mem_addr_int[2:0] == 3'h5; // @[dma_ctrl.scala 315:32]
wire _T_1074 = dma_mem_byteen == 8'hf; // @[dma_ctrl.scala 314:103] wire [2:0] _T_1076 = _T_1063 ? dma_mem_byteen[7:5] : 3'h0; // @[Mux.scala 27:72]
wire _T_1076 = dma_mem_byteen == 8'hf0; // @[dma_ctrl.scala 314:139] wire [3:0] _GEN_91 = {{1'd0}, _T_1076}; // @[Mux.scala 27:72]
wire _T_1077 = _T_1074 | _T_1076; // @[dma_ctrl.scala 314:116] wire [3:0] _T_1083 = _T_1082 | _GEN_91; // @[Mux.scala 27:72]
wire _T_1079 = dma_mem_byteen == 8'hff; // @[dma_ctrl.scala 314:175] wire _T_1066 = dma_mem_addr_int[2:0] == 3'h6; // @[dma_ctrl.scala 316:32]
wire _T_1080 = _T_1077 | _T_1079; // @[dma_ctrl.scala 314:152] wire [1:0] _T_1077 = _T_1066 ? dma_mem_byteen[7:6] : 2'h0; // @[Mux.scala 27:72]
wire _T_1081 = ~_T_1080; // @[dma_ctrl.scala 314:80] wire [3:0] _GEN_92 = {{2'd0}, _T_1077}; // @[Mux.scala 27:72]
wire _T_1082 = _T_1072 & _T_1081; // @[dma_ctrl.scala 314:78] wire [3:0] _T_1084 = _T_1083 | _GEN_92; // @[Mux.scala 27:72]
wire _T_1083 = _T_1069 | _T_1082; // @[dma_ctrl.scala 313:79] wire _T_1069 = dma_mem_addr_int[2:0] == 3'h7; // @[dma_ctrl.scala 317:32]
wire dma_alignment_error = _T_1010 & _T_1083; // @[dma_ctrl.scala 304:87] wire _T_1078 = _T_1069 & dma_mem_byteen[7]; // @[Mux.scala 27:72]
wire [3:0] _GEN_93 = {{3'd0}, _T_1078}; // @[Mux.scala 27:72]
wire [3:0] _T_1085 = _T_1084 | _GEN_93; // @[Mux.scala 27:72]
wire _T_1087 = _T_1085 != 4'hf; // @[dma_ctrl.scala 317:66]
wire _T_1088 = _T_1046 & _T_1087; // @[dma_ctrl.scala 310:78]
wire _T_1089 = _T_1043 | _T_1088; // @[dma_ctrl.scala 309:145]
wire _T_1092 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1022; // @[dma_ctrl.scala 318:45]
wire _T_1094 = dma_mem_byteen == 8'hf; // @[dma_ctrl.scala 318:103]
wire _T_1096 = dma_mem_byteen == 8'hf0; // @[dma_ctrl.scala 318:139]
wire _T_1097 = _T_1094 | _T_1096; // @[dma_ctrl.scala 318:116]
wire _T_1099 = dma_mem_byteen == 8'hff; // @[dma_ctrl.scala 318:175]
wire _T_1100 = _T_1097 | _T_1099; // @[dma_ctrl.scala 318:152]
wire _T_1101 = ~_T_1100; // @[dma_ctrl.scala 318:80]
wire _T_1102 = _T_1092 & _T_1101; // @[dma_ctrl.scala 318:78]
wire _T_1103 = _T_1089 | _T_1102; // @[dma_ctrl.scala 317:79]
wire dma_alignment_error = _T_1010 & _T_1103; // @[dma_ctrl.scala 304:87]
wire _T_79 = dma_address_error | dma_alignment_error; // @[dma_ctrl.scala 208:258] wire _T_79 = dma_address_error | dma_alignment_error; // @[dma_ctrl.scala 208:258]
wire _T_80 = 3'h0 == RdPtr; // @[dma_ctrl.scala 208:288] wire _T_80 = 3'h0 == RdPtr; // @[dma_ctrl.scala 208:288]
wire _T_81 = _T_79 & _T_80; // @[dma_ctrl.scala 208:281] wire _T_81 = _T_79 & _T_80; // @[dma_ctrl.scala 208:281]
@ -470,12 +485,12 @@ module dma_ctrl(
wire _T_184 = _T_167 & _T_134; // @[dma_ctrl.scala 210:174] wire _T_184 = _T_167 & _T_134; // @[dma_ctrl.scala 210:174]
wire _T_189 = _T_167 & _T_152; // @[dma_ctrl.scala 210:174] wire _T_189 = _T_167 & _T_152; // @[dma_ctrl.scala 210:174]
wire [4:0] fifo_pend_en = {_T_189,_T_184,_T_179,_T_174,_T_169}; // @[Cat.scala 29:58] wire [4:0] fifo_pend_en = {_T_189,_T_184,_T_179,_T_174,_T_169}; // @[Cat.scala 29:58]
wire _T_1107 = _T_995 & _T_996[0]; // @[dma_ctrl.scala 324:66] wire _T_1127 = _T_995 & _T_996[0]; // @[dma_ctrl.scala 328:66]
wire _T_1109 = _T_1000 | dma_mem_addr_in_pic; // @[dma_ctrl.scala 324:134] wire _T_1129 = _T_1000 | dma_mem_addr_in_pic; // @[dma_ctrl.scala 328:134]
wire _T_1110 = ~_T_1109; // @[dma_ctrl.scala 324:88] wire _T_1130 = ~_T_1129; // @[dma_ctrl.scala 328:88]
wire _T_1113 = dma_mem_sz_int[1:0] != 2'h2; // @[dma_ctrl.scala 324:191] wire _T_1133 = dma_mem_sz_int[1:0] != 2'h2; // @[dma_ctrl.scala 328:191]
wire _T_1114 = _T_1110 | _T_1113; // @[dma_ctrl.scala 324:167] wire _T_1134 = _T_1130 | _T_1133; // @[dma_ctrl.scala 328:167]
wire dma_dbg_cmd_error = _T_1107 & _T_1114; // @[dma_ctrl.scala 324:84] wire dma_dbg_cmd_error = _T_1127 & _T_1134; // @[dma_ctrl.scala 328:84]
wire _T_197 = _T_79 | dma_dbg_cmd_error; // @[dma_ctrl.scala 212:114] wire _T_197 = _T_79 | dma_dbg_cmd_error; // @[dma_ctrl.scala 212:114]
wire _T_199 = _T_197 & _T_80; // @[dma_ctrl.scala 212:135] wire _T_199 = _T_197 & _T_80; // @[dma_ctrl.scala 212:135]
wire _T_200 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[dma_ctrl.scala 212:198] wire _T_200 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[dma_ctrl.scala 212:198]
@ -571,9 +586,9 @@ module dma_ctrl(
wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75] wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75]
wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91] wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91]
wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58] wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58]
wire _T_1265 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 498:61] wire _T_1285 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 502:61]
wire _T_1266 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 498:105] wire _T_1286 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 502:105]
wire bus_rsp_sent = _T_1265 | _T_1266; // @[dma_ctrl.scala 498:83] wire bus_rsp_sent = _T_1285 | _T_1286; // @[dma_ctrl.scala 502:83]
wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99] wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99]
wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120] wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120]
reg [2:0] RspPtr; // @[Reg.scala 27:20] reg [2:0] RspPtr; // @[Reg.scala 27:20]
@ -658,7 +673,7 @@ module dma_ctrl(
reg fifo_tag_0; // @[Reg.scala 27:20] reg fifo_tag_0; // @[Reg.scala 27:20]
reg wrbuf_tag; // @[Reg.scala 27:20] reg wrbuf_tag; // @[Reg.scala 27:20]
reg rdbuf_tag; // @[Reg.scala 27:20] reg rdbuf_tag; // @[Reg.scala 27:20]
wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 463:43] wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 467:43]
reg fifo_tag_1; // @[Reg.scala 27:20] reg fifo_tag_1; // @[Reg.scala 27:20]
reg fifo_tag_2; // @[Reg.scala 27:20] reg fifo_tag_2; // @[Reg.scala 27:20]
reg fifo_tag_3; // @[Reg.scala 27:20] reg fifo_tag_3; // @[Reg.scala 27:20]
@ -672,6 +687,9 @@ module dma_ctrl(
wire WrPtrEn = |fifo_cmd_en; // @[dma_ctrl.scala 266:30] wire WrPtrEn = |fifo_cmd_en; // @[dma_ctrl.scala 266:30]
wire RdPtrEn = _T_165 | _T_197; // @[dma_ctrl.scala 268:93] wire RdPtrEn = _T_165 | _T_197; // @[dma_ctrl.scala 268:93]
wire RspPtrEn = io_dma_dbg_cmd_done | _T_406; // @[dma_ctrl.scala 270:39] wire RspPtrEn = io_dma_dbg_cmd_done | _T_406; // @[dma_ctrl.scala 270:39]
wire [3:0] _T_959 = {3'h0,axi_mstr_prty_en}; // @[Cat.scala 29:58]
wire [3:0] _T_961 = {3'h0,bus_rsp_sent}; // @[Cat.scala 29:58]
wire [3:0] num_fifo_vld_tmp = _T_959 - _T_961; // @[dma_ctrl.scala 291:62]
wire [3:0] _T_966 = {3'h0,fifo_valid[0]}; // @[Cat.scala 29:58] wire [3:0] _T_966 = {3'h0,fifo_valid[0]}; // @[Cat.scala 29:58]
wire [3:0] _T_969 = {3'h0,fifo_valid[1]}; // @[Cat.scala 29:58] wire [3:0] _T_969 = {3'h0,fifo_valid[1]}; // @[Cat.scala 29:58]
wire [3:0] _T_972 = {3'h0,fifo_valid[2]}; // @[Cat.scala 29:58] wire [3:0] _T_972 = {3'h0,fifo_valid[2]}; // @[Cat.scala 29:58]
@ -681,91 +699,92 @@ module dma_ctrl(
wire [3:0] _T_982 = _T_980 + _T_972; // @[dma_ctrl.scala 293:102] wire [3:0] _T_982 = _T_980 + _T_972; // @[dma_ctrl.scala 293:102]
wire [3:0] _T_984 = _T_982 + _T_975; // @[dma_ctrl.scala 293:102] wire [3:0] _T_984 = _T_982 + _T_975; // @[dma_ctrl.scala 293:102]
wire [3:0] num_fifo_vld_tmp2 = _T_984 + _T_978; // @[dma_ctrl.scala 293:102] wire [3:0] num_fifo_vld_tmp2 = _T_984 + _T_978; // @[dma_ctrl.scala 293:102]
wire _T_1123 = |fifo_valid; // @[dma_ctrl.scala 334:30] wire [3:0] num_fifo_vld = num_fifo_vld_tmp + num_fifo_vld_tmp2; // @[dma_ctrl.scala 295:45]
wire fifo_empty = ~_T_1123; // @[dma_ctrl.scala 334:17] wire _T_1143 = |fifo_valid; // @[dma_ctrl.scala 338:30]
wire [4:0] _T_1086 = fifo_valid >> RspPtr; // @[dma_ctrl.scala 320:39] wire fifo_empty = ~_T_1143; // @[dma_ctrl.scala 338:17]
wire [4:0] _T_1088 = fifo_dbg >> RspPtr; // @[dma_ctrl.scala 320:58] wire [4:0] _T_1106 = fifo_valid >> RspPtr; // @[dma_ctrl.scala 324:39]
wire _T_1090 = _T_1086[0] & _T_1088[0]; // @[dma_ctrl.scala 320:48] wire [4:0] _T_1108 = fifo_dbg >> RspPtr; // @[dma_ctrl.scala 324:58]
wire [4:0] _T_1091 = fifo_done >> RspPtr; // @[dma_ctrl.scala 320:78] wire _T_1110 = _T_1106[0] & _T_1108[0]; // @[dma_ctrl.scala 324:48]
wire [31:0] _GEN_44 = 3'h1 == RspPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 321:49] wire [4:0] _T_1111 = fifo_done >> RspPtr; // @[dma_ctrl.scala 324:78]
wire [31:0] _GEN_45 = 3'h2 == RspPtr ? fifo_addr_2 : _GEN_44; // @[dma_ctrl.scala 321:49] wire [31:0] _GEN_44 = 3'h1 == RspPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 325:49]
wire [31:0] _GEN_46 = 3'h3 == RspPtr ? fifo_addr_3 : _GEN_45; // @[dma_ctrl.scala 321:49] wire [31:0] _GEN_45 = 3'h2 == RspPtr ? fifo_addr_2 : _GEN_44; // @[dma_ctrl.scala 325:49]
wire [31:0] _GEN_47 = 3'h4 == RspPtr ? fifo_addr_4 : _GEN_46; // @[dma_ctrl.scala 321:49] wire [31:0] _GEN_46 = 3'h3 == RspPtr ? fifo_addr_3 : _GEN_45; // @[dma_ctrl.scala 325:49]
wire [63:0] _GEN_49 = 3'h1 == RspPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 321:71] wire [31:0] _GEN_47 = 3'h4 == RspPtr ? fifo_addr_4 : _GEN_46; // @[dma_ctrl.scala 325:49]
wire [63:0] _GEN_50 = 3'h2 == RspPtr ? fifo_data_2 : _GEN_49; // @[dma_ctrl.scala 321:71] wire [63:0] _GEN_49 = 3'h1 == RspPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 325:71]
wire [63:0] _GEN_51 = 3'h3 == RspPtr ? fifo_data_3 : _GEN_50; // @[dma_ctrl.scala 321:71] wire [63:0] _GEN_50 = 3'h2 == RspPtr ? fifo_data_2 : _GEN_49; // @[dma_ctrl.scala 325:71]
wire [63:0] _GEN_52 = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 321:71] wire [63:0] _GEN_51 = 3'h3 == RspPtr ? fifo_data_3 : _GEN_50; // @[dma_ctrl.scala 325:71]
wire [1:0] _GEN_54 = 3'h1 == RspPtr ? fifo_error_1 : fifo_error_0; // @[dma_ctrl.scala 322:47] wire [63:0] _GEN_52 = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 325:71]
wire [1:0] _GEN_55 = 3'h2 == RspPtr ? fifo_error_2 : _GEN_54; // @[dma_ctrl.scala 322:47] wire [1:0] _GEN_54 = 3'h1 == RspPtr ? fifo_error_1 : fifo_error_0; // @[dma_ctrl.scala 326:47]
wire [1:0] _GEN_56 = 3'h3 == RspPtr ? fifo_error_3 : _GEN_55; // @[dma_ctrl.scala 322:47] wire [1:0] _GEN_55 = 3'h2 == RspPtr ? fifo_error_2 : _GEN_54; // @[dma_ctrl.scala 326:47]
wire [1:0] _GEN_57 = 3'h4 == RspPtr ? fifo_error_4 : _GEN_56; // @[dma_ctrl.scala 322:47] wire [1:0] _GEN_56 = 3'h3 == RspPtr ? fifo_error_3 : _GEN_55; // @[dma_ctrl.scala 326:47]
wire _T_1116 = dma_mem_addr_in_dccm | dma_mem_addr_in_pic; // @[dma_ctrl.scala 328:80] wire [1:0] _GEN_57 = 3'h4 == RspPtr ? fifo_error_4 : _GEN_56; // @[dma_ctrl.scala 326:47]
wire [4:0] _T_1145 = fifo_rpend >> RdPtr; // @[dma_ctrl.scala 347:54] wire _T_1136 = dma_mem_addr_in_dccm | dma_mem_addr_in_pic; // @[dma_ctrl.scala 332:80]
wire _T_1147 = ~_T_1145[0]; // @[dma_ctrl.scala 347:43] wire [4:0] _T_1165 = fifo_rpend >> RdPtr; // @[dma_ctrl.scala 351:54]
wire _T_1148 = _T_990[0] & _T_1147; // @[dma_ctrl.scala 347:41] wire _T_1167 = ~_T_1165[0]; // @[dma_ctrl.scala 351:43]
wire _T_1152 = _T_1148 & _T_994; // @[dma_ctrl.scala 347:62] wire _T_1168 = _T_990[0] & _T_1167; // @[dma_ctrl.scala 351:41]
wire _T_1155 = ~_T_197; // @[dma_ctrl.scala 347:84] wire _T_1172 = _T_1168 & _T_994; // @[dma_ctrl.scala 351:62]
wire dma_mem_req = _T_1152 & _T_1155; // @[dma_ctrl.scala 347:82] wire _T_1175 = ~_T_197; // @[dma_ctrl.scala 351:84]
wire _T_1117 = dma_mem_req & _T_1116; // @[dma_ctrl.scala 328:56] wire dma_mem_req = _T_1172 & _T_1175; // @[dma_ctrl.scala 351:82]
wire _T_1137 = dma_mem_req & _T_1136; // @[dma_ctrl.scala 332:56]
reg [2:0] dma_nack_count; // @[Reg.scala 27:20] reg [2:0] dma_nack_count; // @[Reg.scala 27:20]
wire _T_1118 = dma_nack_count >= io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[dma_ctrl.scala 328:121] wire _T_1138 = dma_nack_count >= io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[dma_ctrl.scala 332:121]
wire _T_1120 = dma_mem_req & dma_mem_addr_in_iccm; // @[dma_ctrl.scala 329:56] wire _T_1140 = dma_mem_req & dma_mem_addr_in_iccm; // @[dma_ctrl.scala 333:56]
wire _T_1127 = ~_T_165; // @[dma_ctrl.scala 339:77] wire _T_1147 = ~_T_165; // @[dma_ctrl.scala 343:77]
wire [2:0] _T_1129 = _T_1127 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [2:0] _T_1149 = _T_1147 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_1131 = _T_1129 & dma_nack_count; // @[dma_ctrl.scala 339:155] wire [2:0] _T_1151 = _T_1149 & dma_nack_count; // @[dma_ctrl.scala 343:155]
wire _T_1135 = dma_mem_req & _T_1127; // @[dma_ctrl.scala 339:203] wire _T_1155 = dma_mem_req & _T_1147; // @[dma_ctrl.scala 343:203]
wire [2:0] _T_1138 = dma_nack_count + 3'h1; // @[dma_ctrl.scala 339:304] wire [2:0] _T_1158 = dma_nack_count + 3'h1; // @[dma_ctrl.scala 343:304]
wire _T_1164 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1076; // @[dma_ctrl.scala 353:84] wire _T_1184 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1096; // @[dma_ctrl.scala 357:84]
wire [31:0] _T_1168 = {dma_mem_addr_int[31:3],1'h1,dma_mem_addr_int[1:0]}; // @[Cat.scala 29:58] wire [31:0] _T_1188 = {dma_mem_addr_int[31:3],1'h1,dma_mem_addr_int[1:0]}; // @[Cat.scala 29:58]
wire _T_1176 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1077; // @[dma_ctrl.scala 354:84] wire _T_1196 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1097; // @[dma_ctrl.scala 358:84]
wire [4:0] _T_1179 = fifo_write >> RdPtr; // @[dma_ctrl.scala 356:53] wire [4:0] _T_1199 = fifo_write >> RdPtr; // @[dma_ctrl.scala 360:53]
wire [63:0] _GEN_75 = 3'h1 == RdPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 357:40] wire [63:0] _GEN_75 = 3'h1 == RdPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 361:40]
wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[dma_ctrl.scala 357:40] wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[dma_ctrl.scala 361:40]
wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[dma_ctrl.scala 357:40] wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[dma_ctrl.scala 361:40]
reg dma_dbg_cmd_done_q; // @[dma_ctrl.scala 377:12] reg dma_dbg_cmd_done_q; // @[dma_ctrl.scala 381:12]
wire _T_1192 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 382:44] wire _T_1212 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44]
wire _T_1193 = _T_1192 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 382:65] wire _T_1213 = _T_1212 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 386:65]
wire bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 497:60] wire bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 501:60]
wire _T_1194 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 383:44] wire _T_1214 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 387:44]
wire _T_1195 = _T_1194 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 383:60] wire _T_1215 = _T_1214 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60]
wire _T_1196 = _T_1195 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 383:94] wire _T_1216 = _T_1215 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 387:94]
wire _T_1197 = _T_1196 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 383:116] wire _T_1217 = _T_1216 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 387:116]
wire _T_1199 = _T_1197 | _T_1123; // @[dma_ctrl.scala 383:137] wire _T_1219 = _T_1217 | _T_1143; // @[dma_ctrl.scala 387:137]
wire wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 405:47] wire wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 409:47]
wire wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 406:46] wire wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 410:46]
wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 407:40] wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 411:40]
wire _T_1201 = ~wrbuf_en; // @[dma_ctrl.scala 408:51] wire _T_1221 = ~wrbuf_en; // @[dma_ctrl.scala 412:51]
wire wrbuf_rst = wrbuf_cmd_sent & _T_1201; // @[dma_ctrl.scala 408:49] wire wrbuf_rst = wrbuf_cmd_sent & _T_1221; // @[dma_ctrl.scala 412:49]
wire _T_1203 = ~wrbuf_data_en; // @[dma_ctrl.scala 409:51] wire _T_1223 = ~wrbuf_data_en; // @[dma_ctrl.scala 413:51]
wire wrbuf_data_rst = wrbuf_cmd_sent & _T_1203; // @[dma_ctrl.scala 409:49] wire wrbuf_data_rst = wrbuf_cmd_sent & _T_1223; // @[dma_ctrl.scala 413:49]
wire _T_1204 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 411:63] wire _T_1224 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 415:63]
wire _T_1205 = ~wrbuf_rst; // @[dma_ctrl.scala 411:92] wire _T_1225 = ~wrbuf_rst; // @[dma_ctrl.scala 415:92]
wire _T_1208 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 413:63] wire _T_1228 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 417:63]
wire _T_1209 = ~wrbuf_data_rst; // @[dma_ctrl.scala 413:102] wire _T_1229 = ~wrbuf_data_rst; // @[dma_ctrl.scala 417:102]
wire rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 433:59] wire rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 437:59]
wire _T_1214 = ~axi_mstr_sel; // @[dma_ctrl.scala 434:44] wire _T_1234 = ~axi_mstr_sel; // @[dma_ctrl.scala 438:44]
wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_1214; // @[dma_ctrl.scala 434:42] wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_1234; // @[dma_ctrl.scala 438:42]
wire _T_1216 = ~rdbuf_en; // @[dma_ctrl.scala 435:63] wire _T_1236 = ~rdbuf_en; // @[dma_ctrl.scala 439:63]
wire rdbuf_rst = rdbuf_cmd_sent & _T_1216; // @[dma_ctrl.scala 435:61] wire rdbuf_rst = rdbuf_cmd_sent & _T_1236; // @[dma_ctrl.scala 439:61]
wire _T_1217 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 437:51] wire _T_1237 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 441:51]
wire _T_1218 = ~rdbuf_rst; // @[dma_ctrl.scala 437:80] wire _T_1238 = ~rdbuf_rst; // @[dma_ctrl.scala 441:80]
wire _T_1222 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 449:44] wire _T_1242 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 453:44]
wire _T_1223 = wrbuf_vld & _T_1222; // @[dma_ctrl.scala 449:42] wire _T_1243 = wrbuf_vld & _T_1242; // @[dma_ctrl.scala 453:42]
wire _T_1226 = wrbuf_data_vld & _T_1222; // @[dma_ctrl.scala 450:47] wire _T_1246 = wrbuf_data_vld & _T_1242; // @[dma_ctrl.scala 454:47]
wire _T_1228 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 451:44] wire _T_1248 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 455:44]
wire _T_1229 = rdbuf_vld & _T_1228; // @[dma_ctrl.scala 451:42] wire _T_1249 = rdbuf_vld & _T_1248; // @[dma_ctrl.scala 455:42]
wire axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 470:27] wire axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 474:27]
wire _T_1251 = ~_T_1088[0]; // @[dma_ctrl.scala 477:50] wire _T_1271 = ~_T_1108[0]; // @[dma_ctrl.scala 481:50]
wire _T_1252 = _T_1086[0] & _T_1251; // @[dma_ctrl.scala 477:48] wire _T_1272 = _T_1106[0] & _T_1271; // @[dma_ctrl.scala 481:48]
wire [4:0] _T_1253 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 477:83] wire [4:0] _T_1273 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 481:83]
wire axi_rsp_valid = _T_1252 & _T_1253[0]; // @[dma_ctrl.scala 477:68] wire axi_rsp_valid = _T_1272 & _T_1273[0]; // @[dma_ctrl.scala 481:68]
wire [4:0] _T_1255 = fifo_write >> RspPtr; // @[dma_ctrl.scala 479:39] wire [4:0] _T_1275 = fifo_write >> RspPtr; // @[dma_ctrl.scala 483:39]
wire axi_rsp_write = _T_1255[0]; // @[dma_ctrl.scala 479:39] wire axi_rsp_write = _T_1275[0]; // @[dma_ctrl.scala 483:39]
wire [1:0] _T_1258 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 480:64] wire [1:0] _T_1278 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 484:64]
wire _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 488:33] wire _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 492:33]
wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 488:33] wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 492:33]
wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 488:33] wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 492:33]
wire _T_1261 = ~axi_rsp_write; // @[dma_ctrl.scala 490:46] wire _T_1281 = ~axi_rsp_write; // @[dma_ctrl.scala 494:46]
rvclkhdr rvclkhdr ( // @[lib.scala 352:23] rvclkhdr rvclkhdr ( // @[lib.scala 352:23]
.io_l1clk(rvclkhdr_io_l1clk), .io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk), .io_clk(rvclkhdr_io_clk),
@ -826,19 +845,19 @@ module dma_ctrl(
.io_en(rvclkhdr_9_io_en), .io_en(rvclkhdr_9_io_en),
.io_scan_mode(rvclkhdr_9_io_scan_mode) .io_scan_mode(rvclkhdr_9_io_scan_mode)
); );
rvclkhdr dma_buffer_c1cgc ( // @[dma_ctrl.scala 385:32] rvclkhdr dma_buffer_c1cgc ( // @[dma_ctrl.scala 389:32]
.io_l1clk(dma_buffer_c1cgc_io_l1clk), .io_l1clk(dma_buffer_c1cgc_io_l1clk),
.io_clk(dma_buffer_c1cgc_io_clk), .io_clk(dma_buffer_c1cgc_io_clk),
.io_en(dma_buffer_c1cgc_io_en), .io_en(dma_buffer_c1cgc_io_en),
.io_scan_mode(dma_buffer_c1cgc_io_scan_mode) .io_scan_mode(dma_buffer_c1cgc_io_scan_mode)
); );
rvclkhdr dma_free_cgc ( // @[dma_ctrl.scala 391:28] rvclkhdr dma_free_cgc ( // @[dma_ctrl.scala 395:28]
.io_l1clk(dma_free_cgc_io_l1clk), .io_l1clk(dma_free_cgc_io_l1clk),
.io_clk(dma_free_cgc_io_clk), .io_clk(dma_free_cgc_io_clk),
.io_en(dma_free_cgc_io_en), .io_en(dma_free_cgc_io_en),
.io_scan_mode(dma_free_cgc_io_scan_mode) .io_scan_mode(dma_free_cgc_io_scan_mode)
); );
rvclkhdr dma_bus_cgc ( // @[dma_ctrl.scala 397:27] rvclkhdr dma_bus_cgc ( // @[dma_ctrl.scala 401:27]
.io_l1clk(dma_bus_cgc_io_l1clk), .io_l1clk(dma_bus_cgc_io_l1clk),
.io_clk(dma_bus_cgc_io_clk), .io_clk(dma_bus_cgc_io_clk),
.io_en(dma_bus_cgc_io_en), .io_en(dma_bus_cgc_io_en),
@ -862,43 +881,43 @@ module dma_ctrl(
.io_en(rvclkhdr_12_io_en), .io_en(rvclkhdr_12_io_en),
.io_scan_mode(rvclkhdr_12_io_scan_mode) .io_scan_mode(rvclkhdr_12_io_scan_mode)
); );
assign io_dma_dbg_rddata = _GEN_47[2] ? _GEN_52[63:32] : _GEN_52[31:0]; // @[dma_ctrl.scala 321:25] assign io_dma_dbg_rddata = _GEN_47[2] ? _GEN_52[63:32] : _GEN_52[31:0]; // @[dma_ctrl.scala 325:25]
assign io_dma_dbg_cmd_done = _T_1090 & _T_1091[0]; // @[dma_ctrl.scala 320:25] assign io_dma_dbg_cmd_done = _T_1110 & _T_1111[0]; // @[dma_ctrl.scala 324:25]
assign io_dma_dbg_cmd_fail = |_GEN_57; // @[dma_ctrl.scala 322:25] assign io_dma_dbg_cmd_fail = |_GEN_57; // @[dma_ctrl.scala 326:25]
assign io_dbg_dma_io_dma_dbg_ready = fifo_empty & dbg_dma_bubble_bus; // @[dma_ctrl.scala 319:36] assign io_dbg_dma_io_dma_dbg_ready = fifo_empty & dbg_dma_bubble_bus; // @[dma_ctrl.scala 323:36]
assign io_dec_dma_dctl_dma_dma_dccm_stall_any = io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[dma_ctrl.scala 331:42] assign io_dec_dma_dctl_dma_dma_dccm_stall_any = io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[dma_ctrl.scala 335:42]
assign io_dec_dma_tlu_dma_dma_pmu_dccm_read = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & _T_166; // @[dma_ctrl.scala 361:42] assign io_dec_dma_tlu_dma_dma_pmu_dccm_read = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & _T_166; // @[dma_ctrl.scala 365:42]
assign io_dec_dma_tlu_dma_dma_pmu_dccm_write = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 362:42] assign io_dec_dma_tlu_dma_dma_pmu_dccm_write = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 366:42]
assign io_dec_dma_tlu_dma_dma_pmu_any_read = _T_165 & _T_166; // @[dma_ctrl.scala 363:42] assign io_dec_dma_tlu_dma_dma_pmu_any_read = _T_165 & _T_166; // @[dma_ctrl.scala 367:42]
assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 364:42] assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 368:42]
assign io_dec_dma_tlu_dma_dma_dccm_stall_any = _T_1117 & _T_1118; // @[dma_ctrl.scala 328:41] assign io_dec_dma_tlu_dma_dma_dccm_stall_any = _T_1137 & _T_1138; // @[dma_ctrl.scala 332:41]
assign io_dec_dma_tlu_dma_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[dma_ctrl.scala 330:41] assign io_dec_dma_tlu_dma_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[dma_ctrl.scala 334:41]
assign io_dma_axi_aw_ready = ~_T_1223; // @[dma_ctrl.scala 449:27] assign io_dma_axi_aw_ready = ~_T_1243; // @[dma_ctrl.scala 453:27]
assign io_dma_axi_w_ready = ~_T_1226; // @[dma_ctrl.scala 450:27] assign io_dma_axi_w_ready = ~_T_1246; // @[dma_ctrl.scala 454:27]
assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 486:27] assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 490:27]
assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1258; // @[dma_ctrl.scala 487:41] assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 491:41]
assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 488:33] assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 492:33]
assign io_dma_axi_ar_ready = ~_T_1229; // @[dma_ctrl.scala 451:27] assign io_dma_axi_ar_ready = ~_T_1249; // @[dma_ctrl.scala 455:27]
assign io_dma_axi_r_valid = axi_rsp_valid & _T_1261; // @[dma_ctrl.scala 490:27] assign io_dma_axi_r_valid = axi_rsp_valid & _T_1281; // @[dma_ctrl.scala 494:27]
assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 494:37] assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 498:37]
assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 492:43] assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 496:43]
assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1258; // @[dma_ctrl.scala 491:41] assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 495:41]
assign io_dma_axi_r_bits_last = 1'h1; // @[dma_ctrl.scala 493:41] assign io_dma_axi_r_bits_last = 1'h1; // @[dma_ctrl.scala 497:41]
assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1117 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 348:40] assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1137 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 352:40]
assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1164 ? _T_1168 : dma_mem_addr_int; // @[dma_ctrl.scala 353:40] assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1184 ? _T_1188 : dma_mem_addr_int; // @[dma_ctrl.scala 357:40]
assign io_lsu_dma_dma_lsc_ctl_dma_mem_sz = _T_1176 ? 3'h2 : dma_mem_sz_int; // @[dma_ctrl.scala 354:40] assign io_lsu_dma_dma_lsc_ctl_dma_mem_sz = _T_1196 ? 3'h2 : dma_mem_sz_int; // @[dma_ctrl.scala 358:40]
assign io_lsu_dma_dma_lsc_ctl_dma_mem_write = _T_1179[0]; // @[dma_ctrl.scala 356:40] assign io_lsu_dma_dma_lsc_ctl_dma_mem_write = _T_1199[0]; // @[dma_ctrl.scala 360:40]
assign io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = 3'h4 == RdPtr ? fifo_data_4 : _GEN_77; // @[dma_ctrl.scala 357:40] assign io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = 3'h4 == RdPtr ? fifo_data_4 : _GEN_77; // @[dma_ctrl.scala 361:40]
assign io_lsu_dma_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 499:40] assign io_lsu_dma_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 503:40]
assign io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 500:41] assign io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 504:41]
assign io_lsu_dma_dma_mem_tag = RdPtr; // @[dma_ctrl.scala 350:28] assign io_lsu_dma_dma_mem_tag = RdPtr; // @[dma_ctrl.scala 354:28]
assign io_ifu_dma_dma_ifc_dma_iccm_stall_any = _T_1120 & _T_1118; // @[dma_ctrl.scala 329:41] assign io_ifu_dma_dma_ifc_dma_iccm_stall_any = _T_1140 & _T_1138; // @[dma_ctrl.scala 333:41]
assign io_ifu_dma_dma_mem_ctl_dma_iccm_req = _T_1120 & io_iccm_ready; // @[dma_ctrl.scala 349:40] assign io_ifu_dma_dma_mem_ctl_dma_iccm_req = _T_1140 & io_iccm_ready; // @[dma_ctrl.scala 353:40]
assign io_ifu_dma_dma_mem_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 502:39] assign io_ifu_dma_dma_mem_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 506:39]
assign io_ifu_dma_dma_mem_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[dma_ctrl.scala 501:37] assign io_ifu_dma_dma_mem_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[dma_ctrl.scala 505:37]
assign io_ifu_dma_dma_mem_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 504:40] assign io_ifu_dma_dma_mem_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 508:40]
assign io_ifu_dma_dma_mem_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 503:40] assign io_ifu_dma_dma_mem_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 507:40]
assign io_ifu_dma_dma_mem_ctl_dma_mem_tag = io_lsu_dma_dma_mem_tag; // @[dma_ctrl.scala 505:38] assign io_ifu_dma_dma_mem_ctl_dma_mem_tag = io_lsu_dma_dma_mem_tag; // @[dma_ctrl.scala 509:38]
assign rvclkhdr_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_io_clk = clock; // @[lib.scala 354:18]
assign rvclkhdr_io_en = fifo_cmd_en[0]; // @[lib.scala 355:17] assign rvclkhdr_io_en = fifo_cmd_en[0]; // @[lib.scala 355:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
@ -929,15 +948,15 @@ module dma_ctrl(
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_9_io_clk = clock; // @[lib.scala 354:18]
assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[lib.scala 355:17] assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[lib.scala 355:17]
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
assign dma_buffer_c1cgc_io_clk = clock; // @[dma_ctrl.scala 388:33] assign dma_buffer_c1cgc_io_clk = clock; // @[dma_ctrl.scala 392:33]
assign dma_buffer_c1cgc_io_en = _T_1193 | io_clk_override; // @[dma_ctrl.scala 386:33] assign dma_buffer_c1cgc_io_en = _T_1213 | io_clk_override; // @[dma_ctrl.scala 390:33]
assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 387:33] assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 391:33]
assign dma_free_cgc_io_clk = clock; // @[dma_ctrl.scala 394:29] assign dma_free_cgc_io_clk = clock; // @[dma_ctrl.scala 398:29]
assign dma_free_cgc_io_en = _T_1199 | io_clk_override; // @[dma_ctrl.scala 392:29] assign dma_free_cgc_io_en = _T_1219 | io_clk_override; // @[dma_ctrl.scala 396:29]
assign dma_free_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 393:29] assign dma_free_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 397:29]
assign dma_bus_cgc_io_clk = clock; // @[dma_ctrl.scala 400:28] assign dma_bus_cgc_io_clk = clock; // @[dma_ctrl.scala 404:28]
assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 398:28] assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 402:28]
assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 399:28] assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 403:28]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 354:18]
assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 355:17] assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 355:17]
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
@ -1452,21 +1471,21 @@ end // initial
if (reset) begin if (reset) begin
wrbuf_vld <= 1'h0; wrbuf_vld <= 1'h0;
end else begin end else begin
wrbuf_vld <= _T_1204 & _T_1205; wrbuf_vld <= _T_1224 & _T_1225;
end end
end end
always @(posedge dma_bus_clk or posedge reset) begin always @(posedge dma_bus_clk or posedge reset) begin
if (reset) begin if (reset) begin
wrbuf_data_vld <= 1'h0; wrbuf_data_vld <= 1'h0;
end else begin end else begin
wrbuf_data_vld <= _T_1208 & _T_1209; wrbuf_data_vld <= _T_1228 & _T_1229;
end end
end end
always @(posedge dma_bus_clk or posedge reset) begin always @(posedge dma_bus_clk or posedge reset) begin
if (reset) begin if (reset) begin
rdbuf_vld <= 1'h0; rdbuf_vld <= 1'h0;
end else begin end else begin
rdbuf_vld <= _T_1217 & _T_1218; rdbuf_vld <= _T_1237 & _T_1238;
end end
end end
always @(posedge dma_bus_clk or posedge reset) begin always @(posedge dma_bus_clk or posedge reset) begin
@ -1515,7 +1534,7 @@ end // initial
if (reset) begin if (reset) begin
fifo_full <= 1'h0; fifo_full <= 1'h0;
end else begin end else begin
fifo_full <= num_fifo_vld_tmp2 >= 4'h5; fifo_full <= num_fifo_vld >= 4'h5;
end end
end end
always @(posedge dma_bus_clk or posedge reset) begin always @(posedge dma_bus_clk or posedge reset) begin
@ -1864,10 +1883,10 @@ end // initial
end else if (fifo_cmd_en[0]) begin end else if (fifo_cmd_en[0]) begin
if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
_T_850 <= io_dbg_dma_dbg_ib_dbg_cmd_write; _T_850 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
end else if (_T_1241) begin end else if (_T_1261) begin
_T_850 <= axi_mstr_priority; _T_850 <= axi_mstr_priority;
end else begin end else begin
_T_850 <= _T_1240; _T_850 <= _T_1260;
end end
end end
end end
@ -1877,10 +1896,10 @@ end // initial
end else if (fifo_cmd_en[1]) begin end else if (fifo_cmd_en[1]) begin
if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
_T_852 <= io_dbg_dma_dbg_ib_dbg_cmd_write; _T_852 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
end else if (_T_1241) begin end else if (_T_1261) begin
_T_852 <= axi_mstr_priority; _T_852 <= axi_mstr_priority;
end else begin end else begin
_T_852 <= _T_1240; _T_852 <= _T_1260;
end end
end end
end end
@ -1890,10 +1909,10 @@ end // initial
end else if (fifo_cmd_en[2]) begin end else if (fifo_cmd_en[2]) begin
if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
_T_854 <= io_dbg_dma_dbg_ib_dbg_cmd_write; _T_854 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
end else if (_T_1241) begin end else if (_T_1261) begin
_T_854 <= axi_mstr_priority; _T_854 <= axi_mstr_priority;
end else begin end else begin
_T_854 <= _T_1240; _T_854 <= _T_1260;
end end
end end
end end
@ -1903,10 +1922,10 @@ end // initial
end else if (fifo_cmd_en[3]) begin end else if (fifo_cmd_en[3]) begin
if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
_T_856 <= io_dbg_dma_dbg_ib_dbg_cmd_write; _T_856 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
end else if (_T_1241) begin end else if (_T_1261) begin
_T_856 <= axi_mstr_priority; _T_856 <= axi_mstr_priority;
end else begin end else begin
_T_856 <= _T_1240; _T_856 <= _T_1260;
end end
end end
end end
@ -2059,10 +2078,10 @@ end // initial
if (reset) begin if (reset) begin
dma_nack_count <= 3'h0; dma_nack_count <= 3'h0;
end else if (dma_mem_req) begin end else if (dma_mem_req) begin
if (_T_1118) begin if (_T_1138) begin
dma_nack_count <= _T_1131; dma_nack_count <= _T_1151;
end else if (_T_1135) begin end else if (_T_1155) begin
dma_nack_count <= _T_1138; dma_nack_count <= _T_1158;
end else begin end else begin
dma_nack_count <= 3'h0; dma_nack_count <= 3'h0;
end end

20165
quasar_wrapper.fir
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File diff suppressed because it is too large Load Diff

7634
quasar_wrapper.v
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File diff suppressed because it is too large Load Diff

7
src/main/scala/dbg/dbg.scala
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@ -235,7 +235,7 @@ class dbg extends Module with lib with RequireAsyncReset {
val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted) val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted)
val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0)) val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0))
val command_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) { val command_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) {
RegEnable(command_din, 0.U, command_wren) rvdffe(command_din, command_wren,clock,io.scan_mode)
} // dmcommand_reg } // dmcommand_reg
val data0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h4".U) & (dbg_state === state_t.halted) val data0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h4".U) & (dbg_state === state_t.halted)
@ -244,7 +244,7 @@ class dbg extends Module with lib with RequireAsyncReset {
val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1
val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata
val data0_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) { val data0_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) {
RegEnable(data0_din, 0.U, data0_reg_wren) rvdffe(data0_din,data0_reg_wren,clock,io.scan_mode)
} // dbg_data0_reg } // dbg_data0_reg
val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted)) val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted))
@ -450,6 +450,3 @@ class dbg extends Module with lib with RequireAsyncReset {
io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write
io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type
} }
object dbg extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
}

2
src/main/scala/dec/dec_tlu_ctl.scala
View File

@ -2127,7 +2127,7 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm
val dicad1_raw = WireInit(UInt(7.W),0.U) val dicad1_raw = WireInit(UInt(7.W),0.U)
val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1)
val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(70,64)) val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r(6,0), io.ifu_ic_debug_rd_data(70,64))
dicad1_raw := withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} dicad1_raw := withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)}
dicad1 := Cat(0.U(25.W), dicad1_raw) dicad1 := Cat(0.U(25.W), dicad1_raw)

8
src/main/scala/dma_ctrl.scala
View File

@ -294,7 +294,7 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
num_fifo_vld := num_fifo_vld_tmp + num_fifo_vld_tmp2 num_fifo_vld := num_fifo_vld_tmp + num_fifo_vld_tmp2
val fifo_full_spec = (num_fifo_vld_tmp2 >= DMA_BUF_DEPTH.asUInt()) val fifo_full_spec = (num_fifo_vld >= DMA_BUF_DEPTH.asUInt())
val dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus) val dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus)
@ -310,7 +310,11 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)), (io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)),
(dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)), (dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)),
(dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)), (dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)),
(dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)))) =/= 15.U)) | // Write byte enables not aligned for word store (dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)),
(dma_mem_addr_int(2,0) === 4.U) -> (dma_mem_byteen(7,4)),
(dma_mem_addr_int(2,0) === 5.U) -> (dma_mem_byteen(7,5)),
(dma_mem_addr_int(2,0) === 6.U) -> (dma_mem_byteen(7,6)),
(dma_mem_addr_int(2,0) === 7.U) -> (dma_mem_byteen(7)))) =/= "hf".U)) | // Write byte enables not aligned for word store
(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store (io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store

20
src/main/scala/ifu/ifu.scala
View File

@ -13,16 +13,14 @@ class ifu extends Module with lib with RequireAsyncReset {
val exu_flush_path_final = Input(UInt(31.W)) val exu_flush_path_final = Input(UInt(31.W))
val free_clk = Input(Clock()) val free_clk = Input(Clock())
val active_clk = Input(Clock()) val active_clk = Input(Clock())
val ifu_dec = new ifu_dec() val ifu_dec = new ifu_dec() // IFU and DEC interconnects
val exu_ifu = new exu_ifu() val exu_ifu = new exu_ifu() // IFU and EXU interconnects
val iccm = new iccm_mem() val iccm = new iccm_mem() // ICCM memory signals
val ic = new ic_mem() val ic = new ic_mem() // I$ memory signals
// AXI Write Channel val ifu = new axi_channels(IFU_BUS_TAG) // AXI Write Channel
val ifu = new axi_channels(IFU_BUS_TAG)
val ifu_bus_clk_en = Input(Bool()) val ifu_bus_clk_en = Input(Bool())
// DMA signals val ifu_dma = new ifu_dma() // DMA signals
val ifu_dma = new ifu_dma() // ICCM DMA signals
// ICCM
val iccm_dma_ecc_error = Output(Bool()) val iccm_dma_ecc_error = Output(Bool())
val iccm_dma_rvalid = Output(Bool()) val iccm_dma_rvalid = Output(Bool())
val iccm_dma_rdata = Output(UInt(64.W)) val iccm_dma_rdata = Output(UInt(64.W))
@ -87,7 +85,8 @@ class ifu extends Module with lib with RequireAsyncReset {
bp_ctl.io.exu_bp <> io.exu_ifu.exu_bp bp_ctl.io.exu_bp <> io.exu_ifu.exu_bp
bp_ctl.io.exu_flush_final := io.exu_flush_final bp_ctl.io.exu_flush_final := io.exu_flush_final
bp_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb bp_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
// mem-ctl wiring
// mem-ctl Inputs
mem_ctl.io.free_clk := io.free_clk mem_ctl.io.free_clk := io.free_clk
mem_ctl.io.active_clk := io.active_clk mem_ctl.io.active_clk := io.active_clk
mem_ctl.io.exu_flush_final := io.exu_flush_final mem_ctl.io.exu_flush_final := io.exu_flush_final
@ -110,6 +109,7 @@ class ifu extends Module with lib with RequireAsyncReset {
mem_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb mem_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
mem_ctl.io.scan_mode := io.scan_mode mem_ctl.io.scan_mode := io.scan_mode
// DMA to the ICCM
io.iccm_dma_ecc_error := mem_ctl.io.iccm_dma_ecc_error io.iccm_dma_ecc_error := mem_ctl.io.iccm_dma_ecc_error
io.iccm_dma_rvalid := mem_ctl.io.iccm_dma_rvalid io.iccm_dma_rvalid := mem_ctl.io.iccm_dma_rvalid
io.iccm_dma_rdata := mem_ctl.io.iccm_dma_rdata io.iccm_dma_rdata := mem_ctl.io.iccm_dma_rdata

73
src/main/scala/ifu/ifu_aln_ctl.scala
View File

@ -8,27 +8,27 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
val io = IO(new Bundle{ val io = IO(new Bundle{
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val active_clk = Input(Clock()) val active_clk = Input(Clock())
val ifu_async_error_start = Input(Bool()) val ifu_async_error_start = Input(Bool()) // Error coming from mem-ctl
val iccm_rd_ecc_double_err = Input(Bool()) val iccm_rd_ecc_double_err = Input(Bool()) // ICCM double error coming from mem-ctl
val ic_access_fault_f = Input(Bool()) val ic_access_fault_f = Input(Bool()) // Access fault in I$
val ic_access_fault_type_f = Input(UInt(2.W)) val ic_access_fault_type_f = Input(UInt(2.W)) // Type of access fault occured
val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP
val ifu_bp_btb_target_f = Input(UInt(31.W)) val ifu_bp_btb_target_f = Input(UInt(31.W)) // Target for the instruction enqueue in the FP
val ifu_bp_poffset_f = Input(UInt(12.W)) val ifu_bp_poffset_f = Input(UInt(12.W)) // Offset to the current PC for branch
val ifu_bp_hist0_f = Input(UInt(2.W)) val ifu_bp_hist0_f = Input(UInt(2.W)) // History to EXU
val ifu_bp_hist1_f = Input(UInt(2.W)) val ifu_bp_hist1_f = Input(UInt(2.W)) // History to EXU
val ifu_bp_pc4_f = Input(UInt(2.W)) val ifu_bp_pc4_f = Input(UInt(2.W)) // PC4
val ifu_bp_way_f = Input(UInt(2.W)) val ifu_bp_way_f = Input(UInt(2.W)) // Way to help in miss prediction
val ifu_bp_valid_f = Input(UInt(2.W)) val ifu_bp_valid_f = Input(UInt(2.W)) // Valid Branch prediction
val ifu_bp_ret_f = Input(UInt(2.W)) val ifu_bp_ret_f = Input(UInt(2.W)) // BP ret
val exu_flush_final = Input(Bool()) val exu_flush_final = Input(Bool()) // Miss prediction
val dec_aln = new dec_aln() val dec_aln = new dec_aln() // Data going to the dec from the ALN
val ifu_fetch_data_f = Input(UInt(32.W)) val ifu_fetch_data_f = Input(UInt(32.W)) // PC of the current instruction in the FP
val ifu_fetch_val = Input(UInt(2.W)) val ifu_fetch_val = Input(UInt(2.W)) // PC boundary i.e 'x' of 2 or 4
val ifu_fetch_pc = Input(UInt(31.W)) val ifu_fetch_pc = Input(UInt(31.W)) // Current PC
///////////////////////////////////////////////// /////////////////////////////////////////////////
val ifu_fb_consume1 = Output(Bool()) val ifu_fb_consume1 = Output(Bool()) // FP used 1
val ifu_fb_consume2 = Output(Bool()) val ifu_fb_consume2 = Output(Bool()) // FP used 2
}) })
val MHI = 46+BHT_GHR_SIZE // 54 val MHI = 46+BHT_GHR_SIZE // 54
@ -95,12 +95,16 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
val shift_2B = WireInit(Bool(), 0.U) val shift_2B = WireInit(Bool(), 0.U)
val f0_shift_2B = WireInit(Bool(), 0.U) val f0_shift_2B = WireInit(Bool(), 0.U)
// Stall if there is an error in the instrucion
error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
// Flop the stall until flush
error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)} error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
// Write Ptr of the FP
val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)} val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
// Read Ptr of the FP
val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)} val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)}
// Fetch Instruction boundary
val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)} val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)} val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)} val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
@ -108,30 +112,34 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)} val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)} val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)} val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
// Instrution PC to the FP
val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode) val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode)
val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode) val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode)
val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode) val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode)
// Branch data to the FP
brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode) brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode)
brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode) brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode)
brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode) brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode)
// Miscalanious data to the FP including error's
misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode) misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode)
misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode) misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode)
misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode) misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode)
// Instruction in the FP
q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode) q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode)
q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode) q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode)
q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode) q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode)
// Shift FP logic
f2_wr_en := fetch_to_f2 f2_wr_en := fetch_to_f2
f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B
f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
// FP read enable .. 3-bit for Implemenation of 1HMux
val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U) val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
// FP write enable .. 3-bit for Implemenation of 1HMux
qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid) qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
// Read Pointer calculation
// Next rdptr = # of consume + current ptr location (Rounding it from 2)
rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U, rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
(qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U, (qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
(qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U, (qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U,
@ -140,6 +148,7 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
(qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U, (qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U,
(!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr)) (!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr))
// As there is only 1 enqueue so each time move by 1
wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U, wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U,
(qwen(1) & !io.exu_flush_final).asBool -> 2.U, (qwen(1) & !io.exu_flush_final).asBool -> 2.U,
(qwen(2) & !io.exu_flush_final).asBool -> 0.U, (qwen(2) & !io.exu_flush_final).asBool -> 0.U,
@ -166,7 +175,7 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
val q0sel = Cat(q0ptr, !q0ptr) val q0sel = Cat(q0ptr, !q0ptr)
val q1sel = Cat(q1ptr, !q1ptr) val q1sel = Cat(q1ptr, !q1ptr)
// Misc data error, access-fault, type of fault, target, offset and ghr value
misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f, misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f,
io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f) io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
@ -192,10 +201,11 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE) val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0) val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
// Branch information
brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1), brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0), io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0)) io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
// Effective branch information
val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0), val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0),
qren(1).asBool->Cat(brdata2,brdata1), qren(1).asBool->Cat(brdata2,brdata1),
qren(2).asBool->Cat(brdata0,brdata2))) qren(2).asBool->Cat(brdata0,brdata2)))
@ -227,11 +237,13 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
val consume_fb0 = !sf0val(0) & f0val(0) val consume_fb0 = !sf0val(0) & f0val(0)
val consume_fb1 = !sf1val(0) & f1val(0) val consume_fb1 = !sf1val(0) & f1val(0)
// Depending on type of instruction and boundary determine how many FP to consume
io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final
io.ifu_fb_consume2 := consume_fb0 & consume_fb1 & !io.exu_flush_final io.ifu_fb_consume2 := consume_fb0 & consume_fb1 & !io.exu_flush_final
ifvalid := io.ifu_fetch_val(0) ifvalid := io.ifu_fetch_val(0)
// Shift logic for each dequeue
shift_f1_f0 := !sf0_valid & sf1_valid shift_f1_f0 := !sf0_valid & sf1_valid
shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid
shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid
@ -285,6 +297,7 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16))) q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16)))
// Alinging the data according to the boundary of PC
val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0)))) val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0))))
alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U))) alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U)))
@ -317,6 +330,7 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
io.dec_aln.aln_dec.ifu_i0_cinst := aligndata(15,0) io.dec_aln.aln_dec.ifu_i0_cinst := aligndata(15,0)
// Instruction is compressed or not
first4B := aligndata(1,0) === 3.U first4B := aligndata(1,0) === 3.U
val first2B = ~first4B val first2B = ~first4B
@ -334,11 +348,12 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0))) io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0)))
val ifirst = aligndata val ifirst = aligndata
// Expander from 16-bit to 32-bit
val decompressed = Module(new ifu_compress_ctl()) val decompressed = Module(new ifu_compress_ctl())
io.dec_aln.aln_ib.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout)) io.dec_aln.aln_ib.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout))
// Hashing the PC
val firstpc_hash = btb_addr_hash(f0pc) val firstpc_hash = btb_addr_hash(f0pc)
val secondpc_hash = btb_addr_hash(secondpc) val secondpc_hash = btb_addr_hash(secondpc)

39
src/main/scala/ifu/ifu_ifc_ctl.scala
View File

@ -7,32 +7,32 @@ import chisel3.util._
class ifu_ifc_ctl extends Module with lib with RequireAsyncReset { class ifu_ifc_ctl extends Module with lib with RequireAsyncReset {
val io = IO(new Bundle{ val io = IO(new Bundle{
val exu_flush_final = Input(Bool()) val exu_flush_final = Input(Bool()) // Miss Prediction for EXU
val exu_flush_path_final = Input(UInt(31.W)) val exu_flush_path_final = Input(UInt(31.W)) // Replay PC
val free_clk = Input(Clock()) val free_clk = Input(Clock())
val active_clk = Input(Clock()) val active_clk = Input(Clock())
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val ic_hit_f = Input(Bool()) val ic_hit_f = Input(Bool())
val ifu_ic_mb_empty = Input(Bool()) val ifu_ic_mb_empty = Input(Bool()) // Miss buffer of mem-ctl empty
val ifu_fb_consume1 = Input(Bool()) val ifu_fb_consume1 = Input(Bool()) // Consume 1 fetch from FP
val ifu_fb_consume2 = Input(Bool()) val ifu_fb_consume2 = Input(Bool()) // Consume 2 fetch from FP
val ifu_bp_hit_taken_f = Input(Bool()) val ifu_bp_hit_taken_f = Input(Bool()) // Branch taken from BP
val ifu_bp_btb_target_f = Input(UInt(31.W)) val ifu_bp_btb_target_f = Input(UInt(31.W)) // Predicted PC
val ic_dma_active = Input(Bool()) val ic_dma_active = Input(Bool()) // DMA for I$
val ic_write_stall = Input(Bool()) val ic_write_stall = Input(Bool())
val dec_ifc = new dec_ifc() val dec_ifc = new dec_ifc() // DEC to IFC Bundle
val dma_ifc = new dma_ifc() val dma_ifc = new dma_ifc() // DMA to IFC Bundle
val ifc_fetch_addr_f = Output(UInt(31.W)) val ifc_fetch_addr_f = Output(UInt(31.W)) // Previous PC
val ifc_fetch_addr_bf = Output(UInt(31.W)) val ifc_fetch_addr_bf = Output(UInt(31.W)) // Next PC
val ifc_fetch_req_f = Output(Bool()) val ifc_fetch_req_f = Output(Bool()) // Fetch State
val ifc_fetch_uncacheable_bf = Output(Bool()) val ifc_fetch_uncacheable_bf = Output(Bool()) // Fetch req for uncacheable
val ifc_fetch_req_bf = Output(Bool()) val ifc_fetch_req_bf = Output(Bool())
val ifc_fetch_req_bf_raw = Output(Bool()) val ifc_fetch_req_bf_raw = Output(Bool())
val ifc_iccm_access_bf = Output(Bool()) val ifc_iccm_access_bf = Output(Bool()) // ICCM access
val ifc_region_acc_fault_bf = Output(Bool()) val ifc_region_acc_fault_bf = Output(Bool()) // Region access fault
val ifc_dma_access_ok = Output(Bool()) val ifc_dma_access_ok = Output(Bool()) // DMA accesing
}) })
val fetch_addr_bf = WireInit(UInt(31.W), init = 0.U) val fetch_addr_bf = WireInit(UInt(31.W), init = 0.U)
@ -69,6 +69,7 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset {
val sel_next_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f val sel_next_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f
// TODO: Make an assertion for the 1H-Mux under here // TODO: Make an assertion for the 1H-Mux under here
// Next PC calculation
io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC
sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC
sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC
@ -77,6 +78,7 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset {
val address_upper = io.ifc_fetch_addr_f(30,1)+1.U val address_upper = io.ifc_fetch_addr_f(30,1)+1.U
fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-2) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0) fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-2) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
// Next PC to check from which boundary it is comming from
fetch_addr_next := Cat(address_upper, fetch_addr_next_0) fetch_addr_next := Cat(address_upper, fetch_addr_next_0)
io.ifc_fetch_req_bf_raw := ~idle io.ifc_fetch_req_bf_raw := ~idle
@ -103,12 +105,14 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset {
flush_fb := io.exu_flush_final flush_fb := io.exu_flush_final
// Checking FP for PMU
fb_right := ( io.ifu_fb_consume1 & !io.ifu_fb_consume2 & (!io.ifc_fetch_req_f | miss_f)) | fb_right := ( io.ifu_fb_consume1 & !io.ifu_fb_consume2 & (!io.ifc_fetch_req_f | miss_f)) |
(io.ifu_fb_consume2 & io.ifc_fetch_req_f) (io.ifu_fb_consume2 & io.ifc_fetch_req_f)
fb_right2 := (io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)) fb_right2 := (io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f))
fb_left := io.ifc_fetch_req_f & !(io.ifu_fb_consume1 | io.ifu_fb_consume2) & !miss_f fb_left := io.ifc_fetch_req_f & !(io.ifu_fb_consume1 | io.ifu_fb_consume2) & !miss_f
// Shifting the fb to remember the FP state
fb_write_ns := Mux1H(Seq(flush_fb.asBool -> 1.U(4.W), fb_write_ns := Mux1H(Seq(flush_fb.asBool -> 1.U(4.W),
(!flush_fb & fb_right).asBool -> Cat(0.U(1.W), fb_write_f(3,1)), (!flush_fb & fb_right).asBool -> Cat(0.U(1.W), fb_write_f(3,1)),
(!flush_fb & fb_right2).asBool -> Cat(0.U(2.W), fb_write_f(3,2)), (!flush_fb & fb_right2).asBool -> Cat(0.U(2.W), fb_write_f(3,2)),
@ -126,6 +130,7 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset {
io.dec_ifc.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw & io.dec_ifc.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw &
((fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall)) ((fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
// Checking the next PC range and its region to access the ICCM or I$
val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE) val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE)
rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U)) rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U))
else (0.U, 0.U) else (0.U, 0.U)

74
src/main/scala/ifu/ifu_mem_ctl.scala
View File

@ -54,26 +54,7 @@ class mem_ctl_io extends Bundle with lib{
class ifu_mem_ctl extends Module with lib with RequireAsyncReset { class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
val io = IO(new mem_ctl_io) val io = IO(new mem_ctl_io)
io.ifu_axi.w.valid := 0.U
io.ifu_axi.w.bits.data := 0.U
io.ifu_axi.aw.bits.qos := 0.U
io.ifu_axi.aw.bits.addr := 0.U
io.ifu_axi.aw.bits.prot := 0.U
io.ifu_axi.aw.bits.len := 0.U
io.ifu_axi.ar.bits.lock := 0.U
io.ifu_axi.aw.bits.region := 0.U
io.ifu_axi.aw.bits.id := 0.U
io.ifu_axi.aw.valid := 0.U
io.ifu_axi.w.bits.strb := 0.U
io.ifu_axi.aw.bits.cache := 0.U
io.ifu_axi.ar.bits.qos := 0.U
io.ifu_axi.aw.bits.lock := 0.U
io.ifu_axi.b.ready := 0.U
io.ifu_axi.ar.bits.len := 0.U
io.ifu_axi.aw.bits.size := 0.U
io.ifu_axi.ar.bits.prot := 0.U
io.ifu_axi.aw.bits.burst := 0.U
io.ifu_axi.w.bits.last := 0.U
val idle_C :: crit_byp_ok_C :: hit_u_miss_C :: miss_wait_C :: crit_wrd_rdy_C :: scnd_miss_C :: stream_C :: stall_scnd_miss_C :: Nil = Enum(8) val idle_C :: crit_byp_ok_C :: hit_u_miss_C :: miss_wait_C :: crit_wrd_rdy_C :: scnd_miss_C :: stream_C :: stall_scnd_miss_C :: Nil = Enum(8)
val err_stop_idle_C :: err_fetch1_C :: err_fetch2_C :: err_stop_fetch_C :: Nil = Enum(4) val err_stop_idle_C :: err_fetch1_C :: err_fetch2_C :: err_stop_fetch_C :: Nil = Enum(4)
val err_idle_C :: ic_wff_C :: ecc_wff_C :: ecc_cor_C :: dma_sb_err_C :: Nil = Enum(5) val err_idle_C :: ic_wff_C :: ecc_wff_C :: ecc_cor_C :: dma_sb_err_C :: Nil = Enum(5)
@ -104,6 +85,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
val ic_miss_under_miss_f = WireInit(Bool(), false.B) val ic_miss_under_miss_f = WireInit(Bool(), false.B)
val ic_ignore_2nd_miss_f = WireInit(Bool(), false.B) val ic_ignore_2nd_miss_f = WireInit(Bool(), false.B)
val ic_debug_rd_en_ff = WireInit(Bool(), false.B) val ic_debug_rd_en_ff = WireInit(Bool(), false.B)
val debug_data_clk = rvclkhdr(clock, ic_debug_rd_en_ff, io.scan_mode) val debug_data_clk = rvclkhdr(clock, ic_debug_rd_en_ff, io.scan_mode)
val flush_final_f = withClock(io.free_clk){RegNext(io.exu_flush_final, 0.U)} val flush_final_f = withClock(io.free_clk){RegNext(io.exu_flush_final, 0.U)}
val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req
@ -120,11 +102,11 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
val ifu_bp_hit_taken_q_f = io.ifu_bp_hit_taken_f & io.ic_hit_f val ifu_bp_hit_taken_q_f = io.ifu_bp_hit_taken_f & io.ic_hit_f
///////////////////////////////// MISS FSM ///////////////////////////////// ///////////////////////////////// MISS FSM /////////////////////////////////
switch(miss_state){ switch(miss_state){
is (idle_C){ is (idle_C){ // Idle meaning there is not pending miss
miss_nxtstate := Mux((ic_act_miss_f & !io.exu_flush_final).asBool, crit_byp_ok_C, hit_u_miss_C) miss_nxtstate := Mux((ic_act_miss_f & !io.exu_flush_final).asBool, crit_byp_ok_C, hit_u_miss_C)
miss_state_en := ic_act_miss_f & !io.dec_mem_ctrl.dec_tlu_force_halt} miss_state_en := ic_act_miss_f & !io.dec_mem_ctrl.dec_tlu_force_halt}
is (crit_byp_ok_C){ is (crit_byp_ok_C){ // Miss started meaning each beat is checked if, it is the critical word
miss_nxtstate := Mux((io.dec_mem_ctrl.dec_tlu_force_halt | (ic_byp_hit_f & (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) & uncacheable_miss_ff)).asBool, idle_C, miss_nxtstate := Mux((io.dec_mem_ctrl.dec_tlu_force_halt | (ic_byp_hit_f & (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) & uncacheable_miss_ff)).asBool, idle_C,
Mux((ic_byp_hit_f & !last_data_recieved_ff & uncacheable_miss_ff).asBool, miss_wait_C, Mux((ic_byp_hit_f & !last_data_recieved_ff & uncacheable_miss_ff).asBool, miss_wait_C,
Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & uncacheable_miss_ff).asBool, crit_wrd_rdy_C, Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & uncacheable_miss_ff).asBool, crit_wrd_rdy_C,
@ -135,35 +117,36 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C)))))))) Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C))))))))
miss_state_en := io.dec_mem_ctrl.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff) miss_state_en := io.dec_mem_ctrl.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff)
} }
is (crit_wrd_rdy_C){ is (crit_wrd_rdy_C){ // Critical word hit but not complete, its going to be available in next cycle
miss_nxtstate := idle_C miss_nxtstate := idle_C
miss_state_en := io.exu_flush_final | flush_final_f | ic_byp_hit_f | io.dec_mem_ctrl.dec_tlu_force_halt miss_state_en := io.exu_flush_final | flush_final_f | ic_byp_hit_f | io.dec_mem_ctrl.dec_tlu_force_halt
} }
is (stream_C){ is (stream_C){ // The miss was a miss of uncacheable range
miss_nxtstate := Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f)&(!(bus_ifu_wr_en_ff & last_beat)) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C) miss_nxtstate := Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f)&(!(bus_ifu_wr_en_ff & last_beat)) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C)
miss_state_en := io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f | (bus_ifu_wr_en_ff & last_beat) | io.dec_mem_ctrl.dec_tlu_force_halt miss_state_en := io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f | (bus_ifu_wr_en_ff & last_beat) | io.dec_mem_ctrl.dec_tlu_force_halt
} }
is (miss_wait_C){ is (miss_wait_C){ // Critial word hit but the miss is not complete
miss_nxtstate := Mux((io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C) miss_nxtstate := Mux((io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C)
miss_state_en := io.exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | io.dec_mem_ctrl.dec_tlu_force_halt miss_state_en := io.exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | io.dec_mem_ctrl.dec_tlu_force_halt
} }
is (hit_u_miss_C){ is (hit_u_miss_C){ // The critical word was a hit taken, or miss due to a miss predicted pc occured
miss_nxtstate := Mux((ic_miss_under_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, scnd_miss_C, miss_nxtstate := Mux((ic_miss_under_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, scnd_miss_C,
Mux((ic_ignore_2nd_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, stall_scnd_miss_C, idle_C)) Mux((ic_ignore_2nd_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, stall_scnd_miss_C, idle_C))
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | io.dec_mem_ctrl.dec_tlu_force_halt miss_state_en := (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | io.dec_mem_ctrl.dec_tlu_force_halt
} }
is (scnd_miss_C){ is (scnd_miss_C){ // Miss of the different pc occured
miss_nxtstate := Mux(io.dec_mem_ctrl.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final, miss_nxtstate := Mux(io.dec_mem_ctrl.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final,
Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), crit_byp_ok_C)) Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), crit_byp_ok_C))
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_force_halt miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_force_halt
} }
is (stall_scnd_miss_C){ is (stall_scnd_miss_C){ // Miss from the same pc occured
miss_nxtstate := Mux(io.dec_mem_ctrl.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final, miss_nxtstate := Mux(io.dec_mem_ctrl.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final,
Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), idle_C)) Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), idle_C))
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_force_halt miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_force_halt
} }
} }
miss_state := withClock(io.free_clk){RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)} miss_state := withClock(io.free_clk){RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)}
// Calculation all the relevant signals for the miss FSM
val crit_byp_hit_f = WireInit(Bool(), 0.U) val crit_byp_hit_f = WireInit(Bool(), 0.U)
val way_status_mb_scnd_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status_mb_scnd_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
@ -262,6 +245,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
sel_mb_addr_ff := withClock(io.free_clk){RegNext(sel_mb_addr, 0.U)} sel_mb_addr_ff := withClock(io.free_clk){RegNext(sel_mb_addr, 0.U)}
val ifu_bus_rdata_ff = WireInit(UInt(64.W), 0.U) val ifu_bus_rdata_ff = WireInit(UInt(64.W), 0.U)
val ic_miss_buff_half = WireInit(UInt(64.W), 0.U) val ic_miss_buff_half = WireInit(UInt(64.W), 0.U)
// Ecc of the read data from the AXI
val ic_wr_ecc = rvecc_encode_64(ifu_bus_rdata_ff) val ic_wr_ecc = rvecc_encode_64(ifu_bus_rdata_ff)
val ic_miss_buff_ecc = rvecc_encode_64(ic_miss_buff_half) val ic_miss_buff_ecc = rvecc_encode_64(ic_miss_buff_half)
val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U) val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U)
@ -271,6 +256,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
io.dec_mem_ctrl.ifu_ic_error_start := ((if(ICACHE_ECC)io.ic.eccerr.orR()else io.ic.parerr.orR()) & ic_act_hit_f) | ic_rd_parity_final_err io.dec_mem_ctrl.ifu_ic_error_start := ((if(ICACHE_ECC)io.ic.eccerr.orR()else io.ic.parerr.orR()) & ic_act_hit_f) | ic_rd_parity_final_err
val ic_debug_tag_val_rd_out = WireInit(Bool(), 0.U) val ic_debug_tag_val_rd_out = WireInit(Bool(), 0.U)
val ic_debug_ict_array_sel_ff = WireInit(Bool(), 0.U) val ic_debug_ict_array_sel_ff = WireInit(Bool(), 0.U)
val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ic.tag_debug_rd_data(25,21),0.U(32.W),io.ic.tag_debug_rd_data(20,0), 0.U((7-ICACHE_STATUS_BITS).W), way_status, 0.U(3.W),ic_debug_tag_val_rd_out) val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ic.tag_debug_rd_data(25,21),0.U(32.W),io.ic.tag_debug_rd_data(20,0), 0.U((7-ICACHE_STATUS_BITS).W), way_status, 0.U(3.W),ic_debug_tag_val_rd_out)
else Cat(0.U(6.W),io.ic.tag_debug_rd_data(21),0.U(32.W),io.ic.tag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) , else Cat(0.U(6.W),io.ic.tag_debug_rd_data(21),0.U(32.W),io.ic.tag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) ,
io.ic.debug_rd_data) io.ic.debug_rd_data)
@ -395,6 +381,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
ic_miss_buff_half := Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,1.U)===i.U).asBool->ic_miss_buff_data(i))), ic_miss_buff_half := Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,1.U)===i.U).asBool->ic_miss_buff_data(i))),
Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,0.U)===i.U).asBool->ic_miss_buff_data(i)))) Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,0.U)===i.U).asBool->ic_miss_buff_data(i))))
// Parity check for the I$ logic
ic_rd_parity_final_err := io.ic.tag_perr & sel_ic_data & !(ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f) ic_rd_parity_final_err := io.ic.tag_perr & sel_ic_data & !(ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f)
val ifu_ic_rw_int_addr_ff = WireInit(UInt((ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO+1).W), 0.U) val ifu_ic_rw_int_addr_ff = WireInit(UInt((ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO+1).W), 0.U)
@ -408,7 +395,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
io.iccm.buf_correct_ecc := iccm_correct_ecc & !dma_sb_err_state_ff io.iccm.buf_correct_ecc := iccm_correct_ecc & !dma_sb_err_state_ff
dma_sb_err_state_ff := withClock(io.active_clk){RegNext(dma_sb_err_state, false.B)} dma_sb_err_state_ff := withClock(io.active_clk){RegNext(dma_sb_err_state, false.B)}
///////////////////////////////// ERROR FSM ///////////////////////////////// ///////////////////////////////// PARITY ERROR FSM /////////////////////////////////
val perr_nxtstate = WireInit(UInt(3.W), 0.U) val perr_nxtstate = WireInit(UInt(3.W), 0.U)
val perr_state_en = WireInit(Bool(), false.B) val perr_state_en = WireInit(Bool(), false.B)
val iccm_error_start = WireInit(Bool(), false.B) val iccm_error_start = WireInit(Bool(), false.B)
@ -487,6 +474,26 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
val bus_cmd_req_in = (ic_act_miss_f | bus_cmd_req_hold) & !bus_cmd_sent & !io.dec_mem_ctrl.dec_tlu_force_halt val bus_cmd_req_in = (ic_act_miss_f | bus_cmd_req_hold) & !bus_cmd_sent & !io.dec_mem_ctrl.dec_tlu_force_halt
bus_cmd_req_hold := withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)} bus_cmd_req_hold := withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)}
// AXI Read-Channel // AXI Read-Channel
io.ifu_axi.w.valid := 0.U
io.ifu_axi.w.bits.data := 0.U
io.ifu_axi.aw.bits.qos := 0.U
io.ifu_axi.aw.bits.addr := 0.U
io.ifu_axi.aw.bits.prot := 0.U
io.ifu_axi.aw.bits.len := 0.U
io.ifu_axi.ar.bits.lock := 0.U
io.ifu_axi.aw.bits.region := 0.U
io.ifu_axi.aw.bits.id := 0.U
io.ifu_axi.aw.valid := 0.U
io.ifu_axi.w.bits.strb := 0.U
io.ifu_axi.aw.bits.cache := 0.U
io.ifu_axi.ar.bits.qos := 0.U
io.ifu_axi.aw.bits.lock := 0.U
io.ifu_axi.b.ready := 0.U
io.ifu_axi.ar.bits.len := 0.U
io.ifu_axi.aw.bits.size := 0.U
io.ifu_axi.ar.bits.prot := 0.U
io.ifu_axi.aw.bits.burst := 0.U
io.ifu_axi.w.bits.last := 0.U
io.ifu_axi.ar.valid := ifu_bus_cmd_valid io.ifu_axi.ar.valid := ifu_bus_cmd_valid
io.ifu_axi.ar.bits.id := bus_rd_addr_count & Fill(IFU_BUS_TAG, ifu_bus_cmd_valid) io.ifu_axi.ar.bits.id := bus_rd_addr_count & Fill(IFU_BUS_TAG, ifu_bus_cmd_valid)
io.ifu_axi.ar.bits.addr := Cat(ifu_ic_req_addr_f, 0.U(3.W)) & Fill(32, ifu_bus_cmd_valid) io.ifu_axi.ar.bits.addr := Cat(ifu_ic_req_addr_f, 0.U(3.W)) & Fill(32, ifu_bus_cmd_valid)
@ -516,6 +523,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
val ifu_bus_arready = ifu_bus_arready_unq & bus_ifu_bus_clk_en val ifu_bus_arready = ifu_bus_arready_unq & bus_ifu_bus_clk_en
val ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff val ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff
val ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff val ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff
// Write signals to write to the bus
bus_cmd_sent := ifu_bus_arvalid & ifu_bus_arready & miss_pending & !io.dec_mem_ctrl.dec_tlu_force_halt bus_cmd_sent := ifu_bus_arvalid & ifu_bus_arready & miss_pending & !io.dec_mem_ctrl.dec_tlu_force_halt
val bus_last_data_beat = WireInit(Bool(), false.B) val bus_last_data_beat = WireInit(Bool(), false.B)
val bus_inc_data_beat_cnt = bus_ifu_wr_en_ff & !bus_last_data_beat & !io.dec_mem_ctrl.dec_tlu_force_halt val bus_inc_data_beat_cnt = bus_ifu_wr_en_ff & !bus_last_data_beat & !io.dec_mem_ctrl.dec_tlu_force_halt
@ -594,7 +602,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
val ic_fetch_val_int_f = Cat(0.U(2.W), io.ic_fetch_val_f) val ic_fetch_val_int_f = Cat(0.U(2.W), io.ic_fetch_val_f)
val ic_fetch_val_shift_right = ic_fetch_val_int_f << ifu_fetch_addr_int_f(0) val ic_fetch_val_shift_right = ic_fetch_val_int_f << ifu_fetch_addr_int_f(0)
val iccm_rdmux_data = io.iccm.rd_data_ecc val iccm_rdmux_data = io.iccm.rd_data_ecc
// ICCM ECC Check logic
val iccm_ecc_word_enable = (0 until 2).map(i=>((ic_fetch_val_shift_right((2*i+1),(2*i)).orR & !io.exu_flush_final & sel_iccm_data) | iccm_dma_rvalid_in) & !io.dec_mem_ctrl.dec_tlu_core_ecc_disable).reverse.reduce(Cat(_,_)) val iccm_ecc_word_enable = (0 until 2).map(i=>((ic_fetch_val_shift_right((2*i+1),(2*i)).orR & !io.exu_flush_final & sel_iccm_data) | iccm_dma_rvalid_in) & !io.dec_mem_ctrl.dec_tlu_core_ecc_disable).reverse.reduce(Cat(_,_))
val ecc_decoded = (0 until 2).map(i=>rvecc_decode(iccm_ecc_word_enable(i), iccm_rdmux_data((39*i+31),(39*i)), iccm_rdmux_data((39*i+38),(39*i+32)), 0.U)) val ecc_decoded = (0 until 2).map(i=>rvecc_decode(iccm_ecc_word_enable(i), iccm_rdmux_data((39*i+31),(39*i)), iccm_rdmux_data((39*i+38),(39*i+32)), 0.U))
val iccm_corrected_ecc = Wire(Vec(2, UInt(7.W))) val iccm_corrected_ecc = Wire(Vec(2, UInt(7.W)))
@ -628,7 +636,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
io.ic.wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes) io.ic.wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes)
io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff))) io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff)))
reset_all_tags := withClock(io.active_clk){RegNext(io.dec_mem_ctrl.dec_tlu_fence_i_wb, false.B)} reset_all_tags := withClock(io.active_clk){RegNext(io.dec_mem_ctrl.dec_tlu_fence_i_wb, false.B)}
// I$ status and P-LRU
val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss
val ifu_status_wr_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array, io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), val ifu_status_wr_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array, io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3),
ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
@ -688,8 +696,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j => val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j =>
Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_)) Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
// Making a sudo LRU // Making sudo LRU
// val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, Bool()))
val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
if (ICACHE_NUM_WAYS == 4) { if (ICACHE_NUM_WAYS == 4) {
replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
@ -762,6 +769,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
ic_debug_ict_array_sel_ff := withClock(debug_c1_clk){RegNext(ic_debug_ict_array_sel_in, 0.U)} ic_debug_ict_array_sel_ff := withClock(debug_c1_clk){RegNext(ic_debug_ict_array_sel_in, 0.U)}
ic_debug_rd_en_ff := withClock(io.free_clk){RegNext(io.ic.debug_rd_en, false.B)} ic_debug_rd_en_ff := withClock(io.free_clk){RegNext(io.ic.debug_rd_en, false.B)}
io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegNext(ic_debug_rd_en_ff, 0.U)} io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegNext(ic_debug_rd_en_ff, 0.U)}
// Memory protection each access enable with its Mask
val ifc_region_acc_okay = !(Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR()) | val ifc_region_acc_okay = !(Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR()) |
(INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) | (INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) |
(INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) | (INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) |

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@ -58,6 +58,8 @@ class ahb_out extends Bundle{
val htrans = Output(UInt(2.W)) val htrans = Output(UInt(2.W))
val hwrite = Output(Bool()) // ahb bus write val hwrite = Output(Bool()) // ahb bus write
val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data
} }
class ahb_channel extends Bundle{ class ahb_channel extends Bundle{
val in = Input(new ahb_in) val in = Input(new ahb_in)

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