dma added
This commit is contained in:
waleed-lm
parent
0f1f134851
commit
2876baddb0
335
.idea/misc.xml
335
.idea/misc.xml
|
|
@ -4,6 +4,71 @@
|
||||||
<component name="SVCompilerDirectivesDefines">
|
<component name="SVCompilerDirectivesDefines">
|
||||||
<option name="define">
|
<option name="define">
|
||||||
<map>
|
<map>
|
||||||
|
<entry key="EL2_LOCAL_RAM_TEST_IO">
|
||||||
|
<value>
|
||||||
|
<Define>
|
||||||
|
<option name="definitions">
|
||||||
|
<list>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="668" />
|
||||||
|
<option name="replacementList" value="input logic WE, input logic ME, input logic CLK" />
|
||||||
|
<option name="source" value="mem_lib.sv" />
|
||||||
|
</Body>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
</Define>
|
||||||
|
</value>
|
||||||
|
</entry>
|
||||||
|
<entry key="EL2_RAM">
|
||||||
|
<value>
|
||||||
|
<Define>
|
||||||
|
<option name="definitions">
|
||||||
|
<list>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="788" />
|
||||||
|
<option name="parameters">
|
||||||
|
<list>
|
||||||
|
<Parameter>
|
||||||
|
<option name="name" value="depth" />
|
||||||
|
</Parameter>
|
||||||
|
<Parameter>
|
||||||
|
<option name="name" value="width" />
|
||||||
|
</Parameter>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="replacementList" value="module ram_``depth``x``width( input logic [$clog2(depth)-1:0] ADR, input logic [(width-1):0] D, output logic [(width-1):0] Q, `EL2_LOCAL_RAM_TEST_IO ); reg [(width-1):0] ram_core [(depth-1):0]; always @(posedge CLK) begin if (ME && WE) ram_core[ADR] = D; if (ME && ~WE) Q <= ram_core[ADR]; end endmodule" />
|
||||||
|
<option name="source" value="mem_lib.sv" />
|
||||||
|
</Body>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
</Define>
|
||||||
|
</value>
|
||||||
|
</entry>
|
||||||
|
<entry key="EL2_RAM_BE">
|
||||||
|
<value>
|
||||||
|
<Define>
|
||||||
|
<option name="definitions">
|
||||||
|
<list>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="1437" />
|
||||||
|
<option name="parameters">
|
||||||
|
<list>
|
||||||
|
<Parameter>
|
||||||
|
<option name="name" value="depth" />
|
||||||
|
</Parameter>
|
||||||
|
<Parameter>
|
||||||
|
<option name="name" value="width" />
|
||||||
|
</Parameter>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="replacementList" value="module ram_be_``depth``x``width( input logic [$clog2(depth)-1:0] ADR, input logic [(width-1):0] D, WEM, output logic [(width-1):0] Q, `EL2_LOCAL_RAM_TEST_IO ); reg [(width-1):0] ram_core [(depth-1):0]; always @(posedge CLK) begin if (ME && WE) ram_core[ADR] = D & WEM | ~WEM & ram_core[ADR]; if (ME && ~WE) Q <= ram_core[ADR]; end endmodule" />
|
||||||
|
<option name="source" value="mem_lib.sv" />
|
||||||
|
</Body>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
</Define>
|
||||||
|
</value>
|
||||||
|
</entry>
|
||||||
<entry key="RANDOM">
|
<entry key="RANDOM">
|
||||||
<value>
|
<value>
|
||||||
<Define>
|
<Define>
|
||||||
|
|
@ -84,6 +149,31 @@
|
||||||
<option name="replacementList" value="$random" />
|
<option name="replacementList" value="$random" />
|
||||||
<option name="source" value="el2_ifu_mem_ctl.v" />
|
<option name="source" value="el2_ifu_mem_ctl.v" />
|
||||||
</Body>
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="44499" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="dbg.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="9623" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="lsu.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="55649" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="dma_ctrl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="151383" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="pic_ctrl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="198988" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="lsu_bus_buffer.v" />
|
||||||
|
</Body>
|
||||||
</list>
|
</list>
|
||||||
</option>
|
</option>
|
||||||
<option name="dependencies">
|
<option name="dependencies">
|
||||||
|
|
@ -98,6 +188,11 @@
|
||||||
<option value="el2_exu_alu_ctl.v" />
|
<option value="el2_exu_alu_ctl.v" />
|
||||||
<option value="el2_lsu.v" />
|
<option value="el2_lsu.v" />
|
||||||
<option value="el2_ifu_mem_ctl.v" />
|
<option value="el2_ifu_mem_ctl.v" />
|
||||||
|
<option value="dbg.v" />
|
||||||
|
<option value="lsu.v" />
|
||||||
|
<option value="dma_ctrl.v" />
|
||||||
|
<option value="pic_ctrl.v" />
|
||||||
|
<option value="lsu_bus_buffer.v" />
|
||||||
</set>
|
</set>
|
||||||
</option>
|
</option>
|
||||||
</Define>
|
</Define>
|
||||||
|
|
@ -828,6 +923,246 @@
|
||||||
<option name="offset" value="411331" />
|
<option name="offset" value="411331" />
|
||||||
<option name="source" value="el2_ifu_mem_ctl.v" />
|
<option name="source" value="el2_ifu_mem_ctl.v" />
|
||||||
</Body>
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="44300" />
|
||||||
|
<option name="source" value="dbg.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="44357" />
|
||||||
|
<option name="source" value="dbg.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_REG_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="44408" />
|
||||||
|
<option name="source" value="dbg.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_MEM_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="44459" />
|
||||||
|
<option name="source" value="dbg.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="9424" />
|
||||||
|
<option name="source" value="lsu.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="9481" />
|
||||||
|
<option name="source" value="lsu.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_REG_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="9532" />
|
||||||
|
<option name="source" value="lsu.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_MEM_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="9583" />
|
||||||
|
<option name="source" value="lsu.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="55450" />
|
||||||
|
<option name="source" value="dma_ctrl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="55507" />
|
||||||
|
<option name="source" value="dma_ctrl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_REG_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="55558" />
|
||||||
|
<option name="source" value="dma_ctrl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_MEM_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="55609" />
|
||||||
|
<option name="source" value="dma_ctrl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="151184" />
|
||||||
|
<option name="source" value="pic_ctrl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="151241" />
|
||||||
|
<option name="source" value="pic_ctrl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_REG_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="151292" />
|
||||||
|
<option name="source" value="pic_ctrl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_MEM_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="151343" />
|
||||||
|
<option name="source" value="pic_ctrl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="198789" />
|
||||||
|
<option name="source" value="lsu_bus_buffer.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="198846" />
|
||||||
|
<option name="source" value="lsu_bus_buffer.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_REG_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="198897" />
|
||||||
|
<option name="source" value="lsu_bus_buffer.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_MEM_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="198948" />
|
||||||
|
<option name="source" value="lsu_bus_buffer.v" />
|
||||||
|
</Body>
|
||||||
</list>
|
</list>
|
||||||
</option>
|
</option>
|
||||||
</Define>
|
</Define>
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<module external.linked.project.id="chisel-module-template-build" external.linked.project.path="$MODULE_DIR$/../../project" external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" sbt.imports="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.scala.xml.{TopScope=&gt;SUB:DOLLARscope}" sbt.resolvers="https://oss.sonatype.org/content/repositories/snapshots|maven|sonatype-snapshots, https://repo1.maven.org/maven2/|maven|public, https://oss.sonatype.org/content/repositories/releases|maven|sonatype-releases, file:/home/waleedbinehsan/.sbt/preloaded|maven|local-preloaded, /home/waleedbinehsan/.ivy2/cache|ivy|Local cache" type="SBT_MODULE" version="4">
|
<module external.linked.project.id="chisel-module-template-build" external.linked.project.path="$MODULE_DIR$/../../project" external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" sbt.imports="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.scala.xml.{TopScope=&gt;SUB:DOLLARscope}" sbt.resolvers="https://oss.sonatype.org/content/repositories/releases|maven|sonatype-releases, /home/abdulhameed.akram/.ivy2/cache|ivy|Local cache, https://oss.sonatype.org/content/repositories/snapshots|maven|sonatype-snapshots, file:/home/abdulhameed.akram/.sbt/preloaded|maven|local-preloaded, https://repo1.maven.org/maven2/|maven|public" type="SBT_MODULE" version="4">
|
||||||
<component name="NewModuleRootManager">
|
<component name="NewModuleRootManager">
|
||||||
<output url="file://$MODULE_DIR$/../../project/target/idea-classes" />
|
<output url="file://$MODULE_DIR$/../../project/target/idea-classes" />
|
||||||
<output-test url="file://$MODULE_DIR$/../../project/target/idea-test-classes" />
|
<output-test url="file://$MODULE_DIR$/../../project/target/idea-test-classes" />
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<module external.linked.project.id="quasar [file:/home/waleedbinehsan/Desktop/Quasar/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
|
<module external.linked.project.id="quasar [file:/home/abdulhameed.akram/Music/Quasar/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
|
||||||
<component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_1_8">
|
<component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_1_8">
|
||||||
<output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" />
|
<output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" />
|
||||||
<output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" />
|
<output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" />
|
||||||
|
|
|
||||||
|
|
@ -1 +1,3 @@
|
||||||
/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
|
/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
|
||||||
|
/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv
|
||||||
|
/home/waleedbinehsan/Desktop/Quasar/mem.sv
|
||||||
Binary file not shown.
|
|
@ -0,0 +1 @@
|
||||||
|
sbt.internal.DslEntry
|
||||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1 @@
|
||||||
|
sbt.internal.DslEntry
|
||||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1 @@
|
||||||
|
sbt.internal.DslEntry
|
||||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1 @@
|
||||||
|
sbt.internal.DslEntry
|
||||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1 @@
|
||||||
|
sbt.internal.DslEntry
|
||||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1 @@
|
||||||
|
sbt.internal.DslEntry
|
||||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1 @@
|
||||||
|
sbt.internal.DslEntry
|
||||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1 @@
|
||||||
|
sbt.internal.DslEntry
|
||||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1 @@
|
||||||
|
sbt.internal.DslEntry
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1 @@
|
||||||
|
sbt.internal.DslEntry
|
||||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1 @@
|
||||||
|
sbt.internal.DslEntry
|
||||||
Binary file not shown.
|
|
@ -1 +1 @@
|
||||||
-1177411650
|
1437988962
|
||||||
File diff suppressed because one or more lines are too long
|
|
@ -1 +1 @@
|
||||||
23355001
|
-1413115869
|
||||||
|
|
@ -1 +1 @@
|
||||||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-structure-extractor\",\"revision\":\"2018.2.1+4-88400d3f\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-shell\",\"revision\":\"2018.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-compiler-indices\",\"revision\":\"0.1.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"}}
|
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"}}
|
||||||
|
|
@ -1,3 +1,3 @@
|
||||||
[0m[[0m[0mdebug[0m] [0m[0m"not up to date. inChanged = true, force = false[0m
|
[debug] "not up to date. inChanged = true, force = false
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")...[0m
|
[debug] Updating ProjectRef(uri("file:/home/abdulhameed.akram/Music/Quasar/project/"), "quasar-build")...
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")[0m
|
[debug] Done updating ProjectRef(uri("file:/home/abdulhameed.akram/Music/Quasar/project/"), "quasar-build")
|
||||||
|
|
|
||||||
File diff suppressed because one or more lines are too long
|
|
@ -1 +1 @@
|
||||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/Quasar/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]]
|
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/abdulhameed.akram/Music/Quasar/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]]
|
||||||
File diff suppressed because one or more lines are too long
|
|
@ -1 +1 @@
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mFull compilation, no sources in previous analysis.[0m
|
[debug] Full compilation, no sources in previous analysis.
|
||||||
|
|
|
||||||
|
|
@ -1,2 +1,2 @@
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mCopy resource mappings: [0m
|
[debug] Copy resource mappings:
|
||||||
[0m[[0m[0mdebug[0m] [0m[0m [0m
|
[debug]
|
||||||
|
|
|
||||||
File diff suppressed because one or more lines are too long
|
|
@ -1 +1 @@
|
||||||
/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes
|
/home/abdulhameed.akram/Music/Quasar/project/target/scala-2.12/sbt-1.0/classes
|
||||||
|
|
|
||||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -1 +1 @@
|
||||||
/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar
|
/home/abdulhameed.akram/Music/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/abdulhameed.akram/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
|
||||||
|
|
|
||||||
|
|
@ -1 +1 @@
|
||||||
/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes
|
/home/abdulhameed.akram/Music/Quasar/project/target/scala-2.12/sbt-1.0/classes
|
||||||
|
|
|
||||||
|
|
@ -1 +1 @@
|
||||||
/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar
|
|
||||||
|
|
|
||||||
|
|
@ -1 +1 @@
|
||||||
/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar
|
/home/abdulhameed.akram/Music/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/abdulhameed.akram/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
|
||||||
|
|
|
||||||
|
|
@ -1 +1 @@
|
||||||
/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes
|
/home/abdulhameed.akram/Music/Quasar/project/target/scala-2.12/sbt-1.0/classes
|
||||||
|
|
|
||||||
|
|
@ -1 +1 @@
|
||||||
/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar
|
|
||||||
|
|
|
||||||
8816
quasar_wrapper.fir
8816
quasar_wrapper.fir
File diff suppressed because one or more lines are too long
6922
quasar_wrapper.v
6922
quasar_wrapper.v
File diff suppressed because it is too large
Load Diff
|
|
@ -311,7 +311,7 @@ class dbg extends Module with lib with RequireAsyncReset {
|
||||||
Fill(32, io.dmi_reg_addr === "h40".U) & haltsum0_reg | Fill(32, io.dmi_reg_addr === "h38".U) & sbcs_reg |
|
Fill(32, io.dmi_reg_addr === "h40".U) & haltsum0_reg | Fill(32, io.dmi_reg_addr === "h38".U) & sbcs_reg |
|
||||||
Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg |
|
Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg |
|
||||||
Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg
|
Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg
|
||||||
0
|
0
|
||||||
dbg_state := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l & temp_rst).asAsyncReset()) {
|
dbg_state := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l & temp_rst).asAsyncReset()) {
|
||||||
RegEnable(dbg_nxtstate, 0.U, dbg_state_en)
|
RegEnable(dbg_nxtstate, 0.U, dbg_state_en)
|
||||||
} // dbg_state_reg
|
} // dbg_state_reg
|
||||||
|
|
@ -450,3 +450,6 @@ class dbg extends Module with lib with RequireAsyncReset {
|
||||||
io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write
|
io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write
|
||||||
io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type
|
io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type
|
||||||
}
|
}
|
||||||
|
object dgb extends App {
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
|
||||||
|
}
|
||||||
|
|
@ -10,11 +10,13 @@ import lsu._
|
||||||
|
|
||||||
class dec_decode_ctl extends Module with lib with RequireAsyncReset{
|
class dec_decode_ctl extends Module with lib with RequireAsyncReset{
|
||||||
val io = IO(new Bundle{
|
val io = IO(new Bundle{
|
||||||
val decode_exu = Flipped(new decode_exu)
|
val decode_exu = Flipped(new decode_exu) //connection with exu top
|
||||||
val dec_alu = Flipped(new dec_alu)
|
val dec_alu = Flipped(new dec_alu) //connection with alu
|
||||||
val dec_div = Flipped(new dec_div)
|
val dec_div = Flipped(new dec_div) //connection with divider
|
||||||
val dctl_busbuff = Flipped(new dctl_busbuff())
|
val dctl_busbuff = Flipped(new dctl_busbuff()) //connection with bus buffer
|
||||||
val dctl_dma = new dctl_dma
|
val dctl_dma = new dctl_dma //connection with dma
|
||||||
|
val dec_aln = Flipped(new aln_dec) //connection with aligner
|
||||||
|
val dbg_dctl = new dbg_dctl() //connection with dbg
|
||||||
val dec_tlu_flush_extint = Input(Bool())
|
val dec_tlu_flush_extint = Input(Bool())
|
||||||
val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event
|
val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event
|
||||||
val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder
|
val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder
|
||||||
|
|
@ -88,12 +90,8 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
|
||||||
val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating
|
val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating
|
||||||
val dec_div_active = Output(Bool()) // non-block divide is active
|
val dec_div_active = Output(Bool()) // non-block divide is active
|
||||||
val scan_mode = Input(Bool())
|
val scan_mode = Input(Bool())
|
||||||
|
|
||||||
val dec_aln = Flipped(new aln_dec)
|
|
||||||
val dbg_dctl = new dbg_dctl()
|
|
||||||
})
|
})
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////
|
//packets zero initialization
|
||||||
// //packets zero initialization
|
|
||||||
io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p)
|
io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p)
|
||||||
// Vals defined
|
// Vals defined
|
||||||
val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U)
|
val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U)
|
||||||
|
|
@ -114,17 +112,16 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
|
||||||
val i0_rs2_class_d = Wire(new class_pkt_t)
|
val i0_rs2_class_d = Wire(new class_pkt_t)
|
||||||
val i0_rs1_depth_d = WireInit(UInt(2.W),0.U)
|
val i0_rs1_depth_d = WireInit(UInt(2.W),0.U)
|
||||||
val i0_rs2_depth_d = WireInit(UInt(2.W),0.U)
|
val i0_rs2_depth_d = WireInit(UInt(2.W),0.U)
|
||||||
val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
|
val cam_wen = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
|
||||||
val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
|
val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
|
||||||
val cam_write=WireInit(UInt(1.W), 0.U)
|
val cam_write = WireInit(UInt(1.W), 0.U)
|
||||||
val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
val cam_inv_reset_val = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||||
val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
val cam_data_reset_val = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||||
val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
val nonblock_load_write = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||||
val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
|
val cam_raw = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
|
||||||
val cam_in =Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
|
val cam_in = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
|
||||||
//val i0_temp = Wire(new inst_pkt_t)
|
val i0_dp = Wire(new dec_pkt_t)
|
||||||
val i0_dp= Wire(new dec_pkt_t)
|
val i0_dp_raw = Wire(new dec_pkt_t)
|
||||||
val i0_dp_raw= Wire(new dec_pkt_t)
|
|
||||||
val i0_rs1bypass = WireInit(UInt(3.W), 0.U)
|
val i0_rs1bypass = WireInit(UInt(3.W), 0.U)
|
||||||
val i0_rs2bypass = WireInit(UInt(3.W), 0.U)
|
val i0_rs2bypass = WireInit(UInt(3.W), 0.U)
|
||||||
val illegal_lockout = WireInit(UInt(1.W), 0.U)
|
val illegal_lockout = WireInit(UInt(1.W), 0.U)
|
||||||
|
|
@ -189,14 +186,13 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
|
||||||
(illegal_lockout_in ^ illegal_lockout ) // replaces active_clk
|
(illegal_lockout_in ^ illegal_lockout ) // replaces active_clk
|
||||||
|
|
||||||
|
|
||||||
val data_gate_clk= rvclkhdr(clock,data_gate_en.asBool(),io.scan_mode)
|
val data_gate_clk = rvclkhdr(clock,data_gate_en.asBool(),io.scan_mode)
|
||||||
|
// End - Data gating
|
||||||
// End - Data gating }}
|
|
||||||
|
|
||||||
val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode
|
val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode
|
||||||
io.decode_exu.dec_i0_predict_p_d.bits.misp :=0.U
|
io.decode_exu.dec_i0_predict_p_d.bits.misp := 0.U
|
||||||
io.decode_exu.dec_i0_predict_p_d.bits.ataken :=0.U
|
io.decode_exu.dec_i0_predict_p_d.bits.ataken := 0.U
|
||||||
io.decode_exu.dec_i0_predict_p_d.bits.boffset :=0.U
|
io.decode_exu.dec_i0_predict_p_d.bits.boffset := 0.U
|
||||||
io.decode_exu.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error
|
io.decode_exu.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error
|
||||||
io.decode_exu.dec_i0_predict_p_d.bits.pja := i0_pja
|
io.decode_exu.dec_i0_predict_p_d.bits.pja := i0_pja
|
||||||
io.decode_exu.dec_i0_predict_p_d.bits.pret := i0_pret
|
io.decode_exu.dec_i0_predict_p_d.bits.pret := i0_pret
|
||||||
|
|
@ -224,7 +220,6 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
|
||||||
// on i0 instruction fetch access fault turn anything into a nop
|
// on i0 instruction fetch access fault turn anything into a nop
|
||||||
// nop => alu rs1 imm12 rd lor
|
// nop => alu rs1 imm12 rd lor
|
||||||
val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d
|
val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d
|
||||||
|
|
||||||
val i0_instr_error = i0_icaf_d;
|
val i0_instr_error = i0_icaf_d;
|
||||||
i0_dp := i0_dp_raw
|
i0_dp := i0_dp_raw
|
||||||
when((i0_br_error_all | i0_instr_error).asBool){
|
when((i0_br_error_all | i0_instr_error).asBool){
|
||||||
|
|
@ -242,7 +237,6 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
|
||||||
|
|
||||||
// branches that can be predicted
|
// branches that can be predicted
|
||||||
val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
|
val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
|
||||||
|
|
||||||
val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
|
val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
|
||||||
val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
|
val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
|
||||||
val i0_ap_pc2 = !io.dec_i0_pc4_d
|
val i0_ap_pc2 = !io.dec_i0_pc4_d
|
||||||
|
|
|
||||||
|
|
@ -109,7 +109,6 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{
|
||||||
val target_mispredict = io.pp_in.bits.pret & (io.pp_in.bits.prett =/= aout(31,1)) //predicted return target != aout
|
val target_mispredict = io.pp_in.bits.pret & (io.pp_in.bits.prett =/= aout(31,1)) //predicted return target != aout
|
||||||
|
|
||||||
io.flush_upper_out := (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x & !io.dec_tlu_flush_lower_r
|
io.flush_upper_out := (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x & !io.dec_tlu_flush_lower_r
|
||||||
//there was no entire pipe flush (& previous cycle flush ofc(why check?)) therfore signAL 1 to flush instruction before X stage
|
|
||||||
io.flush_final_out := ( (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x ) | io.dec_tlu_flush_lower_r
|
io.flush_final_out := ( (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x ) | io.dec_tlu_flush_lower_r
|
||||||
//there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe
|
//there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -58,12 +58,10 @@ class ahb_out extends Bundle{
|
||||||
val htrans = Output(UInt(2.W))
|
val htrans = Output(UInt(2.W))
|
||||||
val hwrite = Output(Bool()) // ahb bus write
|
val hwrite = Output(Bool()) // ahb bus write
|
||||||
val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data
|
val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
class ahb_channel extends Bundle{
|
class ahb_channel extends Bundle{
|
||||||
val in = Input(new ahb_in)
|
val in = new ahb_in
|
||||||
val out = Output(new ahb_out)
|
val out = new ahb_out
|
||||||
}
|
}
|
||||||
class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{
|
class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{
|
||||||
val aw = Decoupled(new write_addr(BUS_TAG))
|
val aw = Decoupled(new write_addr(BUS_TAG))
|
||||||
|
|
|
||||||
|
|
@ -28,8 +28,8 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
|
||||||
// val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now)
|
// val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now)
|
||||||
// val ahb_hwrite = Input(Bool()) // ahb bus write
|
// val ahb_hwrite = Input(Bool()) // ahb bus write
|
||||||
// val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data
|
// val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data
|
||||||
val ahb_hsel = Input(Bool()) // this slave was selected
|
// val ahb_hsel = Input(Bool()) // this slave was selected
|
||||||
val ahb_hreadyin = Input(Bool()) // previous hready was accepted or not
|
// val ahb_hreadyin = Input(Bool()) // previous hready was accepted or not
|
||||||
// outputs
|
// outputs
|
||||||
val axi_awvalid = Output(Bool())
|
val axi_awvalid = Output(Bool())
|
||||||
val axi_awid = Output(UInt(TAG.W))
|
val axi_awid = Output(UInt(TAG.W))
|
||||||
|
|
@ -51,7 +51,10 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
|
||||||
val axi_arlen = Output(UInt(8.W))
|
val axi_arlen = Output(UInt(8.W))
|
||||||
val axi_arburst = Output(UInt(2.W))
|
val axi_arburst = Output(UInt(2.W))
|
||||||
val axi_rready = Output(Bool())
|
val axi_rready = Output(Bool())
|
||||||
val ahb = Flipped(new ahb_channel())
|
val ahb = new Bundle{
|
||||||
|
val sig = Flipped(new ahb_channel())
|
||||||
|
val hsel = Input(Bool())
|
||||||
|
val hreadyin = Input(Bool())}
|
||||||
// val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data
|
// val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data
|
||||||
// val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction
|
// val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction
|
||||||
// val ahb_hresp = Output(Bool()) // slave response (high indicates erro)
|
// val ahb_hresp = Output(Bool()) // slave response (high indicates erro)
|
||||||
|
|
@ -115,18 +118,18 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
|
||||||
switch(buf_state) {
|
switch(buf_state) {
|
||||||
|
|
||||||
is(idle) {
|
is(idle) {
|
||||||
buf_nxtstate := Mux(io.ahb.out.hwrite, wr, rd)
|
buf_nxtstate := Mux(io.ahb.sig.out.hwrite, wr, rd)
|
||||||
buf_state_en := ahb_hready & io.ahb.out.htrans(1) & io.ahb_hsel // only transition on a valid hrtans
|
buf_state_en := ahb_hready & io.ahb.sig.out.htrans(1) & io.ahb.hsel // only transition on a valid hrtans
|
||||||
}
|
}
|
||||||
is(wr) { // Write command recieved last cycle
|
is(wr) { // Write command recieved last cycle
|
||||||
buf_nxtstate := Mux((io.ahb.in.hresp | (io.ahb.out.htrans(1, 0) === "b0".U) | !io.ahb_hsel).asBool, idle, Mux(io.ahb.out.hwrite, wr, rd))
|
buf_nxtstate := Mux((io.ahb.sig.in.hresp | (io.ahb.sig.out.htrans(1, 0) === "b0".U) | !io.ahb.hsel).asBool, idle, Mux(io.ahb.sig.out.hwrite, wr, rd))
|
||||||
buf_state_en := (!cmdbuf_full | io.ahb.in.hresp)
|
buf_state_en := (!cmdbuf_full | io.ahb.sig.in.hresp)
|
||||||
cmdbuf_wr_en := !cmdbuf_full & !(io.ahb.in.hresp | ((io.ahb.out.htrans(1, 0) === "b01".U(2.W)) & io.ahb_hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now.
|
cmdbuf_wr_en := !cmdbuf_full & !(io.ahb.sig.in.hresp | ((io.ahb.sig.out.htrans(1, 0) === "b01".U(2.W)) & io.ahb.hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now.
|
||||||
}
|
}
|
||||||
is(rd) { // Read command recieved last cycle.
|
is(rd) { // Read command recieved last cycle.
|
||||||
buf_nxtstate := Mux(io.ahb.in.hresp, idle, pend) // If error go to idle, else wait for read data
|
buf_nxtstate := Mux(io.ahb.sig.in.hresp, idle, pend) // If error go to idle, else wait for read data
|
||||||
buf_state_en := (!cmdbuf_full | io.ahb.in.hresp) // only when command can go, or if its an error
|
buf_state_en := (!cmdbuf_full | io.ahb.sig.in.hresp) // only when command can go, or if its an error
|
||||||
cmdbuf_wr_en := !io.ahb.in.hresp & !cmdbuf_full // send command only when no error
|
cmdbuf_wr_en := !io.ahb.sig.in.hresp & !cmdbuf_full // send command only when no error
|
||||||
}
|
}
|
||||||
is(pend) { // Read Command has been sent. Waiting on Data.
|
is(pend) { // Read Command has been sent. Waiting on Data.
|
||||||
buf_nxtstate := idle // go back for next command and present data next cycle
|
buf_nxtstate := idle // go back for next command and present data next cycle
|
||||||
|
|
@ -143,11 +146,11 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
|
||||||
(Fill(8,ahb_hsize_q(2,0) === 3.U) & 255.U)
|
(Fill(8,ahb_hsize_q(2,0) === 3.U) & 255.U)
|
||||||
|
|
||||||
// AHB signals
|
// AHB signals
|
||||||
io.ahb.in.hready := Mux(io.ahb.in.hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend) & !buf_read_error))
|
io.ahb.sig.in.hready := Mux(io.ahb.sig.in.hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend) & !buf_read_error))
|
||||||
ahb_hready := io.ahb.in.hready & io.ahb_hreadyin
|
ahb_hready := io.ahb.sig.in.hready & io.ahb.hreadyin
|
||||||
ahb_htrans_in := Fill(2,io.ahb_hsel) & io.ahb.out.htrans(1,0)
|
ahb_htrans_in := Fill(2,io.ahb.hsel) & io.ahb.sig.out.htrans(1,0)
|
||||||
io.ahb.in.hrdata := buf_rdata(63,0)
|
io.ahb.sig.in.hrdata := buf_rdata(63,0)
|
||||||
io.ahb.in.hresp := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle) &
|
io.ahb.sig.in.hresp := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle) &
|
||||||
((!(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM
|
((!(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM
|
||||||
((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & !((ahb_hsize_q(1,0) === 2.U) | (ahb_hsize_q(1,0) === 3.U))) | // ICCM Rd/Wr OR DCCM Wr not the right size
|
((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & !((ahb_hsize_q(1,0) === 2.U) | (ahb_hsize_q(1,0) === 3.U))) | // ICCM Rd/Wr OR DCCM Wr not the right size
|
||||||
((ahb_hsize_q(2,0) === 1.U) & ahb_haddr_q(0)) | // HW size but unaligned
|
((ahb_hsize_q(2,0) === 1.U) & ahb_haddr_q(0)) | // HW size but unaligned
|
||||||
|
|
@ -161,22 +164,22 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
|
||||||
buf_read_error := withClock(ahb_clk){RegNext(buf_read_error_in,0.U)}
|
buf_read_error := withClock(ahb_clk){RegNext(buf_read_error_in,0.U)}
|
||||||
|
|
||||||
// All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.
|
// All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.
|
||||||
ahb_hresp_q := withClock(ahb_clk){RegNext(io.ahb.in.hresp,0.U)}
|
ahb_hresp_q := withClock(ahb_clk){RegNext(io.ahb.sig.in.hresp,0.U)}
|
||||||
ahb_hready_q := withClock(ahb_clk){RegNext(ahb_hready,0.U)}
|
ahb_hready_q := withClock(ahb_clk){RegNext(ahb_hready,0.U)}
|
||||||
ahb_htrans_q := withClock(ahb_clk){RegNext(ahb_htrans_in,0.U)}
|
ahb_htrans_q := withClock(ahb_clk){RegNext(ahb_htrans_in,0.U)}
|
||||||
ahb_hsize_q := withClock(ahb_addr_clk){RegNext(io.ahb.out.hsize,0.U)}
|
ahb_hsize_q := withClock(ahb_addr_clk){RegNext(io.ahb.sig.out.hsize,0.U)}
|
||||||
ahb_hwrite_q := withClock(ahb_addr_clk){RegNext(io.ahb.out.hwrite,0.U)}
|
ahb_hwrite_q := withClock(ahb_addr_clk){RegNext(io.ahb.sig.out.hwrite,0.U)}
|
||||||
ahb_haddr_q := withClock(ahb_addr_clk){RegNext(io.ahb.out.haddr,0.U)}
|
ahb_haddr_q := withClock(ahb_addr_clk){RegNext(io.ahb.sig.out.haddr,0.U)}
|
||||||
|
|
||||||
// Clock header logic
|
// Clock header logic
|
||||||
ahb_bus_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb.out.htrans(1))
|
ahb_bus_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb.sig.out.htrans(1))
|
||||||
buf_rdata_clk_en := io.bus_clk_en & buf_rdata_en;
|
buf_rdata_clk_en := io.bus_clk_en & buf_rdata_en;
|
||||||
|
|
||||||
ahb_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
|
ahb_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
|
||||||
ahb_addr_clk := rvclkhdr(clock, ahb_bus_addr_clk_en, io.scan_mode)
|
ahb_addr_clk := rvclkhdr(clock, ahb_bus_addr_clk_en, io.scan_mode)
|
||||||
buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode)
|
buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode)
|
||||||
|
|
||||||
cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb.in.hresp & !cmdbuf_write)
|
cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb.sig.in.hresp & !cmdbuf_write)
|
||||||
cmdbuf_full := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)))
|
cmdbuf_full := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)))
|
||||||
//rvdffsc
|
//rvdffsc
|
||||||
cmdbuf_vld := withClock(bus_clk) {RegNext((Mux(cmdbuf_wr_en.asBool(),"b1".U,cmdbuf_vld) & !cmdbuf_rst), 0.U)}
|
cmdbuf_vld := withClock(bus_clk) {RegNext((Mux(cmdbuf_wr_en.asBool(),"b1".U,cmdbuf_vld) & !cmdbuf_rst), 0.U)}
|
||||||
|
|
@ -193,7 +196,7 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
|
||||||
|
|
||||||
//rvdffe
|
//rvdffe
|
||||||
cmdbuf_addr := rvdffe(ahb_haddr_q, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode)
|
cmdbuf_addr := rvdffe(ahb_haddr_q, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode)
|
||||||
cmdbuf_wdata := rvdffe(io.ahb.out.hwdata, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode)
|
cmdbuf_wdata := rvdffe(io.ahb.sig.out.hwdata, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode)
|
||||||
|
|
||||||
// AXI Write Command Channel
|
// AXI Write Command Channel
|
||||||
io.axi_awvalid := cmdbuf_vld & cmdbuf_write
|
io.axi_awvalid := cmdbuf_vld & cmdbuf_write
|
||||||
|
|
|
||||||
|
|
@ -17,7 +17,10 @@ class quasar_bundle extends Bundle with lib{
|
||||||
val ahb = new ahb_channel
|
val ahb = new ahb_channel
|
||||||
val lsu_ahb = new ahb_channel
|
val lsu_ahb = new ahb_channel
|
||||||
val sb_ahb = new ahb_channel
|
val sb_ahb = new ahb_channel
|
||||||
val dma_ahb = Flipped(new ahb_channel)
|
val dma = new Bundle{
|
||||||
|
val ahb= Flipped(new ahb_channel())
|
||||||
|
val hsel = Input(Bool())
|
||||||
|
val hreadyin = Input(Bool())}
|
||||||
|
|
||||||
val dbg_rst_l = Input(AsyncReset())
|
val dbg_rst_l = Input(AsyncReset())
|
||||||
val rst_vec = Input(UInt(31.W))
|
val rst_vec = Input(UInt(31.W))
|
||||||
|
|
@ -88,7 +91,7 @@ class quasar_bundle extends Bundle with lib{
|
||||||
// val sb_hresp = Input(Bool())
|
// val sb_hresp = Input(Bool())
|
||||||
//
|
//
|
||||||
// // DMA slave
|
// // DMA slave
|
||||||
val dma_hsel = Input(Bool())
|
// dma_hsel = Input(Bool())
|
||||||
// val dma_haddr = Input(UInt(32.W))
|
// val dma_haddr = Input(UInt(32.W))
|
||||||
// val dma_hburst = Input(UInt(3.W))
|
// val dma_hburst = Input(UInt(3.W))
|
||||||
// val dma_hmastlock = Input(Bool())
|
// val dma_hmastlock = Input(Bool())
|
||||||
|
|
@ -97,7 +100,7 @@ class quasar_bundle extends Bundle with lib{
|
||||||
// val dma_htrans = Input(UInt(2.W))
|
// val dma_htrans = Input(UInt(2.W))
|
||||||
// val dma_hwrite = Input(Bool())
|
// val dma_hwrite = Input(Bool())
|
||||||
// val dma_hwdata = Input(UInt(64.W))
|
// val dma_hwdata = Input(UInt(64.W))
|
||||||
val dma_hreadyin = Input(Bool())
|
// val dma_hreadyin = Input(Bool())
|
||||||
// val dma_hrdata = Output(UInt(64.W))
|
// val dma_hrdata = Output(UInt(64.W))
|
||||||
// val dma_hreadyout = Output(Bool())
|
// val dma_hreadyout = Output(Bool())
|
||||||
// val dma_hresp = Output(Bool())
|
// val dma_hresp = Output(Bool())
|
||||||
|
|
@ -408,8 +411,8 @@ class quasar extends Module with RequireAsyncReset with lib {
|
||||||
// dma_ahb_to_axi4.io.ahb_htrans := io.dma_htrans
|
// dma_ahb_to_axi4.io.ahb_htrans := io.dma_htrans
|
||||||
// dma_ahb_to_axi4.io.ahb_hwrite := io.dma_hwrite
|
// dma_ahb_to_axi4.io.ahb_hwrite := io.dma_hwrite
|
||||||
// dma_ahb_to_axi4.io.ahb_hwdata := io.dma_hwdata
|
// dma_ahb_to_axi4.io.ahb_hwdata := io.dma_hwdata
|
||||||
dma_ahb_to_axi4.io.ahb_hsel := io.dma_hsel
|
dma_ahb_to_axi4.io.ahb.hsel := io.dma.hsel
|
||||||
dma_ahb_to_axi4.io.ahb_hreadyin := io.dma_hreadyin
|
dma_ahb_to_axi4.io.ahb.hreadyin := io.dma.hreadyin
|
||||||
lsu.io.axi.aw.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready)
|
lsu.io.axi.aw.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready)
|
||||||
lsu.io.axi.w.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready)
|
lsu.io.axi.w.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready)
|
||||||
lsu.io.axi.b.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid)
|
lsu.io.axi.b.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid)
|
||||||
|
|
@ -484,7 +487,7 @@ class quasar extends Module with RequireAsyncReset with lib {
|
||||||
// io.sb_hwrite := sb_axi4_to_ahb.io.ahb_hwrite
|
// io.sb_hwrite := sb_axi4_to_ahb.io.ahb_hwrite
|
||||||
// io.sb_hwdata := sb_axi4_to_ahb.io.ahb_hwdata
|
// io.sb_hwdata := sb_axi4_to_ahb.io.ahb_hwdata
|
||||||
|
|
||||||
io.dma_ahb <> dma_ahb_to_axi4.io.ahb
|
io.dma.ahb <> dma_ahb_to_axi4.io.ahb.sig
|
||||||
// io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata
|
// io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata
|
||||||
// io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout
|
// io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout
|
||||||
// io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp
|
// io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp
|
||||||
|
|
@ -522,7 +525,7 @@ class quasar extends Module with RequireAsyncReset with lib {
|
||||||
// io.sb_hwrite := 0.U
|
// io.sb_hwrite := 0.U
|
||||||
// io.sb_hwdata := 0.U
|
// io.sb_hwdata := 0.U
|
||||||
|
|
||||||
io.dma_ahb.in <> 0.U.asTypeOf(io.dma_ahb.in)
|
io.dma.ahb.in <> 0.U.asTypeOf(io.dma.ahb.in)
|
||||||
// io.dma_hrdata := 0.U
|
// io.dma_hrdata := 0.U
|
||||||
// io.dma_hreadyout := 0.U
|
// io.dma_hreadyout := 0.U
|
||||||
// io.dma_hresp := 0.U
|
// io.dma_hresp := 0.U
|
||||||
|
|
|
||||||
|
|
@ -19,8 +19,11 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
|
||||||
val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
|
val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
|
||||||
|
|
||||||
// DMA slave
|
// DMA slave
|
||||||
val dma_hsel = Input(Bool())
|
|
||||||
val dma_ahb = Flipped(new ahb_channel())
|
val dma = new Bundle{
|
||||||
|
val ahb= Flipped(new ahb_channel())
|
||||||
|
val hsel = Input(Bool())
|
||||||
|
val hreadyin = Input(Bool())}
|
||||||
// val dma_haddr = Input(UInt(32.W))
|
// val dma_haddr = Input(UInt(32.W))
|
||||||
// val dma_hburst = Input(UInt(3.W))
|
// val dma_hburst = Input(UInt(3.W))
|
||||||
// val dma_hmastlock = Input(Bool())
|
// val dma_hmastlock = Input(Bool())
|
||||||
|
|
@ -29,7 +32,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
|
||||||
// val dma_htrans = Input(UInt(2.W))
|
// val dma_htrans = Input(UInt(2.W))
|
||||||
// val dma_hwrite = Input(Bool())
|
// val dma_hwrite = Input(Bool())
|
||||||
// val dma_hwdata = Input(UInt(64.W))
|
// val dma_hwdata = Input(UInt(64.W))
|
||||||
val dma_hreadyin = Input(Bool())
|
|
||||||
// val dma_hrdata = Output(UInt(64.W))
|
// val dma_hrdata = Output(UInt(64.W))
|
||||||
// val dma_hreadyout = Output(Bool())
|
// val dma_hreadyout = Output(Bool())
|
||||||
// val dma_hresp = Output(Bool())
|
// val dma_hresp = Output(Bool())
|
||||||
|
|
@ -112,7 +115,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
|
||||||
swerv.io.ahb.in <> 0.U.asTypeOf(swerv.io.ahb.in)
|
swerv.io.ahb.in <> 0.U.asTypeOf(swerv.io.ahb.in)
|
||||||
swerv.io.lsu_ahb.in <> 0.U.asTypeOf(swerv.io.lsu_ahb.in)
|
swerv.io.lsu_ahb.in <> 0.U.asTypeOf(swerv.io.lsu_ahb.in)
|
||||||
swerv.io.sb_ahb.in <> 0.U.asTypeOf(swerv.io.sb_ahb.in)
|
swerv.io.sb_ahb.in <> 0.U.asTypeOf(swerv.io.sb_ahb.in)
|
||||||
io.dma_ahb.in <> 0.U.asTypeOf(io.dma_ahb.in)
|
io.dma.ahb.in <> 0.U.asTypeOf(io.dma.ahb.in)
|
||||||
// swerv.io.sb_hready := 0.U
|
// swerv.io.sb_hready := 0.U
|
||||||
// swerv.io.hrdata := 0.U
|
// swerv.io.hrdata := 0.U
|
||||||
// swerv.io.sb_hresp := 0.U
|
// swerv.io.sb_hresp := 0.U
|
||||||
|
|
@ -154,8 +157,8 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
|
||||||
swerv.io.dma_axi <> io.dma_axi
|
swerv.io.dma_axi <> io.dma_axi
|
||||||
|
|
||||||
// DMA Slave
|
// DMA Slave
|
||||||
swerv.io.dma_hsel := io.dma_hsel
|
swerv.io.dma.hsel := io.dma.hsel
|
||||||
swerv.io.dma_ahb.out <> io.dma_ahb.out
|
swerv.io.dma.ahb.out <> io.dma.ahb.out
|
||||||
// swerv.io.dma_haddr := io.dma_haddr
|
// swerv.io.dma_haddr := io.dma_haddr
|
||||||
// swerv.io.dma_hburst := io.dma_hburst
|
// swerv.io.dma_hburst := io.dma_hburst
|
||||||
// swerv.io.dma_hmastlock := io.dma_hmastlock
|
// swerv.io.dma_hmastlock := io.dma_hmastlock
|
||||||
|
|
@ -164,7 +167,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
|
||||||
// swerv.io.dma_htrans := io.dma_htrans
|
// swerv.io.dma_htrans := io.dma_htrans
|
||||||
// swerv.io.dma_hwrite := io.dma_hwrite
|
// swerv.io.dma_hwrite := io.dma_hwrite
|
||||||
// swerv.io.dma_hwdata := io.dma_hwdata
|
// swerv.io.dma_hwdata := io.dma_hwdata
|
||||||
swerv.io.dma_hreadyin := io.dma_hreadyin
|
swerv.io.dma.hreadyin := io.dma.hreadyin
|
||||||
|
|
||||||
swerv.io.lsu_bus_clk_en
|
swerv.io.lsu_bus_clk_en
|
||||||
swerv.io.ifu_bus_clk_en
|
swerv.io.ifu_bus_clk_en
|
||||||
|
|
|
||||||
|
|
@ -4,3 +4,4 @@
|
||||||
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
|
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
|
||||||
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
|
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
|
||||||
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
|
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
|
||||||
|
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
|
||||||
|
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue