dma added

This commit is contained in:
waleed-lm 2020-12-11 12:20:12 +05:00
parent 0f1f134851
commit 2876baddb0
171 changed files with 8599 additions and 8127 deletions

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@ -4,6 +4,71 @@
<component name="SVCompilerDirectivesDefines"> <component name="SVCompilerDirectivesDefines">
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<option name="replacementList" value="module ram_``depth``x``width( &#10; input logic [$clog2(depth)-1:0] ADR, &#10; input logic [(width-1):0] D, &#10; output logic [(width-1):0] Q, &#10; `EL2_LOCAL_RAM_TEST_IO &#10;); &#10;reg [(width-1):0] ram_core [(depth-1):0]; &#10; &#10;always @(posedge CLK) begin &#10; if (ME &amp;&amp; WE) ram_core[ADR] = D; &#10; if (ME &amp;&amp; ~WE) Q &lt;= ram_core[ADR]; &#10;end &#10; &#10;endmodule" />
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<option name="replacementList" value="module ram_be_``depth``x``width( &#10; input logic [$clog2(depth)-1:0] ADR, &#10; input logic [(width-1):0] D, WEM, &#10; output logic [(width-1):0] Q, &#10; `EL2_LOCAL_RAM_TEST_IO &#10;); &#10;reg [(width-1):0] ram_core [(depth-1):0]; &#10; &#10;always @(posedge CLK) begin &#10; if (ME &amp;&amp; WE) ram_core[ADR] = D &amp; WEM | ~WEM &amp; ram_core[ADR];&#10; if (ME &amp;&amp; ~WE) Q &lt;= ram_core[ADR]; &#10;end &#10; &#10; &#10;endmodule" />
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@ -84,6 +149,31 @@
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@ -98,6 +188,11 @@
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@ -828,6 +923,246 @@
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@ -1,5 +1,5 @@
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@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<module external.linked.project.id="quasar [file:/home/waleedbinehsan/Desktop/Quasar/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4"> <module external.linked.project.id="quasar [file:/home/abdulhameed.akram/Music/Quasar/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
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@ -1 +1,3 @@
/home/waleedbinehsan/Desktop/Quasar/gated_latch.v /home/waleedbinehsan/Desktop/Quasar/gated_latch.v
/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv
/home/waleedbinehsan/Desktop/Quasar/mem.sv

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-1177411650 1437988962

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[debug] "not up to date. inChanged = true, force = false [debug] "not up to date. inChanged = true, force = false
[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")... [debug] Updating ProjectRef(uri("file:/home/abdulhameed.akram/Music/Quasar/project/"), "quasar-build")...
[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build") [debug] Done updating ProjectRef(uri("file:/home/abdulhameed.akram/Music/Quasar/project/"), "quasar-build")

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[debug] Full compilation, no sources in previous analysis. [debug] Full compilation, no sources in previous analysis.

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[debug] Copy resource mappings:  [debug] Copy resource mappings:
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/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar /home/abdulhameed.akram/Music/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/abdulhameed.akram/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes

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/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes /home/abdulhameed.akram/Music/Quasar/project/target/scala-2.12/sbt-1.0/classes

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/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

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@ -311,7 +311,7 @@ class dbg extends Module with lib with RequireAsyncReset {
Fill(32, io.dmi_reg_addr === "h40".U) & haltsum0_reg | Fill(32, io.dmi_reg_addr === "h38".U) & sbcs_reg | Fill(32, io.dmi_reg_addr === "h40".U) & haltsum0_reg | Fill(32, io.dmi_reg_addr === "h38".U) & sbcs_reg |
Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg | Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg |
Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg
0 0
dbg_state := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l & temp_rst).asAsyncReset()) { dbg_state := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l & temp_rst).asAsyncReset()) {
RegEnable(dbg_nxtstate, 0.U, dbg_state_en) RegEnable(dbg_nxtstate, 0.U, dbg_state_en)
} // dbg_state_reg } // dbg_state_reg
@ -450,3 +450,6 @@ class dbg extends Module with lib with RequireAsyncReset {
io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write
io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type
} }
object dgb extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
}

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@ -10,263 +10,257 @@ import lsu._
class dec_decode_ctl extends Module with lib with RequireAsyncReset{ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
val io = IO(new Bundle{ val io = IO(new Bundle{
val decode_exu = Flipped(new decode_exu) val decode_exu = Flipped(new decode_exu) //connection with exu top
val dec_alu = Flipped(new dec_alu) val dec_alu = Flipped(new dec_alu) //connection with alu
val dec_div = Flipped(new dec_div) val dec_div = Flipped(new dec_div) //connection with divider
val dctl_busbuff = Flipped(new dctl_busbuff()) val dctl_busbuff = Flipped(new dctl_busbuff()) //connection with bus buffer
val dctl_dma = new dctl_dma val dctl_dma = new dctl_dma //connection with dma
val dec_tlu_flush_extint = Input(Bool()) val dec_aln = Flipped(new aln_dec) //connection with aligner
val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event val dbg_dctl = new dbg_dctl() //connection with dbg
val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder val dec_tlu_flush_extint = Input(Bool())
val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event
val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder
val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder
val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches
val lsu_trigger_match_m = Input(UInt(4.W)) // lsu trigger matches val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r
val lsu_pmu_misaligned_m = Input(Bool()) // perf mon: load/store misalign val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only
val dec_tlu_debug_stall = Input(Bool()) // debug stall decode val lsu_trigger_match_m = Input(UInt(4.W)) // lsu trigger matches
val dec_tlu_flush_leak_one_r = Input(Bool()) // leak1 instruction val lsu_pmu_misaligned_m = Input(Bool()) // perf mon: load/store misalign
val dec_debug_fence_d = Input(Bool()) // debug fence instruction val dec_tlu_debug_stall = Input(Bool()) // debug stall decode
val dec_i0_icaf_d = Input(Bool()) // icache access fault val dec_tlu_flush_leak_one_r = Input(Bool()) // leak1 instruction
val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group val dec_debug_fence_d = Input(Bool()) // debug fence instruction
val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type val dec_i0_icaf_d = Input(Bool()) // icache access fault
val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group
val dec_i0_brp = Flipped(Valid(new br_pkt_t)) // branch packet val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type
val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error
val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR val dec_i0_brp = Flipped(Valid(new br_pkt_t)) // branch packet
val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
val dec_i0_pc_d = Input(UInt(31.W)) // pc val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
val lsu_idle_any = Input(Bool()) // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
val lsu_load_stall_any = Input(Bool()) // stall any load at decode val dec_i0_pc_d = Input(UInt(31.W)) // pc
val lsu_store_stall_any = Input(Bool()) // stall any store at decode6 val lsu_idle_any = Input(Bool()) // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode
val exu_div_wren = Input(Bool()) // nonblocking divide write enable to GPR. val lsu_load_stall_any = Input(Bool()) // stall any load at decode
val dec_tlu_i0_kill_writeb_wb = Input(Bool()) // I0 is flushed, don't writeback any results to arch state val lsu_store_stall_any = Input(Bool()) // stall any store at decode6
val dec_tlu_flush_lower_wb = Input(Bool()) // trap lower flush val exu_div_wren = Input(Bool()) // nonblocking divide write enable to GPR.
val dec_tlu_i0_kill_writeb_r = Input(Bool()) // I0 is flushed, don't writeback any results to arch state val dec_tlu_i0_kill_writeb_wb = Input(Bool()) // I0 is flushed, don't writeback any results to arch state
val dec_tlu_flush_lower_r = Input(Bool()) // trap lower flush val dec_tlu_flush_lower_wb = Input(Bool()) // trap lower flush
val dec_tlu_flush_pause_r = Input(Bool()) // don't clear pause state on initial lower flush val dec_tlu_i0_kill_writeb_r = Input(Bool()) // I0 is flushed, don't writeback any results to arch state
val dec_tlu_presync_d = Input(Bool()) // CSR read needs to be presync'd val dec_tlu_flush_lower_r = Input(Bool()) // trap lower flush
val dec_tlu_postsync_d = Input(Bool()) // CSR ops that need to be postsync'd val dec_tlu_flush_pause_r = Input(Bool()) // don't clear pause state on initial lower flush
val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B val dec_tlu_presync_d = Input(Bool()) // CSR read needs to be presync'd
val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb val dec_tlu_postsync_d = Input(Bool()) // CSR ops that need to be postsync'd
val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B
val lsu_result_m = Input(UInt(32.W)) // load result val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation
val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D val lsu_result_m = Input(UInt(32.W)) // load result
val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing
val dec_ib0_valid_d = Input(Bool()) // inst valid at decode val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D
val free_clk = Input(Clock()) val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode
val active_clk = Input(Clock()) // clk except for halt / pause val dec_ib0_valid_d = Input(Bool()) // inst valid at decode
val clk_override = Input(Bool()) // test stuff val free_clk = Input(Clock())
val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source val active_clk = Input(Clock()) // clk except for halt / pause
val dec_i0_rs2_d = Output(UInt(5.W)) val clk_override = Input(Bool()) // test stuff
val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source
val dec_i0_wen_r = Output(Bool()) // i0 write enable val dec_i0_rs2_d = Output(UInt(5.W))
val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's
val lsu_p = Valid(new lsu_pkt_t) // load/store packet val dec_i0_wen_r = Output(Bool()) // i0 write enable
val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data
val dec_lsu_valid_raw_d = Output(Bool()) val lsu_p = Valid(new lsu_pkt_t) // load/store packet
val dec_lsu_offset_d = Output(UInt(12.W)) val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR
val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal val dec_lsu_valid_raw_d = Output(Bool())
val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal val dec_lsu_offset_d = Output(UInt(12.W))
val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal
val dec_csr_wen_r = Output(Bool()) // csr write enable at r val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal
val dec_csr_wraddr_r = Output(UInt(12.W)) // write address for csr val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr
val dec_csr_wrdata_r = Output(UInt(32.W)) // csr write data at r val dec_csr_wen_r = Output(Bool()) // csr write enable at r
val dec_csr_stall_int_ff = Output(Bool()) // csr is mie/mstatus val dec_csr_wraddr_r = Output(UInt(12.W)) // write address for csr
val dec_tlu_i0_valid_r = Output(Bool()) // i0 valid inst at c val dec_csr_wrdata_r = Output(UInt(32.W)) // csr write data at r
val dec_tlu_packet_r = Output(new trap_pkt_t) // trap packet val dec_csr_stall_int_ff = Output(Bool()) // csr is mie/mstatus
val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc val dec_tlu_i0_valid_r = Output(Bool()) // i0 valid inst at c
val dec_illegal_inst = Output(UInt(32.W)) // illegal inst val dec_tlu_packet_r = Output(new trap_pkt_t) // trap packet
val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc
val dec_pmu_decode_stall = Output(Bool()) // decode is stalled val dec_illegal_inst = Output(UInt(32.W)) // illegal inst
val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded
val dec_pmu_postsync_stall = Output(Bool()) // decode has postsync stall val dec_pmu_decode_stall = Output(Bool()) // decode is stalled
val dec_nonblock_load_wen = Output(Bool()) // write enable for nonblock load val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall
val dec_nonblock_load_waddr = Output(UInt(5.W)) // logical write addr for nonblock load val dec_pmu_postsync_stall = Output(Bool()) // decode has postsync stall
val dec_pause_state = Output(Bool()) // core in pause state val dec_nonblock_load_wen = Output(Bool()) // write enable for nonblock load
val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating val dec_nonblock_load_waddr = Output(UInt(5.W)) // logical write addr for nonblock load
val dec_div_active = Output(Bool()) // non-block divide is active val dec_pause_state = Output(Bool()) // core in pause state
val scan_mode = Input(Bool()) val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating
val dec_div_active = Output(Bool()) // non-block divide is active
val dec_aln = Flipped(new aln_dec) val scan_mode = Input(Bool())
val dbg_dctl = new dbg_dctl()
}) })
///////////////////////////////////////////////////////////////////////////////////////// //packets zero initialization
// //packets zero initialization io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p)
io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p)
// Vals defined // Vals defined
val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U) val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U)
val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U) val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U)
val i0r = Wire(new reg_pkt_t) val i0r = Wire(new reg_pkt_t)
val d_t = Wire(new trap_pkt_t) val d_t = Wire(new trap_pkt_t)
val x_t = Wire(new trap_pkt_t) val x_t = Wire(new trap_pkt_t)
val x_t_in = Wire(new trap_pkt_t) val x_t_in = Wire(new trap_pkt_t)
val r_t = Wire(new trap_pkt_t) val r_t = Wire(new trap_pkt_t)
val r_t_in = Wire(new trap_pkt_t) val r_t_in = Wire(new trap_pkt_t)
val d_d = Wire(Valid(new dest_pkt_t)) val d_d = Wire(Valid(new dest_pkt_t))
val x_d = Wire(Valid(new dest_pkt_t)) val x_d = Wire(Valid(new dest_pkt_t))
val r_d = Wire(Valid(new dest_pkt_t)) val r_d = Wire(Valid(new dest_pkt_t))
val r_d_in = Wire(Valid(new dest_pkt_t)) val r_d_in = Wire(Valid(new dest_pkt_t))
val wbd = Wire(Valid(new dest_pkt_t)) val wbd = Wire(Valid(new dest_pkt_t))
val i0_d_c = Wire(new class_pkt_t) val i0_d_c = Wire(new class_pkt_t)
val i0_rs1_class_d = Wire(new class_pkt_t) val i0_rs1_class_d = Wire(new class_pkt_t)
val i0_rs2_class_d = Wire(new class_pkt_t) val i0_rs2_class_d = Wire(new class_pkt_t)
val i0_rs1_depth_d = WireInit(UInt(2.W),0.U) val i0_rs1_depth_d = WireInit(UInt(2.W),0.U)
val i0_rs2_depth_d = WireInit(UInt(2.W),0.U) val i0_rs2_depth_d = WireInit(UInt(2.W),0.U)
val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) val cam_wen = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
val cam_write=WireInit(UInt(1.W), 0.U) val cam_write = WireInit(UInt(1.W), 0.U)
val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) val cam_inv_reset_val = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) val cam_data_reset_val = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) val nonblock_load_write = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) val cam_raw = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
val cam_in =Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) val cam_in = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
//val i0_temp = Wire(new inst_pkt_t) val i0_dp = Wire(new dec_pkt_t)
val i0_dp= Wire(new dec_pkt_t) val i0_dp_raw = Wire(new dec_pkt_t)
val i0_dp_raw= Wire(new dec_pkt_t) val i0_rs1bypass = WireInit(UInt(3.W), 0.U)
val i0_rs1bypass = WireInit(UInt(3.W), 0.U) val i0_rs2bypass = WireInit(UInt(3.W), 0.U)
val i0_rs2bypass = WireInit(UInt(3.W), 0.U) val illegal_lockout = WireInit(UInt(1.W), 0.U)
val illegal_lockout = WireInit(UInt(1.W), 0.U) val postsync_stall = WireInit(UInt(1.W), 0.U)
val postsync_stall = WireInit(UInt(1.W), 0.U) val ps_stall_in = WireInit(UInt(1.W), 0.U)
val ps_stall_in = WireInit(UInt(1.W), 0.U) val i0_pipe_en = WireInit(UInt(4.W), 0.U)
val i0_pipe_en = WireInit(UInt(4.W), 0.U) val i0_load_block_d = WireInit(UInt(1.W), 0.U)
val i0_load_block_d = WireInit(UInt(1.W), 0.U) val load_ldst_bypass_d = WireInit(UInt(1.W), 0.U)
val load_ldst_bypass_d = WireInit(UInt(1.W), 0.U) val store_data_bypass_d = WireInit(UInt(1.W), 0.U)
val store_data_bypass_d = WireInit(UInt(1.W), 0.U) val store_data_bypass_m = WireInit(UInt(1.W), 0.U)
val store_data_bypass_m = WireInit(UInt(1.W), 0.U) val tlu_wr_pause_r1 = WireInit(UInt(1.W), 0.U)
val tlu_wr_pause_r1 = WireInit(UInt(1.W), 0.U) val tlu_wr_pause_r2 = WireInit(UInt(1.W), 0.U)
val tlu_wr_pause_r2 = WireInit(UInt(1.W), 0.U) val leak1_i1_stall = WireInit(UInt(1.W), 0.U)
val leak1_i1_stall = WireInit(UInt(1.W), 0.U) val leak1_i0_stall = WireInit(UInt(1.W), 0.U)
val leak1_i0_stall = WireInit(UInt(1.W), 0.U) val pause_state = WireInit(Bool(), 0.B)
val pause_state = WireInit(Bool(), 0.B) val flush_final_r = WireInit(UInt(1.W), 0.U)
val flush_final_r = WireInit(UInt(1.W), 0.U) val illegal_lockout_in = WireInit(UInt(1.W), 0.U)
val illegal_lockout_in = WireInit(UInt(1.W), 0.U) val lsu_idle = WireInit(Bool(), 0.B)
val lsu_idle = WireInit(Bool(), 0.B) val pause_state_in = WireInit(Bool(), 0.B)
val pause_state_in = WireInit(Bool(), 0.B) val leak1_mode = WireInit(UInt(1.W), 0.U)
val leak1_mode = WireInit(UInt(1.W), 0.U) val i0_pcall = WireInit(UInt(1.W), 0.U)
val i0_pcall = WireInit(UInt(1.W), 0.U) val i0_pja = WireInit(UInt(1.W), 0.U)
val i0_pja = WireInit(UInt(1.W), 0.U) val i0_pret = WireInit(UInt(1.W), 0.U)
val i0_pret = WireInit(UInt(1.W), 0.U) val i0_legal_decode_d = WireInit(UInt(1.W), 0.U)
val i0_legal_decode_d = WireInit(UInt(1.W), 0.U) val i0_pcall_raw = WireInit(UInt(1.W), 0.U)
val i0_pcall_raw = WireInit(UInt(1.W), 0.U) val i0_pja_raw = WireInit(UInt(1.W), 0.U)
val i0_pja_raw = WireInit(UInt(1.W), 0.U) val i0_pret_raw = WireInit(UInt(1.W), 0.U)
val i0_pret_raw = WireInit(UInt(1.W), 0.U) val i0_br_offset = WireInit(UInt(12.W), 0.U)
val i0_br_offset = WireInit(UInt(12.W), 0.U) val i0_csr_write_only_d = WireInit(UInt(1.W), 0.U)
val i0_csr_write_only_d = WireInit(UInt(1.W), 0.U) val i0_jal = WireInit(UInt(1.W), 0.U)
val i0_jal = WireInit(UInt(1.W), 0.U) val i0_wen_r = WireInit(UInt(1.W), 0.U)
val i0_wen_r = WireInit(UInt(1.W), 0.U) val i0_x_ctl_en = WireInit(UInt(1.W), 0.U)
val i0_x_ctl_en = WireInit(UInt(1.W), 0.U) val i0_r_ctl_en = WireInit(UInt(1.W), 0.U)
val i0_r_ctl_en = WireInit(UInt(1.W), 0.U) val i0_wb_ctl_en = WireInit(UInt(1.W), 0.U)
val i0_wb_ctl_en = WireInit(UInt(1.W), 0.U) val i0_x_data_en = WireInit(UInt(1.W), 0.U)
val i0_x_data_en = WireInit(UInt(1.W), 0.U) val i0_r_data_en = WireInit(UInt(1.W), 0.U)
val i0_r_data_en = WireInit(UInt(1.W), 0.U) val i0_wb_data_en = WireInit(UInt(1.W), 0.U)
val i0_wb_data_en = WireInit(UInt(1.W), 0.U) val i0_wb1_data_en = WireInit(UInt(1.W), 0.U)
val i0_wb1_data_en = WireInit(UInt(1.W), 0.U) val i0_nonblock_load_stall = WireInit(UInt(1.W), 0.U)
val i0_nonblock_load_stall = WireInit(UInt(1.W), 0.U) val csr_ren_qual_d = WireInit(Bool(), 0.B)
val csr_ren_qual_d = WireInit(Bool(), 0.B) val lsu_decode_d = WireInit(UInt(1.W), 0.U)
val lsu_decode_d = WireInit(UInt(1.W), 0.U) val mul_decode_d = WireInit(UInt(1.W), 0.U)
val mul_decode_d = WireInit(UInt(1.W), 0.U) val div_decode_d = WireInit(UInt(1.W), 0.U)
val div_decode_d = WireInit(UInt(1.W), 0.U) val write_csr_data = WireInit(UInt(32.W),0.U)
val write_csr_data = WireInit(UInt(32.W),0.U) val i0_result_corr_r = WireInit(UInt(32.W),0.U)
val i0_result_corr_r = WireInit(UInt(32.W),0.U) val presync_stall = WireInit(UInt(1.W), 0.U)
val presync_stall = WireInit(UInt(1.W), 0.U) val i0_nonblock_div_stall = WireInit(UInt(1.W), 0.U)
val i0_nonblock_div_stall = WireInit(UInt(1.W), 0.U) val debug_fence = WireInit(Bool(), 0.B)
val debug_fence = WireInit(Bool(), 0.B) val i0_immed_d = WireInit(UInt(32.W), 0.U)
val i0_immed_d = WireInit(UInt(32.W), 0.U) val i0_result_x = WireInit(UInt(32.W), 0.U)
val i0_result_x = WireInit(UInt(32.W), 0.U) val i0_result_r = WireInit(UInt(32.W), 0.U)
val i0_result_r = WireInit(UInt(32.W), 0.U)
////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////
// Start - Data gating {{ // Start - Data gating {{
val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk
(tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk (tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk
(io.dec_tlu_flush_extint ^ io.decode_exu.dec_extint_stall) | (io.dec_tlu_flush_extint ^ io.decode_exu.dec_extint_stall) |
(leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk (leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk
(leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk (leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk
(pause_state_in ^ pause_state ) | // replaces free_clk (pause_state_in ^ pause_state ) | // replaces free_clk
(ps_stall_in ^ postsync_stall ) | // replaces free_clk (ps_stall_in ^ postsync_stall ) | // replaces free_clk
(io.exu_flush_final ^ flush_final_r ) | // replaces free_clk (io.exu_flush_final ^ flush_final_r ) | // replaces free_clk
(illegal_lockout_in ^ illegal_lockout ) // replaces active_clk (illegal_lockout_in ^ illegal_lockout ) // replaces active_clk
val data_gate_clk= rvclkhdr(clock,data_gate_en.asBool(),io.scan_mode) val data_gate_clk = rvclkhdr(clock,data_gate_en.asBool(),io.scan_mode)
// End - Data gating
// End - Data gating }} val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode
io.decode_exu.dec_i0_predict_p_d.bits.misp := 0.U
val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode io.decode_exu.dec_i0_predict_p_d.bits.ataken := 0.U
io.decode_exu.dec_i0_predict_p_d.bits.misp :=0.U io.decode_exu.dec_i0_predict_p_d.bits.boffset := 0.U
io.decode_exu.dec_i0_predict_p_d.bits.ataken :=0.U io.decode_exu.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error
io.decode_exu.dec_i0_predict_p_d.bits.boffset :=0.U io.decode_exu.dec_i0_predict_p_d.bits.pja := i0_pja
io.decode_exu.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error io.decode_exu.dec_i0_predict_p_d.bits.pret := i0_pret
io.decode_exu.dec_i0_predict_p_d.bits.pja := i0_pja io.decode_exu.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett
io.decode_exu.dec_i0_predict_p_d.bits.pret := i0_pret io.decode_exu.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d
io.decode_exu.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett io.decode_exu.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist
io.decode_exu.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d io.decode_exu.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d
io.decode_exu.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
io.decode_exu.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d
val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
// no toffset error for a pret // no toffset error for a pret
val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw
val i0_ret_error = i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw; val i0_ret_error = i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw;
val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
io.decode_exu.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode io.decode_exu.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode
io.decode_exu.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode io.decode_exu.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode
io.decode_exu.i0_predict_index_d := io.dec_i0_bp_index io.decode_exu.i0_predict_index_d := io.dec_i0_bp_index
io.decode_exu.i0_predict_btag_d := io.dec_i0_bp_btag io.decode_exu.i0_predict_btag_d := io.dec_i0_bp_btag
val i0_br_error_all = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode val i0_br_error_all = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode
io.decode_exu.dec_i0_predict_p_d.bits.toffset := i0_br_offset io.decode_exu.dec_i0_predict_p_d.bits.toffset := i0_br_offset
io.decode_exu.i0_predict_fghr_d := io.dec_i0_bp_fghr io.decode_exu.i0_predict_fghr_d := io.dec_i0_bp_fghr
io.decode_exu.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way io.decode_exu.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way
// end // end
// on br error turn anything into a nop // on br error turn anything into a nop
// on i0 instruction fetch access fault turn anything into a nop // on i0 instruction fetch access fault turn anything into a nop
// nop => alu rs1 imm12 rd lor // nop => alu rs1 imm12 rd lor
val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d
val i0_instr_error = i0_icaf_d;
val i0_instr_error = i0_icaf_d; i0_dp := i0_dp_raw
i0_dp := i0_dp_raw
when((i0_br_error_all | i0_instr_error).asBool){ when((i0_br_error_all | i0_instr_error).asBool){
i0_dp := 0.U.asTypeOf(i0_dp) i0_dp := 0.U.asTypeOf(i0_dp)
i0_dp.alu := 1.B i0_dp.alu := 1.B
i0_dp.rs1 := 1.B i0_dp.rs1 := 1.B
i0_dp.rs2 := 1.B i0_dp.rs2 := 1.B
i0_dp.lor := 1.B i0_dp.lor := 1.B
i0_dp.legal := 1.B i0_dp.legal := 1.B
i0_dp.postsync := 1.B i0_dp.postsync := 1.B
} }
val i0 = io.dec_i0_instr_d val i0 = io.dec_i0_instr_d
io.decode_exu.dec_i0_select_pc_d := i0_dp.pc io.decode_exu.dec_i0_select_pc_d := i0_dp.pc
// branches that can be predicted // branches that can be predicted
val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret; val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br val i0_ap_pc2 = !io.dec_i0_pc4_d
val i0_ap_pc2 = !io.dec_i0_pc4_d val i0_ap_pc4 = io.dec_i0_pc4_d
val i0_ap_pc4 = io.dec_i0_pc4_d
io.decode_exu.i0_ap.predict_nt := i0_predict_nt io.decode_exu.i0_ap.predict_nt := i0_predict_nt
io.decode_exu.i0_ap.predict_t := i0_predict_t io.decode_exu.i0_ap.predict_t := i0_predict_t
io.decode_exu.i0_ap.add := i0_dp.add io.decode_exu.i0_ap.add := i0_dp.add
io.decode_exu.i0_ap.sub := i0_dp.sub io.decode_exu.i0_ap.sub := i0_dp.sub
io.decode_exu.i0_ap.land := i0_dp.land io.decode_exu.i0_ap.land := i0_dp.land
io.decode_exu.i0_ap.lor := i0_dp.lor io.decode_exu.i0_ap.lor := i0_dp.lor
io.decode_exu.i0_ap.lxor := i0_dp.lxor io.decode_exu.i0_ap.lxor := i0_dp.lxor
io.decode_exu.i0_ap.sll := i0_dp.sll io.decode_exu.i0_ap.sll := i0_dp.sll
io.decode_exu.i0_ap.srl := i0_dp.srl io.decode_exu.i0_ap.srl := i0_dp.srl
io.decode_exu.i0_ap.sra := i0_dp.sra io.decode_exu.i0_ap.sra := i0_dp.sra
io.decode_exu.i0_ap.slt := i0_dp.slt io.decode_exu.i0_ap.slt := i0_dp.slt
io.decode_exu.i0_ap.unsign := i0_dp.unsign io.decode_exu.i0_ap.unsign := i0_dp.unsign
io.decode_exu.i0_ap.beq := i0_dp.beq io.decode_exu.i0_ap.beq := i0_dp.beq
io.decode_exu.i0_ap.bne := i0_dp.bne io.decode_exu.i0_ap.bne := i0_dp.bne
io.decode_exu.i0_ap.blt := i0_dp.blt io.decode_exu.i0_ap.blt := i0_dp.blt
io.decode_exu.i0_ap.bge := i0_dp.bge io.decode_exu.i0_ap.bge := i0_dp.bge
io.decode_exu.i0_ap.csr_write := i0_csr_write_only_d io.decode_exu.i0_ap.csr_write := i0_csr_write_only_d
io.decode_exu.i0_ap.csr_imm := i0_dp.csr_imm io.decode_exu.i0_ap.csr_imm := i0_dp.csr_imm
io.decode_exu.i0_ap.jal := i0_jal io.decode_exu.i0_ap.jal := i0_jal
// non block load cam logic // non block load cam logic
// val found=Wire(UInt(1.W)) // val found=Wire(UInt(1.W))

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@ -109,7 +109,6 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{
val target_mispredict = io.pp_in.bits.pret & (io.pp_in.bits.prett =/= aout(31,1)) //predicted return target != aout val target_mispredict = io.pp_in.bits.pret & (io.pp_in.bits.prett =/= aout(31,1)) //predicted return target != aout
io.flush_upper_out := (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x & !io.dec_tlu_flush_lower_r io.flush_upper_out := (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x & !io.dec_tlu_flush_lower_r
//there was no entire pipe flush (& previous cycle flush ofc(why check?)) therfore signAL 1 to flush instruction before X stage
io.flush_final_out := ( (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x ) | io.dec_tlu_flush_lower_r io.flush_final_out := ( (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x ) | io.dec_tlu_flush_lower_r
//there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe //there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe

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@ -58,12 +58,10 @@ class ahb_out extends Bundle{
val htrans = Output(UInt(2.W)) val htrans = Output(UInt(2.W))
val hwrite = Output(Bool()) // ahb bus write val hwrite = Output(Bool()) // ahb bus write
val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data
} }
class ahb_channel extends Bundle{ class ahb_channel extends Bundle{
val in = Input(new ahb_in) val in = new ahb_in
val out = Output(new ahb_out) val out = new ahb_out
} }
class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{ class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{
val aw = Decoupled(new write_addr(BUS_TAG)) val aw = Decoupled(new write_addr(BUS_TAG))

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@ -28,8 +28,8 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
// val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now) // val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now)
// val ahb_hwrite = Input(Bool()) // ahb bus write // val ahb_hwrite = Input(Bool()) // ahb bus write
// val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data // val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data
val ahb_hsel = Input(Bool()) // this slave was selected // val ahb_hsel = Input(Bool()) // this slave was selected
val ahb_hreadyin = Input(Bool()) // previous hready was accepted or not // val ahb_hreadyin = Input(Bool()) // previous hready was accepted or not
// outputs // outputs
val axi_awvalid = Output(Bool()) val axi_awvalid = Output(Bool())
val axi_awid = Output(UInt(TAG.W)) val axi_awid = Output(UInt(TAG.W))
@ -51,7 +51,10 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
val axi_arlen = Output(UInt(8.W)) val axi_arlen = Output(UInt(8.W))
val axi_arburst = Output(UInt(2.W)) val axi_arburst = Output(UInt(2.W))
val axi_rready = Output(Bool()) val axi_rready = Output(Bool())
val ahb = Flipped(new ahb_channel()) val ahb = new Bundle{
val sig = Flipped(new ahb_channel())
val hsel = Input(Bool())
val hreadyin = Input(Bool())}
// val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data // val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data
// val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction // val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction
// val ahb_hresp = Output(Bool()) // slave response (high indicates erro) // val ahb_hresp = Output(Bool()) // slave response (high indicates erro)
@ -115,18 +118,18 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
switch(buf_state) { switch(buf_state) {
is(idle) { is(idle) {
buf_nxtstate := Mux(io.ahb.out.hwrite, wr, rd) buf_nxtstate := Mux(io.ahb.sig.out.hwrite, wr, rd)
buf_state_en := ahb_hready & io.ahb.out.htrans(1) & io.ahb_hsel // only transition on a valid hrtans buf_state_en := ahb_hready & io.ahb.sig.out.htrans(1) & io.ahb.hsel // only transition on a valid hrtans
} }
is(wr) { // Write command recieved last cycle is(wr) { // Write command recieved last cycle
buf_nxtstate := Mux((io.ahb.in.hresp | (io.ahb.out.htrans(1, 0) === "b0".U) | !io.ahb_hsel).asBool, idle, Mux(io.ahb.out.hwrite, wr, rd)) buf_nxtstate := Mux((io.ahb.sig.in.hresp | (io.ahb.sig.out.htrans(1, 0) === "b0".U) | !io.ahb.hsel).asBool, idle, Mux(io.ahb.sig.out.hwrite, wr, rd))
buf_state_en := (!cmdbuf_full | io.ahb.in.hresp) buf_state_en := (!cmdbuf_full | io.ahb.sig.in.hresp)
cmdbuf_wr_en := !cmdbuf_full & !(io.ahb.in.hresp | ((io.ahb.out.htrans(1, 0) === "b01".U(2.W)) & io.ahb_hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now. cmdbuf_wr_en := !cmdbuf_full & !(io.ahb.sig.in.hresp | ((io.ahb.sig.out.htrans(1, 0) === "b01".U(2.W)) & io.ahb.hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now.
} }
is(rd) { // Read command recieved last cycle. is(rd) { // Read command recieved last cycle.
buf_nxtstate := Mux(io.ahb.in.hresp, idle, pend) // If error go to idle, else wait for read data buf_nxtstate := Mux(io.ahb.sig.in.hresp, idle, pend) // If error go to idle, else wait for read data
buf_state_en := (!cmdbuf_full | io.ahb.in.hresp) // only when command can go, or if its an error buf_state_en := (!cmdbuf_full | io.ahb.sig.in.hresp) // only when command can go, or if its an error
cmdbuf_wr_en := !io.ahb.in.hresp & !cmdbuf_full // send command only when no error cmdbuf_wr_en := !io.ahb.sig.in.hresp & !cmdbuf_full // send command only when no error
} }
is(pend) { // Read Command has been sent. Waiting on Data. is(pend) { // Read Command has been sent. Waiting on Data.
buf_nxtstate := idle // go back for next command and present data next cycle buf_nxtstate := idle // go back for next command and present data next cycle
@ -143,11 +146,11 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
(Fill(8,ahb_hsize_q(2,0) === 3.U) & 255.U) (Fill(8,ahb_hsize_q(2,0) === 3.U) & 255.U)
// AHB signals // AHB signals
io.ahb.in.hready := Mux(io.ahb.in.hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend) & !buf_read_error)) io.ahb.sig.in.hready := Mux(io.ahb.sig.in.hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend) & !buf_read_error))
ahb_hready := io.ahb.in.hready & io.ahb_hreadyin ahb_hready := io.ahb.sig.in.hready & io.ahb.hreadyin
ahb_htrans_in := Fill(2,io.ahb_hsel) & io.ahb.out.htrans(1,0) ahb_htrans_in := Fill(2,io.ahb.hsel) & io.ahb.sig.out.htrans(1,0)
io.ahb.in.hrdata := buf_rdata(63,0) io.ahb.sig.in.hrdata := buf_rdata(63,0)
io.ahb.in.hresp := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle) & io.ahb.sig.in.hresp := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle) &
((!(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM ((!(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM
((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & !((ahb_hsize_q(1,0) === 2.U) | (ahb_hsize_q(1,0) === 3.U))) | // ICCM Rd/Wr OR DCCM Wr not the right size ((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & !((ahb_hsize_q(1,0) === 2.U) | (ahb_hsize_q(1,0) === 3.U))) | // ICCM Rd/Wr OR DCCM Wr not the right size
((ahb_hsize_q(2,0) === 1.U) & ahb_haddr_q(0)) | // HW size but unaligned ((ahb_hsize_q(2,0) === 1.U) & ahb_haddr_q(0)) | // HW size but unaligned
@ -161,22 +164,22 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
buf_read_error := withClock(ahb_clk){RegNext(buf_read_error_in,0.U)} buf_read_error := withClock(ahb_clk){RegNext(buf_read_error_in,0.U)}
// All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer. // All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.
ahb_hresp_q := withClock(ahb_clk){RegNext(io.ahb.in.hresp,0.U)} ahb_hresp_q := withClock(ahb_clk){RegNext(io.ahb.sig.in.hresp,0.U)}
ahb_hready_q := withClock(ahb_clk){RegNext(ahb_hready,0.U)} ahb_hready_q := withClock(ahb_clk){RegNext(ahb_hready,0.U)}
ahb_htrans_q := withClock(ahb_clk){RegNext(ahb_htrans_in,0.U)} ahb_htrans_q := withClock(ahb_clk){RegNext(ahb_htrans_in,0.U)}
ahb_hsize_q := withClock(ahb_addr_clk){RegNext(io.ahb.out.hsize,0.U)} ahb_hsize_q := withClock(ahb_addr_clk){RegNext(io.ahb.sig.out.hsize,0.U)}
ahb_hwrite_q := withClock(ahb_addr_clk){RegNext(io.ahb.out.hwrite,0.U)} ahb_hwrite_q := withClock(ahb_addr_clk){RegNext(io.ahb.sig.out.hwrite,0.U)}
ahb_haddr_q := withClock(ahb_addr_clk){RegNext(io.ahb.out.haddr,0.U)} ahb_haddr_q := withClock(ahb_addr_clk){RegNext(io.ahb.sig.out.haddr,0.U)}
// Clock header logic // Clock header logic
ahb_bus_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb.out.htrans(1)) ahb_bus_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb.sig.out.htrans(1))
buf_rdata_clk_en := io.bus_clk_en & buf_rdata_en; buf_rdata_clk_en := io.bus_clk_en & buf_rdata_en;
ahb_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) ahb_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
ahb_addr_clk := rvclkhdr(clock, ahb_bus_addr_clk_en, io.scan_mode) ahb_addr_clk := rvclkhdr(clock, ahb_bus_addr_clk_en, io.scan_mode)
buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode) buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode)
cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb.in.hresp & !cmdbuf_write) cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb.sig.in.hresp & !cmdbuf_write)
cmdbuf_full := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready))) cmdbuf_full := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)))
//rvdffsc //rvdffsc
cmdbuf_vld := withClock(bus_clk) {RegNext((Mux(cmdbuf_wr_en.asBool(),"b1".U,cmdbuf_vld) & !cmdbuf_rst), 0.U)} cmdbuf_vld := withClock(bus_clk) {RegNext((Mux(cmdbuf_wr_en.asBool(),"b1".U,cmdbuf_vld) & !cmdbuf_rst), 0.U)}
@ -193,7 +196,7 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
//rvdffe //rvdffe
cmdbuf_addr := rvdffe(ahb_haddr_q, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode) cmdbuf_addr := rvdffe(ahb_haddr_q, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode)
cmdbuf_wdata := rvdffe(io.ahb.out.hwdata, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode) cmdbuf_wdata := rvdffe(io.ahb.sig.out.hwdata, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode)
// AXI Write Command Channel // AXI Write Command Channel
io.axi_awvalid := cmdbuf_vld & cmdbuf_write io.axi_awvalid := cmdbuf_vld & cmdbuf_write

View File

@ -17,7 +17,10 @@ class quasar_bundle extends Bundle with lib{
val ahb = new ahb_channel val ahb = new ahb_channel
val lsu_ahb = new ahb_channel val lsu_ahb = new ahb_channel
val sb_ahb = new ahb_channel val sb_ahb = new ahb_channel
val dma_ahb = Flipped(new ahb_channel) val dma = new Bundle{
val ahb= Flipped(new ahb_channel())
val hsel = Input(Bool())
val hreadyin = Input(Bool())}
val dbg_rst_l = Input(AsyncReset()) val dbg_rst_l = Input(AsyncReset())
val rst_vec = Input(UInt(31.W)) val rst_vec = Input(UInt(31.W))
@ -88,7 +91,7 @@ class quasar_bundle extends Bundle with lib{
// val sb_hresp = Input(Bool()) // val sb_hresp = Input(Bool())
// //
// // DMA slave // // DMA slave
val dma_hsel = Input(Bool()) // dma_hsel = Input(Bool())
// val dma_haddr = Input(UInt(32.W)) // val dma_haddr = Input(UInt(32.W))
// val dma_hburst = Input(UInt(3.W)) // val dma_hburst = Input(UInt(3.W))
// val dma_hmastlock = Input(Bool()) // val dma_hmastlock = Input(Bool())
@ -97,7 +100,7 @@ class quasar_bundle extends Bundle with lib{
// val dma_htrans = Input(UInt(2.W)) // val dma_htrans = Input(UInt(2.W))
// val dma_hwrite = Input(Bool()) // val dma_hwrite = Input(Bool())
// val dma_hwdata = Input(UInt(64.W)) // val dma_hwdata = Input(UInt(64.W))
val dma_hreadyin = Input(Bool()) // val dma_hreadyin = Input(Bool())
// val dma_hrdata = Output(UInt(64.W)) // val dma_hrdata = Output(UInt(64.W))
// val dma_hreadyout = Output(Bool()) // val dma_hreadyout = Output(Bool())
// val dma_hresp = Output(Bool()) // val dma_hresp = Output(Bool())
@ -408,8 +411,8 @@ class quasar extends Module with RequireAsyncReset with lib {
// dma_ahb_to_axi4.io.ahb_htrans := io.dma_htrans // dma_ahb_to_axi4.io.ahb_htrans := io.dma_htrans
// dma_ahb_to_axi4.io.ahb_hwrite := io.dma_hwrite // dma_ahb_to_axi4.io.ahb_hwrite := io.dma_hwrite
// dma_ahb_to_axi4.io.ahb_hwdata := io.dma_hwdata // dma_ahb_to_axi4.io.ahb_hwdata := io.dma_hwdata
dma_ahb_to_axi4.io.ahb_hsel := io.dma_hsel dma_ahb_to_axi4.io.ahb.hsel := io.dma.hsel
dma_ahb_to_axi4.io.ahb_hreadyin := io.dma_hreadyin dma_ahb_to_axi4.io.ahb.hreadyin := io.dma.hreadyin
lsu.io.axi.aw.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) lsu.io.axi.aw.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready)
lsu.io.axi.w.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) lsu.io.axi.w.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready)
lsu.io.axi.b.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) lsu.io.axi.b.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid)
@ -484,7 +487,7 @@ class quasar extends Module with RequireAsyncReset with lib {
// io.sb_hwrite := sb_axi4_to_ahb.io.ahb_hwrite // io.sb_hwrite := sb_axi4_to_ahb.io.ahb_hwrite
// io.sb_hwdata := sb_axi4_to_ahb.io.ahb_hwdata // io.sb_hwdata := sb_axi4_to_ahb.io.ahb_hwdata
io.dma_ahb <> dma_ahb_to_axi4.io.ahb io.dma.ahb <> dma_ahb_to_axi4.io.ahb.sig
// io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata // io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata
// io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout // io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout
// io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp // io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp
@ -522,7 +525,7 @@ class quasar extends Module with RequireAsyncReset with lib {
// io.sb_hwrite := 0.U // io.sb_hwrite := 0.U
// io.sb_hwdata := 0.U // io.sb_hwdata := 0.U
io.dma_ahb.in <> 0.U.asTypeOf(io.dma_ahb.in) io.dma.ahb.in <> 0.U.asTypeOf(io.dma.ahb.in)
// io.dma_hrdata := 0.U // io.dma_hrdata := 0.U
// io.dma_hreadyout := 0.U // io.dma_hreadyout := 0.U
// io.dma_hresp := 0.U // io.dma_hresp := 0.U

View File

@ -19,8 +19,11 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG)) val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
// DMA slave // DMA slave
val dma_hsel = Input(Bool())
val dma_ahb = Flipped(new ahb_channel()) val dma = new Bundle{
val ahb= Flipped(new ahb_channel())
val hsel = Input(Bool())
val hreadyin = Input(Bool())}
// val dma_haddr = Input(UInt(32.W)) // val dma_haddr = Input(UInt(32.W))
// val dma_hburst = Input(UInt(3.W)) // val dma_hburst = Input(UInt(3.W))
// val dma_hmastlock = Input(Bool()) // val dma_hmastlock = Input(Bool())
@ -29,7 +32,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
// val dma_htrans = Input(UInt(2.W)) // val dma_htrans = Input(UInt(2.W))
// val dma_hwrite = Input(Bool()) // val dma_hwrite = Input(Bool())
// val dma_hwdata = Input(UInt(64.W)) // val dma_hwdata = Input(UInt(64.W))
val dma_hreadyin = Input(Bool())
// val dma_hrdata = Output(UInt(64.W)) // val dma_hrdata = Output(UInt(64.W))
// val dma_hreadyout = Output(Bool()) // val dma_hreadyout = Output(Bool())
// val dma_hresp = Output(Bool()) // val dma_hresp = Output(Bool())
@ -112,7 +115,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
swerv.io.ahb.in <> 0.U.asTypeOf(swerv.io.ahb.in) swerv.io.ahb.in <> 0.U.asTypeOf(swerv.io.ahb.in)
swerv.io.lsu_ahb.in <> 0.U.asTypeOf(swerv.io.lsu_ahb.in) swerv.io.lsu_ahb.in <> 0.U.asTypeOf(swerv.io.lsu_ahb.in)
swerv.io.sb_ahb.in <> 0.U.asTypeOf(swerv.io.sb_ahb.in) swerv.io.sb_ahb.in <> 0.U.asTypeOf(swerv.io.sb_ahb.in)
io.dma_ahb.in <> 0.U.asTypeOf(io.dma_ahb.in) io.dma.ahb.in <> 0.U.asTypeOf(io.dma.ahb.in)
// swerv.io.sb_hready := 0.U // swerv.io.sb_hready := 0.U
// swerv.io.hrdata := 0.U // swerv.io.hrdata := 0.U
// swerv.io.sb_hresp := 0.U // swerv.io.sb_hresp := 0.U
@ -154,8 +157,8 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
swerv.io.dma_axi <> io.dma_axi swerv.io.dma_axi <> io.dma_axi
// DMA Slave // DMA Slave
swerv.io.dma_hsel := io.dma_hsel swerv.io.dma.hsel := io.dma.hsel
swerv.io.dma_ahb.out <> io.dma_ahb.out swerv.io.dma.ahb.out <> io.dma.ahb.out
// swerv.io.dma_haddr := io.dma_haddr // swerv.io.dma_haddr := io.dma_haddr
// swerv.io.dma_hburst := io.dma_hburst // swerv.io.dma_hburst := io.dma_hburst
// swerv.io.dma_hmastlock := io.dma_hmastlock // swerv.io.dma_hmastlock := io.dma_hmastlock
@ -164,7 +167,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
// swerv.io.dma_htrans := io.dma_htrans // swerv.io.dma_htrans := io.dma_htrans
// swerv.io.dma_hwrite := io.dma_hwrite // swerv.io.dma_hwrite := io.dma_hwrite
// swerv.io.dma_hwdata := io.dma_hwdata // swerv.io.dma_hwdata := io.dma_hwdata
swerv.io.dma_hreadyin := io.dma_hreadyin swerv.io.dma.hreadyin := io.dma.hreadyin
swerv.io.lsu_bus_clk_en swerv.io.lsu_bus_clk_en
swerv.io.ifu_bus_clk_en swerv.io.ifu_bus_clk_en

View File

@ -4,3 +4,4 @@
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure ;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure ;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure ;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure

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