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lsu updated

This commit is contained in:
​Laraib Khan 2020-11-18 15:42:14 +05:00
parent 4b73eb7a6f
commit 2afae08254
370 changed files with 85015 additions and 34076 deletions
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1492
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@ -0,0 +1,135 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_div_wren",
"sources":[
"~el2_exu|el2_exu>io_dec_div_cancel"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_mp_fghr",
"sources":[
"~el2_exu|el2_exu>io_dec_tlu_flush_lower_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_lsu_rs1_d",
"sources":[
"~el2_exu|el2_exu>io_gpr_i0_rs1_d",
"~el2_exu|el2_exu>io_dec_extint_stall",
"~el2_exu|el2_exu>io_dec_tlu_meihap",
"~el2_exu|el2_exu>io_dec_i0_rs1_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d",
"~el2_exu|el2_exu>io_exu_i0_result_x",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_flush_final",
"sources":[
"~el2_exu|el2_exu>io_dec_tlu_flush_lower_r",
"~el2_exu|el2_exu>io_dec_i0_alu_decode_d",
"~el2_exu|el2_exu>io_i0_ap_jal",
"~el2_exu|el2_exu>io_i0_ap_predict_t",
"~el2_exu|el2_exu>io_i0_ap_predict_nt",
"~el2_exu|el2_exu>io_i0_ap_bge",
"~el2_exu|el2_exu>io_i0_ap_sub",
"~el2_exu|el2_exu>io_i0_ap_blt",
"~el2_exu|el2_exu>io_i0_ap_beq",
"~el2_exu|el2_exu>io_i0_ap_bne",
"~el2_exu|el2_exu>io_i0_ap_unsign",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_pret",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_prett",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_pja",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_pcall",
"~el2_exu|el2_exu>io_gpr_i0_rs1_d",
"~el2_exu|el2_exu>io_gpr_i0_rs2_d",
"~el2_exu|el2_exu>io_dec_i0_immed_d",
"~el2_exu|el2_exu>io_dbg_cmd_wrdata",
"~el2_exu|el2_exu>io_dec_i0_rs1_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs2_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d",
"~el2_exu|el2_exu>io_exu_i0_result_x",
"~el2_exu|el2_exu>io_dec_i0_pc_d",
"~el2_exu|el2_exu>io_dec_debug_wdata_rs1_d",
"~el2_exu|el2_exu>io_dec_i0_select_pc_d",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_flush_path_final",
"sources":[
"~el2_exu|el2_exu>io_dec_tlu_flush_path_r",
"~el2_exu|el2_exu>io_dec_tlu_flush_lower_r",
"~el2_exu|el2_exu>io_i0_ap_jal",
"~el2_exu|el2_exu>io_i0_ap_sub",
"~el2_exu|el2_exu>io_dec_i0_pc_d",
"~el2_exu|el2_exu>io_dec_i0_br_immed_d",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_pret",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_pja",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_pcall",
"~el2_exu|el2_exu>io_gpr_i0_rs2_d",
"~el2_exu|el2_exu>io_dec_i0_immed_d",
"~el2_exu|el2_exu>io_gpr_i0_rs1_d",
"~el2_exu|el2_exu>io_dbg_cmd_wrdata",
"~el2_exu|el2_exu>io_dec_i0_rs2_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d",
"~el2_exu|el2_exu>io_exu_i0_result_x",
"~el2_exu|el2_exu>io_dec_i0_rs1_en_d",
"~el2_exu|el2_exu>io_dec_debug_wdata_rs1_d",
"~el2_exu|el2_exu>io_dec_i0_select_pc_d",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_lsu_rs2_d",
"sources":[
"~el2_exu|el2_exu>io_gpr_i0_rs2_d",
"~el2_exu|el2_exu>io_dec_i0_rs2_en_d",
"~el2_exu|el2_exu>io_dec_extint_stall",
"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d",
"~el2_exu|el2_exu>io_exu_i0_result_x",
"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_exu.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_exu|el2_exu>i0_rs2_d"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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35
el2_exu_alu_ctl.anno.json
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@ -40,8 +40,8 @@
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
]
},
@ -82,19 +82,19 @@
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign"
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
]
},
{
@ -118,8 +118,8 @@
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
]
},
@ -139,19 +139,19 @@
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign"
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
]
},
{
@ -165,8 +165,8 @@
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pc_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_brimm_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in"
]
},
{
@ -184,12 +184,12 @@
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
]
},
{
@ -208,8 +208,8 @@
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
]
},
@ -224,6 +224,11 @@
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_exu_alu_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."

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el2_exu_alu_ctl.v
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@ -1,3 +1,24 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module el2_exu_alu_ctl(
input clock,
input reset,
@ -38,7 +59,7 @@ module el2_exu_alu_ctl(
input io_pp_in_valid,
input io_pp_in_br_error,
input io_pp_in_br_start_error,
input [31:0] io_pp_in_prett,
input [30:0] io_pp_in_prett,
input io_pp_in_pcall,
input io_pp_in_pret,
input io_pp_in_pja,
@ -59,7 +80,7 @@ module el2_exu_alu_ctl(
output io_predict_p_out_valid,
output io_predict_p_out_br_error,
output io_predict_p_out_br_start_error,
output [31:0] io_predict_p_out_prett,
output [30:0] io_predict_p_out_prett,
output io_predict_p_out_pcall,
output io_predict_p_out_pret,
output io_predict_p_out_pja,
@ -69,161 +90,194 @@ module el2_exu_alu_ctl(
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [30:0] _T; // @[Reg.scala 27:20]
reg [31:0] _T_1; // @[Reg.scala 27:20]
wire _T_180 = io_ap_sll | io_ap_srl; // @[el2_exu_alu_ctl.scala 80:41]
wire sel_shift = _T_180 | io_ap_sra; // @[el2_exu_alu_ctl.scala 80:53]
wire [9:0] _T_87 = {io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [18:0] _T_96 = {_T_87,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [27:0] _T_105 = {_T_96,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [30:0] _T_108 = {_T_105,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [9:0] _T_119 = {io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [18:0] _T_128 = {_T_119,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [27:0] _T_137 = {_T_128,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [30:0] _T_140 = {_T_137,io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [30:0] _T_141 = _T_108 & _T_140; // @[el2_exu_alu_ctl.scala 72:44]
wire [4:0] _T_146 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [9:0] _T_151 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [18:0] _T_160 = {_T_151,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [27:0] _T_169 = {_T_160,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [30:0] _T_172 = {_T_169,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [30:0] _T_174 = _T_172 & io_a_in[30:0]; // @[el2_exu_alu_ctl.scala 72:90]
wire [30:0] _T_175 = _T_141 | _T_174; // @[el2_exu_alu_ctl.scala 72:68]
wire [62:0] shift_extend = {_T_175,io_a_in}; // @[Cat.scala 29:58]
wire [5:0] _T_56 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58]
wire [5:0] _T_58 = 6'h20 - _T_56; // @[el2_exu_alu_ctl.scala 64:38]
wire [5:0] _T_65 = io_ap_sll ? _T_58 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_66 = io_ap_srl ? _T_56 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_68 = _T_65 | _T_66; // @[Mux.scala 27:72]
wire [5:0] _T_67 = io_ap_sra ? _T_56 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] shift_amount = _T_68 | _T_67; // @[Mux.scala 27:72]
wire [62:0] shift_long = shift_extend >> shift_amount; // @[el2_exu_alu_ctl.scala 75:32]
wire [4:0] _T_76 = _T_146 & io_b_in[4:0]; // @[el2_exu_alu_ctl.scala 69:55]
wire [62:0] _T_77 = 63'hffffffff << _T_76; // @[el2_exu_alu_ctl.scala 69:33]
wire [31:0] shift_mask = _T_77[31:0]; // @[el2_exu_alu_ctl.scala 69:14]
wire [31:0] sout = shift_long[31:0] & shift_mask; // @[el2_exu_alu_ctl.scala 77:34]
wire _T_181 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 81:41]
wire _T_182 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 81:56]
wire sel_adder = _T_181 & _T_182; // @[el2_exu_alu_ctl.scala 81:54]
wire [32:0] _T_5 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
wire [31:0] _T_6 = ~io_b_in; // @[el2_exu_alu_ctl.scala 43:63]
wire [32:0] _T_7 = {1'h0,_T_6}; // @[Cat.scala 29:58]
wire [32:0] _T_9 = _T_5 + _T_7; // @[el2_exu_alu_ctl.scala 43:48]
wire [32:0] _T_11 = _T_9 + 33'h1; // @[el2_exu_alu_ctl.scala 43:73]
wire [32:0] _T_18 = io_ap_sub ? _T_11 : 33'h0; // @[Mux.scala 27:72]
wire _T_13 = ~io_ap_sub; // @[el2_exu_alu_ctl.scala 44:5]
wire [32:0] _T_15 = {1'h0,io_b_in}; // @[Cat.scala 29:58]
wire [32:0] _T_17 = _T_5 + _T_15; // @[el2_exu_alu_ctl.scala 44:48]
wire [32:0] _T_19 = _T_13 ? _T_17 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] aout = _T_18 | _T_19; // @[Mux.scala 27:72]
wire _T_183 = io_ap_jal | io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 82:41]
wire _T_184 = _T_183 | io_pp_in_pja; // @[el2_exu_alu_ctl.scala 82:58]
wire sel_pc = _T_184 | io_pp_in_pret; // @[el2_exu_alu_ctl.scala 82:73]
wire [12:0] _T_187 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_186 = {io_pc_in,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_190 = _T_186[12:1] + _T_187[12:1]; // @[el2_lib.scala 201:31]
wire _T_199 = ~_T_190[12]; // @[el2_lib.scala 205:27]
wire _T_200 = _T_187[12] ^ _T_199; // @[el2_lib.scala 205:25]
wire [18:0] _T_211 = _T_200 ? _T_186[31:13] : 19'h0; // @[Mux.scala 27:72]
wire _T_203 = ~_T_187[12]; // @[el2_lib.scala 206:8]
wire _T_205 = _T_203 & _T_190[12]; // @[el2_lib.scala 206:14]
wire [18:0] _T_193 = _T_186[31:13] + 19'h1; // @[el2_lib.scala 202:27]
wire [18:0] _T_212 = _T_205 ? _T_193 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_214 = _T_211 | _T_212; // @[Mux.scala 27:72]
wire _T_209 = _T_187[12] & _T_199; // @[el2_lib.scala 207:13]
wire [18:0] _T_196 = _T_186[31:13] - 19'h1; // @[el2_lib.scala 203:27]
wire [18:0] _T_213 = _T_209 ? _T_196 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_215 = _T_214 | _T_213; // @[Mux.scala 27:72]
wire [31:0] pcout = {_T_215,_T_190[11:0],1'h0}; // @[Cat.scala 29:58]
wire _T_35 = ~io_ap_unsign; // @[el2_exu_alu_ctl.scala 53:30]
wire neg = aout[31]; // @[el2_exu_alu_ctl.scala 52:34]
wire _T_23 = ~io_a_in[31]; // @[el2_exu_alu_ctl.scala 48:14]
wire [31:0] bm = io_ap_sub ? _T_6 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17]
wire _T_25 = ~bm[31]; // @[el2_exu_alu_ctl.scala 48:29]
wire _T_26 = _T_23 & _T_25; // @[el2_exu_alu_ctl.scala 48:27]
wire _T_28 = _T_26 & neg; // @[el2_exu_alu_ctl.scala 48:37]
wire _T_31 = io_a_in[31] & bm[31]; // @[el2_exu_alu_ctl.scala 48:66]
wire _T_33 = ~neg; // @[el2_exu_alu_ctl.scala 48:78]
wire _T_34 = _T_31 & _T_33; // @[el2_exu_alu_ctl.scala 48:76]
wire ov = _T_28 | _T_34; // @[el2_exu_alu_ctl.scala 48:50]
wire _T_36 = neg ^ ov; // @[el2_exu_alu_ctl.scala 53:51]
wire _T_37 = _T_35 & _T_36; // @[el2_exu_alu_ctl.scala 53:44]
wire cout = aout[32]; // @[el2_exu_alu_ctl.scala 46:18]
wire _T_38 = ~cout; // @[el2_exu_alu_ctl.scala 53:78]
wire _T_39 = io_ap_unsign & _T_38; // @[el2_exu_alu_ctl.scala 53:76]
wire lt = _T_37 | _T_39; // @[el2_exu_alu_ctl.scala 53:58]
wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 85:40]
wire [31:0] _T_228 = {31'h0,slt_one}; // @[Cat.scala 29:58]
wire [31:0] _T_47 = io_csr_ren_in ? io_b_in : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_42 = io_a_in & io_b_in; // @[el2_exu_alu_ctl.scala 59:39]
wire [31:0] _T_48 = io_ap_land ? _T_42 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_51 = _T_47 | _T_48; // @[Mux.scala 27:72]
wire [31:0] _T_44 = io_a_in | io_b_in; // @[el2_exu_alu_ctl.scala 60:39]
wire [31:0] _T_49 = io_ap_lor ? _T_44 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_52 = _T_51 | _T_49; // @[Mux.scala 27:72]
wire [31:0] _T_46 = io_a_in ^ io_b_in; // @[el2_exu_alu_ctl.scala 61:39]
wire [31:0] _T_50 = io_ap_lxor ? _T_46 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] lout = _T_52 | _T_50; // @[Mux.scala 27:72]
wire eq = io_a_in == io_b_in; // @[el2_exu_alu_ctl.scala 50:38]
wire ne = ~eq; // @[el2_exu_alu_ctl.scala 51:29]
wire ge = ~lt; // @[el2_exu_alu_ctl.scala 54:29]
wire _T_236 = io_ap_beq & eq; // @[el2_exu_alu_ctl.scala 105:40]
wire _T_237 = io_ap_bne & ne; // @[el2_exu_alu_ctl.scala 105:59]
wire _T_238 = _T_236 | _T_237; // @[el2_exu_alu_ctl.scala 105:46]
wire _T_239 = io_ap_blt & lt; // @[el2_exu_alu_ctl.scala 105:85]
wire _T_240 = _T_238 | _T_239; // @[el2_exu_alu_ctl.scala 105:72]
wire _T_241 = io_ap_bge & ge; // @[el2_exu_alu_ctl.scala 105:104]
wire _T_242 = _T_240 | _T_241; // @[el2_exu_alu_ctl.scala 105:91]
wire actual_taken = _T_242 | sel_pc; // @[el2_exu_alu_ctl.scala 105:110]
wire _T_243 = io_valid_in & io_ap_predict_nt; // @[el2_exu_alu_ctl.scala 110:42]
wire _T_244 = ~actual_taken; // @[el2_exu_alu_ctl.scala 110:63]
wire _T_245 = _T_243 & _T_244; // @[el2_exu_alu_ctl.scala 110:61]
wire _T_246 = ~sel_pc; // @[el2_exu_alu_ctl.scala 110:79]
wire _T_247 = _T_245 & _T_246; // @[el2_exu_alu_ctl.scala 110:77]
wire _T_248 = io_valid_in & io_ap_predict_t; // @[el2_exu_alu_ctl.scala 110:104]
wire _T_249 = _T_248 & actual_taken; // @[el2_exu_alu_ctl.scala 110:123]
wire _T_251 = _T_249 & _T_246; // @[el2_exu_alu_ctl.scala 110:139]
wire _T_258 = io_ap_predict_t & _T_244; // @[el2_exu_alu_ctl.scala 115:45]
wire _T_259 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 115:82]
wire cond_mispredict = _T_258 | _T_259; // @[el2_exu_alu_ctl.scala 115:62]
wire _T_262 = io_pp_in_prett[31:1] != aout[31:1]; // @[el2_exu_alu_ctl.scala 118:68]
wire target_mispredict = io_pp_in_pret & _T_262; // @[el2_exu_alu_ctl.scala 118:44]
wire _T_263 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 120:42]
wire _T_264 = _T_263 | target_mispredict; // @[el2_exu_alu_ctl.scala 120:60]
wire _T_265 = _T_264 & io_valid_in; // @[el2_exu_alu_ctl.scala 120:81]
wire _T_266 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 120:97]
wire _T_267 = _T_265 & _T_266; // @[el2_exu_alu_ctl.scala 120:95]
wire _T_268 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 120:119]
wire _T_278 = io_pp_in_hist[1] & io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 126:39]
wire _T_280 = ~io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 126:63]
wire _T_281 = _T_280 & actual_taken; // @[el2_exu_alu_ctl.scala 126:81]
wire _T_282 = _T_278 | _T_281; // @[el2_exu_alu_ctl.scala 126:60]
wire _T_284 = ~io_pp_in_hist[1]; // @[el2_exu_alu_ctl.scala 127:6]
wire _T_286 = _T_284 & _T_244; // @[el2_exu_alu_ctl.scala 127:24]
wire _T_288 = io_pp_in_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 127:62]
wire _T_289 = _T_286 | _T_288; // @[el2_exu_alu_ctl.scala 127:42]
wire _T_293 = _T_266 & _T_268; // @[el2_exu_alu_ctl.scala 130:51]
wire _T_294 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 130:90]
assign io_result_ff = _T_1; // @[el2_exu_alu_ctl.scala 37:16]
assign io_flush_upper_out = _T_267 & _T_268; // @[el2_exu_alu_ctl.scala 120:26]
assign io_flush_final_out = _T_267 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 122:26]
assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 112:22]
assign io_pc_ff = _T; // @[el2_exu_alu_ctl.scala 35:12]
assign io_pred_correct_out = _T_247 | _T_251; // @[el2_exu_alu_ctl.scala 110:26]
assign io_predict_p_out_misp = _T_293 & _T_294; // @[el2_exu_alu_ctl.scala 129:30 el2_exu_alu_ctl.scala 130:30]
assign io_predict_p_out_ataken = _T_242 | sel_pc; // @[el2_exu_alu_ctl.scala 129:30 el2_exu_alu_ctl.scala 131:30]
assign io_predict_p_out_boffset = io_pp_in_boffset; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_pc4 = io_pp_in_pc4; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_hist = {_T_282,_T_289}; // @[el2_exu_alu_ctl.scala 129:30 el2_exu_alu_ctl.scala 132:30]
assign io_predict_p_out_toffset = io_pp_in_toffset; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_br_error = io_pp_in_br_error; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_br_start_error = io_pp_in_br_start_error; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_prett = io_pp_in_prett; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_pcall = io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_pret = io_pp_in_pret; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_pja = io_pp_in_pja; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_way = io_pp_in_way; // @[el2_exu_alu_ctl.scala 129:30]
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
reg [30:0] _T_1; // @[el2_lib.scala 514:16]
reg [31:0] _T_3; // @[el2_lib.scala 514:16]
wire [31:0] _T_5 = ~io_b_in; // @[el2_exu_alu_ctl.scala 39:37]
wire [31:0] bm = io_ap_sub ? _T_5 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17]
wire [32:0] _T_8 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
wire [32:0] _T_10 = {1'h0,_T_5}; // @[Cat.scala 29:58]
wire [32:0] _T_12 = _T_8 + _T_10; // @[el2_exu_alu_ctl.scala 42:55]
wire [32:0] _T_13 = {32'h0,io_ap_sub}; // @[Cat.scala 29:58]
wire [32:0] _T_15 = _T_12 + _T_13; // @[el2_exu_alu_ctl.scala 42:80]
wire [32:0] _T_18 = {1'h0,io_b_in}; // @[Cat.scala 29:58]
wire [32:0] _T_20 = _T_8 + _T_18; // @[el2_exu_alu_ctl.scala 42:132]
wire [32:0] _T_23 = _T_20 + _T_13; // @[el2_exu_alu_ctl.scala 42:157]
wire [32:0] aout = io_ap_sub ? _T_15 : _T_23; // @[el2_exu_alu_ctl.scala 42:14]
wire cout = aout[32]; // @[el2_exu_alu_ctl.scala 43:18]
wire _T_26 = ~io_a_in[31]; // @[el2_exu_alu_ctl.scala 45:14]
wire _T_28 = ~bm[31]; // @[el2_exu_alu_ctl.scala 45:29]
wire _T_29 = _T_26 & _T_28; // @[el2_exu_alu_ctl.scala 45:27]
wire _T_31 = _T_29 & aout[31]; // @[el2_exu_alu_ctl.scala 45:37]
wire _T_34 = io_a_in[31] & bm[31]; // @[el2_exu_alu_ctl.scala 45:66]
wire _T_36 = ~aout[31]; // @[el2_exu_alu_ctl.scala 45:78]
wire _T_37 = _T_34 & _T_36; // @[el2_exu_alu_ctl.scala 45:76]
wire ov = _T_31 | _T_37; // @[el2_exu_alu_ctl.scala 45:50]
wire eq = $signed(io_a_in) == $signed(io_b_in); // @[el2_exu_alu_ctl.scala 47:38]
wire ne = ~eq; // @[el2_exu_alu_ctl.scala 48:29]
wire _T_39 = ~io_ap_unsign; // @[el2_exu_alu_ctl.scala 50:30]
wire _T_40 = aout[31] ^ ov; // @[el2_exu_alu_ctl.scala 50:51]
wire _T_41 = _T_39 & _T_40; // @[el2_exu_alu_ctl.scala 50:44]
wire _T_42 = ~cout; // @[el2_exu_alu_ctl.scala 50:78]
wire _T_43 = io_ap_unsign & _T_42; // @[el2_exu_alu_ctl.scala 50:76]
wire lt = _T_41 | _T_43; // @[el2_exu_alu_ctl.scala 50:58]
wire ge = ~lt; // @[el2_exu_alu_ctl.scala 51:29]
wire [31:0] _T_63 = $signed(io_a_in) & $signed(io_b_in); // @[Mux.scala 27:72]
wire [31:0] _T_66 = $signed(io_a_in) | $signed(io_b_in); // @[Mux.scala 27:72]
wire [31:0] _T_69 = $signed(io_a_in) ^ $signed(io_b_in); // @[Mux.scala 27:72]
wire [31:0] _T_70 = io_csr_ren_in ? $signed(io_b_in) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_71 = io_ap_land ? $signed(_T_63) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_72 = io_ap_lor ? $signed(_T_66) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_73 = io_ap_lxor ? $signed(_T_69) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_75 = $signed(_T_70) | $signed(_T_71); // @[Mux.scala 27:72]
wire [31:0] _T_77 = $signed(_T_75) | $signed(_T_72); // @[Mux.scala 27:72]
wire [5:0] _T_84 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58]
wire [5:0] _T_86 = 6'h20 - _T_84; // @[el2_exu_alu_ctl.scala 61:38]
wire [5:0] _T_93 = io_ap_sll ? _T_86 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_94 = io_ap_srl ? _T_84 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_95 = io_ap_sra ? _T_84 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_96 = _T_93 | _T_94; // @[Mux.scala 27:72]
wire [5:0] shift_amount = _T_96 | _T_95; // @[Mux.scala 27:72]
wire [4:0] _T_102 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [4:0] _T_104 = _T_102 & io_b_in[4:0]; // @[el2_exu_alu_ctl.scala 66:61]
wire [62:0] _T_105 = 63'hffffffff << _T_104; // @[el2_exu_alu_ctl.scala 66:39]
wire [9:0] _T_115 = {io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [18:0] _T_124 = {_T_115,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [27:0] _T_133 = {_T_124,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [30:0] _T_136 = {_T_133,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [9:0] _T_147 = {io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [18:0] _T_156 = {_T_147,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [27:0] _T_165 = {_T_156,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [30:0] _T_168 = {_T_165,io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [30:0] _T_169 = _T_136 & _T_168; // @[el2_exu_alu_ctl.scala 69:44]
wire [9:0] _T_179 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [18:0] _T_188 = {_T_179,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [27:0] _T_197 = {_T_188,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [30:0] _T_200 = {_T_197,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [30:0] _T_202 = _T_200 & io_a_in[30:0]; // @[el2_exu_alu_ctl.scala 69:90]
wire [30:0] _T_203 = _T_169 | _T_202; // @[el2_exu_alu_ctl.scala 69:68]
wire [62:0] shift_extend = {_T_203,io_a_in}; // @[Cat.scala 29:58]
wire [62:0] shift_long = shift_extend >> shift_amount[4:0]; // @[el2_exu_alu_ctl.scala 72:32]
wire [31:0] shift_mask = _T_105[31:0]; // @[el2_exu_alu_ctl.scala 66:14]
wire [31:0] sout = shift_long[31:0] & shift_mask; // @[el2_exu_alu_ctl.scala 74:34]
wire _T_210 = io_ap_sll | io_ap_srl; // @[el2_exu_alu_ctl.scala 77:41]
wire sel_shift = _T_210 | io_ap_sra; // @[el2_exu_alu_ctl.scala 77:53]
wire _T_211 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 78:41]
wire _T_212 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 78:56]
wire sel_adder = _T_211 & _T_212; // @[el2_exu_alu_ctl.scala 78:54]
wire _T_213 = io_ap_jal | io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 79:41]
wire _T_214 = _T_213 | io_pp_in_pja; // @[el2_exu_alu_ctl.scala 79:58]
wire sel_pc = _T_214 | io_pp_in_pret; // @[el2_exu_alu_ctl.scala 79:73]
wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40]
wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_221 = _T_217[12:1] + _T_218[12:1]; // @[el2_lib.scala 208:31]
wire [18:0] _T_224 = _T_217[31:13] + 19'h1; // @[el2_lib.scala 209:27]
wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 210:27]
wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 212:28]
wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 212:26]
wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:8]
wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:14]
wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:14]
wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_245 = _T_242 | _T_243; // @[Mux.scala 27:72]
wire [18:0] _T_246 = _T_245 | _T_244; // @[Mux.scala 27:72]
wire [31:0] pcout = {_T_246,_T_221[11:0],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_250 = $signed(_T_77) | $signed(_T_73); // @[el2_exu_alu_ctl.scala 88:24]
wire [31:0] _T_251 = {31'h0,slt_one}; // @[Cat.scala 29:58]
wire [31:0] _T_252 = _T_250 | _T_251; // @[el2_exu_alu_ctl.scala 88:31]
wire [31:0] _T_259 = io_ap_csr_imm ? $signed(io_b_in) : $signed(io_a_in); // @[el2_exu_alu_ctl.scala 92:51]
wire [31:0] _T_260 = sel_shift ? sout : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_261 = sel_adder ? aout[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_262 = sel_pc ? pcout : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_263 = io_ap_csr_write ? _T_259 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_264 = _T_260 | _T_261; // @[Mux.scala 27:72]
wire [31:0] _T_265 = _T_264 | _T_262; // @[Mux.scala 27:72]
wire [31:0] _T_266 = _T_265 | _T_263; // @[Mux.scala 27:72]
wire _T_271 = io_ap_beq & eq; // @[el2_exu_alu_ctl.scala 101:40]
wire _T_272 = io_ap_bne & ne; // @[el2_exu_alu_ctl.scala 101:59]
wire _T_273 = _T_271 | _T_272; // @[el2_exu_alu_ctl.scala 101:46]
wire _T_274 = io_ap_blt & lt; // @[el2_exu_alu_ctl.scala 101:85]
wire _T_275 = _T_273 | _T_274; // @[el2_exu_alu_ctl.scala 101:72]
wire _T_276 = io_ap_bge & ge; // @[el2_exu_alu_ctl.scala 101:104]
wire _T_277 = _T_275 | _T_276; // @[el2_exu_alu_ctl.scala 101:91]
wire actual_taken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 101:110]
wire _T_278 = io_valid_in & io_ap_predict_nt; // @[el2_exu_alu_ctl.scala 106:42]
wire _T_279 = ~actual_taken; // @[el2_exu_alu_ctl.scala 106:63]
wire _T_280 = _T_278 & _T_279; // @[el2_exu_alu_ctl.scala 106:61]
wire _T_281 = ~sel_pc; // @[el2_exu_alu_ctl.scala 106:79]
wire _T_282 = _T_280 & _T_281; // @[el2_exu_alu_ctl.scala 106:77]
wire _T_283 = io_valid_in & io_ap_predict_t; // @[el2_exu_alu_ctl.scala 106:104]
wire _T_284 = _T_283 & actual_taken; // @[el2_exu_alu_ctl.scala 106:123]
wire _T_286 = _T_284 & _T_281; // @[el2_exu_alu_ctl.scala 106:139]
wire _T_293 = io_ap_predict_t & _T_279; // @[el2_exu_alu_ctl.scala 111:45]
wire _T_294 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 111:82]
wire cond_mispredict = _T_293 | _T_294; // @[el2_exu_alu_ctl.scala 111:62]
wire _T_296 = io_pp_in_prett != aout[31:1]; // @[el2_exu_alu_ctl.scala 114:62]
wire target_mispredict = io_pp_in_pret & _T_296; // @[el2_exu_alu_ctl.scala 114:44]
wire _T_297 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 116:42]
wire _T_298 = _T_297 | target_mispredict; // @[el2_exu_alu_ctl.scala 116:60]
wire _T_299 = _T_298 & io_valid_in; // @[el2_exu_alu_ctl.scala 116:81]
wire _T_300 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 116:97]
wire _T_301 = _T_299 & _T_300; // @[el2_exu_alu_ctl.scala 116:95]
wire _T_302 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 116:119]
wire _T_312 = io_pp_in_hist[1] & io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:39]
wire _T_314 = ~io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:63]
wire _T_315 = _T_314 & actual_taken; // @[el2_exu_alu_ctl.scala 122:81]
wire _T_316 = _T_312 | _T_315; // @[el2_exu_alu_ctl.scala 122:60]
wire _T_318 = ~io_pp_in_hist[1]; // @[el2_exu_alu_ctl.scala 123:6]
wire _T_320 = _T_318 & _T_279; // @[el2_exu_alu_ctl.scala 123:24]
wire _T_322 = io_pp_in_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 123:62]
wire _T_323 = _T_320 | _T_322; // @[el2_exu_alu_ctl.scala 123:42]
wire _T_327 = _T_300 & _T_302; // @[el2_exu_alu_ctl.scala 126:51]
wire _T_328 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 126:90]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
assign io_result_ff = _T_3; // @[el2_exu_alu_ctl.scala 37:16]
assign io_flush_upper_out = _T_301 & _T_302; // @[el2_exu_alu_ctl.scala 116:26]
assign io_flush_final_out = _T_301 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 118:26]
assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22]
assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12]
assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26]
assign io_predict_p_out_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:30]
assign io_predict_p_out_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:30]
assign io_predict_p_out_boffset = io_pp_in_boffset; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_pc4 = io_pp_in_pc4; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:30]
assign io_predict_p_out_toffset = io_pp_in_toffset; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_br_error = io_pp_in_br_error; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_br_start_error = io_pp_in_br_start_error; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_prett = io_pp_in_prett; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_pcall = io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_pret = io_pp_in_pret; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_pja = io_pp_in_pja; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_way = io_pp_in_way; // @[el2_exu_alu_ctl.scala 125:30]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_io_en = io_enable; // @[el2_lib.scala 511:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_1_io_en = io_enable; // @[el2_lib.scala 511:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
@ -260,42 +314,34 @@ initial begin
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T = _RAND_0[30:0];
_T_1 = _RAND_0[30:0];
_RAND_1 = {1{`RANDOM}};
_T_1 = _RAND_1[31:0];
_T_3 = _RAND_1[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_1 = 31'h0;
end
if (reset) begin
_T_3 = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
_T <= 31'h0;
end else if (io_enable) begin
_T <= io_pc_in;
_T_1 <= 31'h0;
end else begin
_T_1 <= io_pc_in;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin
_T_1 <= 32'h0;
end else if (io_enable) begin
if (sel_shift) begin
_T_1 <= sout;
end else if (sel_adder) begin
_T_1 <= aout[31:0];
end else if (sel_pc) begin
_T_1 <= pcout;
end else if (io_ap_csr_write) begin
if (io_ap_csr_imm) begin
_T_1 <= io_b_in;
end else begin
_T_1 <= io_a_in;
end
end else if (slt_one) begin
_T_1 <= _T_228;
end else begin
_T_1 <= lout;
end
_T_3 <= 32'h0;
end else begin
_T_3 <= _T_252 | _T_266;
end
end
endmodule

277
el2_lsu.anno.json
View File

@ -20,6 +20,53 @@
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_rdaddr",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m",
"sources":[
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_match_",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_match_",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wren",
@ -28,9 +75,9 @@
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
@ -48,7 +95,27 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_hi",
"sink":"~el2_lsu|el2_lsu>io_lsu_load_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_hi",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
@ -61,9 +128,11 @@
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
@ -73,9 +142,9 @@
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
@ -99,9 +168,9 @@
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
@ -118,13 +187,6 @@
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_ready",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_wren",
@ -134,48 +196,46 @@
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_hi",
"sources":[
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_match_",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_match_",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_ready",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_wraddr",
@ -184,9 +244,29 @@
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_store_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
@ -194,9 +274,19 @@
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_trxn",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_axi_arready",
"~el2_lsu|el2_lsu>io_lsu_axi_awready",
"~el2_lsu|el2_lsu>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_dma_ecc_error",
@ -215,37 +305,39 @@
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_busy",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_axi_arready",
"~el2_lsu|el2_lsu>io_lsu_axi_awready",
"~el2_lsu|el2_lsu>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_lo",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_hi",
"sink":"~el2_lsu|el2_lsu>io_lsu_result_m",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
@ -258,9 +350,9 @@
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
@ -276,15 +368,37 @@
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_lo",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_mken",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
@ -303,38 +417,9 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_lo",
"sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_valid_m",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_rdaddr",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
]
},
{
@ -345,9 +430,9 @@
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
@ -356,47 +441,43 @@
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_store_stall_any",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_misaligned",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_hi",
"sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_inv_r",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_hi",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
@ -406,8 +487,8 @@
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
"target":"el2_lsu.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",

22331
el2_lsu.fir
View File

File diff suppressed because it is too large Load Diff

13483
el2_lsu.v
View File

File diff suppressed because it is too large Load Diff

70
el2_lsu_bus_buffer.anno.json
View File

@ -1,4 +1,22 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_lo",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_hi",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_valid_m",
@ -22,6 +40,15 @@
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_hi",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
@ -61,19 +88,12 @@
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_araddr",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awaddr"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_lo",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
]
},
@ -86,23 +106,16 @@
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arsize",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awsize"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_buffer_full_any",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_d",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_dec_lsu_valid_raw_d",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r"
]
},
{
@ -127,13 +140,6 @@
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arcache",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awcache"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_tag_m",
@ -142,15 +148,6 @@
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_hi",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data",
@ -162,6 +159,11 @@
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu_bus_buffer.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."

12565
el2_lsu_bus_buffer.fir
View File

File diff suppressed because it is too large Load Diff

6752
el2_lsu_bus_buffer.v
View File

File diff suppressed because it is too large Load Diff

59
el2_lsu_bus_intf.anno.json
View File

@ -6,23 +6,6 @@
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_bus_read_data_m",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_store_data_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_by",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_word",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_inv_r",
@ -32,16 +15,24 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_trxn",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_bus_read_data_m",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_store_data_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_by",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_word",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_half",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_busy",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_trxn",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
@ -58,14 +49,23 @@
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_valid",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_is_sideeffects_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_by",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_by",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_word",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_half",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_word",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_half",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m"
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_busy",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
]
},
{
@ -82,6 +82,11 @@
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu_bus_intf.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."

13674
el2_lsu_bus_intf.fir
View File

File diff suppressed because it is too large Load Diff

7516
el2_lsu_bus_intf.v
View File

File diff suppressed because it is too large Load Diff

962
el2_pic_ctrl.anno.json
View File

@ -1,7 +1,7 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_pic_ctrl|el2_pic_ctrl>io_test",
"sink":"~el2_pic_ctrl|el2_pic_ctrl>io_picm_rd_data",
"sources":[
"~el2_pic_ctrl|el2_pic_ctrl>io_extintsrc_req"
]
@ -10,10 +10,966 @@
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>selected_int_priority"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_32"
},
{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_33"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_pic_ctrl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
"target":"el2_pic_ctrl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",

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/home/laraibkhan/Desktop/SweRV-Chislified/TEC_RV_ICG.v
/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v

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module TEC_RV_ICG(
module gated_latch
(
input logic SE, EN, CK,
output Q

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{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-structure-extractor\",\"revision\":\"2018.2.1+4-88400d3f\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-shell\",\"revision\":\"2018.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-compiler-indices\",\"revision\":\"0.1.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"}}

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target/scala-2.12/classes/vsrc/TEC_RV_ICG.v → src/main/resources/vsrc/gated_latch.v
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@ -1,5 +1,4 @@
module TEC_RV_ICG(
module gated_latch
(
input logic SE, EN, CK,
output Q

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src/main/scala/dbg/el2_dbg.scala Normal file
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package dbg
import chisel3._
import chisel3.util._
import lib._
object state_t {
val idle = 0.U(3.W)
val halting = 1.U(3.W)
val halted = 2.U(3.W)
val cmd_start = 3.U(3.W)
val cmd_wait = 4.U(3.W)
val cmd_done = 5.U(3.W)
val resuming = 6.U(3.W)
}
object sb_state_t {
val sbidle = 0.U(4.W)
val wait_rd = 1.U(4.W)
val wait_wr = 2.U(4.W)
val cmd_rd = 3.U(4.W)
val cmd_wr = 4.U(4.W)
val cmd_wr_addr = 5.U(4.W)
val cmd_wr_data = 6.U(4.W)
val rsp_rd = 7.U(4.W)
val rsp_wr = 8.U(4.W)
val done = 9.U(4.W)
}
class el2_dbg extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle {
val dbg_cmd_addr = Output(UInt(32.W))
val dbg_cmd_wrdata = Output(UInt(32.W))
val dbg_cmd_valid = Output(Bool())
val dbg_cmd_write = Output(Bool())
val dbg_cmd_type = Output(UInt(2.W))
val dbg_cmd_size = Output(UInt(2.W))
val dbg_core_rst_l = Output(Bool())
val core_dbg_rddata = Input(UInt(32.W))
val core_dbg_cmd_done = Input(Bool())
val core_dbg_cmd_fail = Input(Bool())
val dbg_dma_bubble = Output(Bool())
val dma_dbg_ready = Input(Bool())
val dbg_halt_req = Output(Bool())
val dbg_resume_req = Output(Bool())
val dec_tlu_debug_mode = Input(Bool())
val dec_tlu_dbg_halted = Input(Bool())
val dec_tlu_mpc_halted_only = Input(Bool())
val dec_tlu_resume_ack = Input(Bool())
val dmi_reg_en = Input(Bool())
val dmi_reg_addr = Input(UInt(7.W))
val dmi_reg_wr_en = Input(Bool())
val dmi_reg_wdata = Input(UInt(32.W))
val dmi_reg_rdata = Output(UInt(32.W))
val sb_axi_awvalid = Output(Bool())
val sb_axi_awready = Input(Bool())
val sb_axi_awid = Output(UInt(SB_BUS_TAG.W))
val sb_axi_awaddr = Output(UInt(32.W))
val sb_axi_awregion = Output(UInt(4.W))
val sb_axi_awlen = Output(UInt(8.W))
val sb_axi_awsize = Output(UInt(3.W))
val sb_axi_awburst = Output(UInt(2.W))
val sb_axi_awlock = Output(Bool())
val sb_axi_awcache = Output(UInt(4.W))
val sb_axi_awprot = Output(UInt(3.W))
val sb_axi_awqos = Output(UInt(4.W))
val sb_axi_wvalid = Output(Bool())
val sb_axi_wready = Input(Bool())
val sb_axi_wdata = Output(UInt(64.W))
val sb_axi_wstrb = Output(UInt(8.W))
val sb_axi_wlast = Output(Bool())
val sb_axi_bvalid = Input(Bool())
val sb_axi_bready = Output(Bool())
val sb_axi_bresp = Input(UInt(2.W))
val sb_axi_arvalid = Output(Bool())
val sb_axi_arready = Input(Bool())
val sb_axi_arid = Output(UInt(SB_BUS_TAG.W))
val sb_axi_araddr = Output(UInt(32.W))
val sb_axi_arregion = Output(UInt(4.W))
val sb_axi_arlen = Output(UInt(8.W))
val sb_axi_arsize = Output(UInt(3.W))
val sb_axi_arburst = Output(UInt(2.W))
val sb_axi_arlock = Output(Bool())
val sb_axi_arcache = Output(UInt(4.W))
val sb_axi_arprot = Output(UInt(3.W))
val sb_axi_arqos = Output(UInt(4.W))
val sb_axi_rvalid = Input(Bool())
val sb_axi_rready = Output(Bool())
val sb_axi_rdata = Input(UInt(64.W))
val sb_axi_rresp = Input(UInt(2.W))
val dbg_bus_clk_en = Input(Bool())
val dbg_rst_l = Input(Bool())
val clk_override = Input(Bool())
val scan_mode = Input(Bool())
})
val dbg_state = WireInit(state_t.idle)
val dbg_state_en = WireInit(false.B)
val sb_state = WireInit(sb_state_t.sbidle)
val sb_state_en = WireInit(Bool(), false.B)
val dmcontrol_reg = WireInit(0.U(32.W))
val sbaddress0_reg = WireInit(0.U(32.W))
val sbcs_sbbusy_wren = WireInit(false.B)
val sbcs_sberror_wren = WireInit(false.B)
val sb_bus_rdata = WireInit(0.U(64.W))
val sbaddress0_reg_wren1 = WireInit(false.B)
val dmstatus_reg = WireInit(0.U(32.W))
val dmstatus_havereset = WireInit(false.B)
val dmstatus_resumeack = WireInit(false.B)
val dmstatus_unavail = WireInit(false.B)
val dmstatus_running = WireInit(false.B)
val dmstatus_halted = WireInit(false.B)
val abstractcs_busy_wren = WireInit(false.B)
val abstractcs_busy_din = WireInit(false.B)
val sb_bus_cmd_read = WireInit(false.B)
val sb_bus_cmd_write_addr = WireInit(false.B)
val sb_bus_cmd_write_data = WireInit(false.B)
val sb_bus_rsp_read = WireInit(false.B)
val sb_bus_rsp_error = WireInit(false.B)
val sb_bus_rsp_write = WireInit(false.B)
val sbcs_sbbusy_din = WireInit(false.B)
val sbcs_sberror_din = WireInit(0.U(3.W))
val data1_reg = WireInit(0.U(32.W))
val sbcs_reg = WireInit(0.U(32.W))
val dbg_free_clken = io.dmi_reg_en | (dbg_state =/= state_t.idle) | dbg_state_en | io.dec_tlu_dbg_halted | io.clk_override
val sb_free_clken = io.dmi_reg_en | sb_state_en | (sb_state =/= sb_state_t.sbidle) | io.clk_override;
val dbg_free_clk = rvclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc
val sb_free_clk = rvclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc
val dbg_dm_rst_l = io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)
io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool()
val sbcs_wren = (io.dmi_reg_addr === "h38".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (sb_state === sb_state_t.sbidle)
val sbcs_sbbusyerror_wren = (sbcs_wren & io.dmi_reg_wdata(22)) | ((sb_state =/= sb_state_t.sbidle) & io.dmi_reg_en &
((io.dmi_reg_addr === "h39".U) | (io.dmi_reg_addr === "h3c".U) | (io.dmi_reg_addr === "h3d".U)))
val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt()
val temp_sbcs_22 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren)
} // sbcs_sbbusyerror_reg
val temp_sbcs_21 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren)
} // sbcs_sbbusy_reg
val temp_sbcs_20 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren)
} // sbcs_sbreadonaddr_reg
val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren)
} // sbcs_misc_reg
val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren)
} // sbcs_error_reg
sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W))
val sbcs_unaligned = (sbcs_reg(19, 17) === "b001".U) & sbaddress0_reg(0) |
(sbcs_reg(19, 17) === "b010".U) & sbaddress0_reg(1, 0).orR |
(sbcs_reg(19, 17) === "b011".U) & sbaddress0_reg(2, 0).orR
val sbcs_illegal_size = sbcs_reg(19)
val sbaddress0_incr = Fill(4, (sbcs_reg(19, 17) === "h0".U)) & "b0001".U | Fill(4, (sbcs_reg(19, 17) === "h1".U)) & "b0010".U |
Fill(4, (sbcs_reg(19, 17) === "h2".U)) & "b0100".U | Fill(4, (sbcs_reg(19, 17) === "h3".U)) & "b1000".U
val sbdata0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U)
val sbdata0_reg_wren1 = (sb_state === sb_state_t.rsp_rd) & sb_state_en & !sbcs_sberror_wren
val sbdata0_reg_wren = sbdata0_reg_wren0 | sbdata0_reg_wren1
val sbdata1_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3d".U)
val sbdata1_reg_wren1 = (sb_state === sb_state_t.rsp_rd) & sb_state_en & !sbcs_sberror_wren
val sbdata1_reg_wren = sbdata1_reg_wren0 | sbdata1_reg_wren1
val sbdata0_din = Fill(32, sbdata0_reg_wren0) & io.dmi_reg_wdata |
Fill(32, sbdata0_reg_wren1) & sb_bus_rdata(31, 0)
val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata |
Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32)
val sbdata0_reg = withReset(!dbg_dm_rst_l) {
rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode)
} // dbg_sbdata0_reg
val sbdata1_reg = withReset(!dbg_dm_rst_l) {
rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode)
} // dbg_sbdata1_reg
val sbaddress0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h39".U)
val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1
val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata |
Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr))
sbaddress0_reg := withReset(!dbg_dm_rst_l) {
rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode)
} // dbg_sbaddress0_reg
val sbreadonaddr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h39".U) & sbcs_reg(20)
val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15)
val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U)
val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en
val dm_temp = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
RegEnable(
Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)),
0.U, dmcontrol_wren)
} // dmcontrolff
val dm_temp_0 = withClockAndReset(dbg_free_clk, io.dbg_rst_l) {
RegEnable(io.dmi_reg_wdata(0), 0.U, dmcontrol_wren)
} // dmcontrol_dmactive_ff
val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0)
dmcontrol_reg := temp
val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
RegNext(dmcontrol_wren, 0.U)
} // dmcontrol_wrenff
dmstatus_reg := Cat(0.U(12.W), Fill(2, dmstatus_havereset), Fill(2, dmstatus_resumeack), 0.U(2.W), Fill(2, dmstatus_unavail), Fill(2, dmstatus_running), Fill(2, dmstatus_halted), 1.U(1.W), 0.U(3.W), 2.U(4.W))
val dmstatus_resumeack_wren = (dbg_state === state_t.resuming) & io.dec_tlu_resume_ack | dmstatus_resumeack & !dmcontrol_reg(30)
val dmstatus_resumeack_din = (dbg_state === state_t.resuming) & io.dec_tlu_resume_ack
val dmstatus_havereset_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_wdata(1) & io.dmi_reg_en & io.dmi_reg_wr_en
val dmstatus_havereset_rst = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_wdata(28) & io.dmi_reg_en & io.dmi_reg_wr_en;
val temp_rst = reset.asBool()
dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool()
dmstatus_running := ~(dmstatus_unavail | dmstatus_halted)
dmstatus_resumeack := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren)
} // dmstatus_resumeack_reg
dmstatus_halted := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U)
} // dmstatus_halted_reg
dmstatus_havereset := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
RegEnable(~dmstatus_havereset_rst, 0.U, dmstatus_havereset_wren)
} // dmstatus_havereset_reg
val haltsum0_reg = Cat(0.U(31.W), dmstatus_halted)
val abstractcs_reg = WireInit(2.U(32.W))
val abstractcs_error_sel0 = abstractcs_reg(12) & io.dmi_reg_en & (io.dmi_reg_wr_en & ((io.dmi_reg_addr === "h16".U) | (io.dmi_reg_addr === "h17".U)) | (io.dmi_reg_addr === "h4".U))
val abstractcs_error_sel1 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h17".U) & !((io.dmi_reg_wdata(31, 24) === 0.U) | (io.dmi_reg_wdata(31, 24) === "h2".U))
val abstractcs_error_sel2 = io.core_dbg_cmd_done & io.core_dbg_cmd_fail
val abstractcs_error_sel3 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h17".U) & !dmstatus_reg(9);
val abstractcs_error_sel4 = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en &
((io.dmi_reg_wdata(22, 20) =/= "b010".U) | ((io.dmi_reg_wdata(31, 24) === "h2".U) && data1_reg(1, 0).orR))
val abstractcs_error_sel5 = (io.dmi_reg_addr === "h16".U) & io.dmi_reg_en & io.dmi_reg_wr_en
val abstractcs_error_selor = abstractcs_error_sel0 | abstractcs_error_sel1 | abstractcs_error_sel2 | abstractcs_error_sel3 | abstractcs_error_sel4 | abstractcs_error_sel5
val abstractcs_error_din = (Fill(3, abstractcs_error_sel0) & "b001".U) |
(Fill(3, abstractcs_error_sel1) & "b010".U) |
(Fill(3, abstractcs_error_sel2) & "b011".U) |
(Fill(3, abstractcs_error_sel3) & "b100".U) |
(Fill(3, abstractcs_error_sel4) & "b111".U) |
(Fill(3, abstractcs_error_sel5) & (~io.dmi_reg_wdata(10, 8)).asUInt() & abstractcs_reg(10, 8)) |
(Fill(3, (~abstractcs_error_selor).asUInt()) & abstractcs_reg(10, 8))
val abs_temp_12 = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren)
} // dmabstractcs_busy_reg
val abs_temp_10_8 = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
RegNext(abstractcs_error_din(2, 0), 0.U)
} // dmabstractcs_error_reg
abstractcs_reg := Cat(0.U(19.W), abs_temp_12, 0.U(1.W), abs_temp_10_8, 2.U(8.W))
val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted)
val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0))
val command_reg = withReset(!dbg_dm_rst_l) {
RegEnable(command_din, 0.U, command_wren)
} // dmcommand_reg
val data0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h4".U) & (dbg_state === state_t.halted)
val data0_reg_wren1 = io.core_dbg_cmd_done & (dbg_state === state_t.cmd_wait) & !command_reg(16)
val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1
val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata
val data0_reg = withReset(!dbg_dm_rst_l) {
RegEnable(data0_din, 0.U, data0_reg_wren)
} // dbg_data0_reg
val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted))
val data1_din = Fill(32, data1_reg_wren) & io.dmi_reg_wdata
data1_reg := withReset(!dbg_dm_rst_l) {
rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode)
} // dbg_data1_reg
val dbg_nxtstate = WireInit(state_t.idle)
dbg_nxtstate := state_t.idle
dbg_state_en := false.B
abstractcs_busy_wren := false.B
abstractcs_busy_din := false.B
io.dbg_halt_req := false.B
io.dbg_resume_req := false.B
switch(dbg_state) {
is(state_t.idle) {
dbg_nxtstate := Mux(dmstatus_reg(9) | io.dec_tlu_mpc_halted_only, state_t.halted, state_t.halting)
dbg_state_en := ((dmcontrol_reg(31) & !io.dec_tlu_debug_mode) | dmstatus_reg(9) | io.dec_tlu_mpc_halted_only) & !dmcontrol_reg(1)
io.dbg_halt_req := (dmcontrol_reg(31) & !dmcontrol_reg(1)).asBool()
}
is(state_t.halting) {
dbg_nxtstate := Mux(dmcontrol_reg(1), state_t.idle, state_t.halted)
dbg_state_en := dmstatus_reg(9) | dmcontrol_reg(1)
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool()
}
is(state_t.halted) {
dbg_nxtstate := Mux(dmstatus_reg(9) & !dmcontrol_reg(1),
Mux(dmcontrol_reg(30) & !dmcontrol_reg(3), state_t.resuming, state_t.cmd_start),
Mux(dmcontrol_reg(31), state_t.halting, state_t.idle))
dbg_state_en := dmstatus_reg(9) & dmcontrol_reg(30) & !dmcontrol_reg(31) & dmcontrol_wren_Q | command_wren |
dmcontrol_reg(1) | !(dmstatus_reg(9) | io.dec_tlu_mpc_halted_only)
abstractcs_busy_wren := dbg_state_en & (dbg_nxtstate === state_t.cmd_start)
abstractcs_busy_din := "b1".U
io.dbg_resume_req := (dbg_state_en & (dbg_nxtstate === state_t.resuming)).asBool()
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool()
}
is(state_t.cmd_start) {
dbg_nxtstate := Mux(dmcontrol_reg(1), state_t.idle, Mux(abstractcs_reg(10, 8).orR, state_t.cmd_done, state_t.cmd_wait))
dbg_state_en := io.dbg_cmd_valid | abstractcs_reg(10, 8).orR | dmcontrol_reg(1)
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool()
}
is(state_t.cmd_wait) {
dbg_nxtstate := Mux(dmcontrol_reg(1), state_t.idle, state_t.cmd_done)
dbg_state_en := io.core_dbg_cmd_done | dmcontrol_reg(1)
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool()
}
is(state_t.cmd_done) {
dbg_nxtstate := Mux(dmcontrol_reg(1), state_t.idle, state_t.halted)
dbg_state_en := true.B
abstractcs_busy_wren := dbg_state_en
abstractcs_busy_din := "b0".U
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool()
}
is(state_t.resuming) {
dbg_nxtstate := state_t.idle;
dbg_state_en := dmstatus_reg(17) | dmcontrol_reg(1)
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool()
}}
val dmi_reg_rdata_din = Fill(32, io.dmi_reg_addr === "h4".U).asUInt & data0_reg | Fill(32, io.dmi_reg_addr === "h5".U) & data1_reg |
Fill(32, io.dmi_reg_addr === "h10".U) & dmcontrol_reg | Fill(32, io.dmi_reg_addr === "h11".U) & dmstatus_reg |
Fill(32, io.dmi_reg_addr === "h16".U) & abstractcs_reg | Fill(32, io.dmi_reg_addr === "h17".U) & command_reg |
Fill(32, io.dmi_reg_addr === "h40".U) & haltsum0_reg | Fill(32, io.dmi_reg_addr === "h38".U) & sbcs_reg |
Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg |
Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg
dbg_state := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l & temp_rst) {
RegEnable(dbg_nxtstate, 0.U, dbg_state_en)
} // dbg_state_reg
io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en)
} // dmi_rddata_reg
io.dbg_cmd_addr := Mux((command_reg(31, 24) === "h2".U), Cat(data1_reg(31, 2), "b00".U), Cat(0.U(20.W), command_reg(11, 0)))
io.dbg_cmd_wrdata := data0_reg(31, 0)
io.dbg_cmd_valid := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) & io.dma_dbg_ready).asBool()
io.dbg_cmd_write := command_reg(16).asBool()
io.dbg_cmd_type := Mux((command_reg(31, 24) === "h2".U), "b10".U, Cat("b0".U, (command_reg(15, 12) === "b0".U)))
io.dbg_cmd_size := command_reg(21, 20)
io.dbg_dma_bubble := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) | (dbg_state === state_t.cmd_wait)).asBool()
val sb_nxtstate = WireInit(sb_state_t.sbidle)
sb_nxtstate := sb_state_t.sbidle
//sb_state_en := true.B
sbcs_sbbusy_wren := false.B
sbcs_sbbusy_din := false.B
sbcs_sberror_wren := false.B
sbcs_sberror_din := 0.U(3.W)
sbaddress0_reg_wren1 := false.B
switch(sb_state) {
is(sb_state_t.sbidle) {
sb_nxtstate := Mux(sbdata0wr_access, sb_state_t.wait_wr, sb_state_t.wait_rd)
sb_state_en := sbdata0wr_access | sbreadondata_access | sbreadonaddr_access
sbcs_sbbusy_wren := sb_state_en
sbcs_sbbusy_din := true.B
sbcs_sberror_wren := sbcs_wren & io.dmi_reg_wdata(14, 12).orR
sbcs_sberror_din := !io.dmi_reg_wdata(14, 12) & sbcs_reg(14, 12)
}
is(sb_state_t.wait_rd) {
sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_rd)
sb_state_en := io.dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size
sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size
sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U, "b100".U)
}
is(sb_state_t.wait_wr) {
sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_wr)
sb_state_en := io.dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size
sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size;
sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U, "b100".U)
}
is(sb_state_t.cmd_rd) {
sb_nxtstate := sb_state_t.rsp_rd
sb_state_en := sb_bus_cmd_read & io.dbg_bus_clk_en
}
is(sb_state_t.cmd_wr) {
sb_nxtstate := Mux(sb_bus_cmd_write_addr & sb_bus_cmd_write_data, sb_state_t.rsp_wr, Mux(sb_bus_cmd_write_data, sb_state_t.cmd_wr_addr, sb_state_t.cmd_wr_data))
sb_state_en := (sb_bus_cmd_write_addr | sb_bus_cmd_write_data) & io.dbg_bus_clk_en
}
is(sb_state_t.cmd_wr_addr) {
sb_nxtstate := sb_state_t.rsp_wr
sb_state_en := sb_bus_cmd_write_addr & io.dbg_bus_clk_en
}
is(sb_state_t.cmd_wr_data) {
sb_nxtstate := sb_state_t.rsp_wr
sb_state_en := sb_bus_cmd_write_data & io.dbg_bus_clk_en
}
is(sb_state_t.rsp_rd) {
sb_nxtstate := sb_state_t.done
sb_state_en := sb_bus_rsp_read & io.dbg_bus_clk_en
sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error
sbcs_sberror_din := "b010".U
}
is(sb_state_t.rsp_wr) {
sb_nxtstate := sb_state_t.done;
sb_state_en := sb_bus_rsp_write & io.dbg_bus_clk_en
sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error
sbcs_sberror_din := "b010".U
}
is(sb_state_t.done) {
sb_nxtstate := sb_state_t.sbidle;
sb_state_en := true.B
sbcs_sbbusy_wren := true.B
sbcs_sbbusy_din := false.B
sbaddress0_reg_wren1 := sbcs_reg(16)
}}
sb_state := withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
RegEnable(sb_nxtstate, 0.U, sb_state_en)
} // sb_state_reg
sb_bus_cmd_read := io.sb_axi_arvalid & io.sb_axi_arready
sb_bus_cmd_write_addr := io.sb_axi_awvalid & io.sb_axi_awready
sb_bus_cmd_write_data := io.sb_axi_wvalid & io.sb_axi_wready
sb_bus_rsp_read := io.sb_axi_rvalid & io.sb_axi_rready
sb_bus_rsp_write := io.sb_axi_bvalid & io.sb_axi_bready
sb_bus_rsp_error := sb_bus_rsp_read & io.sb_axi_rresp(1, 0).orR | sb_bus_rsp_write & io.sb_axi_bresp(1, 0).orR
io.sb_axi_awvalid := ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_addr)).asBool()
io.sb_axi_awaddr := sbaddress0_reg
io.sb_axi_awid := 0.U
io.sb_axi_awsize := sbcs_reg(19, 17)
io.sb_axi_awprot := 0.U
io.sb_axi_awcache := "b1111".U
io.sb_axi_awregion := sbaddress0_reg(31, 28)
io.sb_axi_awlen := 0.U
io.sb_axi_awburst := "b01".U
io.sb_axi_awqos := 0.U
io.sb_axi_awlock := false.B
io.sb_axi_wvalid := ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_data)).asBool()
io.sb_axi_wdata := Fill(64, (sbcs_reg(19, 17) === 0.U)) & Fill(8, (sbdata0_reg(7, 0))) | Fill(64, (sbcs_reg(19, 17) === "h1".U)) & Fill(4, sbdata0_reg(15, 0)) |
Fill(64, (sbcs_reg(19, 17) === "h2".U)) & Fill(2, (sbdata0_reg(31, 0))) | Fill(64, (sbcs_reg(19, 17) === "h3".U)) & Cat(sbdata1_reg(31, 0), sbdata0_reg(31, 0))
io.sb_axi_wstrb := Fill(8, (sbcs_reg(19, 17) === "h0".U)) & ("h1".U(8.W) << sbaddress0_reg(2, 0)) |
Fill(8, (sbcs_reg(19, 17) === "h1".U)) & ("h3".U(8.W) << Cat(sbaddress0_reg(2, 1), "b0".U)) |
Fill(8, (sbcs_reg(19, 17) === "h2".U)) & ("hf".U(8.W) << Cat(sbaddress0_reg(2), "b00".U)) |
Fill(8, (sbcs_reg(19, 17) === "h3".U)) & "hff".U
io.sb_axi_wlast := true.B
io.sb_axi_arvalid := (sb_state === sb_state_t.cmd_rd).asBool()
io.sb_axi_araddr := sbaddress0_reg
io.sb_axi_arid := 0.U
io.sb_axi_arsize := sbcs_reg(19, 17)
io.sb_axi_arprot := 0.U
io.sb_axi_arcache := 0.U
io.sb_axi_arregion := sbaddress0_reg(31, 28)
io.sb_axi_arlen := 0.U
io.sb_axi_arburst := "b01".U
io.sb_axi_arqos := 0.U
io.sb_axi_arlock := false.B
io.sb_axi_bready := true.B
io.sb_axi_rready := true.B
sb_bus_rdata := Fill(64, (sbcs_reg(19, 17) === "h0".U)) & ((io.sb_axi_rdata(63, 0) >> 8.U * sbaddress0_reg(2, 0)) & "hff".U(64.W)) |
Fill(64, (sbcs_reg(19, 17) === "h1".U)) & ((io.sb_axi_rdata(63, 0) >> 16.U * sbaddress0_reg(2, 1)) & "hffff".U(64.W)) |
Fill(64, (sbcs_reg(19, 17) === "h2".U)) & ((io.sb_axi_rdata(63, 0) >> 32.U * sbaddress0_reg(2)) & "hffff_ffff".U(64.W)) |
Fill(64, (sbcs_reg(19, 17) === "h3".U)) & io.sb_axi_rdata(63, 0)
}
object debug extends App {
chisel3.Driver.emitVerilog(new el2_dbg)
}

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src/main/scala/dec/el2_dec.scala Normal file
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package dec
import chisel3._
import chisel3.util._
import include._
import lib._
class el2_dec_IO extends Bundle with el2_lib {
//val clk = Input(Clock())
val free_clk = Input(Clock())
val active_clk = Input(Clock())
val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
val dec_extint_stall = Output(Bool())
val dec_i0_decode_d = Output(Bool())
val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating
// val rst_l = Input(Bool()) // reset, active low
val rst_vec = Input(UInt(32.W)) // [31:1] reset vector, from core pins
val nmi_int = Input(Bool()) // NMI pin
val nmi_vec = Input(UInt(32.W)) // [31:1] NMI vector, from pins
val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU
val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU
val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw)
val o_cpu_halt_ack = Output(Bool()) // Halt request ack
val o_cpu_run_ack = Output(Bool()) // Run request ack
val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
val core_id = Input(UInt(32.W)) // [31:4] CORE ID
// external MPC halt/run interface
val mpc_debug_halt_req = Input(Bool()) // Async halt request
val mpc_debug_run_req = Input(Bool()) // Async run request
val mpc_reset_run_req = Input(Bool()) // Run/halt after reset
val mpc_debug_halt_ack = Output(Bool()) // Halt ack
val mpc_debug_run_ack = Output(Bool()) // Run ack
val debug_brkpt_status = Output(Bool()) // debug breakpoint
val exu_pmu_i0_br_misp = Input(Bool()) // slot 0 branch misp
val exu_pmu_i0_br_ataken = Input(Bool()) // slot 0 branch actual taken
val exu_pmu_i0_pc4 = Input(Bool()) // slot 0 4 byte branch
val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m
val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r
val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back
val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error
val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data
val lsu_pmu_bus_trxn = Input(Bool()) // D side bus transaction
val lsu_pmu_bus_misaligned = Input(Bool()) // D side bus misaligned
val lsu_pmu_bus_error = Input(Bool()) // D side bus error
val lsu_pmu_bus_busy = Input(Bool()) // D side bus busy
val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned
val lsu_pmu_load_external_m = Input(Bool()) // D side bus load
val lsu_pmu_store_external_m = Input(Bool()) // D side bus store
val dma_pmu_dccm_read = Input(Bool()) // DMA DCCM read
val dma_pmu_dccm_write = Input(Bool()) // DMA DCCM write
val dma_pmu_any_read = Input(Bool()) // DMA read
val dma_pmu_any_write = Input(Bool()) // DMA write
val lsu_fir_addr = Input(UInt(32.W)) //[31:1] Fast int address
val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error
val ifu_pmu_instr_aligned = Input(Bool()) // aligned instructions
val ifu_pmu_fetch_stall = Input(Bool()) // fetch unit stalled
val ifu_pmu_ic_miss = Input(Bool()) // icache miss
val ifu_pmu_ic_hit = Input(Bool()) // icache hit
val ifu_pmu_bus_error = Input(Bool()) // Instruction side bus error
val ifu_pmu_bus_busy = Input(Bool()) // Instruction side bus busy
val ifu_pmu_bus_trxn = Input(Bool()) // Instruction side bus transaction
val ifu_ic_error_start = Input(Bool()) // IC single bit error
val ifu_iccm_rd_ecc_single_err = Input(Bool()) // ICCM single bit error
val lsu_trigger_match_m = Input(UInt(4.W))
val dbg_cmd_valid = Input(Bool()) // debugger abstract command valid
val dbg_cmd_write = Input(Bool()) // command is a write
val dbg_cmd_type = Input(UInt(2.W)) // command type
val dbg_cmd_addr = Input(UInt(32.W)) // command address
val dbg_cmd_wrdata = Input(UInt(2.W)) // command write data, for fence/fence_i
val ifu_i0_icaf = Input(Bool()) // icache access fault
val ifu_i0_icaf_type = Input(UInt(2.W))
val ifu_i0_icaf_f1 = Input(Bool()) // i0 has access fault on second fetch group
val ifu_i0_dbecc = Input(Bool()) // icache/iccm double-bit error
val lsu_idle_any = Input(Bool()) // lsu idle for halting
val i0_brp = Input(new el2_br_pkt_t) // branch packet
val ifu_i0_bp_index = Input(UInt(BTB_ADDR_HI.W)) // BP index
val ifu_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
val ifu_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
val lsu_error_pkt_r = Input(new el2_lsu_error_pkt_t) // LSU exception/error packet
val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter
val lsu_imprecise_error_load_any = Input(Bool()) // LSU imprecise load bus error
val lsu_imprecise_error_store_any = Input(Bool()) // LSU imprecise store bus error
val lsu_imprecise_error_addr_any = Input(UInt(32.W)) // LSU imprecise bus error address
val exu_div_result = Input(UInt(32.W)) // final div result
val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR
val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instruction
val lsu_result_m = Input(UInt(32.W)) // load result
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data
val lsu_load_stall_any = Input(Bool()) // This is for blocking loads
val lsu_store_stall_any = Input(Bool()) // This is for blocking stores
val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode, pmu event
val dma_iccm_stall_any = Input(Bool()) // iccm stalled, pmu event
val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error
val exu_flush_final = Input(Bool()) // slot0 flush
val exu_npc_r = Input(UInt(32.W)) // next PC
val exu_i0_result_x = Input(UInt(32.W)) // alu result x
val ifu_i0_valid = Input(Bool()) // fetch valids to instruction buffer
val ifu_i0_instr = Input(UInt(32.W)) // fetch inst's to instruction buffer
val ifu_i0_pc = Input(UInt(32.W)) // pc's for instruction buffer
val ifu_i0_pc4 = Input(Bool()) // indication of 4B or 2B for corresponding inst
val exu_i0_pc_x = Input(UInt(32.W)) // pc's for e1 from the alu's
val mexintpend = Input(Bool()) // External interrupt pending
val timer_int = Input(Bool()) // Timer interrupt pending (from pin)
val soft_int = Input(Bool()) // Software interrupt pending (from pin)
val pic_claimid = Input(UInt(8.W)) // PIC claimid
val pic_pl = Input(UInt(4.W)) // PIC priv level
val mhwakeup = Input(Bool()) // High priority wakeup
val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC, Current priv level
val dec_tlu_meipt = Output(UInt(4.W)) // to PIC
val ifu_ic_debug_rd_data = Input(UInt(70.W)) // diagnostic icache read data
val ifu_ic_debug_rd_data_valid = Input(Bool()) // diagnostic icache read data valid
val dec_tlu_ic_diag_pkt = Output(new el2_cache_debug_pkt_t) // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
// Debug start
val dbg_halt_req = Input(Bool()) // DM requests a halt
val dbg_resume_req = Input(Bool()) // DM requests a resume
val ifu_miss_state_idle = Input(Bool()) // I-side miss buffer empty
val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command
val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode
val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge
val dec_tlu_flush_noredir_r = Output(Bool()) // Tell fetch to idle on this flush
val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC
val dec_tlu_flush_leak_one_r = Output(Bool()) // single step
val dec_tlu_flush_err_r = Output(Bool()) // iside perr/ecc rfpc
val dec_tlu_meihap = Output(UInt(32.W)) // Fast ext int base
val dec_debug_wdata_rs1_d = Output(Bool()) // insert debug write data into rs1 at decode
val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data
val dec_dbg_cmd_done = Output(Bool()) // abstract command is done
val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address)
val trigger_pkt_any = Output(Vec(4,new el2_trigger_pkt_t)) // info needed by debug trigger blocks
val dec_tlu_force_halt = Output(UInt(1.W)) // halt has been forced
// Debug end
// branch info from pipe0 for errors or counter updates
val exu_i0_br_hist_r = Input(UInt(2.W)) // history
val exu_i0_br_error_r = Input(Bool()) // error
val exu_i0_br_start_error_r = Input(Bool()) // start error
val exu_i0_br_valid_r = Input(Bool()) // valid
val exu_i0_br_mp_r = Input(Bool()) // mispredict
val exu_i0_br_middle_r = Input(Bool()) // middle of bank
val exu_i0_br_way_r = Input(Bool()) // way hit or repl
val dec_i0_rs1_en_d = Output(Bool()) // Qualify GPR RS1 data
val dec_i0_rs2_en_d = Output(Bool()) // Qualify GPR RS2 data
val gpr_i0_rs1_d = Output(UInt(32.W)) // gpr rs1 data
val gpr_i0_rs2_d = Output(UInt(32.W)) // gpr rs2 data
val dec_i0_immed_d = Output(UInt(32.W)) // immediate data
val dec_i0_br_immed_d = Output(UInt(13.W)) // br immediate data
val i0_ap = Output(new el2_alu_pkt_t)// alu packet
val dec_i0_alu_decode_d = Output(Bool()) // schedule on D-stage alu
val dec_i0_select_pc_d = Output(Bool()) // select pc onto rs1 for jal's
val dec_i0_pc_d = Output(UInt(32.W)) // pc's at decode
val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // rs1 bypass enable
val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // rs2 bypass enable
val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // rs1 bypass data
val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // rs2 bypass data
val lsu_p = Output(new el2_lsu_pkt_t) // lsu packet
val mul_p = Output(new el2_mul_pkt_t) // mul packet
val div_p = Output(new el2_div_pkt_t) // div packet
val dec_div_cancel = Output(Bool()) // cancel divide operation
val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses
val dec_csr_ren_d = Output(Bool()) // csr read enable
val dec_tlu_flush_lower_r = Output(Bool()) // tlu flush due to late mp, exception, rfpc, or int
val dec_tlu_flush_path_r = Output(UInt(32.W)) // tlu flush target
val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state
val dec_tlu_fence_i_r = Output(Bool()) // flush is a fence_i rfnpc, flush icache
val pred_correct_npc_x = Output(UInt(32.W)) // npc if prediction is correct at e2 stage
val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet
val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc
val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
val dec_i0_predict_p_d = Output(new el2_predict_pkt_t) // prediction packet to alus
val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr
val i0_predict_index_d = Output(UInt(BHT_ADDR_HI.W)) // DEC predict index
val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag
val dec_lsu_valid_raw_d = Output(Bool())
val dec_tlu_mrac_ff = Output(UInt(32.W)) // CSR for memory region control
val dec_data_en = Output(UInt(2.W)) // clock-gate control logic
val dec_ctl_en = Output(UInt(2.W))
val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction
val rv_trace_pkt = Output(new el2_trace_pkt_t) // trace packet
// feature disable from mfdc
val dec_tlu_external_ldfwd_disable = Output(Bool()) // disable external load forwarding
val dec_tlu_sideeffect_posted_disable = Output(Bool()) // disable posted stores to side-effect address
val dec_tlu_core_ecc_disable = Output(Bool()) // disable core ECC
val dec_tlu_bpred_disable = Output(Bool()) // disable branch prediction
val dec_tlu_wb_coalescing_disable = Output(Bool()) // disable writebuffer coalescing
val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16]
// clock gating overrides from mcgc
val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating
val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating
val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating
val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating
val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating
val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating
val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating
val dec_tlu_i0_commit_cmt = Output(Bool()) // committed i0 instruction
val scan_mode = Input(Bool())
}
class el2_dec extends Module with param with RequireAsyncReset{
val io = IO(new el2_dec_IO)
io.dec_i0_pc_d := 0.U
// val dec_ib0_valid_d = WireInit(Bool(),0.B)
//
// val dec_pmu_instr_decoded = WireInit(Bool(),0.B)
// val dec_pmu_decode_stall = WireInit(Bool(),0.B)
// val dec_pmu_presync_stall = WireInit(Bool(),0.B)
// val dec_pmu_postsync_stall = WireInit(Bool(),0.B)
//
// val dec_tlu_wr_pause_r = WireInit(UInt(1.W),0.U) // CSR write to pause reg is at R.
//
// val dec_i0_rs1_d = WireInit(UInt(5.W),0.U)
// val dec_i0_rs2_d = WireInit(UInt(5.W),0.U)
//
// val dec_i0_instr_d = WireInit(UInt(32.W),0.U)
//
// val dec_tlu_pipelining_disable = WireInit(UInt(1.W),0.U)
// val dec_i0_waddr_r = WireInit(UInt(5.W),0.U)
// val dec_i0_wen_r = WireInit(UInt(5.W),0.U)
// val dec_i0_wdata_r = WireInit(UInt(32.W),0.U)
// val dec_csr_wen_r = WireInit(UInt(1.W),0.U) // csr write enable at wb
// val dec_csr_wraddr_r = WireInit(UInt(12.W),0.U) // write address for csryes
// val dec_csr_wrdata_r = WireInit(UInt(32.W),0.U) // csr write data at wb
//
// val dec_csr_rdaddr_d = WireInit(UInt(12.W),0.U) // read address for csr
// val dec_csr_rddata_d = WireInit(UInt(32.W),0.U) // csr read data at wb
// val dec_csr_legal_d = WireInit(Bool(),0.B) // csr indicates legal operation
//
// val dec_csr_wen_unq_d = WireInit(Bool(),0.B) // valid csr with write - for csr legal
// val dec_csr_any_unq_d = WireInit(Bool(),0.B) // valid csr - for csr legal
// val dec_csr_stall_int_ff = WireInit(Bool(),0.B) // csr is mie/mstatus
//
// val dec_tlu_packet_r = Wire(new el2_trap_pkt_t)
//
// val dec_i0_pc4_d = WireInit(UInt(1.W),0.U)
// val dec_tlu_presync_d = WireInit(UInt(1.W),0.U)
// val dec_tlu_postsync_d = WireInit(UInt(1.W),0.U)
// val dec_tlu_debug_stall = WireInit(UInt(1.W),0.U)
// val dec_illegal_inst = WireInit(UInt(32.W),0.U)
// val dec_i0_icaf_d = WireInit(UInt(1.W),0.U)
// val dec_i0_dbecc_d = WireInit(UInt(1.W),0.U)
// val dec_i0_icaf_f1_d = WireInit(UInt(1.W),0.U)
// val dec_i0_trigger_match_d = WireInit(UInt(4.W),0.U)
// val dec_debug_fence_d = WireInit(UInt(1.W),0.U)
// val dec_nonblock_load_wen = WireInit(UInt(1.W),0.U)
// val dec_nonblock_load_waddr = WireInit(UInt(5.W),0.U)
// val dec_tlu_flush_pause_r = WireInit(UInt(1.W),0.U)
// val dec_i0_brp = Wire(new el2_br_pkt_t)
// val dec_i0_bp_index = WireInit(UInt(BTB_ADDR_HI.W),0.U)
// val dec_i0_bp_fghr = WireInit(UInt(BHT_GHR_SIZE.W),0.U)
// val dec_i0_bp_btag = WireInit(UInt(BTB_BTAG_SIZE.W),0.U)
//
// val dec_tlu_i0_pc_r = WireInit(UInt(32.W),0.U)
// val dec_tlu_i0_kill_writeb_wb = WireInit(Bool(),0.B)
// val dec_tlu_flush_lower_wb = WireInit(Bool(),0.B)
// val dec_tlu_i0_valid_r = WireInit(Bool(),0.B)
//
// val dec_pause_state = WireInit(Bool(),0.B)
//
// val dec_i0_icaf_type_d = WireInit(UInt(2.W),0.U) // i0 instruction access fault type
//
// val dec_tlu_flush_extint = WireInit(Bool(),0.B)// Fast ext int started
//
val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U)
val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U)
val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U)
val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U)
val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U)
val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U)
val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B)
//
// val div_waddr_wb = WireInit(UInt(5.W),0.U)
//
// val dec_div_active = WireInit(Bool(),0.B)
//--------------------------------------------------------------------------//
val instbuff = Module(new el2_dec_ib_ctl)
val decode = Module(new el2_dec_decode_ctl)
val gpr = Module(new el2_dec_gpr_ctl)
val tlu = Module(new el2_dec_tlu_ctl)
val dec_trigger = Module(new el2_dec_trigger)
//instbuff.io <> io // error "Connection between left (el2_dec_ib_ctl_IO(IO io in el2_dec_ib_ctl)) and source (el2_dec_IO("
//--------------------------------------------------------------------------//
//connections for el2_dec_Ib
//inputs
instbuff.io.dbg_cmd_valid := io.dbg_cmd_valid
instbuff.io.dbg_cmd_write := io.dbg_cmd_write
instbuff.io.dbg_cmd_type := io.dbg_cmd_type
instbuff.io.dbg_cmd_addr := io.dbg_cmd_addr
instbuff.io.i0_brp := io.i0_brp
instbuff.io.ifu_i0_bp_index := io.ifu_i0_bp_index
instbuff.io.ifu_i0_bp_fghr := io.ifu_i0_bp_fghr
instbuff.io.ifu_i0_bp_btag := io.ifu_i0_bp_btag
instbuff.io.ifu_i0_pc4 := io.ifu_i0_pc4
instbuff.io.ifu_i0_valid := io.ifu_i0_valid
instbuff.io.ifu_i0_icaf := io.ifu_i0_icaf
instbuff.io.ifu_i0_icaf_type := io.ifu_i0_icaf_type
instbuff.io.ifu_i0_icaf_f1 := io.ifu_i0_icaf_f1
instbuff.io.ifu_i0_dbecc := io.ifu_i0_dbecc
instbuff.io.ifu_i0_instr := io.ifu_i0_instr
instbuff.io.ifu_i0_pc := io.ifu_i0_pc
//outputs
decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
decode.io.dec_i0_icaf_type_d :=instbuff.io.dec_i0_icaf_type_d
decode.io.dec_i0_instr_d :=instbuff.io.dec_i0_instr_d
decode.io.dec_i0_pc_d :=instbuff.io.dec_i0_pc_d
decode.io.dec_i0_pc4_d :=instbuff.io.dec_i0_pc4_d
decode.io.dec_i0_brp :=instbuff.io.dec_i0_brp
decode.io.dec_i0_bp_index :=instbuff.io.dec_i0_bp_index
decode.io.dec_i0_bp_fghr :=instbuff.io.dec_i0_bp_fghr
decode.io.dec_i0_bp_btag :=instbuff.io.dec_i0_bp_btag
decode.io.dec_i0_icaf_d :=instbuff.io.dec_i0_icaf_d
decode.io.dec_i0_icaf_f1_d :=instbuff.io.dec_i0_icaf_f1_d
decode.io.dec_i0_dbecc_d :=instbuff.io.dec_i0_dbecc_d
io.dec_debug_wdata_rs1_d := instbuff.io.dec_debug_wdata_rs1_d
decode.io.dec_debug_fence_d :=instbuff.io.dec_debug_fence_d
//--------------------------------------------------------------------------//
//connections for dec_trigger
//dec_trigger.io <> io
//inputs
dec_trigger.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d
dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any
//output
val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
dontTouch(dec_i0_trigger_match_d)
//--------------------------------------------------------------------------//
//connections for el2_dec_decode
// decode.io <> io
//inputs
decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
decode.io.dec_tlu_force_halt := tlu.io.dec_tlu_force_halt
decode.io.ifu_i0_cinst := io.ifu_i0_cinst
decode.io.lsu_nonblock_load_valid_m := io.lsu_nonblock_load_valid_m
decode.io.lsu_nonblock_load_tag_m := io.lsu_nonblock_load_tag_m
decode.io.lsu_nonblock_load_inv_r := io.lsu_nonblock_load_inv_r
decode.io.lsu_nonblock_load_inv_tag_r := io.lsu_nonblock_load_inv_tag_r
decode.io.lsu_nonblock_load_data_valid := io.lsu_nonblock_load_data_valid
decode.io.lsu_nonblock_load_data_error := io.lsu_nonblock_load_data_error
decode.io.lsu_nonblock_load_data_tag := io.lsu_nonblock_load_data_tag
decode.io.lsu_nonblock_load_data := io.lsu_nonblock_load_data
decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d
decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable
decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m
decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_bus_misaligned
decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
decode.io.dec_tlu_flush_leak_one_r := tlu.io.dec_tlu_flush_leak_one_r
decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d
decode.io.dbg_cmd_wrdata := io.dbg_cmd_wrdata
decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d
decode.io.dec_i0_icaf_f1_d := instbuff.io.dec_i0_icaf_f1_d
decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d
decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d
decode.io.dec_i0_brp := instbuff.io.dec_i0_brp
decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index
decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr
decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag
decode.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d
decode.io.lsu_idle_any := io.lsu_idle_any
decode.io.lsu_load_stall_any := io.lsu_load_stall_any
decode.io.lsu_store_stall_any := io.lsu_store_stall_any
decode.io.dma_dccm_stall_any := io.dma_dccm_stall_any
decode.io.exu_div_wren := io.exu_div_wren
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
decode.io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r
decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc_d
decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
decode.io.exu_csr_rs1_x := io.exu_csr_rs1_x
decode.io.lsu_result_m := io.lsu_result_m
decode.io.lsu_result_corr_r := io.lsu_result_corr_r
decode.io.exu_flush_final := io.exu_flush_final
decode.io.exu_i0_pc_x := io.exu_i0_pc_x
decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d
decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
decode.io.exu_i0_result_x := io.exu_i0_result_x
//decode.io.clk := io.clk
decode.io.free_clk := io.free_clk
decode.io.active_clk := io.active_clk
decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override
// decode.io.rst_l := io.rst_l
decode.io.scan_mode := io.scan_mode
//outputs
io.dec_extint_stall := decode.io.dec_extint_stall
dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer
dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer
io.dec_i0_rs1_en_d := decode.io.dec_i0_rs1_en_d
io.dec_i0_rs2_en_d := decode.io.dec_i0_rs2_en_d
gpr.io.raddr0 := decode.io.dec_i0_rs1_d
gpr.io.raddr1 := decode.io.dec_i0_rs2_d
io.dec_i0_immed_d := decode.io.dec_i0_immed_d
io.dec_i0_br_immed_d := decode.io.dec_i0_br_immed_d
io.i0_ap := decode.io.i0_ap
io.dec_i0_decode_d := decode.io.dec_i0_decode_d
io.dec_i0_alu_decode_d := decode.io.dec_i0_alu_decode_d
io.dec_i0_rs1_bypass_data_d := decode.io.dec_i0_rs1_bypass_data_d
io.dec_i0_rs2_bypass_data_d := decode.io.dec_i0_rs2_bypass_data_d
gpr.io.waddr0 := decode.io.dec_i0_waddr_r
gpr.io.wen0 := decode.io.dec_i0_wen_r
gpr.io.wd0 := decode.io.dec_i0_wdata_r
io.dec_i0_select_pc_d := decode.io.dec_i0_select_pc_d
io.dec_i0_rs1_bypass_en_d := decode.io.dec_i0_rs1_bypass_en_d
io.dec_i0_rs2_bypass_en_d := decode.io.dec_i0_rs2_bypass_en_d
io.lsu_p := decode.io.lsu_p
io.mul_p := decode.io.mul_p
io.div_p := decode.io.div_p
gpr.io.waddr2 := decode.io.div_waddr_wb
io.dec_div_cancel := decode.io.dec_div_cancel
io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d
io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d
io.dec_csr_ren_d := decode.io.dec_csr_ren_d
tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r
tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r
tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
io.pred_correct_npc_x := decode.io.pred_correct_npc_x
io.dec_i0_predict_p_d := decode.io.dec_i0_predict_p_d
io.i0_predict_fghr_d := decode.io.i0_predict_fghr_d
io.i0_predict_index_d := decode.io.i0_predict_index_d
io.i0_predict_btag_d := decode.io.i0_predict_btag_d
io.dec_data_en := decode.io.dec_data_en
io.dec_ctl_en := decode.io.dec_ctl_en
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_instr_decoded
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_decode_stall
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_presync_stall
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall
tlu.io.dec_pmu_postsync_stall := decode.io.dec_nonblock_load_wen
tlu.io.dec_pmu_postsync_stall := decode.io.dec_nonblock_load_waddr
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pause_state
io.dec_pause_state_cg := decode.io.dec_pause_state_cg
tlu.io.dec_div_active := decode.io.dec_div_active
//--------------------------------------------------------------------------//
//connections for gprfile
// gpr.io <> io
//inputs
gpr.io.raddr0 := decode.io.dec_i0_rs1_d
gpr.io.raddr1 := decode.io.dec_i0_rs2_d
gpr.io.wen0 := decode.io.dec_i0_wen_r
gpr.io.waddr0 := decode.io.dec_i0_waddr_r
gpr.io.wd0 := decode.io.dec_i0_wdata_r
gpr.io.wen1 := decode.io.dec_nonblock_load_wen
gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr
gpr.io.wd1 := io.lsu_nonblock_load_data
gpr.io.wen2 := io.exu_div_wren
gpr.io.waddr2 := decode.io.div_waddr_wb
gpr.io.wd2 := io.exu_div_result
//gpr.io.clk := io.clk
//gpr.io.rst_l := io.rst_l
gpr.io.scan_mode := io.scan_mode
// outputs
io.gpr_i0_rs1_d := gpr.io.rd0
io.gpr_i0_rs2_d := gpr.io.rd1
//--------------------------------------------------------------------------//
//connection for dec_tlu
// tlu.io <> io
//inputs
//tlu.io.clk := io.clk
tlu.io.active_clk := io.active_clk
tlu.io.free_clk := io.free_clk
// tlu.io.rst_l := io.rst_l
tlu.io.scan_mode := io.scan_mode
tlu.io.rst_vec := io.rst_vec
tlu.io.nmi_int := io.nmi_int
tlu.io.nmi_vec := io.nmi_vec
tlu.io.i_cpu_halt_req := io.i_cpu_halt_req
tlu.io.i_cpu_run_req := io.i_cpu_run_req
tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any
tlu.io.ifu_pmu_instr_aligned := io.ifu_pmu_instr_aligned
tlu.io.ifu_pmu_fetch_stall := io.ifu_pmu_fetch_stall
tlu.io.ifu_pmu_ic_miss := io.ifu_pmu_ic_miss
tlu.io.ifu_pmu_ic_hit := io.ifu_pmu_ic_hit
tlu.io.ifu_pmu_bus_error := io.ifu_pmu_bus_error
tlu.io.ifu_pmu_bus_busy := io.ifu_pmu_bus_busy
tlu.io.ifu_pmu_bus_trxn := io.ifu_pmu_bus_trxn
tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded
tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall
tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall
tlu.io.lsu_store_stall_any := io.lsu_store_stall_any
tlu.io.dma_dccm_stall_any := io.dma_dccm_stall_any
tlu.io.dma_iccm_stall_any := io.dma_iccm_stall_any
tlu.io.exu_pmu_i0_br_misp := io.exu_pmu_i0_br_misp
tlu.io.exu_pmu_i0_br_ataken := io.exu_pmu_i0_br_ataken
tlu.io.exu_pmu_i0_pc4 := io.exu_pmu_i0_pc4
tlu.io.lsu_pmu_bus_trxn := io.lsu_pmu_bus_trxn
tlu.io.lsu_pmu_bus_misaligned := io.lsu_pmu_bus_misaligned
tlu.io.lsu_pmu_bus_error := io.lsu_pmu_bus_error
tlu.io.lsu_pmu_bus_busy := io.lsu_pmu_bus_busy
tlu.io.lsu_pmu_load_external_m := io.lsu_pmu_load_external_m
tlu.io.lsu_pmu_store_external_m := io.lsu_pmu_store_external_m
tlu.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read
tlu.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write
tlu.io.dma_pmu_any_read := io.dma_pmu_any_read
tlu.io.dma_pmu_any_write := io.dma_pmu_any_write
tlu.io.lsu_fir_addr := io.lsu_fir_addr
tlu.io.lsu_fir_error := io.lsu_fir_error
tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error
tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r
tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr
tlu.io.dec_pause_state := decode.io.dec_pause_state
tlu.io.lsu_imprecise_error_store_any := io.lsu_imprecise_error_store_any
tlu.io.lsu_imprecise_error_load_any := io.lsu_imprecise_error_load_any
tlu.io.lsu_imprecise_error_addr_any := io.lsu_imprecise_error_addr_any
tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r
tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r
tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
tlu.io.exu_npc_r := io.exu_npc_r
tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
tlu.io.dec_i0_decode_d := decode.io.dec_i0_decode_d
tlu.io.exu_i0_br_hist_r := io.exu_i0_br_hist_r
tlu.io.exu_i0_br_error_r := io.exu_i0_br_error_r
tlu.io.exu_i0_br_start_error_r := io.exu_i0_br_start_error_r
tlu.io.exu_i0_br_valid_r := io.exu_i0_br_valid_r
tlu.io.exu_i0_br_mp_r := io.exu_i0_br_mp_r
tlu.io.exu_i0_br_middle_r := io.exu_i0_br_middle_r
tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r
tlu.io.dbg_halt_req := io.dbg_halt_req
tlu.io.dbg_resume_req := io.dbg_resume_req
tlu.io.ifu_miss_state_idle := io.ifu_miss_state_idle
tlu.io.lsu_idle_any := io.lsu_idle_any
tlu.io.dec_div_active := decode.io.dec_div_active
tlu.io.ifu_ic_error_start := io.ifu_ic_error_start
tlu.io.ifu_iccm_rd_ecc_single_err := io.ifu_iccm_rd_ecc_single_err
tlu.io.ifu_ic_debug_rd_data := io.ifu_ic_debug_rd_data
tlu.io.ifu_ic_debug_rd_data_valid := io.ifu_ic_debug_rd_data_valid
tlu.io.pic_claimid := io.pic_claimid
tlu.io.pic_pl := io.pic_pl
tlu.io.mhwakeup := io.mhwakeup
tlu.io.mexintpend := io.mexintpend
tlu.io.timer_int := io.timer_int
tlu.io.soft_int := io.soft_int
tlu.io.core_id := io.core_id
tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req
tlu.io.mpc_debug_run_req := io.mpc_debug_run_req
tlu.io.mpc_reset_run_req := io.mpc_reset_run_req
//outputs
io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done
io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail
io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted
io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode
io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack
decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
io.dec_tlu_flush_noredir_r := tlu.io.dec_tlu_flush_noredir_r
io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only
io.dec_tlu_flush_leak_one_r := tlu.io.dec_tlu_flush_leak_one_r
io.dec_tlu_flush_err_r := tlu.io.dec_tlu_flush_err_r
decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
io.dec_tlu_meihap := tlu.io.dec_tlu_meihap
io.trigger_pkt_any := tlu.io.trigger_pkt_any
io.dec_tlu_ic_diag_pkt := tlu.io.dec_tlu_ic_diag_pkt
io.o_cpu_halt_status := tlu.io.o_cpu_halt_status
io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack
io.o_cpu_run_ack := tlu.io.o_cpu_run_ack
io.o_debug_mode_status := tlu.io.o_debug_mode_status
io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack
io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack
io.debug_brkpt_status := tlu.io.debug_brkpt_status
io.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl
io.dec_tlu_meipt := tlu.io.dec_tlu_meipt
decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
io.dec_tlu_br0_r_pkt := tlu.io.dec_tlu_br0_r_pkt
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
io.dec_tlu_i0_commit_cmt := tlu.io.dec_tlu_i0_commit_cmt
io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r
io.dec_tlu_flush_path_r := tlu.io.dec_tlu_flush_path_r
io.dec_tlu_fence_i_r := tlu.io.dec_tlu_fence_i_r
decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
io.dec_tlu_mrac_ff := tlu.io.dec_tlu_mrac_ff
io.dec_tlu_force_halt := tlu.io.dec_tlu_force_halt
io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0
io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1
io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2
io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3
dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1
dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1
dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1
dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1
dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1
io.dec_tlu_external_ldfwd_disable := tlu.io.dec_tlu_external_ldfwd_disable
io.dec_tlu_sideeffect_posted_disable := tlu.io.dec_tlu_sideeffect_posted_disable
io.dec_tlu_core_ecc_disable := tlu.io.dec_tlu_core_ecc_disable
io.dec_tlu_bpred_disable := tlu.io.dec_tlu_bpred_disable
io.dec_tlu_wb_coalescing_disable := tlu.io.dec_tlu_wb_coalescing_disable
// := tlu.io.dec_tlu_pipelining_disable
io.dec_tlu_dma_qos_prty := tlu.io.dec_tlu_dma_qos_prty
io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override
//decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override
io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override
io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override
io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override
io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override
io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override
io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override
//--------------------------------------------------------------------------//
io.rv_trace_pkt.rv_i_insn_ip := decode.io.dec_i0_inst_wb1
io.rv_trace_pkt.rv_i_address_ip := Cat(decode.io.dec_i0_pc_wb1, 0.U)
io.rv_trace_pkt.rv_i_valid_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1)
io.rv_trace_pkt.rv_i_exception_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1)
io.rv_trace_pkt.rv_i_ecause_ip := tlu.io.dec_tlu_exc_cause_wb1(4,0)
io.rv_trace_pkt.rv_i_interrupt_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, 0.U)
io.rv_trace_pkt.rv_i_tval_ip := tlu.io.dec_tlu_mtval_wb1
// debug command read data
io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
}
object dec_main extends App {
println((new chisel3.stage.ChiselStage).emitVerilog( new el2_dec()))
}

173
src/main/scala/dec/el2_dec_dec_ctl.scala Normal file
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@ -0,0 +1,173 @@
package dec
import chisel3._
import chisel3.util._
class el2_dec_pkt_t extends Bundle{
val alu = Bool()
val rs1 = Bool()
val rs2 = Bool()
val imm12 = Bool()
val rd = Bool()
val shimm5 = Bool()
val imm20 = Bool()
val pc = Bool()
val load = Bool()
val store = Bool()
val lsu = Bool()
val add = Bool()
val sub = Bool()
val land = Bool()
val lor = Bool()
val lxor = Bool()
val sll = Bool()
val sra = Bool()
val srl = Bool()
val slt = Bool()
val unsign = Bool()
val condbr = Bool()
val beq = Bool()
val bne = Bool()
val bge = Bool()
val blt = Bool()
val jal = Bool()
val by = Bool()
val half = Bool()
val word = Bool()
val csr_read = Bool()
val csr_clr = Bool()
val csr_set = Bool()
val csr_write = Bool()
val csr_imm = Bool()
val presync = Bool()
val postsync = Bool()
val ebreak = Bool()
val ecall = Bool()
val mret = Bool()
val mul = Bool()
val rs1_sign = Bool()
val rs2_sign = Bool()
val low = Bool()
val div = Bool()
val rem = Bool()
val fence = Bool()
val fence_i = Bool()
val pm_alu = Bool()
val legal = Bool()
}
class el2_dec_dec_ctl extends Module{
val io = IO (new Bundle{
val ins = Input(UInt(32.W))
val out = Output(new el2_dec_pkt_t)
})
def pattern(y : List[Int]) : Array[UInt] = {
val pat : Array[UInt] = new Array[UInt](y.size)
for (i <- 0 until y.size){
pat(i) = if(y(i)>0) io.ins(y(i)) else !io.ins(y(i).abs)
}
pat
}
io.out.alu := io.ins(2) | io.ins(6) | (!io.ins(25)&io.ins(4)) | (!io.ins(5)&io.ins(4))
io.out.rs1 := pattern(List(-14,-13,-2)).reduce(_&_) | pattern(List(-13,11,-2)).reduce(_&_) |
pattern(List(19,13,-2)).reduce(_&_) | pattern(List(-13,10,-2)).reduce(_&_) |
pattern(List(-18,13,-2)).reduce(_&_) | pattern(List(-13,9,-2)).reduce(_&_) |
pattern(List(17,13,-2)).reduce(_&_) | pattern(List(-13,8,-2)).reduce(_&_) |
pattern(List(16,13,-2)).reduce(_&_) | pattern(List(-13,7,-2)).reduce(_&_) |
pattern(List(15,13,-2)).reduce(_&_) |pattern(List(-4,-3)).reduce(_&_) | pattern(List(-6,-2)).reduce(_&_)
io.out.rs2 := pattern(List(5,-4,-2)).reduce(_&_) | pattern(List(-6,5,-2)).reduce(_&_)
io.out.imm12 := pattern(List(-4,-3,2)).reduce(_&_) | pattern(List(13,-5,4,-2)).reduce(_&_) |
pattern(List(-13,-12,6,4)).reduce(_&_) | pattern(List(-12,-5,4,-2)).reduce(_&_)
io.out.rd := (!io.ins(5) & !io.ins(2)) | (io.ins(5) & io.ins(2)) | io.ins(4)
io.out.shimm5 := pattern(List(-13,12,-5,4,-2)).reduce(_&_)
io.out.imm20 := (io.ins(5)&io.ins(3)) | (io.ins(4)&io.ins(2))
io.out.pc := (!io.ins(5) & !io.ins(3) & io.ins(2)) | (io.ins(5) & io.ins(3))
io.out.load := pattern(List(-5,-4,-2)).reduce(_&_)
io.out.store := pattern(List(-6,5,-4)).reduce(_&_)
io.out.lsu := pattern(List(-6,-4,-2)).reduce(_&_)
io.out.add := pattern(List(-14,-13,-12,-5,4)).reduce(_&_) | pattern(List(-5,-3,2)).reduce(_&_) |
pattern(List(-30,-25,-14,-13,-12,-6,4,-2)).reduce(_&_)
io.out.sub := pattern(List(30,-12,-6,5,4,-2)).reduce(_&_) | pattern(List(-25,-14,13,-6,4,-2)).reduce(_&_) |
pattern(List(-14,13,-5,4,-2)).reduce(_&_) | pattern(List(6,-4,-2)).reduce(_&_)
io.out.land := pattern(List(14,13,12,-5,-2)).reduce(_&_) | pattern(List(-25,14,13,12,-6,-2)).reduce(_&_)
io.out.lor := pattern(List(-6,3)).reduce(_&_) | pattern(List(-25,14,13,-12,-6,-2)).reduce(_&_) |
pattern(List(5,4,2)).reduce(_&_) | pattern(List(-13,-12,6,4)).reduce(_&_) |
pattern(List(14,13,-12,-5,-2)).reduce(_&_)
io.out.lxor := pattern(List(-25,14,-13,-12,4,-2)).reduce(_&_) | pattern(List(14,-13,-12,-5,4,-2)).reduce(_&_)
io.out.sll := pattern(List(-25,-14,-13,12,-6,4,-2)).reduce(_&_)
io.out.sra := pattern(List(30,-13,12,-6,4,-2)).reduce(_&_)
io.out.srl := pattern(List(-30,-25,14,-13,12,-6,4,-2)).reduce(_&_)
io.out.slt := pattern(List(-25,-14,13,12,-6,4,-2)).reduce(_&_) | pattern(List(-14,13,-5,4,-2)).reduce(_&_)
io.out.unsign := pattern(List(-14,13,12,-5,-2)).reduce(_&_) | pattern(List(13,6,-4,-2)).reduce(_&_) |
pattern(List(14,-5,-4)).reduce(_&_) | pattern(List(-25,-14,13,12,-6,-2)).reduce(_&_) |
pattern(List(25,14,12,-6,5,-2)).reduce(_&_)
io.out.condbr := pattern(List(6,-4,-2)).reduce(_&_)
io.out.beq := pattern(List(-14,-12,6,-4,-2)).reduce(_&_)
io.out.bne := pattern(List(-14,12,6,-4,-2)).reduce(_&_)
io.out.bge := pattern(List(14,12,5,-4,-2)).reduce(_&_)
io.out.blt := pattern(List(14,-12,5,-4,-2)).reduce(_&_)
io.out.jal := pattern(List(6,2)).reduce(_&_)
io.out.by := pattern(List(-13,-12,-6,-4,-2)).reduce(_&_)
io.out.half := pattern(List(12,-6,-4,-2)).reduce(_&_)
io.out.word := pattern(List(13,-6,-4)).reduce(_&_)
io.out.csr_read := pattern(List(13,6,4)).reduce(_&_) | pattern(List(7,6,4)).reduce(_&_) |
pattern(List(8,6,4)).reduce(_&_) | pattern(List(9,6,4)).reduce(_&_) | pattern(List(10,6,4)).reduce(_&_) |
pattern(List(11,6,4)).reduce(_&_)
io.out.csr_clr := pattern(List(15,13,12,6,4)).reduce(_&_) | pattern(List(16,13,12,6,4)).reduce(_&_) |
pattern(List(17,13,12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) |
pattern(List(19,-12,6,4)).reduce(_&_)
io.out.csr_write := pattern(List(-13,12,6,4)).reduce(_&_)
io.out.csr_imm := pattern(List(14,-13,6,4)).reduce(_&_) | pattern(List(15,14,6,4)).reduce(_&_) |
pattern(List(16,14,6,4)).reduce(_&_) | pattern(List(17,14,6,4)).reduce(_&_) |
pattern(List(18,14,6,4)).reduce(_&_) | pattern(List(19,14,6,4)).reduce(_&_)
io.out.csr_set := pattern(List(15,-12,6,4)).reduce(_&_) | pattern(List(16,-12,6,4)).reduce(_&_) |
pattern(List(17,-12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) |
pattern(List(19,-12,6,4)).reduce(_&_)
io.out.ebreak := pattern(List(-22,20,-13,-12,6,4)).reduce(_&_)
io.out.ecall := pattern(List(-21,-20,-13,-12,6,4)).reduce(_&_)
io.out.mret := pattern(List(29,-13,-12,6,4)).reduce(_&_)
io.out.mul := pattern(List(25,-14,-6,5,4,-2)).reduce(_&_)
io.out.rs1_sign := pattern(List(25,-14,13,-12,-6,5,4,-2)).reduce(_&_) |
pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_)
io.out.rs2_sign := pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_)
io.out.low := pattern(List(25,-14,-13,-12,5,4,-2)).reduce(_&_)
io.out.div := pattern(List(25,14,-6,5,-2)).reduce(_&_)
io.out.rem := pattern(List(25,14,13,-6,5,-2)).reduce(_&_)
io.out.fence := pattern(List(-5,3)).reduce(_&_)
io.out.fence_i := pattern(List(12,-5,3)).reduce(_&_)
io.out.pm_alu := pattern(List(28,22,-13,-12,4)).reduce(_&_) | pattern(List(4,2)).reduce(_&_) |
pattern(List(-25,-6,4)).reduce(_&_) | pattern(List(-5,4)).reduce(_&_)
io.out.presync := pattern(List(-5,3)).reduce(_&_) | pattern(List(-13,7,6,4)).reduce(_&_) |
pattern(List(-13,8,6,4)).reduce(_&_) | pattern(List(-13,9,6,4)).reduce(_&_) |
pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) |
pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) |
pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) |
pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_)
io.out.postsync := pattern(List(12,-5,3)).reduce(_&_) | pattern(List(-22,-13,-12,6,4)).reduce(_&_) |
pattern(List(-13,7,6,4)).reduce(_&_) | pattern(List(-13,8,6,4)).reduce(_&_) |
pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) |
pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) |
pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) |
pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_)
io.out.legal := pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) |
pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) |
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)).reduce(_&_) |
pattern(List(-31,-30,-29,-28,-27,-26,-25,-6,4,-3,1,0)).reduce(_&_) |
pattern(List(-31,-29,-28,-27,-26,-25,-14,-13,-12,-6,-3,-2,1,0)).reduce(_&_) |
pattern(List(-31,-29,-28,-27,-26,-25,14,-13,12,-6,4,-3,1,0)).reduce(_&_) |
pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)).reduce(_&_) |
pattern(List(-14,-13,-12,6,5,-4,-3,1,0)).reduce(_&_) |
pattern(List(14,6,5,-4,-3,-2,1,0)).reduce(_&_) |
pattern(List(-12,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-13,5,-4,-3,-2,1,0)).reduce(_&_) |
pattern(List(12,6,5,4,-3,-2,1,0)).reduce(_&_) |
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) |
pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) |
pattern(List(-13,-6,-5,-4,-3,-2,1,0)).reduce(_&_) | pattern(List(6,5,-4,3,2,1,0)).reduce(_&_) |
pattern(List(13,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-12,-6,-4,-3,-2,1,0)).reduce(_&_) |
pattern(List(-6,4,-3,-2,1,0)).reduce(_&_)
}
//object dec extends App {
// println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec_dec_ctl()))
//}

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src/main/scala/dec/el2_dec_decode_ctl.scala Normal file
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package dec
import chisel3._
import scala.collection._
import chisel3.util._
import include._
import lib._
class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val io = IO(new Bundle{
val dec_tlu_flush_extint = Input(Bool())
val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event
val dec_extint_stall = Output(Bool())
val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction
val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder
val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder
val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m
val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r
val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back
val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error
val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data
val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches
val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r
val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only
val lsu_trigger_match_m = Input(UInt(4.W)) // lsu trigger matches
val lsu_pmu_misaligned_m = Input(Bool()) // perf mon: load/store misalign
val dec_tlu_debug_stall = Input(Bool()) // debug stall decode
val dec_tlu_flush_leak_one_r = Input(Bool()) // leak1 instruction
val dec_debug_fence_d = Input(Bool()) // debug fence instruction
val dbg_cmd_wrdata = Input(UInt(2.W)) // disambiguate fence, fence_i
val dec_i0_icaf_d = Input(Bool()) // icache access fault
val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group
val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type
val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error
val dec_i0_brp = Input(new el2_br_pkt_t) // branch packet
val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
val dec_i0_pc_d = Input(UInt(31.W)) // pc
val lsu_idle_any = Input(Bool()) // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode
val lsu_load_stall_any = Input(Bool()) // stall any load at decode
val lsu_store_stall_any = Input(Bool()) // stall any store at decode6
val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode
val exu_div_wren = Input(Bool()) // nonblocking divide write enable to GPR.
val dec_tlu_i0_kill_writeb_wb = Input(Bool()) // I0 is flushed, don't writeback any results to arch state
val dec_tlu_flush_lower_wb = Input(Bool()) // trap lower flush
val dec_tlu_i0_kill_writeb_r = Input(Bool()) // I0 is flushed, don't writeback any results to arch state
val dec_tlu_flush_lower_r = Input(Bool()) // trap lower flush
val dec_tlu_flush_pause_r = Input(Bool()) // don't clear pause state on initial lower flush
val dec_tlu_presync_d = Input(Bool()) // CSR read needs to be presync'd
val dec_tlu_postsync_d = Input(Bool()) // CSR ops that need to be postsync'd
val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B
val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb
val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation
val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instr
val lsu_result_m = Input(UInt(32.W)) // load result
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing
val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D
val exu_i0_pc_x = Input(UInt(31.W)) // pcs at e1
val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode
val dec_ib0_valid_d = Input(Bool()) // inst valid at decode
val exu_i0_result_x = Input(UInt(32.W)) // from primary alu's
val free_clk = Input(Clock())
val active_clk = Input(Clock()) // clk except for halt / pause
val clk_override = Input(Bool()) // test stuff
val dec_i0_rs1_en_d = Output(Bool()) // rs1 enable at decode
val dec_i0_rs2_en_d = Output(Bool())
val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source
val dec_i0_rs2_d = Output(UInt(5.W))
val dec_i0_immed_d = Output(UInt(32.W)) // 32b immediate data decode
val dec_i0_br_immed_d = Output(UInt(12.W)) // 12b branch immediate
val i0_ap = Output(new el2_alu_pkt_t) // alu packets
val dec_i0_decode_d = Output(Bool()) // i0 decode
val dec_i0_alu_decode_d = Output(Bool()) // decode to D-stage alu
val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // i0 rs1 bypass data
val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // i0 rs2 bypass data
val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's
val dec_i0_wen_r = Output(Bool()) // i0 write enable
val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data
val dec_i0_select_pc_d = Output(Bool()) // i0 select pc for rs1 - branches
val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // i0 rs1 bypass enable
val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // i0 rs2 bypass enable
val lsu_p = Output(new el2_lsu_pkt_t) // load/store packet
val mul_p = Output(new el2_mul_pkt_t) // multiply packet
val div_p = Output(new el2_div_pkt_t) // divide packet
val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR
val dec_div_cancel = Output(Bool()) // cancel the divide operation
val dec_lsu_valid_raw_d = Output(Bool())
val dec_lsu_offset_d = Output(UInt(12.W))
val dec_csr_ren_d = Output(Bool()) // valid csr decode
val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal
val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal
val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr
val dec_csr_wen_r = Output(Bool()) // csr write enable at r
val dec_csr_wraddr_r = Output(UInt(12.W)) // write address for csr
val dec_csr_wrdata_r = Output(UInt(32.W)) // csr write data at r
val dec_csr_stall_int_ff = Output(Bool()) // csr is mie/mstatus
val dec_tlu_i0_valid_r = Output(Bool()) // i0 valid inst at c
val dec_tlu_packet_r = Output(new el2_trap_pkt_t) // trap packet
val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc
val dec_illegal_inst = Output(UInt(32.W)) // illegal inst
val pred_correct_npc_x = Output(UInt(31.W)) // npc e2 if the prediction is correct
val dec_i0_predict_p_d = Output(new el2_predict_pkt_t) // i0 predict packet decode
val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // i0 predict fghr
val i0_predict_index_d = Output(UInt(((BHT_ADDR_HI-BHT_ADDR_LO)+1).W)) // i0 predict index
val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // i0_predict branch tag
val dec_data_en = Output(UInt(2.W)) // clock-gating logic
val dec_ctl_en = Output(UInt(2.W))
val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded
val dec_pmu_decode_stall = Output(Bool()) // decode is stalled
val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall
val dec_pmu_postsync_stall = Output(Bool()) // decode has postsync stall
val dec_nonblock_load_wen = Output(Bool()) // write enable for nonblock load
val dec_nonblock_load_waddr = Output(UInt(5.W)) // logical write addr for nonblock load
val dec_pause_state = Output(Bool()) // core in pause state
val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating
val dec_div_active = Output(Bool()) // non-block divide is active
val scan_mode = Input(Bool())
})
/////////////////////////////////////////////////////////////////////////////////////////
// //packets zero initialization
io.mul_p := 0.U.asTypeOf(io.mul_p)
// Vals defined
val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U)
val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U)
val i0r = Wire(new el2_reg_pkt_t)
val d_t = Wire(new el2_trap_pkt_t)
val x_t = Wire(new el2_trap_pkt_t)
val x_t_in = Wire(new el2_trap_pkt_t)
val r_t = Wire(new el2_trap_pkt_t)
val r_t_in = Wire(new el2_trap_pkt_t)
val d_d = Wire(new el2_dest_pkt_t)
val x_d = Wire(new el2_dest_pkt_t)
val r_d = Wire(new el2_dest_pkt_t)
val r_d_in = Wire(new el2_dest_pkt_t)
val wbd = Wire(new el2_dest_pkt_t)
val i0_d_c = Wire(new el2_class_pkt_t)
val i0_rs1_class_d = Wire(new el2_class_pkt_t)
val i0_rs2_class_d = Wire(new el2_class_pkt_t)
val i0_rs1_depth_d = WireInit(UInt(2.W),0.U)
val i0_rs2_depth_d = WireInit(UInt(2.W),0.U)
val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
val cam = Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
val cam_write=WireInit(UInt(1.W), 0.U)
val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
val cam_in =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
//val i0_temp = Wire(new el2_inst_pkt_t)
val i0_dp= Wire(new el2_dec_pkt_t)
val i0_dp_raw= Wire(new el2_dec_pkt_t)
val i0_rs1bypass = WireInit(UInt(3.W), 0.U)
val i0_rs2bypass = WireInit(UInt(3.W), 0.U)
val illegal_lockout = WireInit(UInt(1.W), 0.U)
val postsync_stall = WireInit(UInt(1.W), 0.U)
val ps_stall_in = WireInit(UInt(1.W), 0.U)
val i0_pipe_en = WireInit(UInt(4.W), 0.U)
val i0_load_block_d = WireInit(UInt(1.W), 0.U)
val load_ldst_bypass_d = WireInit(UInt(1.W), 0.U)
val store_data_bypass_d = WireInit(UInt(1.W), 0.U)
val store_data_bypass_m = WireInit(UInt(1.W), 0.U)
val tlu_wr_pause_r1 = WireInit(UInt(1.W), 0.U)
val tlu_wr_pause_r2 = WireInit(UInt(1.W), 0.U)
val leak1_i1_stall = WireInit(UInt(1.W), 0.U)
val leak1_i0_stall = WireInit(UInt(1.W), 0.U)
val pause_state = WireInit(Bool(), 0.B)
val flush_final_r = WireInit(UInt(1.W), 0.U)
val illegal_lockout_in = WireInit(UInt(1.W), 0.U)
val lsu_idle = WireInit(Bool(), 0.B)
val pause_state_in = WireInit(Bool(), 0.B)
val leak1_mode = WireInit(UInt(1.W), 0.U)
val i0_pcall = WireInit(UInt(1.W), 0.U)
val i0_pja = WireInit(UInt(1.W), 0.U)
val i0_pret = WireInit(UInt(1.W), 0.U)
val i0_legal_decode_d = WireInit(UInt(1.W), 0.U)
val i0_pcall_raw = WireInit(UInt(1.W), 0.U)
val i0_pja_raw = WireInit(UInt(1.W), 0.U)
val i0_pret_raw = WireInit(UInt(1.W), 0.U)
val i0_br_offset = WireInit(UInt(12.W), 0.U)
val i0_csr_write_only_d = WireInit(UInt(1.W), 0.U)
val i0_jal = WireInit(UInt(1.W), 0.U)
val i0_wen_r = WireInit(UInt(1.W), 0.U)
val i0_x_ctl_en = WireInit(UInt(1.W), 0.U)
val i0_r_ctl_en = WireInit(UInt(1.W), 0.U)
val i0_wb_ctl_en = WireInit(UInt(1.W), 0.U)
val i0_x_data_en = WireInit(UInt(1.W), 0.U)
val i0_r_data_en = WireInit(UInt(1.W), 0.U)
val i0_wb_data_en = WireInit(UInt(1.W), 0.U)
val i0_wb1_data_en = WireInit(UInt(1.W), 0.U)
val i0_nonblock_load_stall = WireInit(UInt(1.W), 0.U)
val csr_ren_qual_d = WireInit(Bool(), 0.B)
val lsu_decode_d = WireInit(UInt(1.W), 0.U)
val mul_decode_d = WireInit(UInt(1.W), 0.U)
val div_decode_d = WireInit(UInt(1.W), 0.U)
val write_csr_data = WireInit(UInt(32.W),0.U)
val i0_result_corr_r = WireInit(UInt(32.W),0.U)
val presync_stall = WireInit(UInt(1.W), 0.U)
val i0_nonblock_div_stall = WireInit(UInt(1.W), 0.U)
val debug_fence = WireInit(Bool(), 0.B)
val i0_immed_d = WireInit(UInt(32.W), 0.U)
val i0_result_x = WireInit(UInt(32.W), 0.U)
val i0_result_r = WireInit(UInt(32.W), 0.U)
//////////////////////////////////////////////////////////////////////
// Start - Data gating {{
val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk
(tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk
(io.dec_tlu_flush_extint ^ io.dec_extint_stall) |
(leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk
(leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk
(pause_state_in ^ pause_state ) | // replaces free_clk
(ps_stall_in ^ postsync_stall ) | // replaces free_clk
(io.exu_flush_final ^ flush_final_r ) | // replaces free_clk
(illegal_lockout_in ^ illegal_lockout ) // replaces active_clk
val data_gated_cgc= Module(new rvclkhdr)
data_gated_cgc.io.en := data_gate_en
data_gated_cgc.io.scan_mode :=io.scan_mode
data_gated_cgc.io.clk :=clock
val data_gate_clk =data_gated_cgc.io.l1clk
// End - Data gating }}
val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode
io.dec_i0_predict_p_d.misp :=0.U
io.dec_i0_predict_p_d.ataken :=0.U
io.dec_i0_predict_p_d.boffset :=0.U
io.dec_i0_predict_p_d.pcall := i0_pcall // don't mark as pcall if branch error
io.dec_i0_predict_p_d.pja := i0_pja
io.dec_i0_predict_p_d.pret := i0_pret
io.dec_i0_predict_p_d.prett := io.dec_i0_brp.prett
io.dec_i0_predict_p_d.pc4 := io.dec_i0_pc4_d
io.dec_i0_predict_p_d.hist := io.dec_i0_brp.hist
io.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d
val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
// no toffset error for a pret
val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.hist(1) & (io.dec_i0_brp.toffset =/= i0_br_offset) & !i0_pret_raw
val i0_ret_error = i0_brp_valid & io.dec_i0_brp.ret & !i0_pret_raw;
val i0_br_error = io.dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
io.dec_i0_predict_p_d.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode
io.dec_i0_predict_p_d.br_start_error := io.dec_i0_brp.br_start_error & i0_legal_decode_d & !leak1_mode
io.i0_predict_index_d := io.dec_i0_bp_index
io.i0_predict_btag_d := io.dec_i0_bp_btag
val i0_br_error_all = (i0_br_error | io.dec_i0_brp.br_start_error) & !leak1_mode
io.dec_i0_predict_p_d.toffset := i0_br_offset
io.i0_predict_fghr_d := io.dec_i0_bp_fghr
io.dec_i0_predict_p_d.way := io.dec_i0_brp.way
// end
// on br error turn anything into a nop
// on i0 instruction fetch access fault turn anything into a nop
// nop => alu rs1 imm12 rd lor
val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d
val i0_instr_error = i0_icaf_d;
i0_dp := i0_dp_raw
when((i0_br_error_all | i0_instr_error).asBool){
i0_dp := 0.U.asTypeOf(i0_dp)
i0_dp.alu := 1.B
i0_dp.rs1 := 1.B
i0_dp.rs2 := 1.B
i0_dp.lor := 1.B
i0_dp.legal := 1.B
i0_dp.postsync := 1.B
}
val i0 = io.dec_i0_instr_d
io.dec_i0_select_pc_d := i0_dp.pc;
// branches that can be predicted
val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
val i0_predict_nt = !(io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
val i0_predict_t = (io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
val i0_ap_pc2 = !io.dec_i0_pc4_d
val i0_ap_pc4 = io.dec_i0_pc4_d
io.i0_ap.predict_nt := i0_predict_nt
io.i0_ap.predict_t := i0_predict_t
io.i0_ap.add := i0_dp.add
io.i0_ap.sub := i0_dp.sub
io.i0_ap.land := i0_dp.land
io.i0_ap.lor := i0_dp.lor
io.i0_ap.lxor := i0_dp.lxor
io.i0_ap.sll := i0_dp.sll
io.i0_ap.srl := i0_dp.srl
io.i0_ap.sra := i0_dp.sra
io.i0_ap.slt := i0_dp.slt
io.i0_ap.unsign := i0_dp.unsign
io.i0_ap.beq := i0_dp.beq
io.i0_ap.bne := i0_dp.bne
io.i0_ap.blt := i0_dp.blt
io.i0_ap.bge := i0_dp.bge
io.i0_ap.csr_write := i0_csr_write_only_d
io.i0_ap.csr_imm := i0_dp.csr_imm
io.i0_ap.jal := i0_jal
// non block load cam logic
// val found=Wire(UInt(1.W))
cam_wen := Mux1H((0 until LSU_NUM_NBLOAD).map(i=>(0 to i).map(j=> if(i==j) !cam(j).valid else cam(j).valid).reduce(_.asBool&_.asBool).asBool -> (cam_write << i)))
cam_write := io.lsu_nonblock_load_valid_m
val cam_write_tag = io.lsu_nonblock_load_tag_m(LSU_NUM_NBLOAD_WIDTH-1,0)
val cam_inv_reset = io.lsu_nonblock_load_inv_r
val cam_inv_reset_tag = io.lsu_nonblock_load_inv_tag_r(LSU_NUM_NBLOAD_WIDTH-1,0)
val cam_data_reset = io.lsu_nonblock_load_data_valid | io.lsu_nonblock_load_data_error
val cam_data_reset_tag = io.lsu_nonblock_load_data_tag(LSU_NUM_NBLOAD_WIDTH-1,0)
val nonblock_load_rd = Mux(x_d.i0load.asBool, x_d.i0rd, 0.U(5.W)) // rd data
val load_data_tag = io.lsu_nonblock_load_data_tag
// case of multiple loads to same dest ie. x1 ... you have to invalidate the older one
// don't writeback a nonblock load
val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)}
val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load
for(i <- 0 until LSU_NUM_NBLOAD){
cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).tag) & cam(i).valid
cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).tag) & cam_raw(i).valid
cam_in(i):=0.U.asTypeOf(cam(0))
cam(i):=cam_raw(i)
when(cam_data_reset_val(i).asBool){
cam(i).valid := 0.U(1.W)
}
when(cam_wen(i).asBool){
cam_in(i).valid := 1.U(1.W)
cam_in(i).wb := 0.U(1.W)
cam_in(i).tag := cam_write_tag
cam_in(i).rd := nonblock_load_rd
}.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).rd) && cam(i).wb.asBool)){
cam_in(i).valid := 0.U
}.otherwise{
cam_in(i) := cam(i)
}
when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).tag) && cam(i).valid===1.U){
cam_in(i).wb := 1.U
}
// force debug halt forces cam valids to 0; highest priority
when(io.dec_tlu_force_halt){
cam_in(i).valid := 0.U
}
cam_raw(i):=withClock(io.free_clk){RegNext(cam_in(i),0.U.asTypeOf(cam(0)))}
nonblock_load_write(i) := (load_data_tag === cam_raw(i).tag) & cam_raw(i).valid
}
io.dec_nonblock_load_waddr:=0.U(5.W)
// cancel if any younger inst (including another nonblock) committing this cycle
val nonblock_load_cancel = ((r_d_in.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r)
io.dec_nonblock_load_wen := (io.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel)
val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs2_en_d)
i0_nonblock_load_stall := i0_nonblock_boundary_stall
val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).rd === i0r.rs2))
val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) )
io.dec_nonblock_load_waddr:=waddr
i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall
//i0_nonblock_load_stall:=ld_stall_2
// end non block load cam logic
// pmu start
val csr_read = csr_ren_qual_d
val csr_write = io.dec_csr_wen_unq_d
val i0_br_unpred = i0_dp.jal & !i0_predict_br
// the classes must be mutually exclusive with one another
import el2_inst_pkt_t._
d_t.pmu_i0_itype :=Fill(4,i0_legal_decode_d) & MuxCase(NULL ,Array(
i0_dp.jal -> JAL,
i0_dp.condbr -> CONDBR,
i0_dp.mret -> MRET,
i0_dp.fence_i -> FENCEI,
i0_dp.fence -> FENCE,
i0_dp.ecall -> ECALL,
i0_dp.ebreak -> EBREAK,
( csr_read & csr_write).asBool -> CSRRW,
(!csr_read & csr_write).asBool -> CSRWRITE,
( csr_read & !csr_write).asBool -> CSRREAD,
i0_dp.pm_alu -> ALU,
i0_dp.store -> STORE,
i0_dp.load -> LOAD,
i0_dp.mul -> MUL))
// end pmu
val i0_dec =Module(new el2_dec_dec_ctl)
i0_dec.io.ins:= i0
i0_dp_raw:=i0_dec.io.out
lsu_idle:=withClock(io.active_clk){RegNext(io.lsu_idle_any,0.U)}
// can't make this clock active_clock
leak1_i1_stall_in := (io.dec_tlu_flush_leak_one_r | (leak1_i1_stall & !io.dec_tlu_flush_lower_r))
leak1_i1_stall := withClock(data_gate_clk){RegNext(leak1_i1_stall_in,0.U)}
leak1_mode := leak1_i1_stall
leak1_i0_stall_in := ((io.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r))
leak1_i0_stall := withClock(data_gate_clk){RegNext(leak1_i0_stall_in,0.U)}
// 12b jal's can be predicted - these are calls
val i0_pcall_imm = Cat(i0(31),i0(19,12),i0(20),i0(30,21),0.U(1.W))
val i0_pcall_12b_offset = Mux(i0_pcall_imm(12).asBool, i0_pcall_imm(20,13) === 0xff.U , i0_pcall_imm(20,13) === 0.U(8.W))
val i0_pcall_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & (i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W))
val i0_pja_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & !(i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W))
i0_pcall_raw := i0_dp_raw.jal & i0_pcall_case // this includes ja
i0_pcall := i0_dp.jal & i0_pcall_case
i0_pja_raw := i0_dp_raw.jal & i0_pja_case
i0_pja := i0_dp.jal & i0_pja_case
i0_br_offset := Mux((i0_pcall_raw | i0_pja_raw).asBool, i0_pcall_imm(12,1) , Cat(i0(31),i0(7),i0(30,25),i0(11,8)))
// jalr with rd==0, rs1==1 or rs1==5 is a ret
val i0_pret_case = (i0_dp_raw.jal & i0_dp_raw.imm12 & (i0r.rd === 0.U(5.W)) & (i0r.rs1===1.U(5.W) | i0r.rs1 === 5.U(5.W)))
i0_pret_raw := i0_dp_raw.jal & i0_pret_case
i0_pret := i0_dp.jal & i0_pret_case
i0_jal := i0_dp.jal & !i0_pcall_case & !i0_pja_case & !i0_pret_case
///////////////////////////////////////////////////////////////////////////////////////////////////////////
io.div_p.valid := div_decode_d
io.div_p.unsign := i0_dp.unsign
io.div_p.rem := i0_dp.rem
io.mul_p.valid := mul_decode_d
io.mul_p.rs1_sign := i0_dp.rs1_sign
io.mul_p.rs2_sign := i0_dp.rs2_sign
io.mul_p.low := i0_dp.low
io.dec_extint_stall := withClock(data_gate_clk){RegNext(io.dec_tlu_flush_extint,0.U)}
io.lsu_p := 0.U.asTypeOf(io.lsu_p)
when (io.dec_extint_stall){
io.lsu_p.load := 1.U(1.W)
io.lsu_p.word := 1.U(1.W)
io.lsu_p.fast_int := 1.U(1.W)
io.lsu_p.valid := 1.U(1.W)
}.otherwise {
io.lsu_p.valid := lsu_decode_d
io.lsu_p.load := i0_dp.load
io.lsu_p.store := i0_dp.store
io.lsu_p.by := i0_dp.by
io.lsu_p.half := i0_dp.half
io.lsu_p.word := i0_dp.word
io.lsu_p.load_ldst_bypass_d := load_ldst_bypass_d
io.lsu_p.store_data_bypass_d := store_data_bypass_d
io.lsu_p.store_data_bypass_m := store_data_bypass_m
io.lsu_p.unsign := i0_dp.unsign
}
//////////////////////////////////////
io.dec_csr_ren_d := i0_dp.csr_read //H: assigning csr read enable signal decoded from decode_ctl going as input to EXU
csr_ren_qual_d := i0_dp.csr_read & i0_legal_decode_d.asBool //csr_ren_qual_d assigned as csr_read above
val i0_csr_write = i0_dp.csr_write & !io.dec_debug_fence_d
val csr_clr_d = i0_dp.csr_clr & i0_legal_decode_d.asBool
val csr_set_d = i0_dp.csr_set & i0_legal_decode_d.asBool
val csr_write_d = i0_csr_write & i0_legal_decode_d.asBool
i0_csr_write_only_d := i0_csr_write & !i0_dp.csr_read
io.dec_csr_wen_unq_d := (i0_dp.csr_clr | i0_dp.csr_set | i0_csr_write) // for csr legal, can't write read-only csr
//dec_csr_wen_unq_d assigned as csr_write above
io.dec_csr_rdaddr_d := i0(31,20)
io.dec_csr_wraddr_r := r_d.csrwaddr //r_d is a el2_dest_pkt
// make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb
// also use valid so it's flushable
io.dec_csr_wen_r := r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_r;
// If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write.
io.dec_csr_stall_int_ff := ((r_d.csrwaddr === "h300".U) | (r_d.csrwaddr === "h304".U)) & r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_wb;
val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)}
val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)}
val csr_set_x = withClock(io.active_clk){RegNext(csr_set_d, init=0.B)}
val csr_write_x = withClock(io.active_clk){RegNext(csr_write_d, init=0.B)}
val csr_imm_x = withClock(io.active_clk){RegNext(i0_dp.csr_imm, init=0.U)}
// perform the update operation if any
val csrimm_x = rvdffe(i0(19,15),i0_x_data_en.asBool,clock,io.scan_mode)
val csr_rddata_x = rvdffe(io.dec_csr_rddata_d,i0_x_data_en.asBool,clock,io.scan_mode)
val csr_mask_x = Mux1H(Seq(
csr_imm_x.asBool -> Cat(repl(27,0.U),csrimm_x(4,0)),
!csr_imm_x.asBool -> io.exu_csr_rs1_x))
val write_csr_data_x = Mux1H(Seq(
csr_clr_x -> (csr_rddata_x & (~csr_mask_x).asUInt),
csr_set_x -> (csr_rddata_x | csr_mask_x),
csr_write_x -> ( csr_mask_x)))
// pause instruction
val clear_pause = (io.dec_tlu_flush_lower_r & !io.dec_tlu_flush_pause_r) | (pause_state & (write_csr_data === 0.U(31.W))) // if 0 or 1 then exit pause state - 1 cycle pause
pause_state_in := (io.dec_tlu_wr_pause_r | pause_state) & !clear_pause
pause_state := withClock(data_gate_clk){RegNext(pause_state_in, 0.U)}
io.dec_pause_state := pause_state
tlu_wr_pause_r1 := RegNext(io.dec_tlu_wr_pause_r, 0.U)
tlu_wr_pause_r2 := RegNext(tlu_wr_pause_r1, 0.U)
//pause for clock gating
io.dec_pause_state_cg := (pause_state & (!tlu_wr_pause_r1 && !tlu_wr_pause_r2))
// end pause
val write_csr_data_in = Mux(pause_state,(write_csr_data - 1.U(32.W)),
Mux(io.dec_tlu_wr_pause_r,io.dec_csr_wrdata_r,write_csr_data_x))
val csr_data_wen = ((csr_clr_x | csr_set_x | csr_write_x) & csr_read_x) | io.dec_tlu_wr_pause_r | pause_state
write_csr_data := rvdffe(write_csr_data_in,csr_data_wen,clock,io.scan_mode)
// will hold until write-back at which time the CSR will be updated while GPR is possibly written with prior CSR
val pause_stall = pause_state
// for csr write only data is produced by the alu
io.dec_csr_wrdata_r := Mux(r_d.csrwonly.asBool,i0_result_corr_r,write_csr_data)
val prior_csr_write = x_d.csrwonly | r_d.csrwonly | wbd.csrwonly;
val debug_fence_i = io.dec_debug_fence_d & io.dbg_cmd_wrdata(0)
val debug_fence_raw = io.dec_debug_fence_d & io.dbg_cmd_wrdata(1)
debug_fence := debug_fence_raw | debug_fence_i
// some CSR reads need to be presync'd
val i0_presync = i0_dp.presync | io.dec_tlu_presync_d | debug_fence_i | debug_fence_raw | io.dec_tlu_pipelining_disable // both fence's presync
// some CSR writes need to be postsync'd
val i0_postsync = i0_dp.postsync | io.dec_tlu_postsync_d | debug_fence_i | (i0_csr_write_only_d & (i0(31,20) === "h7c2".U))
val any_csr_d = i0_dp.csr_read | i0_csr_write
io.dec_csr_any_unq_d := any_csr_d
val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d)
val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.ifu_i0_cinst))
// illegal inst handling
val shift_illegal = io.dec_i0_decode_d & !i0_legal//lm: valid but not legal
val illegal_inst_en = shift_illegal & !illegal_lockout
io.dec_illegal_inst := rvdffe(i0_inst_d,illegal_inst_en,clock,io.scan_mode)
illegal_lockout_in := (shift_illegal | illegal_lockout) & !flush_final_r
illegal_lockout := withClock(data_gate_clk){RegNext(illegal_lockout_in, 0.U)}
val i0_div_prior_div_stall = i0_dp.div & io.dec_div_active
//stalls signals
val i0_block_raw_d = (i0_dp.csr_read & prior_csr_write) | io.dec_extint_stall | pause_stall |
leak1_i0_stall | io.dec_tlu_debug_stall | postsync_stall | presync_stall |
((i0_dp.fence | debug_fence) & !lsu_idle) | i0_nonblock_load_stall |
i0_load_block_d | i0_nonblock_div_stall | i0_div_prior_div_stall
val i0_store_stall_d = i0_dp.store & (io.lsu_store_stall_any | io.dma_dccm_stall_any)
val i0_load_stall_d = i0_dp.load & (io.lsu_load_stall_any | io.dma_dccm_stall_any)
val i0_block_d = i0_block_raw_d | i0_store_stall_d | i0_load_stall_d
val i0_exublock_d = i0_block_raw_d
//decode valid
io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
val i0_exudecode_d = io.dec_ib0_valid_d & !i0_exublock_d & !io.dec_tlu_flush_lower_r & !flush_final_r
val i0_exulegal_decode_d = i0_exudecode_d & i0_legal
// performance monitor signals
io.dec_pmu_instr_decoded := io.dec_i0_decode_d
io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_i0_decode_d
io.dec_pmu_postsync_stall := postsync_stall.asBool
io.dec_pmu_presync_stall := presync_stall.asBool
val prior_inflight_x = x_d.i0valid
val prior_inflight_wb = r_d.i0valid
val prior_inflight = prior_inflight_x | prior_inflight_wb
val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight)
presync_stall := (i0_presync & prior_inflight_eff)
postsync_stall := withClock(data_gate_clk){RegNext(ps_stall_in, 0.U)}
// illegals will postsync
ps_stall_in := (io.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x)
io.dec_i0_alu_decode_d := i0_exulegal_decode_d & i0_dp.alu
lsu_decode_d := i0_legal_decode_d & i0_dp.lsu
mul_decode_d := i0_exulegal_decode_d & i0_dp.mul
div_decode_d := i0_exulegal_decode_d & i0_dp.div
io.dec_tlu_i0_valid_r := r_d.i0valid & !io.dec_tlu_flush_lower_wb
//traps for TLU (tlu stuff)
d_t.legal := i0_legal_decode_d
d_t.icaf := i0_icaf_d & i0_legal_decode_d // dbecc is icaf exception
d_t.icaf_f1 := io.dec_i0_icaf_f1_d & i0_legal_decode_d // this includes icaf and dbecc
d_t.icaf_type := io.dec_i0_icaf_type_d
d_t.fence_i := (i0_dp.fence_i | debug_fence_i) & i0_legal_decode_d
// put pmu info into the trap packet
d_t.pmu_i0_br_unpred := i0_br_unpred
d_t.pmu_divide := 0.U(1.W)
d_t.pmu_lsu_misaligned := 0.U(1.W)
d_t.i0trigger := io.dec_i0_trigger_match_d & repl(4,io.dec_i0_decode_d)
x_t := rvdffe(d_t,i0_x_ctl_en.asBool,clock,io.scan_mode)
x_t_in := x_t
x_t_in.i0trigger := x_t.i0trigger & ~(repl(4,io.dec_tlu_flush_lower_wb))
r_t := rvdffe(x_t_in,i0_x_ctl_en.asBool,clock,io.scan_mode)
val lsu_trigger_match_r = RegNext(io.lsu_trigger_match_m, 0.U)
val lsu_pmu_misaligned_r = RegNext(io.lsu_pmu_misaligned_m, 0.U)
r_t_in := r_t
r_t_in.i0trigger := (repl(4,(r_d.i0load | r_d.i0store)) & lsu_trigger_match_r) | r_t.i0trigger
r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage
when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) }
io.dec_tlu_packet_r := r_t_in
io.dec_tlu_packet_r.pmu_divide := r_d.i0div & r_d.i0valid
// end tlu stuff
flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)}
io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
i0r.rs1 := i0(19,15) //H: assigning reg packets the instructions bits
i0r.rs2 := i0(24,20)
i0r.rd := i0(11,7)
io.dec_i0_rs1_en_d := i0_dp.rs1 & (i0r.rs1 =/= 0.U(5.W)) // if rs1_en=0 then read will be all 0's
io.dec_i0_rs2_en_d := i0_dp.rs2 & (i0r.rs2 =/= 0.U(5.W))
val i0_rd_en_d = i0_dp.rd & (i0r.rd =/= 0.U(5.W))
io.dec_i0_rs1_d := i0r.rs1//H:assiging packets to output signals leading to gprfile
io.dec_i0_rs2_d := i0r.rs2
val i0_jalimm20 = i0_dp.jal & i0_dp.imm20 // H:jal (used at line 915)
val i0_uiimm20 = !i0_dp.jal & i0_dp.imm20
io.dec_i0_immed_d := Mux1H(Seq(
i0_dp.csr_read -> io.dec_csr_rddata_d,
!i0_dp.csr_read -> i0_immed_d))
i0_immed_d := Mux1H(Seq(
i0_dp.imm12 -> Cat(repl(20,i0(31)),i0(31,20)), // jalr
i0_dp.shimm5 -> Cat(repl(27,0.U),i0(24,20)),
i0_jalimm20 -> Cat(repl(12,i0(31)),i0(19,12),i0(20),i0(30,21),0.U),
i0_uiimm20 -> Cat(i0(31,12),repl(12,0.U)),
(i0_csr_write_only_d & i0_dp.csr_imm).asBool -> Cat(repl(27,0.U),i0(19,15)))) // for csr's that only write
i0_legal_decode_d := io.dec_i0_decode_d & i0_legal
i0_d_c.mul := i0_dp.mul & i0_legal_decode_d
i0_d_c.load := i0_dp.load & i0_legal_decode_d
i0_d_c.alu := i0_dp.alu & i0_legal_decode_d
val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c, i0_x_ctl_en.asBool)}
val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c, i0_r_ctl_en.asBool)}
i0_pipe_en := Cat(io.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)})
i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override)
i0_r_ctl_en := (i0_pipe_en(2,1).orR | io.clk_override)
i0_wb_ctl_en := (i0_pipe_en(1,0).orR | io.clk_override)
i0_x_data_en := ( i0_pipe_en(3) | io.clk_override)
i0_r_data_en := ( i0_pipe_en(2) | io.clk_override)
i0_wb_data_en := ( i0_pipe_en(1) | io.clk_override)
i0_wb1_data_en := ( i0_pipe_en(0) | io.clk_override)
io.dec_data_en := Cat(i0_x_data_en, i0_r_data_en)
io.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en)
d_d.i0rd := i0r.rd
d_d.i0v := i0_rd_en_d & i0_legal_decode_d
d_d.i0valid := io.dec_i0_decode_d // has flush_final_r
d_d.i0load := i0_dp.load & i0_legal_decode_d
d_d.i0store := i0_dp.store & i0_legal_decode_d
d_d.i0div := i0_dp.div & i0_legal_decode_d
d_d.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d
d_d.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d
d_d.csrwaddr := i0(31,20)
x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode)
val x_d_in = Wire(new el2_dest_pkt_t)
x_d_in := x_d
x_d_in.i0v := x_d.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
x_d_in.i0valid := x_d.i0valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
r_d := rvdffe(x_d_in,i0_r_ctl_en.asBool,clock,io.scan_mode)
r_d_in := r_d
r_d_in.i0rd := r_d.i0rd
r_d_in.i0v := (r_d.i0v & !io.dec_tlu_flush_lower_wb)
r_d_in.i0valid := (r_d.i0valid & !io.dec_tlu_flush_lower_wb)
r_d_in.i0load := r_d.i0load & !io.dec_tlu_flush_lower_wb
r_d_in.i0store := r_d.i0store & !io.dec_tlu_flush_lower_wb
wbd := rvdffe(r_d_in,i0_wb_ctl_en.asBool,clock,io.scan_mode)
io.dec_i0_waddr_r := r_d_in.i0rd
i0_wen_r := r_d_in.i0v & !io.dec_tlu_i0_kill_writeb_r
io.dec_i0_wen_r := i0_wen_r & !r_d_in.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe
io.dec_i0_wdata_r := i0_result_corr_r
val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode)
if ( LOAD_TO_USE_PLUS1 == 1 ) {
i0_result_x := io.exu_i0_result_x
i0_result_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_m, i0_result_r_raw)
}
else {
i0_result_x := Mux((x_d.i0v & x_d.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x)
i0_result_r := i0_result_r_raw
}
// correct lsu load data - don't use for bypass, do pass down the pipe
i0_result_corr_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw)
io.dec_i0_br_immed_d := Mux((io.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2))
val last_br_immed_d = WireInit(UInt(12.W),0.U)
last_br_immed_d := Mux((io.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset)
val last_br_immed_x = WireInit(UInt(12.W),0.U)
last_br_immed_x := rvdffe(last_br_immed_d,i0_x_data_en.asBool,clock,io.scan_mode)
// divide stuff
val div_e1_to_r = (x_d.i0div & x_d.i0valid) | (r_d.i0div & r_d.i0valid)
val div_flush = (x_d.i0div & x_d.i0valid & (x_d.i0rd === 0.U(5.W))) |
(x_d.i0div & x_d.i0valid & io.dec_tlu_flush_lower_r ) |
(r_d.i0div & r_d.i0valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r)
// cancel if any younger inst committing this cycle to same dest as nonblock divide
val nonblock_div_cancel = (io.dec_div_active & div_flush) |
(io.dec_div_active & !div_e1_to_r & (r_d.i0rd === io.div_waddr_wb) & i0_wen_r)
io.dec_div_cancel := nonblock_div_cancel.asBool
val i0_div_decode_d = i0_legal_decode_d & i0_dp.div
val div_active_in = i0_div_decode_d | (io.dec_div_active & !io.exu_div_wren & !nonblock_div_cancel)
io.dec_div_active := withClock(io.free_clk){RegNext(div_active_in, 0.U)}
// nonblocking div scheme
i0_nonblock_div_stall := (io.dec_i0_rs1_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs1)) |
(io.dec_i0_rs2_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs2))
io.div_waddr_wb := RegEnable(i0r.rd,0.U,i0_div_decode_d.asBool)
///div end
//for tracing instruction
val i0_wb_en = i0_wb_data_en
val i0_wb1_en = i0_wb1_data_en
val div_inst = rvdffe(i0_inst_d(24,7),i0_div_decode_d.asBool,clock,io.scan_mode)
val i0_inst_x = rvdffe(i0_inst_d,i0_x_data_en.asBool,clock,io.scan_mode)
val i0_inst_r = rvdffe(i0_inst_x,i0_r_data_en.asBool,clock,io.scan_mode)
val i0_inst_wb_in = i0_inst_r
val i0_inst_wb = rvdffe(i0_inst_wb_in,i0_wb_en.asBool,clock,io.scan_mode)
io.dec_i0_inst_wb1 := rvdffe(i0_inst_wb,i0_wb1_en.asBool,clock,io.scan_mode)
val i0_pc_wb = rvdffe(io.dec_tlu_i0_pc_r,i0_wb_en.asBool,clock,io.scan_mode)
io.dec_i0_pc_wb1 := rvdffe(i0_pc_wb,i0_wb1_en.asBool,clock,io.scan_mode)
val dec_i0_pc_r = rvdffe(io.exu_i0_pc_x,i0_r_data_en.asBool,clock,io.scan_mode)
io.dec_tlu_i0_pc_r := dec_i0_pc_r
//end tracing
val temp_pred_correct_npc_x = rvbradder(Cat(io.exu_i0_pc_x,0.U),Cat(last_br_immed_x,0.U))
io.pred_correct_npc_x := temp_pred_correct_npc_x(31,1)
// scheduling logic for primary alu's
val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.i0v & (x_d.i0rd === i0r.rs1)
val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.i0v & (r_d.i0rd === i0r.rs1)
val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.i0v & (x_d.i0rd === i0r.rs2)
val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.i0v & (r_d.i0rd === i0r.rs2)
// order the producers as follows: , i0_x, i0_r, i0_wb
i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d)))
i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U))
i0_rs2_class_d := Mux(i0_rs2_depend_i0_x.asBool,i0_x_c,Mux(i0_rs2_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs2_class_d)))
i0_rs2_depth_d := Mux(i0_rs2_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs2_depend_i0_r.asBool, 2.U(2.W), 0.U))
// stores will bypass load data in the lsu pipe
if (LOAD_TO_USE_PLUS1 == 1) {
i0_load_block_d := (i0_rs1_class_d.load & i0_rs1_depth_d) | (i0_rs2_class_d.load & i0_rs2_depth_d(0) & !i0_dp.store)
load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(1) & i0_rs1_class_d.load
store_data_bypass_d := i0_dp.store & (i0_rs2_depth_d(1) & i0_rs2_class_d.load)
store_data_bypass_m := i0_dp.store & (i0_rs2_depth_d(0) & i0_rs2_class_d.load)
}
else {
i0_load_block_d := 0.B
load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(0) & i0_rs1_class_d.load
store_data_bypass_d := i0_dp.store & i0_rs2_depth_d(0) & i0_rs2_class_d.load
store_data_bypass_m := 0.B
}
// add nonblock load rs1/rs2 bypass cases
val i0_rs1_nonblock_load_bypass_en_d = io.dec_i0_rs1_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs1)
val i0_rs2_nonblock_load_bypass_en_d = io.dec_i0_rs2_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs2)
// bit 2 is priority match, bit 0 lowest priority , i0_x, i0_r
i0_rs1bypass := Cat((i0_rs1_depth_d(0) &(i0_rs1_class_d.alu | i0_rs1_class_d.mul)),(i0_rs1_depth_d(0) & (i0_rs1_class_d.load)), (i0_rs1_depth_d(1) & (i0_rs1_class_d.alu | i0_rs1_class_d.mul | i0_rs1_class_d.load)))
i0_rs2bypass := Cat((i0_rs2_depth_d(0) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul)),(i0_rs2_depth_d(0) & (i0_rs2_class_d.load)),(i0_rs2_depth_d(1) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul | i0_rs2_class_d.load)))
io.dec_i0_rs1_bypass_en_d := Cat(i0_rs1bypass(2),(i0_rs1bypass(1) | i0_rs1bypass(0) | (!i0_rs1bypass(2) & i0_rs1_nonblock_load_bypass_en_d)))
io.dec_i0_rs2_bypass_en_d := Cat(i0_rs2bypass(2),(i0_rs2bypass(1) | i0_rs2bypass(0) | (!i0_rs2bypass(2) & i0_rs2_nonblock_load_bypass_en_d)))
io.dec_i0_rs1_bypass_data_d := Mux1H(Seq(
i0_rs1bypass(1).asBool -> io.lsu_result_m,
i0_rs1bypass(0).asBool -> i0_result_r,
(!i0_rs1bypass(1) & !i0_rs1bypass(0) & i0_rs1_nonblock_load_bypass_en_d).asBool -> io.lsu_nonblock_load_data,
))
io.dec_i0_rs2_bypass_data_d := Mux1H(Seq(
i0_rs2bypass(1).asBool -> io.lsu_result_m,
i0_rs2bypass(0).asBool -> i0_result_r,
(!i0_rs2bypass(1) & !i0_rs2bypass(0) & i0_rs2_nonblock_load_bypass_en_d).asBool -> io.lsu_nonblock_load_data,
))
io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dma_dccm_stall_any & !i0_block_raw_d) | io.dec_extint_stall)
io.dec_lsu_offset_d := Mux1H(Seq(
(!io.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20),
(!io.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7))))
}
object dec_decode extends App{
println("Generating Verilog...")
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec_decode_ctl()))
}

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package dec
import chisel3._
import scala.collection._
import chisel3.util._
import include._
import lib._
class el2_dec_gpr_ctl extends Module with RequireAsyncReset with el2_lib {
val io =IO(new el2_dec_gpr_ctl_IO)
val w0v =Wire(Vec(32,UInt(1.W)))
val w1v =Wire(Vec(32,UInt(1.W)))
val w2v =Wire(Vec(32,UInt(1.W)))
val gpr_in =Wire(Vec(32,UInt(32.W)))
val gpr_out =Wire(Vec(32,UInt(32.W)))
val gpr_wr_en =Wire(UInt(32.W))
w0v(0):=0.U
w1v(0):=0.U
w2v(0):=0.U
gpr_out(0):=0.U
gpr_in(0):=0.U
io.rd0:=0.U
io.rd1:=0.U
gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_))
// GPR Write logic
for (j <-1 until 32){
w0v(j) := io.wen0 & (io.waddr0===j.asUInt)
w1v(j) := io.wen1 & (io.waddr1===j.asUInt)
w2v(j) := io.wen2 & (io.waddr2===j.asUInt)
gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2)
}
// GPR Write Enables for power savings
for (j <-1 until 32){
gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode)
}
// GPR Read logic
io.rd0:=Mux1H((1 until 32).map(i => (io.raddr0===i.U).asBool -> gpr_out(i)))
io.rd1:=Mux1H((1 until 32).map(i => (io.raddr1===i.U).asBool -> gpr_out(i)))
}
class el2_dec_gpr_ctl_IO extends Bundle{
val raddr0=Input(UInt(5.W)) // logical read addresses
val raddr1=Input(UInt(5.W))
val wen0=Input(UInt(1.W)) // write enable
val waddr0=Input(UInt(5.W)) // write address
val wd0=Input(UInt(32.W)) // write data
val wen1=Input(UInt(1.W)) // write enable
val waddr1=Input(UInt(5.W)) // write address
val wd1=Input(UInt(32.W)) // write data
val wen2=Input(UInt(1.W)) // write enable
val waddr2=Input(UInt(5.W)) // write address
val wd2=Input(UInt(32.W)) // write data
val rd0=Output(UInt(32.W)) // read data
val rd1=Output(UInt(32.W))
val scan_mode=Input(Bool())
}
object gpr_gen extends App{
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_gpr_ctl)))
}

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package dec
import include._
import chisel3._
import chisel3.util._
import lib._
class el2_dec_ib_ctl_IO extends Bundle with param{
val dbg_cmd_valid =Input(UInt(1.W)) // valid dbg cmd
val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write
val dbg_cmd_type =Input(UInt(2.W)) // dbg type
val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0
val i0_brp =Input(new el2_br_pkt_t) // i0 branch packet from aligner
val ifu_i0_bp_index =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size)
val ifu_i0_bp_fghr =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR
val ifu_i0_bp_btag =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag
val ifu_i0_pc4 =Input(UInt(1.W)) // i0 is 4B inst else 2B
val ifu_i0_valid =Input(UInt(1.W)) // i0 valid from ifu
val ifu_i0_icaf =Input(UInt(1.W)) // i0 instruction access fault
val ifu_i0_icaf_type =Input(UInt(2.W)) // i0 instruction access fault type
val ifu_i0_icaf_f1 =Input(UInt(1.W)) // i0 has access fault on second fetch group
val ifu_i0_dbecc =Input(UInt(1.W)) // i0 double-bit error
val ifu_i0_instr =Input(UInt(32.W)) // i0 instruction from the aligner
val ifu_i0_pc =Input(UInt(31.W)) // i0 pc from the aligner
val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid
val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type
val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode
val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode
val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B
val dec_i0_brp =Output(new el2_br_pkt_t) // i0 branch packet at decode
val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR
val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag
val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode
val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group
val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode
val dec_debug_wdata_rs1_d =Output(UInt(1.W)) // put debug write data onto rs1 source: machine is halted
val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst
}
class el2_dec_ib_ctl extends Module with param{
val io=IO(new el2_dec_ib_ctl_IO)
io.dec_i0_icaf_f1_d :=io.ifu_i0_icaf_f1
io.dec_i0_dbecc_d :=io.ifu_i0_dbecc
io.dec_i0_icaf_d :=io.ifu_i0_icaf
io.dec_i0_pc_d :=io.ifu_i0_pc
io.dec_i0_pc4_d :=io.ifu_i0_pc4
io.dec_i0_icaf_type_d :=io.ifu_i0_icaf_type
io.dec_i0_brp :=io.i0_brp
io.dec_i0_bp_index :=io.ifu_i0_bp_index
io.dec_i0_bp_fghr :=io.ifu_i0_bp_fghr
io.dec_i0_bp_btag :=io.ifu_i0_bp_btag
// GPR accesses
// put reg to read on rs1
// read -> or %x0, %reg,%x0 {000000000000,reg[4:0],110000000110011}
// put write date on rs1
// write -> or %reg, %x0, %x0 {00000000000000000110,reg[4:0],0110011}
// CSR accesses
// csr is of form rd, csr, rs1
// read -> csrrs %x0, %csr, %x0 {csr[11:0],00000010000001110011}
// put write data on rs1
// write -> csrrw %x0, %csr, %x0 {csr[11:0],00000001000001110011}
val debug_valid =io.dbg_cmd_valid & (io.dbg_cmd_type =/= 2.U)
val debug_read =debug_valid & !io.dbg_cmd_write
val debug_write =debug_valid & io.dbg_cmd_write
val debug_read_gpr = debug_read & (io.dbg_cmd_type===0.U)
val debug_write_gpr = debug_write & (io.dbg_cmd_type===0.U)
val debug_read_csr = debug_read & (io.dbg_cmd_type===1.U)
val debug_write_csr = debug_write & (io.dbg_cmd_type===1.U)
val dreg = io.dbg_cmd_addr(4,0)
val dcsr = io.dbg_cmd_addr(11,0)
val ib0_debug_in =Mux1H(Seq(
debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U),
debug_write_gpr.asBool -> Cat("b00000000000000000110".U(20.W),dreg,"b0110011".U(7.W)),
debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U(20.W)),
debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U(20.W))
))
// machine is in halted state, pipe empty, write will always happen next cycle
io.dec_debug_wdata_rs1_d := debug_write_gpr | debug_write_csr
// special fence csr for use only in debug mode
io.dec_debug_fence_d := debug_write_csr & (dcsr === 0x7C4.U)
io.dec_ib0_valid_d := io.ifu_i0_valid | debug_valid
io.dec_i0_instr_d := Mux(debug_valid.asBool,ib0_debug_in,io.ifu_i0_instr)
}
object ib_gen extends App{
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_ib_ctl)))
}

2872
src/main/scala/dec/el2_dec_tlu_ctl.scala Normal file
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File diff suppressed because it is too large Load Diff

20
src/main/scala/dec/el2_dec_trigger.scala Normal file
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@ -0,0 +1,20 @@
package dec
import chisel3.util._
import chisel3._
import include.el2_trigger_pkt_t
import lib._
class el2_dec_trigger extends Module with el2_lib {
val io = IO(new Bundle {
val trigger_pkt_any = Input(Vec(4, new el2_trigger_pkt_t))
val dec_i0_pc_d = Input(UInt(31.W))
val dec_i0_trigger_match_d = Output(UInt(4.W))
})
val dec_i0_match_data = VecInit.tabulate(4)(i => repl(32, (!io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).execute)) & Cat(io.dec_i0_pc_d, io.trigger_pkt_any(i).tdata2(0)))
io.dec_i0_trigger_match_d := (0 until 4).map(j =>io.trigger_pkt_any(j).execute & io.trigger_pkt_any(j).m & rvmaskandmatch(io.trigger_pkt_any(j).tdata2, dec_i0_match_data(j), io.trigger_pkt_any(j).match_.asBool())).reverse.reduce(Cat(_,_))
}
object dec_trig extends App {
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_trigger())))
}

14
src/main/scala/dmi/dmi_jtag_to_core_sync.scala
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@ -12,11 +12,11 @@ class dmi_jtag_to_core_sync extends Module with el2_lib with RequireAsyncReset {
val wr_en = Input(UInt(1.W))// 1 bit Write enable from JTAG
// Processor Signals
// val rst_n = Input(Bool()) // Core reset
// val clk = Input(Bool()) // Core clock
val reg_en = Output(UInt(1.W)) // 1 bit Write interface bit to Processor
val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor
})
// val rst_n = Input(Bool()) // Core reset
// val clk = Input(Bool()) // Core clock
val reg_en = Output(UInt(1.W)) // 1 bit Write interface bit to Processor
val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor
})
val c_rd_en =WireInit(0.U(1.W))
val c_wr_en =WireInit(0.U(1.W))
val rden =WireInit(0.U(3.W))
@ -25,8 +25,8 @@ class dmi_jtag_to_core_sync extends Module with el2_lib with RequireAsyncReset {
// synchronizers
rden := RegNext(Cat(rden(1,0),io.rd_en),0.U)
wren := RegNext(Cat(wren(1,0),io.wr_en),0.U)
c_rd_en := rden(1) & !rden(2)
c_wr_en := wren(1) & !wren(2)
c_rd_en := rden(1) & !rden(2)
c_wr_en := wren(1) & !wren(2)
// Outputs
io.reg_en := c_wr_en | c_rd_en
io.reg_wr_en := c_wr_en

27
src/main/scala/dmi/dmi_wrapper.scala
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@ -8,23 +8,23 @@ import lib._
class dmi_wrapper extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{
// JTAG signals
//val trst_n =Input(UInt(1.W)) // JTAG reset
//val tck =Input(UInt(1.W)) // JTAG clock
val trst_n = Input(AsyncReset())
val tck = Input(Clock()) // JTAG clock
val tms =Input(UInt(1.W)) // Test mode select
val tdi =Input(UInt(1.W)) // Test Data Input
val tdo =Output(UInt(1.W)) // Test Data Output
val tdoEnable =Output(UInt(1.W)) // Test Data Output enable
// Processor Signals
// val core_rst_n =Input(UInt(1.W)) // Core reset
// val core_clk =Input(UInt(1.W)) // Core clock
val jtag_id = Input(UInt(32.W)) // JTAG ID
val rd_data = Input(UInt(32.W)) // 32 bit Read data from Processor
val reg_wr_data = Output(UInt(32.W)) // 32 bit Write data to Processor
val reg_wr_addr = Output(UInt(7.W)) // 7 bit reg address to Processor
val reg_en = Output(UInt(1.W)) // 1 bit Read enable to Processor
val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor
val dmi_hard_reset = Output(UInt(1.W))
// val core_rst_n =Input(UInt(1.W)) // Core reset
// val core_clk =Input(UInt(1.W)) // Core clock
val jtag_id = Input(UInt(32.W)) // JTAG ID
val rd_data = Input(UInt(32.W)) // 32 bit Read data from Processor
val reg_wr_data = Output(UInt(32.W)) // 32 bit Write data to Processor
val reg_wr_addr = Output(UInt(7.W)) // 7 bit reg address to Processor
val reg_en = Output(UInt(1.W)) // 1 bit Read enable to Processor
val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor
val dmi_hard_reset = Output(UInt(1.W))
})
//Wire Declaration
val rd_en = WireInit(0.U(1.W))
@ -33,8 +33,8 @@ class dmi_wrapper extends Module with el2_lib with RequireAsyncReset {
//jtag_tap instantiation
val i_jtag_tap = Module(new rvjtag_tap())
//.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
//.tck(tck), // dedicated JTAG TCK pad signal
i_jtag_tap.io.trst := io.trst_n // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
i_jtag_tap.io.tck := io.tck // dedicated JTAG TCK pad signal
i_jtag_tap.io.tms := io.tms // dedicated JTAG TMS pad signal
i_jtag_tap.io.tdi := io.tdi // dedicated JTAG TDI pad signal
io.tdo := i_jtag_tap.io.tdo // dedicated JTAG TDO pad signal
@ -56,7 +56,6 @@ class dmi_wrapper extends Module with el2_lib with RequireAsyncReset {
val i_dmi_jtag_to_core_sync = Module(new dmi_jtag_to_core_sync())
i_dmi_jtag_to_core_sync.io.wr_en := wr_en // 1 bit Write enable
i_dmi_jtag_to_core_sync.io.rd_en := rd_en // 1 bit Read enable
io.reg_en :=i_dmi_jtag_to_core_sync.io.reg_en // 1 bit Write interface bit
io.reg_wr_en := i_dmi_jtag_to_core_sync.io.reg_wr_en // 1 bit Write enable
}

145
src/main/scala/dmi/rvjtag_tap.scala
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@ -1,23 +1,22 @@
package dmi
import chisel3._
import scala.collection._
import chisel3.util._
import include._
import lib._
class rvjtag_tap extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{
val trst = Input(Bool())
val tck = Input(Bool())
val trst = Input(AsyncReset())
val tck = Input(Clock())
val tms = Input(Bool())
val tdi = Input(Bool())
val dmi_reset = Input(Bool())
val dmi_hard_reset = Input(Bool())
val dmi_reset = Output(Bool())
val dmi_hard_reset = Output(Bool())
val rd_status = Input(UInt(2.W))
val dmi_stat = Input(UInt(2.W))
val idle = Input(UInt(3.W))
val version = Input(UInt(4.W))
val jtag_id = Input(UInt(32.W))
val jtag_id = Input(UInt(31.W))
val rd_data = Input(UInt(32.W))
val tdo = Output(Bool())
@ -27,65 +26,97 @@ class rvjtag_tap extends Module with el2_lib with RequireAsyncReset {
val wr_data = Output(UInt(32.W))
val wr_addr = Output(UInt(AWIDTH.W))
})
val AWIDTH = 7.U(6.W)
val AWIDTH = 7
val USER_DR_LENGTH = AWIDTH + 34
val sr = RegInit(0.U(USER_DR_LENGTH.W))
val nsr = RegInit(0.U(USER_DR_LENGTH.W))
val dr = RegInit(0.U(USER_DR_LENGTH.W))
val nsr = WireInit(0.U(USER_DR_LENGTH.W))
val sr = withClockAndReset (io.tck,io.trst) {RegNext(nsr,0.U)}
val dr = WireInit(0.U(USER_DR_LENGTH.W))
///////////////////////////////////////////////////////
// Tap controller
///////////////////////////////////////////////////////
val state = RegInit(test_logic_reset_state)
val nstate = RegInit(test_logic_reset_state)
//logic[3:0] state, nstate;
val ir = WireInit(0.U(5.W))
val jtag_reset = WireInit(UInt(1.W))
val shift_dr = WireInit(UInt(1.W))
val pause_dr = WireInit(UInt(1.W))
val update_dr = WireInit(UInt(1.W))
val capture_dr = WireInit(UInt(1.W))
val shift_ir = WireInit(UInt(1.W))
val pause_ir = WireInit(UInt(1.W))
val update_ir = WireInit(UInt(1.W))
val capture_ir = WireInit(UInt(1.W))
val dr_en = WireInit(UInt(2.W))
val devid_sel = WireInit(UInt(1.W))
val abits = WireInit(UInt(6.W))
val abits = AWIDTH(5,0)
val test_logic_reset_state :: run_test_idle_state :: select_dr_scan_state :: capture_dr_state :: shift_dr_state :: exit1_dr_state :: pause_dr_state :: exit2_dr_state :: update_dr_state :: select_ir_scan_state :: capture_ir_state :: shift_ir_state :: exit1_ir_state :: pause_ir_state :: exit2_ir_state :: update_ir_state :: Nil = Enum(16)
switch(state){
is(test_logic_reset_state){ nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state)}
is(run_test_idle_state){nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) }
is(select_dr_scan_state){nstate := Mux(io.tms,select_ir_scan_state,capture_dr_state) }
is(capture_dr_state){nstate := Mux(io.tms,exit1_dr_state,shift_dr_state) }
is(shift_dr_state){nstate := Mux(io.tms,exit1_dr_state,shift_dr_state) }
is(exit1_dr_state){nstate := Mux(io.tms,update_dr_state,pause_dr_state) }
is(pause_dr_state){nstate := Mux(io.tms,exit2_dr_state,pause_dr_state) }
is(exit2_dr_state){nstate := Mux(io.tms,update_dr_state,shift_dr_state) }
is(update_dr_state){nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) }
is(select_ir_scan_state){nstate := Mux(io.tms,test_logic_reset_state,capture_ir_state) }
is(capture_ir_state){nstate := Mux(io.tms,exit1_ir_state,shift_i``r_state) }
is(shift_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) }
is(exit1_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) }
is(pause_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) }
is(exit2_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) }
is(update_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) }
}
val nstate = WireInit(test_logic_reset_state)
val state = withClockAndReset(io.tck,io.trst) {RegNext(nstate,test_logic_reset_state)}
val ir = WireInit(0.U(5.W))
val jtag_reset = WireInit(Bool(),false.B)
val shift_dr = WireInit(UInt(1.W),init = 0.U)
val pause_dr = WireInit(UInt(1.W),init = 0.U)
val update_dr = WireInit(Bool(),false.B)
val capture_dr = WireInit(UInt(1.W),init = 0.U)
val shift_ir = WireInit(UInt(1.W),init = 0.U)
val pause_ir = WireInit(UInt(1.W),init = 0.U)
val update_ir = WireInit(Bool(),false.B)
val capture_ir = WireInit(UInt(1.W),init = 0.U)
val dr_en = WireInit(UInt(2.W),init = 0.U)
val devid_sel = WireInit(Bool(),false.B)
val abits = AWIDTH.U(6.W)
/////////////////////////////////////////////////////////////////////////////////////////////////
switch (state) {
is(test_logic_reset_state) {nstate := Mux(io.tms, test_logic_reset_state, run_test_idle_state)
jtag_reset := 1.U }
is(run_test_idle_state) {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) }
is(select_dr_scan_state) {nstate := Mux(io.tms,select_ir_scan_state,capture_dr_state) }
is(capture_dr_state) {nstate := Mux(io.tms,exit1_dr_state,shift_dr_state)
capture_dr := 1.U }
is(shift_dr_state) {nstate := Mux(io.tms,exit1_dr_state,shift_dr_state)
shift_dr := 1.U }
is(exit1_dr_state) {nstate := Mux(io.tms,update_dr_state,pause_dr_state) }
is(pause_dr_state) {nstate := Mux(io.tms,exit2_dr_state,pause_dr_state)
pause_dr := 1.U }
is(exit2_dr_state) {nstate := Mux(io.tms,update_dr_state,shift_dr_state) }
is(update_dr_state) {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state)
update_dr := 1.U }
is(select_ir_scan_state) {nstate := Mux(io.tms,test_logic_reset_state,capture_ir_state) }
is(capture_ir_state) {nstate := Mux(io.tms,exit1_ir_state,shift_ir_state)
capture_ir := 1.U }
is(shift_ir_state) {nstate := Mux(io.tms,exit1_ir_state,shift_ir_state)
shift_ir := 1.U }
is(exit1_ir_state) {nstate := Mux(io.tms,update_ir_state,pause_ir_state) }
is(pause_ir_state) {nstate := Mux(io.tms,exit2_ir_state,pause_ir_state)
pause_ir := 1.U }
is(exit2_ir_state) {nstate := Mux(io.tms,update_ir_state,shift_ir_state) }
is(update_ir_state) {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state)
update_ir := 1.U }
}
io.tdoEnable := shift_dr | shift_ir
///////////////////////////////////////////////////////
// IR register
//////////////////////////////////////////////////////
ir := withClockAndReset(io.tck,io.trst) {RegNext(Mux(jtag_reset,1.U,Mux(update_ir,Mux((sr(4,0)===0.U).asBool,"h1f".U,sr(4,0)),0.U)),1.U)}
devid_sel := ir==="b00001".U(5.W)
dr_en := Cat(ir===17.U,ir===16.U)
///////////////////////////////////////////////////////
// Shift register
///////////////////////////////////////////////////////
when(shift_dr===1.U){
when(dr_en(1)===true.B){nsr :=Cat(io.tdi, sr(USER_DR_LENGTH-1,1))}
.elsewhen(dr_en(0)===1.U || devid_sel===true.B){nsr := Cat(Fill(USER_DR_LENGTH-32,0.U) , io.tdi, sr(31,1))}
.otherwise{nsr := Cat(Fill(USER_DR_LENGTH-1,0.U),io.tdi)} // bypass
}
.elsewhen(capture_dr ===1.U){
when(dr_en(0)){nsr := Cat(Fill(USER_DR_LENGTH-15,0.U) ,io.idle, io.dmi_stat,abits,io.version)}
.elsewhen(dr_en(1)){nsr := Cat(Fill(AWIDTH,0.U),io.rd_data,io.rd_status)}
.elsewhen(devid_sel){nsr := Cat(Fill(USER_DR_LENGTH-32,0.U),io.jtag_id,1.U)}
}
.elsewhen(shift_ir===1.U){nsr := Cat(Fill(USER_DR_LENGTH-5,0.U),io.tdi,sr(4,1))}
.elsewhen(capture_ir===1.U){nsr := Cat(Fill(USER_DR_LENGTH-1,0.U),1.U)}
CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE;
PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE;
EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE;
UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
///////////////////////////////////////////////////////////////////////////////////////////////
// TDO retiming
withClock(io.tck) {io.tdo:=RegNext(sr(0),0.U)}
// DMI CS register
withClockAndReset (io.tck,io.trst) {io.dmi_hard_reset := RegNext(Mux(update_dr & dr_en(0).asBool(),sr(17),0.U),0.U)}
withClockAndReset (io.tck,io.trst) {io.dmi_reset := RegNext(Mux(update_dr & dr_en(0).asBool(),sr(16),0.U),0.U)}
// DR register
withClockAndReset (io.tck,io.trst) {dr := RegNext(Mux(update_dr & dr_en(1).asBool(),sr,Cat(dr(USER_DR_LENGTH-1,2),0.U(2.W))),0.U)}
io.rd_en := dr(0)
io.wr_en := dr(1)
io.wr_data := dr(33,2)
io.wr_addr := dr(40,34)
}
object tapmain extends App{
println("Generate Verilog")
println((new chisel3.stage.ChiselStage).emitVerilog(new rvjtag_tap()))
}

556
src/main/scala/el2_dma_ctrl.scala Normal file
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@ -0,0 +1,556 @@
import chisel3._
import chisel3.util._
import scala.collection._
import lib._
class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle {
val free_clk = Input(Clock())
val dma_bus_clk_en = Input(Bool()) // slave bus clock enable
val clk_override = Input(Bool())
val scan_mode = Input(Bool())
// Debug signals
val dbg_cmd_addr = Input(UInt(32.W))
val dbg_cmd_wrdata = Input(UInt(32.W))
val dbg_cmd_valid = Input(Bool())
val dbg_cmd_write = Input(Bool()) // 1: write command, 0: read_command
val dbg_cmd_type = Input(UInt(2.W)) // 0:gpr 1:csr 2: memory
val dbg_cmd_size = Input(UInt(2.W)) // size of the abstract mem access debug command
val dbg_dma_bubble = Input(Bool()) // Debug needs a bubble to send a valid
val dma_dbg_ready = Output(Bool()) // DMA is ready to accept debug request
val dma_dbg_cmd_done = Output(Bool())
val dma_dbg_cmd_fail = Output(Bool())
val dma_dbg_rddata = Output(UInt(32.W))
// Core side signals
val dma_dccm_req = Output(Bool()) // DMA dccm request (only one of dccm/iccm will be set)
val dma_iccm_req = Output(Bool()) // DMA iccm request
val dma_mem_tag = Output(UInt(3.W)) // DMA Buffer entry number
val dma_mem_addr = Output(UInt(32.W))// DMA request address
val dma_mem_sz = Output(UInt(3.W)) // DMA request size
val dma_mem_write = Output(Bool()) // DMA write to dccm/iccm
val dma_mem_wdata = Output(UInt(64.W))// DMA write data
val dccm_dma_rvalid = Input(Bool()) // dccm data valid for DMA read
val dccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read
val dccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req
val dccm_dma_rdata = Input(UInt(64.W)) // dccm data for DMA read
val iccm_dma_rvalid = Input(Bool()) // iccm data valid for DMA read
val iccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read
val iccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req
val iccm_dma_rdata = Input(UInt(64.W)) // iccm data for DMA read
val dma_dccm_stall_any = Output(Bool()) // stall dccm pipe (bubble) so that DMA can proceed
val dma_iccm_stall_any = Output(Bool()) // stall iccm pipe (bubble) so that DMA can proceed
val dccm_ready = Input(Bool()) // dccm ready to accept DMA request
val iccm_ready = Input(Bool()) // iccm ready to accept DMA request
val dec_tlu_dma_qos_prty = Input(UInt(3.W)) // DMA QoS priority coming from MFDC [18:15]
// PMU signals
val dma_pmu_dccm_read = Output(Bool())
val dma_pmu_dccm_write = Output(Bool())
val dma_pmu_any_read = Output(Bool())
val dma_pmu_any_write = Output(Bool())
// AXI Write Channels
val dma_axi_awvalid = Input(Bool())
val dma_axi_awready = Output(Bool())
val dma_axi_awid = Input(UInt(DMA_BUS_TAG.W))
val dma_axi_awaddr = Input(UInt(32.W))
val dma_axi_awsize = Input(UInt(3.W))
val dma_axi_wvalid = Input(Bool())
val dma_axi_wready = Output(Bool())
val dma_axi_wdata = Input(UInt(64.W))
val dma_axi_wstrb = Input(UInt(8.W))
val dma_axi_bvalid = Output(Bool())
val dma_axi_bready = Input(Bool())
val dma_axi_bresp = Output(UInt(2.W))
val dma_axi_bid = Output(UInt(DMA_BUS_TAG.W))
// AXI Read Channels
val dma_axi_arvalid = Input(Bool())
val dma_axi_arready = Output(Bool())
val dma_axi_arid = Input(UInt(DMA_BUS_TAG.W))
val dma_axi_araddr = Input(UInt(32.W))
val dma_axi_arsize = Input(UInt(3.W))
val dma_axi_rvalid = Output(Bool())
val dma_axi_rready = Input(Bool())
val dma_axi_rid = Output(UInt(DMA_BUS_TAG.W))
val dma_axi_rdata = Output(UInt(64.W))
val dma_axi_rresp = Output(UInt(2.W))
val dma_axi_rlast = Output(Bool())
})
val DEPTH_PTR = log2Ceil(DMA_BUF_DEPTH)
val fifo_error = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
val fifo_error_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_done = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_addr = Wire(Vec(DMA_BUF_DEPTH, UInt(32.W)))
val fifo_sz = Wire(Vec(DMA_BUF_DEPTH,UInt(3.W)))
val fifo_byteen = Wire(Vec(DMA_BUF_DEPTH,UInt(8.W)))
val fifo_data = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
val fifo_tag = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_TAG.W)))
val fifo_mid = Wire(Vec(DMA_BUF_DEPTH,UInt((DMA_BUS_ID:Int).W)))
val fifo_prty = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_PRTY.W)))
val fifo_error_en = WireInit(UInt(DMA_BUF_DEPTH.W),0.U)
val fifo_error_in = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
val fifo_data_in = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
val RspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
val WrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
val RdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
val NxtRspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
val NxtWrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
val NxtRdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
val dma_dbg_cmd_error = WireInit(UInt(1.W),0.U)
val dma_dbg_cmd_done_q = WireInit(UInt(1.W), 0.U)
val fifo_empty = WireInit(UInt(1.W), 0.U)
val dma_address_error = WireInit(UInt(1.W), 0.U)
val dma_alignment_error = WireInit(UInt(1.W), 0.U)
val num_fifo_vld = WireInit(UInt(4.W),0.U)
val dma_mem_req = WireInit(UInt(1.W), 0.U)
val dma_mem_addr_int = WireInit(UInt(32.W), 0.U)
val dma_mem_sz_int = WireInit(UInt(3.W), 0.U)
val dma_mem_byteen = WireInit(UInt(8.W), 0.U)
val dma_nack_count = WireInit(UInt(3.W), 0.U)
val dma_nack_count_csr = WireInit(UInt(3.W), 0.U)
val bus_rsp_valid = WireInit(UInt(1.W), 0.U)
val bus_rsp_sent = WireInit(UInt(1.W), 0.U)
val bus_cmd_valid = WireInit(UInt(1.W), 0.U)
val bus_cmd_sent = WireInit(UInt(1.W), 0.U)
val bus_cmd_write = WireInit(UInt(1.W), 0.U)
val bus_cmd_posted_write = WireInit(UInt(1.W), 0.U)
val bus_cmd_byteen = WireInit(UInt(8.W), 0.U)
val bus_cmd_sz = WireInit(UInt(3.W), 0.U)
val bus_cmd_addr = WireInit(UInt(32.W), 0.U)
val bus_cmd_wdata = WireInit(UInt(64.W), 0.U)
val bus_cmd_tag = WireInit(UInt(DMA_BUS_TAG.W), 0.U)
val bus_cmd_mid = WireInit(UInt((DMA_BUS_ID:Int).W), 0.U)
val bus_cmd_prty = WireInit(UInt(DMA_BUS_PRTY.W), 0.U)
val bus_posted_write_done = WireInit(UInt(1.W), 0.U)
val fifo_full_spec_bus = WireInit(UInt(1.W), 0.U)
val dbg_dma_bubble_bus = WireInit(UInt(1.W), 0.U)
val axi_mstr_priority = WireInit(UInt(1.W), 0.U)
val axi_mstr_sel = WireInit(UInt(1.W), 0.U)
val axi_rsp_sent = WireInit(UInt(1.W), 0.U)
val fifo_cmd_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_data_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_pend_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_error_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_done_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_done_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_reset = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_valid = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_rpend = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_done_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_posted_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_dbg = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val wrbuf_vld = WireInit(UInt(1.W), 0.U)
val wrbuf_data_vld = WireInit(UInt(1.W), 0.U)
val rdbuf_vld = WireInit(UInt(1.W), 0.U)
val dma_free_clk = Wire(Clock())
val dma_bus_clk = Wire(Clock())
val dma_buffer_c1_clk = Wire(Clock())
val fifo_byteen_in = WireInit(UInt(8.W), 0.U)
//------------------------LOGIC STARTS HERE---------------------------------
// DCCM Address check
val (dma_mem_addr_in_dccm,dma_mem_addr_in_dccm_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),DCCM_SADR.U,DCCM_SIZE)
// PIC memory address check
val (dma_mem_addr_in_pic,dma_mem_addr_in_pic_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),PIC_BASE_ADDR.U,PIC_SIZE)
// ICCM Address check
val (dma_mem_addr_in_iccm,dma_mem_addr_in_iccm_region_nc) = if(ICCM_ENABLE) rvrangecheck_ch(dma_mem_addr_int(31,0),ICCM_SADR.U,ICCM_SIZE) else (0.U,0.U)
// FIFO inputs
val fifo_addr_in = Mux(io.dbg_cmd_valid.asBool, io.dbg_cmd_addr(31,0), bus_cmd_addr(31,0))
fifo_byteen_in := Mux(io.dbg_cmd_valid.asBool, "h0f".U << (4.U * io.dbg_cmd_addr(2)), bus_cmd_byteen(7,0))
val fifo_sz_in = Mux(io.dbg_cmd_valid.asBool, Cat(0.U, io.dbg_cmd_size(1,0)), bus_cmd_sz(2,0))
val fifo_write_in = Mux(io.dbg_cmd_valid.asBool, io.dbg_cmd_write, bus_cmd_write)
val fifo_posted_write_in = !io.dbg_cmd_valid & bus_cmd_posted_write
val fifo_dbg_in = io.dbg_cmd_valid
fifo_cmd_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent.asBool & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1).asBool)) & (i.U === WrPtr)).asUInt).reverse.reduce(Cat(_,_))
fifo_data_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1) & io.dbg_cmd_write)) & (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) | (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).reverse.reduce(Cat(_,_))
fifo_pend_en := (0 until DMA_BUF_DEPTH).map(i => ((io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
fifo_error_en := (0 until DMA_BUF_DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) & (i.U === RdPtr)) | ((io.dccm_dma_rvalid & io.dccm_dma_ecc_error) & (i.U === io.dccm_dma_rtag)) | ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
fifo_error_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((((fifo_error_in(i)(1,0).orR) & fifo_error_en(i)) | (fifo_error(i).orR)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
fifo_done_en := (0 until DMA_BUF_DEPTH).map(i => (((fifo_error(i).orR | fifo_error_en(i) | ((io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write)) & (i.U === RdPtr)) | (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
fifo_done_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
fifo_reset := (0 until DMA_BUF_DEPTH).map(i => ((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr))).reverse.reduce(Cat(_,_))
(0 until DMA_BUF_DEPTH).map(i => fifo_error_in(i) := (Mux(io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag), Cat(0.U, io.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), (Cat(0.U, io.iccm_dma_ecc_error)), (Cat((dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error))))))
(0 until DMA_BUF_DEPTH).map(i => fifo_data_in(i) := (Mux(fifo_error_en(i) & (fifo_error_in(i).orR), Cat(Fill(32, 0.U), fifo_addr(i)), Mux(io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag), io.dccm_dma_rdata, Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), io.iccm_dma_rdata, Mux(io.dbg_cmd_valid, Fill(2, io.dbg_cmd_wrdata), bus_cmd_wdata(63,0)))))))
fifo_valid := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_cmd_en(i), 1.U, fifo_valid(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
(0 until DMA_BUF_DEPTH).map(i => fifo_error(i) := withClock(dma_free_clk) {RegNext(Mux(fifo_error_en(i).asBool(),fifo_error_in(i) , fifo_error(i)) & Fill(fifo_error_in(i).getWidth , !fifo_reset(i)), 0.U)})
fifo_error_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_error_bus_en(i), 1.U, fifo_error_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
fifo_rpend := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_pend_en(i), 1.U, fifo_rpend(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
fifo_done := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_en(i), 1.U, fifo_done(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
fifo_done_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_bus_en(i), 1.U, fifo_done_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
(0 until DMA_BUF_DEPTH).map(i => fifo_addr(i) := rvdffe(fifo_addr_in, fifo_cmd_en(i), clock, io.scan_mode))
(0 until DMA_BUF_DEPTH).map(i => fifo_sz(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_sz_in(2,0), 0.U, fifo_cmd_en(i))})
(0 until DMA_BUF_DEPTH).map(i => fifo_byteen(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_byteen_in(7,0), 0.U, fifo_cmd_en(i).asBool())})
fifo_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
fifo_posted_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_posted_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
fifo_dbg := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_buffer_c1_clk) {RegEnable(fifo_dbg_in, 0.U, fifo_cmd_en(i))}).reverse.reduce(Cat(_,_))
(0 until DMA_BUF_DEPTH).map(i => fifo_data(i) := rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode))
(0 until DMA_BUF_DEPTH).map(i => fifo_tag(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_tag, 0.U, fifo_cmd_en(i))})
(0 until DMA_BUF_DEPTH).map(i => fifo_mid(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_mid, 0.U, fifo_cmd_en(i))})
(0 until DMA_BUF_DEPTH).map(i => fifo_prty(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_prty, 0.U, fifo_cmd_en(i))})
// Pointer logic
NxtWrPtr := Mux((WrPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, WrPtr + 1.U)
NxtRdPtr := Mux((RdPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RdPtr + 1.U)
NxtRspPtr := Mux((RspPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RspPtr + 1.U)
val WrPtrEn = fifo_cmd_en.orR
val RdPtrEn = (io.dma_dccm_req | io.dma_iccm_req | (dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error))
val RspPtrEn = (io.dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en)
WrPtr := withClock(dma_free_clk) {
RegEnable(NxtWrPtr, 0.U, WrPtrEn)
}
RdPtr := withClock(dma_free_clk) {
RegEnable(NxtRdPtr, 0.U, RdPtrEn.asBool)
}
RspPtr := withClock(dma_free_clk) {
RegEnable(NxtRspPtr, 0.U, RspPtrEn.asBool)
}
// Miscellaneous signal
val fifo_full = fifo_full_spec_bus;
val num_fifo_vld_tmp = WireInit(UInt(4.W),0.U)
val num_fifo_vld_tmp2 = WireInit(UInt(4.W),0.U)
num_fifo_vld_tmp := (Cat(Fill(3, 0.U), bus_cmd_sent)) - (Cat(Fill(3, 0.U), bus_rsp_sent))
num_fifo_vld_tmp2 := (0 until DMA_BUF_DEPTH).map(i => Cat(Fill(3,0.U), fifo_valid(i))).reduce(_+_)
num_fifo_vld := num_fifo_vld_tmp + num_fifo_vld_tmp2
val fifo_full_spec = (num_fifo_vld_tmp2 >= DMA_BUF_DEPTH.asUInt())
val dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus)
// Error logic
dma_address_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !fifo_dbg(RdPtr) & (~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm)).asUInt // request not for ICCM or DCCM
dma_alignment_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !dma_address_error &
(((dma_mem_sz_int(2,0) === 1.U) & dma_mem_addr_int(0)) | // HW size but unaligned
((dma_mem_sz_int(2,0) === 2.U) & (dma_mem_addr_int(1, 0).orR)) | // W size but unaligned
((dma_mem_sz_int(2,0) === 3.U) & (dma_mem_addr_int(2, 0).orR)) | // DW size but unaligned
(dma_mem_addr_in_iccm & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt ) | // ICCM access not word size
(dma_mem_addr_in_dccm & io.dma_mem_write & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt) | // DCCM write not word size
(io.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)),
(dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)),
(dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)),
(dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)))) =/= 15.U)) | // Write byte enables not aligned for word store
(io.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store
//Dbg outputs
io.dma_dbg_ready := fifo_empty & dbg_dma_bubble_bus
io.dma_dbg_cmd_done := (fifo_valid(RspPtr) & fifo_dbg(RspPtr) & fifo_done(RspPtr))
io.dma_dbg_rddata := Mux(fifo_addr(RspPtr)(2), fifo_data(RspPtr)(63, 32), fifo_data(RspPtr)(31,0))
io.dma_dbg_cmd_fail := fifo_error(RspPtr).orR
dma_dbg_cmd_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & fifo_dbg(RdPtr) & ((~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm | dma_mem_addr_in_pic)).asBool() | (dma_mem_sz_int(1, 0) =/= 2.U)) // Only word accesses allowed
// Block the decode if fifo full
io.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr)
io.dma_iccm_stall_any := dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr);
// Used to indicate ready to debug
fifo_empty := ~(fifo_valid.orR)
// Nack counter, stall the lsu pipe if 7 nacks
dma_nack_count_csr := io.dec_tlu_dma_qos_prty
val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.dma_dccm_req | io.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.dma_dccm_req | io.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U))
dma_nack_count := withClock(dma_free_clk) {
RegEnable(dma_nack_count_d(2,0), 0.U, dma_mem_req.asBool)
}
// Core outputs
dma_mem_req := fifo_valid(RdPtr) & !fifo_rpend(RdPtr) & !fifo_done(RdPtr) & !(dma_address_error | dma_alignment_error | dma_dbg_cmd_error)
io.dma_dccm_req := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & io.dccm_ready;
io.dma_iccm_req := dma_mem_req & dma_mem_addr_in_iccm & io.iccm_ready;
io.dma_mem_tag := RdPtr
dma_mem_addr_int := fifo_addr(RdPtr)
dma_mem_sz_int := fifo_sz(RdPtr)
io.dma_mem_addr := Mux(io.dma_mem_write & (dma_mem_byteen(7,0) === "hf0".U), Cat(dma_mem_addr_int(31, 3), 1.U, dma_mem_addr_int(1, 0)), dma_mem_addr_int(31,0))
io.dma_mem_sz := Mux(io.dma_mem_write & ((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U)), 2.U, dma_mem_sz_int(2,0))
dma_mem_byteen := fifo_byteen(RdPtr)
io.dma_mem_write := fifo_write(RdPtr)
io.dma_mem_wdata := fifo_data(RdPtr)
// PMU outputs
io.dma_pmu_dccm_read := io.dma_dccm_req & !io.dma_mem_write;
io.dma_pmu_dccm_write := io.dma_dccm_req & io.dma_mem_write;
io.dma_pmu_any_read := (io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write;
io.dma_pmu_any_write := (io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write;
// Inputs
fifo_full_spec_bus := withClock(dma_bus_clk) {
RegNext(fifo_full_spec, 0.U)
}
dbg_dma_bubble_bus := withClock(dma_bus_clk) {
RegNext(io.dbg_dma_bubble, 0.U)
}
dma_dbg_cmd_done_q := withClock(io.free_clk) {
RegNext(io.dma_dbg_cmd_done, 0.U)
}
// Clock Gating logic
val dma_buffer_c1_clken = (bus_cmd_valid & io.dma_bus_clk_en) | io.dbg_cmd_valid | io.clk_override
val dma_free_clken = (bus_cmd_valid | bus_rsp_valid | io.dbg_cmd_valid | io.dma_dbg_cmd_done | dma_dbg_cmd_done_q | (fifo_valid.orR) | io.clk_override)
val dma_buffer_c1cgc = Module(new rvclkhdr)
dma_buffer_c1cgc.io.en := dma_buffer_c1_clken
dma_buffer_c1cgc.io.scan_mode := io.scan_mode
dma_buffer_c1cgc.io.clk := clock
dma_buffer_c1_clk := dma_buffer_c1cgc.io.l1clk
val dma_free_cgc = Module(new rvclkhdr)
dma_free_cgc.io.en := dma_free_clken
dma_free_cgc.io.scan_mode := io.scan_mode
dma_free_cgc.io.clk := clock
dma_free_clk := dma_free_cgc.io.l1clk
val dma_bus_cgc = Module(new rvclkhdr)
dma_bus_cgc.io.en := io.dma_bus_clk_en
dma_bus_cgc.io.scan_mode := io.scan_mode
dma_bus_cgc.io.clk := clock
dma_bus_clk := dma_bus_cgc.io.l1clk
// Write channel buffer
val wrbuf_en = io.dma_axi_awvalid & io.dma_axi_awready
val wrbuf_data_en = io.dma_axi_wvalid & io.dma_axi_wready
val wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write
val wrbuf_rst = wrbuf_cmd_sent.asBool & !wrbuf_en
val wrbuf_data_rst = wrbuf_cmd_sent.asBool & !wrbuf_data_en
wrbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_en, 1.U, wrbuf_vld) & !wrbuf_rst, 0.U)}
wrbuf_data_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_data_en, 1.U, wrbuf_data_vld) & !wrbuf_data_rst, 0.U)}
val wrbuf_tag = withClock(dma_bus_clk) {
RegEnable(io.dma_axi_awid, 0.U, wrbuf_en)
}
val wrbuf_sz = withClock(dma_bus_clk) {
RegEnable(io.dma_axi_awsize, 0.U, wrbuf_en)
}
val wrbuf_addr = rvdffe(io.dma_axi_awaddr, wrbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
val wrbuf_data = rvdffe(io.dma_axi_wdata, wrbuf_data_en & io.dma_bus_clk_en, clock, io.scan_mode)
val wrbuf_byteen = withClock(dma_bus_clk) {
RegEnable(io.dma_axi_wstrb, 0.U, wrbuf_data_en)
}
// Read channel buffer
val rdbuf_en = io.dma_axi_arvalid & io.dma_axi_arready
val rdbuf_cmd_sent = bus_cmd_sent & !bus_cmd_write
val rdbuf_rst = rdbuf_cmd_sent.asBool & !rdbuf_en
rdbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(rdbuf_en, 1.U, rdbuf_vld) & !rdbuf_rst, 0.U)}
val rdbuf_tag = withClock(dma_bus_clk) {
RegEnable(io.dma_axi_arid, 0.U, rdbuf_en)
}
val rdbuf_sz = withClock(dma_bus_clk) {
RegEnable(io.dma_axi_arsize, 0.U, rdbuf_en)
}
val rdbuf_addr = rvdffe(io.dma_axi_araddr, rdbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
io.dma_axi_awready := ~(wrbuf_vld & !wrbuf_cmd_sent)
io.dma_axi_wready := ~(wrbuf_data_vld & !wrbuf_cmd_sent)
io.dma_axi_arready := ~(rdbuf_vld & !rdbuf_cmd_sent)
//Generate a single request from read/write channel
bus_cmd_valid := (wrbuf_vld & wrbuf_data_vld) | rdbuf_vld
bus_cmd_sent := bus_cmd_valid & dma_fifo_ready.asUInt
bus_cmd_write := axi_mstr_sel
bus_cmd_posted_write := 0.U;
bus_cmd_addr := Mux(axi_mstr_sel.asBool, wrbuf_addr, rdbuf_addr)
bus_cmd_sz := Mux(axi_mstr_sel.asBool, wrbuf_sz, rdbuf_sz)
bus_cmd_wdata := wrbuf_data
bus_cmd_byteen := wrbuf_byteen
bus_cmd_tag := Mux(axi_mstr_sel.asBool, wrbuf_tag, rdbuf_tag)
bus_cmd_mid := 0.U
bus_cmd_prty := 0.U
// Sel=1 -> write has higher priority
axi_mstr_sel := Mux((wrbuf_vld & wrbuf_data_vld & rdbuf_vld) === 1.U, axi_mstr_priority, wrbuf_vld & wrbuf_data_vld)
val axi_mstr_prty_in = ~axi_mstr_priority
val axi_mstr_prty_en = bus_cmd_sent
axi_mstr_priority := withClock(dma_bus_clk) {
RegEnable(axi_mstr_prty_in, 0.U, axi_mstr_prty_en.asBool)
}
val axi_rsp_valid = fifo_valid(RspPtr) & !fifo_dbg(RspPtr) & fifo_done_bus(RspPtr)
val axi_rsp_rdata = fifo_data(RspPtr)
val axi_rsp_write = fifo_write(RspPtr)
val axi_rsp_error = Mux(fifo_error(RspPtr)(0), 2.U, Mux(fifo_error(RspPtr)(1), 3.U, 0.U));
val axi_rsp_tag = fifo_tag(RspPtr)
// AXI response channel signals
io.dma_axi_bvalid := axi_rsp_valid & axi_rsp_write
io.dma_axi_bresp := axi_rsp_error(1,0)
io.dma_axi_bid := axi_rsp_tag
io.dma_axi_rvalid := axi_rsp_valid & !axi_rsp_write
io.dma_axi_rresp := axi_rsp_error
io.dma_axi_rdata := axi_rsp_rdata(63,0)
io.dma_axi_rlast := 1.U
io.dma_axi_rid := axi_rsp_tag
bus_posted_write_done := 0.U
bus_rsp_valid := (io.dma_axi_bvalid | io.dma_axi_rvalid)
bus_rsp_sent := ((io.dma_axi_bvalid & io.dma_axi_bready) | (io.dma_axi_rvalid & io.dma_axi_rready))
}
object dma extends App{
chisel3.Driver.emitVerilog(new el2_dma_ctrl)
}

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src/main/scala/el2_pic_ctl.scala Normal file
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import chisel3._
import chisel3.util._
import include._
import lib._
import chisel3.experimental.chiselName
@chiselName
class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib {
val io = IO (new Bundle {
val scan_mode = Input(Bool())
val free_clk = Input(Clock () )
val active_clk = Input(Clock () )
val clk_override = Input(Bool () )
val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W))
val picm_rdaddr = Input(UInt(32.W))
val picm_wraddr = Input(UInt(32.W))
val picm_wr_data = Input(UInt(32.W))
val picm_wren = Input(Bool())
val picm_rden = Input(Bool())
val picm_mken = Input(Bool())
val meicurpl = Input(UInt(4.W))
val meipt = Input(UInt(4.W))
val mexintpend = Output(Bool())
val claimid = Output(UInt(8.W))
val pl = Output(UInt(4.W))
val picm_rd_data = Output(UInt(32.W))
val mhwakeup = Output(Bool())
//val level_intpend_w_prior_en = Output(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(INTPRIORITY_BITS.W))))
})
//def el2_cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) =
// (Mux(a_priority<b_priority, b_id, a_id), Mux(a_priority<b_priority, b_priority, a_priority))
def el2_cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) = {
val out_id = WireInit(UInt(ID_BITS.W),init= 0.U)
val out_priority = WireInit(UInt(INTPRIORITY_BITS.W),init= 0.U)
out_id := Mux(a_priority<b_priority, b_id, a_id)
out_priority := Mux(a_priority<b_priority, b_priority, a_priority)
(out_id,out_priority)
}
def el2_configurable_gw (extintsrc_req_sync : UInt, meigwctrl_polarity : UInt, meigwctrl_type : UInt, meigwclr : UInt) = {
val gw_int_pending = WireInit(UInt(1.W),0.U)
val gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & !meigwclr)
gw_int_pending := RegNext(gw_int_pending_in,0.U)
Mux(meigwctrl_type.asBool(), ((extintsrc_req_sync ^ meigwctrl_polarity) | gw_int_pending), (extintsrc_req_sync ^ meigwctrl_polarity))
}
// io.mexintpend := 0.U
// io.claimid := 0.U
// io.pl := 0.U
//io.picm_rd_data := 0.U
//io.mhwakeup := 0.U
val NUM_LEVELS = log2Ceil(PIC_TOTAL_INT_PLUS1)
val INTPRIORITY_BASE_ADDR = aslong(PIC_BASE_ADDR)
val INTPEND_BASE_ADDR = aslong(PIC_BASE_ADDR + 0x00001000)
val INTENABLE_BASE_ADDR = aslong(PIC_BASE_ADDR + 0x00002000)
val EXT_INTR_PIC_CONFIG = aslong(PIC_BASE_ADDR + 0x00003000)
val EXT_INTR_GW_CONFIG = aslong(PIC_BASE_ADDR + 0x00004000)
val EXT_INTR_GW_CLEAR = aslong(PIC_BASE_ADDR + 0x00005000)
val INTPEND_SIZE = PIC_TOTAL_INT_PLUS1 match {
case x if x < 32 => 32
case x if x < 64 => 64
case x if x < 128 => 128
case x if x < 256 => 256
case x if x < 512 => 512
case _ => 1024
}
val INT_GRPS = INTPEND_SIZE / 32
val INTPRIORITY_BITS = 4
val ID_BITS = 8
val GW_CONFIG = WireInit(UInt(PIC_TOTAL_INT_PLUS1.W), init=0.U)
val intpend_rd_out = WireInit(0.U(32.W))
val intenable_rd_out = WireInit(0.U(1.W))
val intpriority_reg_inv = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))
val intpend_reg_extended = WireInit(0.U (INTPEND_SIZE.W))
val selected_int_priority = WireInit(0.U (INTPRIORITY_BITS.W))
val intpend_w_prior_en = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))///////////////////
val intpend_id = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(ID_BITS.W)))
val levelx_intpend_w_prior_en = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2,UInt(INTPRIORITY_BITS.W))))
for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_w_prior_en(i)(j) := 0.U
val levelx_intpend_id = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2,UInt(ID_BITS.W))))
for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_id(i)(j) := 0.U
val l2_intpend_w_prior_en_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt,UInt(INTPRIORITY_BITS.W)))
for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)) l2_intpend_w_prior_en_ff(i) := 0.U
val l2_intpend_id_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt,UInt(ID_BITS.W)))
for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)) l2_intpend_id_ff(i) := 0.U
val config_reg = WireInit(0.U(1.W))
val intpriord = WireInit(0.U(1.W))
val prithresh_reg_write = WireInit(0.U(1.W))
val prithresh_reg_read = WireInit(0.U(1.W))
val picm_wren_ff = WireInit(0.U(1.W))
val picm_rden_ff = WireInit(0.U(1.W))
val picm_raddr_ff = WireInit(0.U(32.W))
val picm_waddr_ff = WireInit(0.U(32.W))
val picm_wr_data_ff = WireInit(0.U(32.W))
val mask = WireInit(0.U(4.W))
val picm_mken_ff = WireInit(0.U(1.W))
val claimid_in = WireInit(0.U(ID_BITS.W))
//val extintsrc_req_gw = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(1.W)))
// clocks
val pic_raddr_c1_clk = Wire(Clock())
val pic_data_c1_clk = Wire(Clock())
val pic_pri_c1_clk = Wire(Clock())
val pic_int_c1_clk = Wire(Clock())
val gw_config_c1_clk = Wire(Clock())
withClock(pic_raddr_c1_clk) {picm_raddr_ff := RegNext(io.picm_rdaddr,0.U)}
withClock(pic_data_c1_clk) {picm_waddr_ff := RegNext (io.picm_wraddr,0.U)}
withClock(io.active_clk) {picm_wren_ff := RegNext(io.picm_wren,0.U)}
withClock(io.active_clk) {picm_rden_ff := RegNext(io.picm_rden,0.U)}
withClock(io.active_clk) {picm_mken_ff := RegNext(io.picm_mken,0.U)}
withClock(pic_data_c1_clk) {picm_wr_data_ff := RegNext(io.picm_wr_data,0.U)}
val temp_raddr_intenable_base_match = ~(picm_raddr_ff ^ INTENABLE_BASE_ADDR.asUInt)
val raddr_intenable_base_match = temp_raddr_intenable_base_match(31,NUM_LEVELS+2).andR//// (31,NUM_LEVELS+2)
val raddr_intpriority_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (INTPRIORITY_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
val raddr_config_gw_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CONFIG>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
val raddr_config_pic_match = picm_raddr_ff(31,0) === (EXT_INTR_PIC_CONFIG).asUInt //(31,0)
val addr_intpend_base_match = picm_raddr_ff(31,6) === (INTPEND_BASE_ADDR>>6).asUInt
val waddr_config_pic_match = picm_waddr_ff(31,0) === (EXT_INTR_PIC_CONFIG).asUInt //(31,0)
val addr_clear_gw_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CLEAR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
val waddr_intpriority_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (INTPRIORITY_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
val waddr_intenable_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (INTENABLE_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
val waddr_config_gw_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CONFIG>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
val picm_bypass_ff = picm_rden_ff & picm_wren_ff & ( picm_raddr_ff === picm_waddr_ff)
// ---- Clock gating section ------
// c1 clock enables
val pic_raddr_c1_clken = io.picm_mken | io.picm_rden | io.clk_override
val pic_data_c1_clken = io.picm_wren | io.clk_override
val pic_pri_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intpriority_base_match & picm_rden_ff) | io.clk_override
val pic_int_c1_clken = (waddr_intenable_base_match & picm_wren_ff) | (raddr_intenable_base_match & picm_rden_ff) | io.clk_override
val gw_config_c1_clken = (waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff) | io.clk_override
// C1 - 1 clock pulse for data
pic_raddr_c1_clk := rvclkhdr(clock,pic_raddr_c1_clken,io.scan_mode)
pic_data_c1_clk := rvclkhdr(clock,pic_data_c1_clken,io.scan_mode)
pic_pri_c1_clk := rvclkhdr(clock,pic_pri_c1_clken.asBool,io.scan_mode)
pic_int_c1_clk := rvclkhdr(clock,pic_int_c1_clken.asBool,io.scan_mode)
gw_config_c1_clk := rvclkhdr(clock,gw_config_c1_clken.asBool,io.scan_mode)
// ------ end clock gating section ------------------------
val extintsrc_req_sync = Cat(rvsyncss(io.extintsrc_req(PIC_TOTAL_INT_PLUS1-1,1),io.free_clk),io.extintsrc_req(0))
val intpriority_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){waddr_intpriority_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U)
val intpriority_reg_re = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){raddr_intpriority_base_match & (picm_raddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_rden_ff} else 0.U)
val intenable_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){waddr_intenable_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U)
val intenable_reg_re = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){raddr_intenable_base_match & (picm_raddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_rden_ff} else 0.U)
val gw_config_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){waddr_config_gw_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U)
val gw_config_reg_re = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){raddr_config_gw_base_match & (picm_raddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_rden_ff} else 0.U)
val gw_clear_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){addr_clear_gw_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U)
val intpriority_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))
(0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){ intpriority_reg(i) := withClock(pic_pri_c1_clk){RegEnable(picm_wr_data_ff(INTPRIORITY_BITS-1,0),0.U,intpriority_reg_we(i).asBool)}} else intpriority_reg(i) := 0.U(INTPRIORITY_BITS.W))
val intenable_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(1.W)))
(0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){intenable_reg(i) := withClock(pic_int_c1_clk){RegEnable(picm_wr_data_ff(0),0.U,intenable_reg_we(i).asBool)}} else intenable_reg(i) := 0.U(1.W))
val gw_config_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(2.W)))
(0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){ gw_config_reg(i) := withClock(gw_config_c1_clk){RegEnable(picm_wr_data_ff(1,0),0.U,gw_config_reg_we(i).asBool)}} else gw_config_reg(i) := 0.U(2.W))
val extintsrc_req_gw = (0 until PIC_TOTAL_INT_PLUS1).map(i=>if(i>0)
el2_configurable_gw(extintsrc_req_sync(i), gw_config_reg(i)(0), gw_config_reg(i)(1), gw_clear_reg_we(i).asBool())
else 0.U)
//val intpriord = WireInit(Bool(), false.B)
(0 until PIC_TOTAL_INT_PLUS1).map(i=> intpriority_reg_inv(i) := Mux(intpriord.asBool, ~intpriority_reg(i), intpriority_reg(i)))
(0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i) := Fill(INTPRIORITY_BITS, extintsrc_req_gw(i) & intenable_reg(i)) & intpriority_reg_inv(i))
(0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i) := i.U)
if (PIC_2CYCLE == 1) {
val level_intpend_w_prior_en = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(INTPRIORITY_BITS.W)))) //PIC_TOTAL_INT_PLUS1+3 should be there
val level_intpend_id = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(ID_BITS.W)))) //PIC_TOTAL_INT_PLUS1+3 should be there
for(i<-0 until (NUM_LEVELS/2)+1; j<-0 until PIC_TOTAL_INT_PLUS1+3){ //PIC_TOTAL_INT_PLUS1+3 should be there
level_intpend_w_prior_en(i)(j) := 0.U
level_intpend_id(i)(j) := 0.U
}
level_intpend_w_prior_en(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i)) ++ IndexedSeq(0.U(4.W), 0.U(4.W), 0.U(4.W))
level_intpend_id(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i)) ++ IndexedSeq(0.U(8.W), 0.U(8.W), 0.U(8.W))
levelx_intpend_w_prior_en(NUM_LEVELS/2) := (0 until (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_w_prior_en_ff(i)) ++ IndexedSeq(0.U(INTPRIORITY_BITS.W))
levelx_intpend_id(NUM_LEVELS/2) := (0 until (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_id_ff(i)) ++ IndexedSeq(1.U(ID_BITS.W))
/// Do the prioritization of the interrupts here ////////////
for (l <-0 until NUM_LEVELS/2 ; m <- 0 to ((PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(l+1)).toInt)) {
if ( m == (PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(l+1)).toInt) {
level_intpend_w_prior_en(l+1)(m+1) := 0.U
level_intpend_id(l+1)(m+1) := 0.U
}else { val a = 0.U}
val (out_id, out_priority) = el2_cmp_and_mux(level_intpend_id(l)(2*m), level_intpend_w_prior_en(l)(2*m), level_intpend_id(l)((2*m)+1), level_intpend_w_prior_en(l)((2*m)+1))
level_intpend_id(l+1)(m) := out_id
level_intpend_w_prior_en(l+1)(m) := out_priority
}
(0 to PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt).map(i => l2_intpend_w_prior_en_ff(i) := withClock(io.free_clk){RegNext(level_intpend_w_prior_en(NUM_LEVELS/2)(i))})
(0 to PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt).map(i => l2_intpend_id_ff(i) := withClock(io.free_clk){RegNext(level_intpend_id(NUM_LEVELS/2)(i))})
for (j <-NUM_LEVELS/2 until NUM_LEVELS ; k <- 0 to ((PIC_TOTAL_INT_PLUS1)/math.pow(2,(j+1)).toInt)) {
if ( k == (PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(j+1)).toInt) {
levelx_intpend_w_prior_en(j + 1)(k + 1) := 0.U
levelx_intpend_id(j + 1)(k + 1) := 0.U
}else { val a = 0.U}
val (out_id1, out_priority1) = el2_cmp_and_mux(level_intpend_id(j)(2*k), level_intpend_w_prior_en(j)(2*k), level_intpend_id(j)(2*k+1), level_intpend_w_prior_en(j)(2*k+1))
(levelx_intpend_id(j+1)(k)) := out_id1
(levelx_intpend_w_prior_en(j+1)(k)) := out_priority1
}
claimid_in := levelx_intpend_id(NUM_LEVELS - NUM_LEVELS/2)(0) // This is the last level output
selected_int_priority := levelx_intpend_w_prior_en(NUM_LEVELS - NUM_LEVELS/2)(0)
}
else {
val level_intpend_w_prior_en = Wire(Vec((NUM_LEVELS)+1, Vec(PIC_TOTAL_INT_PLUS1+2, UInt(INTPRIORITY_BITS.W))))
val level_intpend_id = Wire(Vec((NUM_LEVELS)+1, Vec(PIC_TOTAL_INT_PLUS1+2, UInt(ID_BITS.W))))
dontTouch(level_intpend_id)
for(i<-0 until (NUM_LEVELS)+1; j<-0 until PIC_TOTAL_INT_PLUS1+2){
level_intpend_w_prior_en(i)(j) := 0.U
level_intpend_id(i)(j) := 0.U
}
level_intpend_w_prior_en(0) := Range(0,PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i)) ++ IndexedSeq(Fill(INTPRIORITY_BITS,0.U),Fill(INTPRIORITY_BITS,0.U))
level_intpend_id(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i)) ++ IndexedSeq(Fill(ID_BITS,1.U),Fill(ID_BITS,1.U)) /*Cat((1.U((1*ID_BITS).W)),*///l2_intpend_id_ff//)
dontTouch(level_intpend_w_prior_en(0))
/// Do the prioritization of the interrupts here ////////////
for (l <-0 until NUM_LEVELS ) {
for (m <- 0 to ((PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,l+1)).toInt) {
if ( m == (PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,l+1).toInt) {
level_intpend_w_prior_en(l+1)(m+1) := 0.U
level_intpend_id(l+1)(m+1) := 0.U
}else { val a = 0.U}
val (out_id, out_priority) = el2_cmp_and_mux(level_intpend_id(l)(2*m), level_intpend_w_prior_en(l)(2*m), level_intpend_id(l)(2*m+1), level_intpend_w_prior_en(l)(2*m+1))
level_intpend_id(l+1)(m) := out_id
level_intpend_w_prior_en(l+1)(m) := out_priority
dontTouch(level_intpend_id(l)(2*m))
}}
claimid_in := level_intpend_id(NUM_LEVELS)(0) // This is the last level output
selected_int_priority := level_intpend_w_prior_en(NUM_LEVELS)(0)
dontTouch(selected_int_priority)
}
// io.level_intpend_w_prior_en := (0 to NUM_LEVELS).map(i=>(0 to PIC_TOTAL_INT_PLUS1+1).map(j=>
// level_intpend_w_prior_en(i)(j)).reverse.reduce(Cat(_,_))).reverse.reduce(Cat(_,_))
///////////////////////////////////////////////////////////////////////
// Config Reg`
///////////////////////////////////////////////////////////////////////
val config_reg_we = waddr_config_pic_match & picm_wren_ff
val config_reg_re = raddr_config_pic_match & picm_rden_ff
val config_reg_in = picm_wr_data_ff(0)
withClock(io.free_clk){config_reg := RegEnable(config_reg_in,0.U,config_reg_we.asBool)}
intpriord := config_reg
val pl_in = selected_int_priority
///////////////////////////////////////////////////////////
/// ClaimId Reg and Corresponding PL
///////////////////////////////////////////////////////////
val pl_in_q = Mux(intpriord.asBool,~pl_in,pl_in).asUInt
withClock(io.free_clk){io.claimid := RegNext(claimid_in,0.U)}
withClock(io.free_clk){io.pl := RegNext(pl_in_q,0.U)}
val meipt_inv = Mux(intpriord.asBool,~io.meipt,io.meipt)
val meicurpl_inv = Mux(intpriord.asBool,~io.meicurpl,io.meicurpl)
val mexintpend_in = ( selected_int_priority > meipt_inv) & ( selected_int_priority > meicurpl_inv)
io.mexintpend := withClock(io.free_clk){RegNext(mexintpend_in,0.U)}
val maxint = Mux(intpriord.asBool,0.U,15.U)
val mhwakeup_in = pl_in_q === maxint
io.mhwakeup := withClock(io.free_clk){RegNext(mhwakeup_in,0.U)}
//////////////////////////////////////////////////////////////////////////
// Reads of register.
// 1- intpending
//////////////////////////////////////////////////////////////////////////
val intpend_reg_read = addr_intpend_base_match & picm_rden_ff
val intpriority_reg_read = raddr_intpriority_base_match & picm_rden_ff
val intenable_reg_read = raddr_intenable_base_match & picm_rden_ff
val gw_config_reg_read = raddr_config_gw_base_match & picm_rden_ff
intpend_reg_extended := Cat(Fill(INTPEND_SIZE-PIC_TOTAL_INT_PLUS1,0.U),(0 until PIC_TOTAL_INT_PLUS1/*extintsrc_req_gw.size*/).map(i => extintsrc_req_gw(i)).reverse.reduce(Cat(_,_)))
val intpend_rd_part_out = Wire(Vec(INT_GRPS,UInt(32.W)))
(0 until INT_GRPS).map (i=> intpend_rd_part_out(i) := Fill(32,(intpend_reg_read & picm_raddr_ff(5,2)) === i.asUInt) & intpend_reg_extended((32*i)+31,32*i))//.reverse.reduce(Cat(_,_))
intpend_rd_out := (0 until INT_GRPS).map (i=>intpend_rd_part_out(i)).reduce (_|_)
for(i <- 0 until PIC_TOTAL_INT_PLUS1) { when (intenable_reg_re(i).asBool){ intenable_rd_out := intenable_reg(i)}.otherwise {intenable_rd_out :=0.U} }
val intpriority_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> intpriority_reg_re(i).asBool -> intpriority_reg(i)))
val gw_config_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> gw_config_reg_re(i).asBool -> gw_config_reg(i)))
//////////////////////////////////////////////////////////////////////////////////////////////////
val picm_rd_data_in = WireInit(UInt(32.W),0.U)
picm_rd_data_in := Mux1H(Seq(
intpend_reg_read.asBool -> intpend_rd_out,
intpriority_reg_read.asBool -> Cat(Fill(32-INTPRIORITY_BITS,0.U),intpriority_rd_out ) ,
intenable_reg_read.asBool -> Cat(Fill(31,0.U),intenable_rd_out),
gw_config_reg_read.asBool -> Cat(Fill(30,0.U),gw_config_rd_out) ,
config_reg_re.asBool -> Cat(Fill(31,0.U),config_reg) ,
(picm_mken_ff & mask(3)).asBool -> Cat(Fill(30,0.U) , "b11".U(2.W)) ,
(picm_mken_ff & mask(2)).asBool -> Cat(Fill(31,0.U) , "b1".U(1.W)),
(picm_mken_ff & mask(1)).asBool -> Cat(Fill(28,0.U) , "b1111".U(4.W)) ,
(picm_mken_ff & mask(0)).asBool -> Fill(32,0.U) ))
io.picm_rd_data := Mux(picm_bypass_ff.asBool, picm_wr_data_ff, picm_rd_data_in)
val address = picm_raddr_ff(14,0)
mask := 1.U(4.W)
switch (address) {
is ("b011000000000000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b100000000000100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000001000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000001100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000010000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000010100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000011000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000011100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000100000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000100100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000101000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000101100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000110000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000110100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000111000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000000111100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001000000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001000100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001001000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001001100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001010000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001010100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001011000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001011100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001100000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001100100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001101000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001101100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001110000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001110100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001111000".U(15.W)) {mask := "b1000".U(4.W)}
is ("b100000001111100".U(15.W)) {mask := "b1000".U(4.W)}
is ("b010000000000100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000001000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000001100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000010000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000010100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000011000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000011100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000100000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000100100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000101000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000101100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000110000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000110100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000111000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000000111100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001000000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001000100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001001000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001001100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001010000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001010100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001011000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001011100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001100000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001100100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001101000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001101100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001110000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001110100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001111000".U(15.W)) {mask := "b0100".U(4.W)}
is ("b010000001111100".U(15.W)) {mask := "b0100".U(4.W)}
is ("b000000000000100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000001000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000001100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000010000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000010100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000011000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000011100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000100000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000100100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000101000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000101100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000110000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000110100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000111000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000000111100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001000000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001000100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001001000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001001100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001010000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001010100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001011000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001011100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001100000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001100100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001101000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001101100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001110000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001110100".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001111000".U(15.W)) {mask := "b0010".U(4.W)}
is ("b000000001111100".U(15.W)) {mask := "b0010".U(4.W)}
}
}
object pic_main extends App{
println("Generating Verilog...")
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_pic_ctrl()))
}

271
src/main/scala/el2_pic_ctrl.scala
View File

@ -1,271 +0,0 @@
//import chisel3._
//import chisel3.util._
//import include._
//import lib._
//import snapshot._
//
//class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib {
// val io = IO (new Bundle {
// val scan_mode = Input(Bool())
// val free_clk = Input(Clock () )
// val active_clk = Input(Clock () )
// val clk_override = Input(Bool () )
// val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W))
// val picm_rdaddr = Input(UInt(32.W))
// val picm_wraddr = Input(UInt(32.W))
// val picm_wr_data = Input(UInt(32.W))
// val picm_wren = Input(Bool())
// val picm_rden = Input(Bool())
// val picm_mken = Input(Bool())
// val meicurpl = Input(UInt(4.W))
// val meipt = Input(UInt(4.W))
//
// val mexintpend = Output(Bool())
// val claimid = Output(UInt(8.W))
// val pl = Output(UInt(4.W))
// val picm_rd_data = Output(UInt(32.W))
// val mhwakeup = Output(Bool())
// val test = Output(UInt())
// })
//
// io.mexintpend := 0.U
// io.claimid := 0.U
// io.pl := 0.U
// io.picm_rd_data := 0.U
// io.mhwakeup := 0.U
//
// val NUM_LEVELS = log2Ceil(PIC_TOTAL_INT_PLUS1)
// val INTPRIORITY_BASE_ADDR = PIC_BASE_ADDR
// val INTPEND_BASE_ADDR = PIC_BASE_ADDR + 0x00001000L
// val INTENABLE_BASE_ADDR = PIC_BASE_ADDR + 0x00002000L
// val EXT_INTR_PIC_CONFIG = PIC_BASE_ADDR + 0x00003000L
// val EXT_INTR_GW_CONFIG = PIC_BASE_ADDR + 0x00004000L
// val EXT_INTR_GW_CLEAR = PIC_BASE_ADDR + 0x00005000L
//
// val INTPEND_SIZE = PIC_TOTAL_INT_PLUS1 match {
// case x if x < 32 => 32
// case x if x < 64 => 64
// case x if x < 128 => 128
// case x if x < 256 => 256
// case x if x < 512 => 512
// case _ => 1024
//
// }
//
// val INT_GRPS = INTPEND_SIZE / 32
// val INTPRIORITY_BITS = 4
// val ID_BITS = 8
// val GW_CONFIG = WireInit(UInt(PIC_TOTAL_INT_PLUS1.W), init=0.U)
//
// // val addr_intpend_base_match = WireInit(0.U(1.W))
// // val raddr_config_pic_match = WireInit(0.U(1.W))
// // val raddr_intenable_base_match = WireInit(0.U(1.W))
//// val raddr_intpriority_base_match = WireInit(0.U(1.W))
// // val raddr_config_gw_base_match = WireInit(0.U(1.W))
// // val waddr_config_pic_match = WireInit(0.U(1.W))
// // val waddr_intpriority_base_match = WireInit(0.U(1.W))
// // val waddr_intenable_base_match = WireInit(0.U(1.W))
// // val waddr_config_gw_base_match = WireInit(0.U(1.W))
// // val addr_clear_gw_base_match = WireInit(0.U(1.W))
//// val mexintpend_in = WireInit(0.U(1.W))
// // val mhwakeup_in = WireInit(0.U(1.W))
// // val intpend_reg_read = WireInit(0.U(1.W))
// val picm_rd_data_in = WireInit(0.U(32.W))
// val intpend_rd_out = WireInit(0.U(32.W))
//// val intenable_rd_out = WireInit(0.U(1.W))
// val intpriority_rd_out = WireInit(0.U (INTPRIORITY_BITS.W))
// val gw_config_rd_out = WireInit(0.U(2.W))
// val intpriority_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))
// intpriority_reg := (0 until PIC_TOTAL_INT_PLUS1).map(i => 0.U)
// // val intpriority_reg_inv = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))
// // intpriority_reg_inv := (0 until PIC_TOTAL_INT_PLUS1).map(i => 0.U)
// val intpriority_reg_we = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
// val intpriority_reg_re = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
// val gw_config_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(2.W)))
// val intenable_reg = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
// val intenable_reg_we = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
// val intenable_reg_re = WireInit(Bool(), init = false.B)
// val gw_config_reg_we = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
// val gw_config_reg_re = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
// val gw_clear_reg_we = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W))
// //
// val intpend_reg_extended = WireInit(0.U (INTPEND_SIZE.W))
//// val maxint = WireInit(0.U (INTPRIORITY_BITS.W))
// val selected_int_priority = WireInit(0.U (INTPRIORITY_BITS.W))
//// val intpend_w_prior_en = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))
//// val intpend_id = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(ID_BITS.W)))
// //val intpend_rd_part_out = Wire(Vec(INT_GRPS,UInt(32.W)))
// // val levelx_intpend_w_prior_en = Wire(Vec(NUM_LEVELS - NUM_LEVELS/2 ,Vec ((PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int])+1,UInt(INTPRIORITY_BITS.W))))
//// val levelx_intpend_id = Wire(Vec(NUM_LEVELS - NUM_LEVELS/2 ,Vec ((PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int])+1,UInt(ID_BITS.W))))
//// val l2_intpend_w_prior_en_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int],UInt(INTPRIORITY_BITS.W)))
// // val l2_intpend_id_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int],UInt(ID_BITS.W)))
// val config_reg = WireInit(0.U(1.W))
//// val intpriord = WireInit(0.U(1.W))
//// val config_reg_we = WireInit(0.U(1.W))
//// val config_reg_re = WireInit(0.U(1.W))
//// val config_reg_in = WireInit(0.U(1.W))
// val prithresh_reg_write = WireInit(0.U(1.W))
// val prithresh_reg_read = WireInit(0.U(1.W))
// // val intpriority_reg_read = WireInit(0.U(1.W))
// //val intenable_reg_read = WireInit(0.U(1.W))
// //val gw_config_reg_read = WireInit(0.U(1.W))
// val picm_wren_ff = WireInit(0.U(1.W))
// val picm_rden_ff = WireInit(0.U(1.W))
// val picm_raddr_ff = WireInit(0.U(32.W))
// val picm_waddr_ff = WireInit(0.U(32.W))
// val picm_wr_data_ff = WireInit(0.U(32.W))
// val mask = WireInit(0.U(4.W))
// val picm_mken_ff = WireInit(0.U(1.W))
// val claimid_in = WireInit(0.U(ID_BITS.W))
// val pl_in = WireInit(0.U(INTPRIORITY_BITS.W))
// // val pl_in_q = WireInit(0.U(INTPRIORITY_BITS.W))
// val extintsrc_req_sync = WireInit(0.U(PIC_TOTAL_INT_PLUS1.W))
// val extintsrc_req_gw = WireInit(0.U(PIC_TOTAL_INT_PLUS1.W))
// // val picm_bypass_ff = WireInit(0.U(1.W))
//
// // clocks
// val pic_raddr_c1_clk = Wire(Clock())
// val pic_data_c1_clk = Wire(Clock())
// val pic_pri_c1_clk = Wire(Clock())
// val pic_int_c1_clk = Wire(Clock())
// val gw_config_c1_clk = Wire(Clock())
//
// withClock(pic_raddr_c1_clk) {picm_raddr_ff := RegNext(io.picm_rdaddr,0.U)}
// withClock(pic_data_c1_clk) {picm_waddr_ff := RegNext (io.picm_wraddr,0.U)}
// withClock(io.active_clk) {picm_wren_ff := RegNext(io.picm_wren,0.U)}
// withClock(io.active_clk) {picm_rden_ff := RegNext(io.picm_rden,0.U)}
// withClock(io.active_clk) {picm_mken_ff := RegNext(io.picm_mken,0.U)}
// withClock(pic_data_c1_clk) {picm_wr_data_ff := RegNext(io.picm_wr_data,0.U)}
//
// val raddr_intenable_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (INTENABLE_BASE_ADDR >>(NUM_LEVELS+2)).asUInt//// (31,NUM_LEVELS+2)
// val raddr_intpriority_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (INTPRIORITY_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
// val raddr_config_gw_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CONFIG>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
// val raddr_config_pic_match = picm_raddr_ff(31,0) === (EXT_INTR_PIC_CONFIG).asUInt //(31,0)
// val addr_intpend_base_match = picm_raddr_ff(31,6) === (INTPEND_BASE_ADDR>>6).asUInt
//
// val waddr_config_pic_match = picm_waddr_ff(31,0) === (EXT_INTR_PIC_CONFIG).asUInt //(31,0)
// val addr_clear_gw_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CLEAR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
// val waddr_intpriority_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (INTPRIORITY_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
// val waddr_intenable_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (INTENABLE_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
// val waddr_config_gw_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CONFIG>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
// val picm_bypass_ff = picm_rden_ff & picm_wren_ff & ( picm_raddr_ff === picm_waddr_ff)
//
// // ---- Clock gating section ------
// // c1 clock enables
// val pic_raddr_c1_clken = io.picm_mken | io.picm_rden | io.clk_override
// val pic_data_c1_clken = io.picm_wren | io.clk_override
// val pic_pri_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intpriority_base_match & picm_rden_ff) | io.clk_override
// val pic_int_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intenable_base_match & picm_rden_ff) | io.clk_override
// val gw_config_c1_clken = (waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff) | io.clk_override
//
// // C1 - 1 clock pulse for data
// val pic_addr_c1_cgc = Module(new rvclkhdr)
// pic_addr_c1_cgc.io.en := pic_raddr_c1_clken ; pic_raddr_c1_clk := pic_addr_c1_cgc.io.l1clk
// pic_addr_c1_cgc.io.clk := clock ; pic_addr_c1_cgc.io.scan_mode := io.scan_mode
//
// val pic_data_c1_cgc = Module(new rvclkhdr)
// pic_data_c1_cgc.io.en := pic_data_c1_clken ; pic_data_c1_clk := pic_data_c1_cgc.io.l1clk
// pic_data_c1_cgc.io.clk := clock ; pic_data_c1_cgc.io.scan_mode := io.scan_mode
//
// val pic_pri_c1_cgc = Module(new rvclkhdr)
// pic_pri_c1_cgc.io.en := pic_pri_c1_clken ; pic_pri_c1_clk := pic_pri_c1_cgc.io.l1clk
// pic_pri_c1_cgc.io.clk := clock ; pic_pri_c1_cgc.io.scan_mode := io.scan_mode
//
// val pic_int_c1_cgc = Module(new rvclkhdr)
// pic_int_c1_cgc.io.en := pic_int_c1_clken ; pic_int_c1_clk := pic_int_c1_cgc.io.l1clk
// pic_int_c1_cgc.io.clk := clock ; pic_int_c1_cgc.io.scan_mode := io.scan_mode
//
// val gw_config_c1_cgc = Module(new rvclkhdr)
// gw_config_c1_cgc.io.en := gw_config_c1_clken ; gw_config_c1_clk := gw_config_c1_cgc.io.l1clk
// gw_config_c1_cgc.io.clk := clock ; gw_config_c1_cgc.io.scan_mode := io.scan_mode
//
// // ------ end clock gating section ------------------------
//
//
// val sync_inst = Module(new rvsyncss(PIC_TOTAL_INT_PLUS1-1))
// sync_inst.io.din := io.extintsrc_req>>1
// extintsrc_req_sync := Cat(sync_inst.io.dout, io.extintsrc_req(0))
// sync_inst.io.clk := io.free_clk
//
// io.test := extintsrc_req_sync
// ///////////////////////////////////////////////////////////////////////
// // Config Reg`
// ///////////////////////////////////////////////////////////////////////
//
// val config_reg_we = waddr_config_pic_match & picm_wren_ff
// val config_reg_re = raddr_config_pic_match & picm_rden_ff
// val config_reg_in = picm_wr_data_ff(0)
// withClock(io.free_clk){config_reg := RegEnable(config_reg_in,0.U,config_reg_we.asBool)}
// val intpriord = config_reg
//
//// ///////////////////////////////////////////////////////////
//// /// ClaimId Reg and Corresponding PL
//// ///////////////////////////////////////////////////////////
//// val pl_in_q = Mux(intpriord.asBool,~pl_in,pl_in).asUInt
//// withClock(io.free_clk){io.claimid := RegNext(claimid_in,0.U)}
//// withClock(io.free_clk){io.pl := RegNext(pl_in_q,0.U)}
//// val meipt_inv = Mux(intpriord.asBool,!io.meipt,io.meipt)
//// val meicurpl_inv = Mux(intpriord.asBool,!io.meicurpl,io.meicurpl)
//// val mexintpend_in = ( selected_int_priority > meipt_inv) & ( selected_int_priority > meicurpl_inv)
//// withClock(io.free_clk){io.mexintpend := RegNext(mexintpend_in,0.U)}
//// val maxint = Mux(intpriord.asBool,0.U,15.U)
//// val mhwakeup_in = pl_in_q === maxint
//// withClock(io.free_clk){io.mhwakeup := RegNext(mhwakeup_in,0.U)}
////
//// //////////////////////////////////////////////////////////////////////////
//// // Reads of register.
//// // 1- intpending
//// //////////////////////////////////////////////////////////////////////////
//// val intpend_reg_read = addr_intpend_base_match & picm_rden_ff
//// val intpriority_reg_read = raddr_intpriority_base_match & picm_rden_ff
//// val intenable_reg_read = raddr_intenable_base_match & picm_rden_ff
//// val gw_config_reg_read = raddr_config_gw_base_match & picm_rden_ff
////
////// val intpend_reg_extended = Cat(INTPEND_SIZE - PIC_TOTAL_INT_PLUS1 , extintsrc_req_gw)
////// assign intpend_reg_extended[INTPEND_SIZE-1:0] = {{INTPEND_SIZE-pt.PIC_TOTAL_INT_PLUS1{1'b0}},extintsrc_req_gw[pt.PIC_TOTAL_INT_PLUS1-1:0]} ;
////
//// val intpend_rd_part_out = (0 until INT_GRPS).map (i=> Fill(32,intpend_reg_read & picm_raddr_ff(5,2) === i.asUInt) & intpend_reg_extended((32*i)+31,32*i)).reverse.reduce(Cat(_,_))
//// intpend_rd_out := VecInit.tabulate(INT_GRPS)(i=>intpend_rd_part_out(i)).reverse.reduce (_|_)
//// val intenable_rd_out = (0 until PIC_TOTAL_INT_PLUS1).map (i=> if (intenable_reg_re(i)) intenable_reg(i) else 0.U)
//// val intpriority_rd_out = (0 until PIC_TOTAL_INT_PLUS1).map (i=> if (intpriority_reg_re(i)) intpriority_reg(i) else 0.U)
//// val gw_config_rd_out = (0 until PIC_TOTAL_INT_PLUS1).map (i=> if (gw_config_reg_re(i)) gw_config_reg(i) else 0.U)
//// //////////////////////////////////////////////////////////////////////////////////////////////////
//// /*
////
//// for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
//// if (intenable_reg_re[i]) begin
//// intenable_rd_out = intenable_reg[i] ;
//// end
//// if (intpriority_reg_re[i]) begin
//// intpriority_rd_out = intpriority_reg[i] ;
//// end
//// if (gw_config_reg_re[i]) begin
//// gw_config_rd_out = gw_config_reg[i] ;
//// end
//// end
//// end
////
////
////
//// always_comb begin : INTPEND_RD
//// intpend_rd_out = '0 ;
//// for (int i=0; i<INT_GRPS; i++) begin
//// intpend_rd_out |= intpend_rd_part_out[i] ;
//// end
//// end
////
////
////
////
////
////
////
////
////*/
//// //////////////////////////////////////////////////////////////////////////////////////////////////////
//}
//
//object pic_main extends App{
// println("Generate Verilog")
// println((new chisel3.stage.ChiselStage).emitVerilog(new el2_pic_ctrl()))
//}

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import chisel3._
import chisel3.util._
import ifu._
import dec._
import exu._
import lsu._
import lib._
import include._
import dbg._
class el2_swerv extends Module with RequireAsyncReset with el2_lib {
val io = IO (new Bundle{
val dbg_rst_l = Input(Bool())
val rst_vec = Input(UInt(31.W))
val nmi_int = Input(Bool())
val nmi_vec = Input(UInt(31.W))
val core_rst_l = Output(AsyncReset())
val trace_rv_i_insn_ip = Output(UInt(32.W))
val trace_rv_i_address_ip = Output(UInt(32.W))
val trace_rv_i_valid_ip = Output(UInt(2.W))
val trace_rv_i_exception_ip = Output(UInt(2.W))
val trace_rv_i_ecause_ip = Output(UInt(5.W))
val trace_rv_i_interrupt_ip = Output(UInt(2.W))
val trace_rv_i_tval_ip = Output(UInt(32.W))
val dccm_clk_override = Output(Bool())
val icm_clk_override = Output(Bool())
val dec_tlu_core_ecc_disable = Output(Bool())
val i_cpu_halt_req = Input(Bool())
val i_cpu_run_req = Input(Bool())
val o_cpu_halt_ack = Output(Bool())
val o_cpu_halt_status = Output(Bool())
val o_cpu_run_ack = Output(Bool())
val o_debug_mode_status = Output(Bool())
val core_id = Input(UInt(28.W))
val mpc_debug_halt_req = Input(Bool())
val mpc_debug_run_req = Input(Bool())
val mpc_reset_run_req = Input(Bool())
val mpc_debug_halt_ack = Output(Bool())
val mpc_debug_run_ack = Output(Bool())
val debug_brkpt_status = Output(Bool())
val dec_tlu_perfcnt0 = Output(Bool())
val dec_tlu_perfcnt1 = Output(Bool())
val dec_tlu_perfcnt2 = Output(Bool())
val dec_tlu_perfcnt3 = Output(Bool())
val dccm_wren = Output(Bool())
val dccm_rden = Output(Bool())
val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
val iccm_rw_addr = Output(UInt(ICCM_BITS.W))
val iccm_wren = Output(Bool())
val iccm_rden = Output(Bool())
val iccm_wr_size = Output(UInt(3.W))
val iccm_wr_data = Output(UInt(78.W))
val iccm_buf_correct_ecc = Output(Bool())
val iccm_correction_state = Output(Bool())
val iccm_rd_data = Input(UInt(64.W))
val iccm_rd_data_ecc = Input(UInt(78.W))
val ic_rw_addr = Output(UInt(31.W))
val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_en = Output(Bool())
val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
val ic_rd_data = Input(UInt(64.W))
val ic_debug_rd_data = Input(UInt(71.W))
val ictag_debug_rd_data = Input(UInt(26.W))
val ic_debug_wr_data = Output(UInt(71.W))
val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_premux_data = Output(UInt(64.W))
val ic_sel_premux_data = Output(Bool())
val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W))
val ic_debug_rd_en = Output(Bool())
val ic_debug_wr_en = Output(Bool())
val ic_debug_tag_array = Output(Bool())
val ic_debug_way = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_perr = Input(Bool())
// AXI Signals
val lsu_axi_awvalid = Output(Bool())
val lsu_axi_awready = Input(Bool())
val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
val lsu_axi_awaddr = Output(UInt(32.W))
val lsu_axi_awregion = Output(UInt(4.W))
val lsu_axi_awlen = Output(UInt(8.W))
val lsu_axi_awsize = Output(UInt(3.W))
val lsu_axi_awburst = Output(UInt(2.W))
val lsu_axi_awlock = Output(Bool())
val lsu_axi_awcache = Output(UInt(4.W))
val lsu_axi_awprot = Output(UInt(3.W))
val lsu_axi_awqos = Output(UInt(4.W))
val lsu_axi_wvalid = Output(Bool())
val lsu_axi_wready = Input(Bool())
val lsu_axi_wdata = Output(UInt(64.W))
val lsu_axi_wstrb = Output(UInt(8.W))
val lsu_axi_wlast = Output(Bool())
val lsu_axi_bvalid = Input(Bool())
val lsu_axi_bready = Output(Bool())
val lsu_axi_bresp = Input(UInt(2.W))
val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
val lsu_axi_arvalid = Output(Bool())
val lsu_axi_arready = Input(Bool())
val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
val lsu_axi_araddr = Output(UInt(32.W))
val lsu_axi_arregion = Output(UInt(4.W))
val lsu_axi_arlen = Output(UInt(8.W))
val lsu_axi_arsize = Output(UInt(3.W))
val lsu_axi_arburst = Output(UInt(2.W))
val lsu_axi_arlock = Output(Bool())
val lsu_axi_arcache = Output(UInt(4.W))
val lsu_axi_arprot = Output(UInt(3.W))
val lsu_axi_arqos = Output(UInt(4.W))
val lsu_axi_rvalid = Input(Bool())
val lsu_axi_rready = Output(Bool())
val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
val lsu_axi_rdata = Input(UInt(64.W))
val lsu_axi_rresp = Input(UInt(2.W))
val lsu_axi_rlast = Input(Bool())
// AXI IFU Signals
val ifu_axi_awvalid = Output(Bool())
val ifu_axi_awready = Input(Bool())
val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_awaddr = Output(UInt(32.W))
val ifu_axi_awregion = Output(UInt(4.W))
val ifu_axi_awlen = Output(UInt(8.W))
val ifu_axi_awsize = Output(UInt(3.W))
val ifu_axi_awburst = Output(UInt(2.W))
val ifu_axi_awlock = Output(Bool())
val ifu_axi_awcache = Output(UInt(4.W))
val ifu_axi_awprot = Output(UInt(3.W))
val ifu_axi_awqos = Output(UInt(4.W))
val ifu_axi_wvalid = Output(Bool())
val ifu_axi_wready = Output(Bool())
val ifu_axi_wdata = Output(UInt(64.W))
val ifu_axi_wstrb = Output(UInt(8.W))
val ifu_axi_wlast = Output(Bool())
val ifu_axi_bvalid = Input(Bool())
val ifu_axi_bready = Output(Bool())
val ifu_axi_bresp = Input(UInt(2.W))
val ifu_axi_bid = Input(UInt(IFU_BUS_TAG.W))
val ifu_axi_arvalid = Output(Bool())
val ifu_axi_arready = Input(Bool())
val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_araddr = Output(UInt(32.W))
val ifu_axi_arregion = Output(UInt(4.W))
val ifu_axi_arlen = Output(UInt(8.W))
val ifu_axi_arsize = Output(UInt(3.W))
val ifu_axi_arburst = Output(UInt(2.W))
val ifu_axi_arlock = Output(Bool())
val ifu_axi_arcache = Output(UInt(4.W))
val ifu_axi_arprot = Output(UInt(3.W))
val ifu_axi_arqos = Output(UInt(4.W))
val ifu_axi_rvalid = Input(Bool())
val ifu_axi_rready = Output(Bool())
val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
val ifu_axi_rdata = Input(UInt(64.W))
val ifu_axi_rresp = Input(UInt(2.W))
val ifu_axi_rlast = Input(Bool())
// SB AXI Signals
val sb_axi_awvalid = Output(Bool())
val sb_axi_awready = Input(Bool())
val sb_axi_awid = Output(UInt(SB_BUS_TAG.W))
val sb_axi_awaddr = Output(UInt(32.W))
val sb_axi_awregion = Output(UInt(4.W))
val sb_axi_awlen = Output(UInt(8.W))
val sb_axi_awsize = Output(UInt(3.W))
val sb_axi_awburst = Output(UInt(2.W))
val sb_axi_awlock = Output(Bool())
val sb_axi_awcache = Output(UInt(4.W))
val sb_axi_awprot = Output(UInt(3.W))
val sb_axi_awqos = Output(UInt(4.W))
val sb_axi_wvalid = Output(Bool())
val sb_axi_wready = Input(Bool())
val sb_axi_wdata = Output(UInt(64.W))
val sb_axi_wstrb = Output(UInt(8.W))
val sb_axi_wlast = Output(Bool())
val sb_axi_bvalid = Input(Bool())
val sb_axi_bready = Output(Bool())
val sb_axi_bresp = Input(UInt(2.W))
val sb_axi_bid = Input(UInt(SB_BUS_TAG.W))
val sb_axi_arvalid = Output(Bool())
val sb_axi_arready = Input(Bool())
val sb_axi_arid = Output(UInt(SB_BUS_TAG.W))
val sb_axi_araddr = Output(UInt(32.W))
val sb_axi_arregion = Output(UInt(4.W))
val sb_axi_arlen = Output(UInt(8.W))
val sb_axi_arsize = Output(UInt(3.W))
val sb_axi_arburst = Output(UInt(2.W))
val sb_axi_arlock = Output(Bool())
val sb_axi_arcache = Output(UInt(4.W))
val sb_axi_arprot = Output(UInt(3.W))
val sb_axi_arqos = Output(UInt(4.W))
val sb_axi_rvalid = Input(Bool())
val sb_axi_rready = Output(Bool())
val sb_axi_rid = Input(UInt(SB_BUS_TAG.W))
val sb_axi_rdata = Input(UInt(64.W))
val sb_axi_rresp = Input(UInt(2.W))
val sb_axi_rlast = Input(Bool())
// DMA signals
val dma_axi_awvalid = Input(Bool())
val dma_axi_awready = Output(Bool())
val dma_axi_awid = Input(UInt(DMA_BUS_TAG.W))
val dma_axi_awaddr = Input(UInt(32.W))
val dma_axi_awsize = Input(UInt(3.W))
val dma_axi_awprot = Input(UInt(3.W))
val dma_axi_awlen = Input(UInt(8.W))
val dma_axi_awburst = Input(UInt(2.W))
val dma_axi_wvalid = Input(Bool())
val dma_axi_wready = Output(Bool())
val dma_axi_wdata = Input(UInt(64.W))
val dma_axi_wstrb = Input(UInt(8.W))
val dma_axi_wlast = Input(Bool())
val dma_axi_bvalid = Output(Bool())
val dma_axi_bready = Input(Bool())
val dma_axi_bresp = Output(UInt(2.W))
val dma_axi_bid = Output(UInt(DMA_BUS_TAG.W))
// AXI Read Channels
val dma_axi_arvalid = Input(Bool())
val dma_axi_arready = Output(Bool())
val dma_axi_arid = Input(UInt(DMA_BUS_TAG.W))
val dma_axi_araddr = Input(UInt(32.W))
val dma_axi_arsize = Input(UInt(3.W))
val dma_axi_arprot = Input(UInt(3.W))
val dma_axi_arlen = Input(UInt(8.W))
val dma_axi_arburst = Input(UInt(2.W))
val dma_axi_rvalid = Output(Bool())
val dma_axi_rready = Input(Bool())
val dma_axi_rid = Output(UInt(DMA_BUS_TAG.W))
val dma_axi_rdata = Output(UInt(64.W))
val dma_axi_rresp = Output(UInt(2.W))
val dma_axi_rlast = Output(Bool())
// AHB Lite Bus
val haddr = Output(UInt(32.W))
val hburst = Output(UInt(3.W))
val hmastlock = Output(Bool())
val hprot = Output(UInt(4.W))
val hsize = Output(UInt(3.W))
val htrans = Output(UInt(2.W))
val hwrite = Output(Bool())
val hrdata = Input(UInt(64.W))
val hready = Input(Bool())
val hresp = Input(Bool())
// AHB Master
val lsu_haddr = Output(UInt(32.W))
val lsu_hburst = Output(UInt(3.W))
val lsu_hmastlock = Output(Bool())
val lsu_hprot = Output(UInt(4.W))
val lsu_hsize = Output(UInt(3.W))
val lsu_htrans = Output(UInt(2.W))
val lsu_hwrite = Output(Bool())
val lsu_hwdata = Output(UInt(64.W))
val lsu_hrdata = Input(UInt(64.W))
val lsu_hready = Input(Bool())
val lsu_hresp = Input(Bool())
// System Bus Debug Master
val sb_haddr = Output(UInt(32.W))
val sb_hburst = Output(UInt(3.W))
val sb_hmastlock = Output(Bool())
val sb_hprot = Output(UInt(4.W))
val sb_hsize = Output(UInt(3.W))
val sb_htrans = Output(UInt(2.W))
val sb_hwrite = Output(Bool())
val sb_hwdata = Output(UInt(64.W))
val sb_hrdata = Input(UInt(64.W))
val sb_hready = Input(Bool())
val sb_hresp = Input(Bool())
// DMA slave
val dma_hsel = Input(Bool())
val dma_haddr = Input(UInt(32.W))
val dma_hburst = Input(UInt(3.W))
val dma_hmastlock = Input(Bool())
val dma_hprot = Input(UInt(4.W))
val dma_hsize = Input(UInt(3.W))
val dma_htrans = Input(UInt(2.W))
val dma_hwrite = Input(Bool())
val dma_hwdata = Input(UInt(64.W))
val dma_hreadyin = Input(Bool())
val dma_hrdata = Output(UInt(64.W))
val dma_hreadyout = Output(Bool())
val dma_hresp = Output(Bool())
val lsu_bus_clk_en = Input(Bool())
val ifu_bus_clk_en = Input(Bool())
val dbg_bus_clk_en = Input(Bool())
val dma_bus_clk_en = Input(Bool())
val dmi_reg_en = Input(Bool())
val dmi_reg_addr = Input(UInt(7.W))
val dmi_reg_wr_en = Input(Bool())
val dmi_reg_wdata = Input(UInt(32.W))
val dmi_reg_rdata = Output(UInt(32.W))
val dmi_hard_reset = Input(Bool())
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
val timer_int = Input(Bool())
val soft_int = Input(Bool())
val scan_mode = Input(Bool())
})
val ifu = Module(new el2_ifu)
val dec = Module(new el2_dec)
val dbg = Module(new el2_dbg)
val exu = Module(new el2_exu)
val lsu = Module(new el2_lsu)
val pic_ctl_inst = Module(new el2_pic_ctrl)
val dma_ctrl = Module(new el2_dma_ctrl)
//val lsu_axi4_to_ahb = Module(new axi4_to_ahb)
//val ifu_axi4_to_ahb = Module(new axi4_to_ahb)
//val sb_axi4_to_ahb = Module(new axi4_to_ahb)
io.core_rst_l := (!(reset.asBool() & (dbg.io.dbg_core_rst_l.asBool() | io.scan_mode))).asAsyncReset()
val active_state = (!dec.io.dec_pause_state_cg | dec.io.dec_tlu_flush_lower_r) | dec.io.dec_tlu_misc_clk_override
val free_clk = rvclkhdr(clock, true.B, io.scan_mode)
val active_clk = rvclkhdr(clock, active_state, io.scan_mode)
val core_dbg_cmd_done = dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done
val core_dbg_cmd_fail = dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail
val core_dbg_rddata = Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata)
// AHB to AXI-4 still remaining
// Lets start with IFU
ifu.reset := io.core_rst_l
ifu.io.scan_mode := io.scan_mode
ifu.io.free_clk := free_clk
ifu.io.active_clk := active_clk
ifu.io.iccm_rd_data_ecc := io.iccm_rd_data_ecc
ifu.io.dec_i0_decode_d := dec.io.dec_i0_decode_d
ifu.io.exu_flush_final := dec.io.exu_flush_final
ifu.io.dec_tlu_i0_commit_cmt := dec.io.dec_tlu_i0_commit_cmt
ifu.io.dec_tlu_flush_err_wb := dec.io.dec_tlu_flush_err_r
ifu.io.dec_tlu_flush_noredir_wb := dec.io.dec_tlu_flush_noredir_r
ifu.io.exu_flush_path_final := exu.io.exu_flush_path_final
ifu.io.dec_tlu_mrac_ff := dec.io.dec_tlu_mrac_ff
ifu.io.dec_tlu_fence_i_wb := dec.io.dec_tlu_fence_i_r
ifu.io.dec_tlu_flush_leak_one_wb := dec.io.dec_tlu_flush_leak_one_r
ifu.io.dec_tlu_bpred_disable := dec.io.dec_tlu_bpred_disable
ifu.io.dec_tlu_core_ecc_disable := dec.io.dec_tlu_core_ecc_disable
ifu.io.dec_tlu_force_halt := dec.io.dec_tlu_force_halt
ifu.io.ifu_axi_arready := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_arready)
ifu.io.ifu_axi_rvalid := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rvalid)
ifu.io.ifu_axi_rid := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rid)
ifu.io.ifu_axi_rdata := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rdata)
ifu.io.ifu_axi_rresp := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rresp)
ifu.io.ifu_bus_clk_en := io.ifu_bus_clk_en
ifu.io.dma_iccm_req := dma_ctrl.io.dma_iccm_req
ifu.io.dma_mem_addr := dma_ctrl.io.dma_mem_addr
ifu.io.dma_mem_sz := dma_ctrl.io.dma_mem_sz
ifu.io.dma_mem_write := dma_ctrl.io.dma_mem_write
ifu.io.dma_mem_wdata := dma_ctrl.io.dma_mem_wdata
ifu.io.dma_mem_tag := dma_ctrl.io.dma_mem_tag
ifu.io.dma_iccm_stall_any := dma_ctrl.io.dma_iccm_stall_any
ifu.io.ic_rd_data := io.ic_rd_data
ifu.io.ic_debug_rd_data := io.ic_debug_rd_data
ifu.io.ictag_debug_rd_data := io.ictag_debug_rd_data
ifu.io.ic_eccerr := io.ic_eccerr
ifu.io.ic_parerr := io.ic_parerr
ifu.io.ic_rd_hit := io.ic_rd_hit
ifu.io.ic_tag_perr := io.ic_tag_perr
ifu.io.iccm_rd_data := io.iccm_rd_data
ifu.io.exu_mp_pkt <> exu.io.exu_mp_pkt
ifu.io.exu_mp_eghr := exu.io.exu_mp_eghr
ifu.io.exu_mp_fghr := exu.io.exu_mp_fghr
ifu.io.exu_mp_index := exu.io.exu_mp_index
ifu.io.exu_mp_btag := exu.io.exu_mp_btag
ifu.io.dec_tlu_br0_r_pkt <> dec.io.dec_tlu_br0_r_pkt
ifu.io.exu_i0_br_fghr_r := exu.io.exu_i0_br_fghr_r
ifu.io.exu_i0_br_index_r := exu.io.exu_i0_br_index_r
ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_tlu_flush_lower_r
ifu.io.dec_tlu_ic_diag_pkt <> dec.io.dec_tlu_ic_diag_pkt
// Lets start with Dec
dec.reset := io.core_rst_l
dec.io.free_clk := free_clk
dec.io.active_clk := active_clk
dec.io.lsu_fastint_stall_any := lsu.io.lsu_fastint_stall_any
dec.io.rst_vec := io.rst_vec
dec.io.nmi_int := io.nmi_int
dec.io.nmi_vec := io.nmi_vec
dec.io.i_cpu_halt_req := io.i_cpu_halt_req
dec.io.i_cpu_run_req := io.i_cpu_run_req
dec.io.core_id := io.core_id
dec.io.mpc_debug_halt_req := io.mpc_debug_halt_req
dec.io.mpc_debug_run_req := io.mpc_debug_run_req
dec.io.mpc_reset_run_req := io.mpc_reset_run_req
dec.io.exu_pmu_i0_br_misp := exu.io.exu_pmu_i0_br_misp
dec.io.exu_pmu_i0_br_ataken := exu.io.exu_pmu_i0_br_ataken
dec.io.exu_pmu_i0_pc4 := exu.io.exu_pmu_i0_pc4
dec.io.lsu_nonblock_load_valid_m := lsu.io.lsu_nonblock_load_valid_m
dec.io.lsu_nonblock_load_tag_m := lsu.io.lsu_nonblock_load_tag_m
dec.io.lsu_nonblock_load_inv_r := lsu.io.lsu_nonblock_load_inv_r
dec.io.lsu_nonblock_load_inv_tag_r := lsu.io.lsu_nonblock_load_inv_tag_r
dec.io.lsu_nonblock_load_data_valid := lsu.io.lsu_nonblock_load_data_valid
dec.io.lsu_nonblock_load_data_error := lsu.io.lsu_nonblock_load_data_error
dec.io.lsu_nonblock_load_data_tag := lsu.io.lsu_nonblock_load_data_tag
dec.io.lsu_nonblock_load_data := lsu.io.lsu_nonblock_load_data
dec.io.lsu_pmu_bus_trxn := lsu.io.lsu_pmu_bus_trxn
dec.io.lsu_pmu_bus_misaligned := lsu.io.lsu_pmu_bus_misaligned
dec.io.lsu_pmu_bus_error := lsu.io.lsu_pmu_bus_error
dec.io.lsu_pmu_bus_busy := lsu.io.lsu_pmu_bus_busy
dec.io.lsu_pmu_misaligned_m := lsu.io.lsu_pmu_misaligned_m
dec.io.lsu_pmu_load_external_m := lsu.io.lsu_pmu_load_external_m
dec.io.lsu_pmu_store_external_m := lsu.io.lsu_pmu_store_external_m
dec.io.dma_pmu_dccm_read := dma_ctrl.io.dma_pmu_dccm_read
dec.io.dma_pmu_dccm_write := dma_ctrl.io.dma_pmu_dccm_write
dec.io.dma_pmu_any_read := dma_ctrl.io.dma_pmu_any_read
dec.io.dma_pmu_any_write := dma_ctrl.io.dma_pmu_any_write
dec.io.lsu_fir_addr := lsu.io.lsu_fir_addr
dec.io.lsu_fir_error := lsu.io.lsu_fir_error
dec.io.ifu_pmu_instr_aligned := ifu.io.ifu_pmu_instr_aligned
dec.io.ifu_pmu_fetch_stall := ifu.io.ifu_pmu_fetch_stall
dec.io.ifu_pmu_ic_miss := ifu.io.ifu_pmu_ic_miss
dec.io.ifu_pmu_ic_hit := ifu.io.ifu_pmu_ic_hit
dec.io.ifu_pmu_bus_error := ifu.io.ifu_pmu_bus_error
dec.io.ifu_pmu_bus_busy := ifu.io.ifu_pmu_bus_busy
dec.io.ifu_pmu_bus_trxn := ifu.io.ifu_pmu_bus_trxn
dec.io.ifu_ic_error_start := ifu.io.ifu_ic_error_start
dec.io.ifu_iccm_rd_ecc_single_err := ifu.io.ifu_iccm_rd_ecc_single_err
dec.io.lsu_trigger_match_m := lsu.io.lsu_trigger_match_m
dec.io.dbg_cmd_valid := dbg.io.dbg_cmd_valid
dec.io.dbg_cmd_write := dbg.io.dbg_cmd_write
dec.io.dbg_cmd_type := dbg.io.dbg_cmd_type
dec.io.dbg_cmd_addr := dbg.io.dbg_cmd_addr
dec.io.dbg_cmd_wrdata := dbg.io.dbg_cmd_wrdata
dec.io.ifu_i0_icaf := ifu.io.ifu_i0_icaf
dec.io.ifu_i0_icaf_type := ifu.io.ifu_i0_icaf_type
dec.io.ifu_i0_icaf_f1 := ifu.io.ifu_i0_icaf_f1
dec.io.ifu_i0_dbecc := ifu.io.ifu_i0_dbecc
dec.io.lsu_idle_any := lsu.io.lsu_idle_any
dec.io.i0_brp := ifu.io.i0_brp
dec.io.ifu_i0_bp_index := ifu.io.ifu_i0_bp_index
dec.io.ifu_i0_bp_fghr := ifu.io.ifu_i0_bp_fghr
dec.io.ifu_i0_bp_btag := ifu.io.ifu_i0_bp_btag
dec.io.lsu_error_pkt_r <> lsu.io.lsu_error_pkt_r
dec.io.lsu_single_ecc_error_incr := lsu.io.lsu_single_ecc_error_incr
dec.io.lsu_imprecise_error_load_any := lsu.io.lsu_imprecise_error_load_any
dec.io.lsu_imprecise_error_store_any := lsu.io.lsu_imprecise_error_store_any
dec.io.lsu_imprecise_error_addr_any := lsu.io.lsu_imprecise_error_addr_any
dec.io.exu_div_result := exu.io.exu_div_result
dec.io.exu_div_wren := exu.io.exu_div_wren
dec.io.exu_csr_rs1_x := exu.io.exu_csr_rs1_x
dec.io.lsu_result_m := lsu.io.lsu_result_m
dec.io.lsu_result_corr_r := lsu.io.lsu_result_corr_r
dec.io.lsu_load_stall_any := lsu.io.lsu_load_stall_any
dec.io.lsu_store_stall_any := lsu.io.lsu_store_stall_any
dec.io.dma_dccm_stall_any := dma_ctrl.io.dma_dccm_stall_any
dec.io.dma_iccm_stall_any := dma_ctrl.io.dma_iccm_stall_any
dec.io.iccm_dma_sb_error := ifu.io.iccm_dma_sb_error
dec.io.exu_flush_final := exu.io.exu_flush_final
dec.io.exu_npc_r := exu.io.exu_npc_r
dec.io.exu_i0_result_x := exu.io.exu_i0_result_x
dec.io.ifu_i0_valid := ifu.io.ifu_i0_valid
dec.io.ifu_i0_instr := ifu.io.ifu_i0_instr
dec.io.ifu_i0_pc := ifu.io.ifu_i0_pc
dec.io.ifu_i0_pc4 := ifu.io.ifu_i0_pc4
dec.io.exu_i0_pc_x := exu.io.exu_i0_pc_x
dec.io.mexintpend := pic_ctl_inst.io.mexintpend
dec.io.soft_int := io.soft_int
dec.io.pic_claimid := pic_ctl_inst.io.claimid
dec.io.pic_pl := pic_ctl_inst.io.pl
dec.io.mhwakeup := pic_ctl_inst.io.mhwakeup
dec.io.ifu_ic_debug_rd_data := ifu.io.ifu_ic_debug_rd_data
dec.io.ifu_ic_debug_rd_data_valid := ifu.io.ifu_ic_debug_rd_data_valid
dec.io.dbg_halt_req := dbg.io.dbg_halt_req
dec.io.dbg_resume_req := dbg.io.dbg_resume_req
dec.io.ifu_miss_state_idle := ifu.io.ifu_miss_state_idle
dec.io.exu_i0_br_hist_r := exu.io.exu_i0_br_hist_r
dec.io.exu_i0_br_error_r := exu.io.exu_i0_br_error_r
dec.io.exu_i0_br_start_error_r := exu.io.exu_i0_br_start_error_r
dec.io.exu_i0_br_valid_r := exu.io.exu_i0_br_valid_r
dec.io.exu_i0_br_mp_r := exu.io.exu_i0_br_mp_r
dec.io.exu_i0_br_middle_r := exu.io.exu_i0_br_middle_r
dec.io.exu_i0_br_way_r := exu.io.exu_i0_br_way_r
dec.io.ifu_i0_cinst := ifu.io.ifu_i0_cinst
dec.io.timer_int := io.timer_int
dec.io.scan_mode := io.scan_mode
// EXU lets go
exu.reset := io.core_rst_l
exu.io.scan_mode := io.scan_mode
exu.io.dec_data_en := dec.io.dec_data_en
exu.io.dec_ctl_en := dec.io.dec_ctl_en
exu.io.dbg_cmd_wrdata := dbg.io.dbg_cmd_wrdata
exu.io.i0_ap := dec.io.i0_ap
exu.io.dec_debug_wdata_rs1_d := dec.io.dec_debug_wdata_rs1_d
exu.io.dec_i0_predict_p_d <> dec.io.dec_i0_predict_p_d
exu.io.i0_predict_fghr_d := dec.io.i0_predict_fghr_d
exu.io.i0_predict_index_d := dec.io.i0_predict_index_d
exu.io.i0_predict_btag_d := dec.io.i0_predict_btag_d
exu.io.dec_i0_rs1_en_d := dec.io.dec_i0_rs1_en_d
exu.io.dec_i0_rs2_en_d := dec.io.dec_i0_rs2_en_d
exu.io.gpr_i0_rs1_d := dec.io.gpr_i0_rs1_d
exu.io.gpr_i0_rs2_d := dec.io.gpr_i0_rs2_d
exu.io.dec_i0_immed_d := dec.io.dec_i0_immed_d
exu.io.dec_i0_rs1_bypass_data_d := dec.io.dec_i0_rs1_bypass_data_d
exu.io.dec_i0_rs2_bypass_data_d := dec.io.dec_i0_rs2_bypass_data_d
exu.io.dec_i0_br_immed_d := dec.io.dec_i0_br_immed_d
exu.io.dec_i0_alu_decode_d := dec.io.dec_i0_alu_decode_d
exu.io.dec_i0_select_pc_d := dec.io.dec_i0_select_pc_d
exu.io.dec_i0_pc_d := dec.io.dec_i0_pc_d
exu.io.dec_i0_rs1_bypass_en_d := dec.io.dec_i0_rs1_bypass_en_d
exu.io.dec_i0_rs2_bypass_en_d := dec.io.dec_i0_rs2_bypass_en_d
exu.io.dec_csr_ren_d := dec.io.dec_csr_ren_d
exu.io.mul_p <> dec.io.mul_p
exu.io.div_p <> dec.io.div_p
exu.io.dec_div_cancel := dec.io.dec_div_cancel
exu.io.pred_correct_npc_x := dec.io.pred_correct_npc_x
exu.io.dec_tlu_flush_lower_r := dec.io.dec_tlu_flush_lower_r
exu.io.dec_tlu_flush_path_r := dec.io.dec_tlu_flush_path_r
exu.io.dec_extint_stall := dec.io.dec_extint_stall
exu.io.dec_tlu_meihap := dec.io.dec_tlu_meihap
// LSU Lets go
lsu.reset := io.core_rst_l
lsu.io.clk_override := dec.io.dec_tlu_lsu_clk_override
lsu.io.dec_tlu_flush_lower_r := dec.io.dec_tlu_flush_lower_r
lsu.io.dec_tlu_i0_kill_writeb_r := dec.io.dec_tlu_i0_kill_writeb_r
lsu.io.dec_tlu_force_halt := dec.io.dec_tlu_force_halt
lsu.io.dec_tlu_external_ldfwd_disable := dec.io.dec_tlu_external_ldfwd_disable
lsu.io.dec_tlu_wb_coalescing_disable := dec.io.dec_tlu_wb_coalescing_disable
lsu.io.dec_tlu_sideeffect_posted_disable := dec.io.dec_tlu_sideeffect_posted_disable
lsu.io.dec_tlu_core_ecc_disable := dec.io.dec_tlu_core_ecc_disable
lsu.io.exu_lsu_rs1_d := exu.io.exu_lsu_rs1_d
lsu.io.exu_lsu_rs2_d := exu.io.exu_lsu_rs2_d
lsu.io.dec_lsu_offset_d := dec.io.dec_lsu_offset_d
lsu.io.lsu_p <> dec.io.lsu_p
lsu.io.dec_lsu_valid_raw_d := dec.io.dec_lsu_valid_raw_d
lsu.io.dec_tlu_mrac_ff := dec.io.dec_tlu_mrac_ff
lsu.io.trigger_pkt_any <> dec.io.trigger_pkt_any
lsu.io.dccm_rd_data_lo := io.dccm_rd_data_lo
lsu.io.dccm_rd_data_hi := io.dccm_rd_data_hi
lsu.io.lsu_axi_awready := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_awready)
lsu.io.lsu_axi_wready := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_wready)
lsu.io.lsu_axi_bvalid := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_bvalid)
lsu.io.lsu_axi_bresp := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_bresp)
lsu.io.lsu_axi_bid := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_bid)
lsu.io.lsu_axi_arready := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_arready)
lsu.io.lsu_axi_rvalid := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_rvalid)
lsu.io.lsu_axi_rid := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_rid)
lsu.io.lsu_axi_rdata := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_rdata)
lsu.io.lsu_axi_rresp := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_rresp)
lsu.io.lsu_axi_rlast := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_rlast)
lsu.io.lsu_bus_clk_en := io.lsu_bus_clk_en
lsu.io.dma_dccm_req := dma_ctrl.io.dma_dccm_req
lsu.io.dma_mem_tag := dma_ctrl.io.dma_mem_tag
lsu.io.dma_mem_addr := dma_ctrl.io.dma_mem_addr
lsu.io.dma_mem_sz := dma_ctrl.io.dma_mem_sz
lsu.io.dma_mem_write := dma_ctrl.io.dma_mem_write
lsu.io.dma_mem_wdata := dma_ctrl.io.dma_mem_wdata
lsu.io.scan_mode := io.scan_mode
lsu.io.free_clk := free_clk
// Debug lets go
dbg.reset := io.core_rst_l
dbg.io.core_dbg_rddata := Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata)
dbg.io.core_dbg_cmd_done := dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done
dbg.io.core_dbg_cmd_fail := dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail
dbg.io.dma_dbg_ready := dma_ctrl.io.dma_dbg_ready
dbg.io.dec_tlu_debug_mode := dec.io.dec_tlu_debug_mode
dbg.io.dec_tlu_dbg_halted := dec.io.dec_tlu_dbg_halted
dbg.io.dec_tlu_mpc_halted_only := dec.io.dec_tlu_mpc_halted_only
dbg.io.dec_tlu_resume_ack := dec.io.dec_tlu_resume_ack
dbg.io.dmi_reg_en := io.dmi_reg_en
dbg.io.dmi_reg_addr := io.dmi_reg_addr
dbg.io.dmi_reg_wr_en := io.dmi_reg_wr_en
dbg.io.dmi_reg_wdata := io.dmi_reg_wdata
dbg.io.sb_axi_awready := io.sb_axi_awready
dbg.io.sb_axi_wready := io.sb_axi_wready
dbg.io.sb_axi_bvalid := io.sb_axi_bvalid
dbg.io.sb_axi_bresp := io.sb_axi_bresp
dbg.io.sb_axi_arready := io.sb_axi_arready
dbg.io.sb_axi_rvalid := io.sb_axi_rvalid
dbg.io.sb_axi_rdata := io.sb_axi_rdata
dbg.io.sb_axi_rresp := io.sb_axi_rresp
dbg.io.dbg_bus_clk_en := io.dbg_bus_clk_en
dbg.io.dbg_rst_l := io.dbg_rst_l
dbg.io.clk_override := dec.io.dec_tlu_misc_clk_override
dbg.io.scan_mode := io.scan_mode
// DMA Lets go
dma_ctrl.reset := io.core_rst_l
dma_ctrl.io.free_clk := free_clk
dma_ctrl.io.dma_bus_clk_en := io.dma_bus_clk_en
dma_ctrl.io.clk_override := dec.io.dec_tlu_misc_clk_override
dma_ctrl.io.scan_mode := io.scan_mode
dma_ctrl.io.dbg_cmd_addr := dbg.io.dbg_cmd_addr
dma_ctrl.io.dbg_cmd_wrdata := dbg.io.dbg_cmd_wrdata
dma_ctrl.io.dbg_cmd_valid := dbg.io.dbg_cmd_valid
dma_ctrl.io.dbg_cmd_write := dbg.io.dbg_cmd_write
dma_ctrl.io.dbg_cmd_type := dbg.io.dbg_cmd_type
dma_ctrl.io.dbg_cmd_size := dbg.io.dbg_cmd_size
dma_ctrl.io.dbg_dma_bubble := dbg.io.dbg_dma_bubble
dma_ctrl.io.dccm_dma_rvalid := lsu.io.dccm_dma_rvalid
dma_ctrl.io.dccm_dma_ecc_error := lsu.io.dccm_dma_ecc_error
dma_ctrl.io.dccm_dma_rtag := lsu.io.dccm_dma_rtag
dma_ctrl.io.dccm_dma_rdata := lsu.io.dccm_dma_rdata
dma_ctrl.io.iccm_dma_rvalid := ifu.io.iccm_dma_rvalid
dma_ctrl.io.iccm_dma_rtag := ifu.io.iccm_dma_rtag
dma_ctrl.io.iccm_dma_rdata := ifu.io.iccm_dma_rdata
dma_ctrl.io.dccm_ready := lsu.io.dccm_ready
dma_ctrl.io.iccm_ready := ifu.io.iccm_ready
dma_ctrl.io.dec_tlu_dma_qos_prty := dec.io.dec_tlu_dma_qos_prty
dma_ctrl.io.dma_axi_awvalid := io.dma_axi_awvalid
dma_ctrl.io.dma_axi_awid := io.dma_axi_awid
dma_ctrl.io.dma_axi_awaddr := io.dma_axi_awaddr
dma_ctrl.io.dma_axi_awsize := io.dma_axi_awsize
dma_ctrl.io.dma_axi_wvalid := io.dma_axi_wvalid
dma_ctrl.io.dma_axi_wdata := io.dma_axi_wdata
dma_ctrl.io.dma_axi_wstrb := io.dma_axi_wstrb
dma_ctrl.io.dma_axi_bready := io.dma_axi_bready
dma_ctrl.io.dma_axi_arvalid := io.dma_axi_arvalid
dma_ctrl.io.dma_axi_arid := io.dma_axi_arid
dma_ctrl.io.dma_axi_araddr := io.dma_axi_araddr
dma_ctrl.io.dma_axi_arsize := io.dma_axi_arsize
dma_ctrl.io.dma_axi_rready := io.dma_axi_rready
dma_ctrl.io.iccm_dma_ecc_error := ifu.io.iccm_dma_ecc_error
// PIC lets go
pic_ctl_inst.io.scan_mode := io.scan_mode
pic_ctl_inst.reset := io.core_rst_l
pic_ctl_inst.io.free_clk := free_clk
pic_ctl_inst.io.active_clk := active_clk
pic_ctl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override
pic_ctl_inst.io.extintsrc_req := io.extintsrc_req
pic_ctl_inst.io.picm_rdaddr := lsu.io.picm_rdaddr
pic_ctl_inst.io.picm_wraddr := lsu.io.picm_wraddr
pic_ctl_inst.io.picm_wr_data := lsu.io.picm_wr_data
pic_ctl_inst.io.picm_wren := lsu.io.picm_wren
pic_ctl_inst.io.picm_rden := lsu.io.picm_rden
pic_ctl_inst.io.picm_mken := lsu.io.picm_mken
pic_ctl_inst.io.meicurpl := dec.io.dec_tlu_meicurpl
pic_ctl_inst.io.meipt := dec.io.dec_tlu_meipt
lsu.io.picm_rd_data := pic_ctl_inst.io.picm_rd_data
// Trace Packet
io.trace_rv_i_insn_ip := dec.io.rv_trace_pkt.rv_i_insn_ip
io.trace_rv_i_address_ip := dec.io.rv_trace_pkt.rv_i_address_ip
io.trace_rv_i_valid_ip := dec.io.rv_trace_pkt.rv_i_valid_ip
io.trace_rv_i_exception_ip := dec.io.rv_trace_pkt.rv_i_exception_ip
io.trace_rv_i_ecause_ip := dec.io.rv_trace_pkt.rv_i_ecause_ip
io.trace_rv_i_interrupt_ip := dec.io.rv_trace_pkt.rv_i_interrupt_ip
io.trace_rv_i_tval_ip := dec.io.rv_trace_pkt.rv_i_tval_ip
// Outputs
io.dccm_clk_override := dec.io.dec_tlu_dccm_clk_override
io.icm_clk_override := dec.io.dec_tlu_icm_clk_override
io.dec_tlu_core_ecc_disable := dec.io.dec_tlu_core_ecc_disable
io.o_cpu_halt_ack := dec.io.o_cpu_halt_ack
io.o_cpu_halt_status := dec.io.o_cpu_halt_status
io.o_cpu_run_ack := dec.io.o_cpu_run_ack
io.o_debug_mode_status := dec.io.o_debug_mode_status
io.mpc_debug_halt_ack := dec.io.mpc_debug_halt_ack
io.mpc_debug_run_ack := dec.io.mpc_debug_run_ack
io.debug_brkpt_status := dec.io.debug_brkpt_status
io.dec_tlu_perfcnt0 := dec.io.dec_tlu_perfcnt0
io.dec_tlu_perfcnt1 := dec.io.dec_tlu_perfcnt1
io.dec_tlu_perfcnt2 := dec.io.dec_tlu_perfcnt2
io.dec_tlu_perfcnt3 := dec.io.dec_tlu_perfcnt3
// LSU Outputs
io.dccm_wren := lsu.io.dccm_wren
io.dccm_rden := lsu.io.dccm_rden
io.dccm_wr_addr_lo := lsu.io.dccm_wr_addr_lo
io.dccm_wr_addr_hi := lsu.io.dccm_wr_addr_hi
io.dccm_rd_addr_lo := lsu.io.dccm_rd_addr_lo
io.dccm_rd_addr_hi := lsu.io.dccm_rd_addr_hi
io.dccm_wr_data_lo := lsu.io.dccm_wr_data_lo
io.dccm_wr_data_hi := lsu.io.dccm_wr_data_hi
// IFU Outputs
io.iccm_rw_addr := ifu.io.iccm_rw_addr
io.iccm_wren := ifu.io.iccm_wren
io.iccm_rden := ifu.io.iccm_rden
io.iccm_wr_size := ifu.io.iccm_wr_size
io.iccm_wr_data := ifu.io.iccm_wr_data
io.iccm_buf_correct_ecc := ifu.io.iccm_buf_correct_ecc
io.iccm_correction_state := ifu.io.iccm_correction_state
io.ic_rw_addr := ifu.io.ic_rw_addr
io.ic_tag_valid := ifu.io.ic_tag_valid
io.ic_wr_en := ifu.io.ic_wr_en
io.ic_rd_en := ifu.io.ic_rd_en
io.ic_wr_data := ifu.io.ic_wr_data
io.ic_debug_wr_data := ifu.io.ic_debug_wr_data
io.ic_premux_data := ifu.io.ic_premux_data
io.ic_sel_premux_data := ifu.io.ic_sel_premux_data
io.ic_debug_addr := ifu.io.ic_debug_addr
io.ic_debug_rd_en := ifu.io.ic_debug_rd_en
io.ic_debug_wr_en := ifu.io.ic_debug_wr_en
io.ic_debug_tag_array := ifu.io.ic_debug_tag_array
io.ic_debug_way := ifu.io.ic_debug_way
// AXI LSU SIDE
io.lsu_axi_awvalid := lsu.io.lsu_axi_awvalid
io.lsu_axi_awid := lsu.io.lsu_axi_awid
io.lsu_axi_awaddr := lsu.io.lsu_axi_awaddr
io.lsu_axi_awregion := lsu.io.lsu_axi_awregion
io.lsu_axi_awlen := lsu.io.lsu_axi_awlen
io.lsu_axi_awsize := lsu.io.lsu_axi_awsize
io.lsu_axi_awburst := lsu.io.lsu_axi_awburst
io.lsu_axi_awlock := lsu.io.lsu_axi_awlock
io.lsu_axi_awcache := lsu.io.lsu_axi_awcache
io.lsu_axi_awprot := lsu.io.lsu_axi_awprot
io.lsu_axi_awqos := lsu.io.lsu_axi_awqos
io.lsu_axi_wvalid := lsu.io.lsu_axi_wvalid
io.lsu_axi_wdata := lsu.io.lsu_axi_wdata
io.lsu_axi_wstrb := lsu.io.lsu_axi_wstrb
io.lsu_axi_wlast := lsu.io.lsu_axi_wlast
io.lsu_axi_bready := lsu.io.lsu_axi_bready
io.lsu_axi_arvalid := lsu.io.lsu_axi_arvalid
io.lsu_axi_arid := lsu.io.lsu_axi_arid
io.lsu_axi_araddr := lsu.io.lsu_axi_araddr
io.lsu_axi_arregion := lsu.io.lsu_axi_arregion
io.lsu_axi_arlen := lsu.io.lsu_axi_arlen
io.lsu_axi_arsize := lsu.io.lsu_axi_arsize
io.lsu_axi_arburst := lsu.io.lsu_axi_arburst
io.lsu_axi_arlock := lsu.io.lsu_axi_arlock
io.lsu_axi_arcache := lsu.io.lsu_axi_arcache
io.lsu_axi_arprot := lsu.io.lsu_axi_arprot
io.lsu_axi_arqos := lsu.io.lsu_axi_arqos
io.lsu_axi_rready := lsu.io.lsu_axi_rready
// AXI IFU
io.ifu_axi_awvalid := ifu.io.ifu_axi_awvalid
io.ifu_axi_awid := ifu.io.ifu_axi_awid
io.ifu_axi_awaddr := ifu.io.ifu_axi_awaddr
io.ifu_axi_awregion := ifu.io.ifu_axi_awregion
io.ifu_axi_awlen := ifu.io.ifu_axi_awlen
io.ifu_axi_awsize := ifu.io.ifu_axi_awsize
io.ifu_axi_awburst := ifu.io.ifu_axi_awburst
io.ifu_axi_awlock := ifu.io.ifu_axi_awlock
io.ifu_axi_awcache := ifu.io.ifu_axi_awcache
io.ifu_axi_awprot := ifu.io.ifu_axi_awprot
io.ifu_axi_awqos := ifu.io.ifu_axi_awqos
io.ifu_axi_wvalid := ifu.io.ifu_axi_wvalid
io.ifu_axi_wdata := ifu.io.ifu_axi_wdata
io.ifu_axi_wstrb := ifu.io.ifu_axi_wstrb
io.ifu_axi_wlast := ifu.io.ifu_axi_wlast
io.ifu_axi_bready := ifu.io.ifu_axi_bready
io.ifu_axi_arvalid := ifu.io.ifu_axi_arvalid
io.ifu_axi_arid := ifu.io.ifu_axi_arid
io.ifu_axi_araddr := ifu.io.ifu_axi_araddr
io.ifu_axi_arregion := ifu.io.ifu_axi_arregion
io.ifu_axi_arlen := ifu.io.ifu_axi_arlen
io.ifu_axi_arsize := ifu.io.ifu_axi_arsize
io.ifu_axi_arburst := ifu.io.ifu_axi_arburst
io.ifu_axi_arlock := ifu.io.ifu_axi_arlock
io.ifu_axi_arcache := ifu.io.ifu_axi_arcache
io.ifu_axi_arprot := ifu.io.ifu_axi_arprot
io.ifu_axi_arqos := ifu.io.ifu_axi_arqos
io.ifu_axi_rready := ifu.io.ifu_axi_rready
// AXI SB Signals
io.sb_axi_awvalid := dbg.io.sb_axi_awvalid
io.sb_axi_awid := dbg.io.sb_axi_awid
io.sb_axi_awaddr := dbg.io.sb_axi_awaddr
io.sb_axi_awregion := dbg.io.sb_axi_awregion
io.sb_axi_awlen := dbg.io.sb_axi_awlen
io.sb_axi_awsize := dbg.io.sb_axi_awsize
io.sb_axi_awburst := dbg.io.sb_axi_awburst
io.sb_axi_awlock := dbg.io.sb_axi_awlock
io.sb_axi_awcache := dbg.io.sb_axi_awcache
io.sb_axi_awprot := dbg.io.sb_axi_awprot
io.sb_axi_awqos := dbg.io.sb_axi_awqos
io.sb_axi_wvalid := dbg.io.sb_axi_wvalid
io.sb_axi_wdata := dbg.io.sb_axi_wdata
io.sb_axi_wstrb := dbg.io.sb_axi_wstrb
io.sb_axi_wlast := dbg.io.sb_axi_wlast
io.sb_axi_bready := dbg.io.sb_axi_bready
io.sb_axi_arvalid := dbg.io.sb_axi_arvalid
io.sb_axi_arid := dbg.io.sb_axi_arid
io.sb_axi_araddr := dbg.io.sb_axi_araddr
io.sb_axi_arregion := dbg.io.sb_axi_arregion
io.sb_axi_arlen := dbg.io.sb_axi_arlen
io.sb_axi_arsize := dbg.io.sb_axi_arsize
io.sb_axi_arburst := dbg.io.sb_axi_arburst
io.sb_axi_arlock := dbg.io.sb_axi_arlock
io.sb_axi_arcache := dbg.io.sb_axi_arcache
io.sb_axi_arprot := dbg.io.sb_axi_arprot
io.sb_axi_arqos := dbg.io.sb_axi_arqos
io.sb_axi_rready := dbg.io.sb_axi_rready
// DMA Output Signals
io.dma_axi_awready := dma_ctrl.io.dma_axi_awready
io.dma_axi_wready := dma_ctrl.io.dma_axi_wready
io.dma_axi_bvalid := dma_ctrl.io.dma_axi_bvalid
io.dma_axi_bresp := dma_ctrl.io.dma_axi_bresp
io.dma_axi_bid := dma_ctrl.io.dma_axi_bid
io.dma_axi_arready := dma_ctrl.io.dma_axi_arready
io.dma_axi_rvalid := dma_ctrl.io.dma_axi_rvalid
io.dma_axi_rid := dma_ctrl.io.dma_axi_rid
io.dma_axi_rdata := dma_ctrl.io.dma_axi_rdata
io.dma_axi_rresp := dma_ctrl.io.dma_axi_rresp
io.dma_axi_rlast := dma_ctrl.io.dma_axi_rlast
// AHB Signals
io.hburst := 0.U
io.hmastlock := 0.U
io.hprot := 0.U
io.hsize := 0.U
io.htrans := 0.U
io.hwrite := 0.U
io.haddr := 0.U
io.lsu_haddr := 0.U
io.lsu_hburst := 0.U
io.lsu_hmastlock := 0.U
io.lsu_hprot := 0.U
io.lsu_hsize := 0.U
io.lsu_htrans := 0.U
io.lsu_hwrite := 0.U
io.lsu_hwdata := 0.U
io.sb_haddr := 0.U
io.sb_hburst := 0.U
io.sb_hmastlock := 0.U
io.sb_hprot := 0.U
io.sb_hsize := 0.U
io.sb_htrans := 0.U
io.sb_hwrite := 0.U
io.sb_hwdata := 0.U
io.dma_hrdata := 0.U
io.dma_hreadyout := 0.U
io.dma_hresp := 0.U
io.ifu_axi_wready := 0.U
io.dma_hresp := 0.U //dbg.io.dma_hresp
io.dmi_reg_rdata := 0.U
}
object SWERV extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_swerv()))
}

73
src/main/scala/exu/el2_exu.scala
View File

@ -4,10 +4,12 @@ import scala.collection._
import chisel3.util._
import include._
import lib._
import chisel3.experimental.chiselName
class el2_exu extends Module with param{
@chiselName
class el2_exu extends Module with el2_lib with RequireAsyncReset{
val io=IO(new el2_exu_IO)
val PREDPIPESIZE = BTB_ADDR_HI - BTB_ADDR_LO + BHT_GHR_SIZE + BTB_BTAG_SIZE
val PREDPIPESIZE = BTB_ADDR_HI - BTB_ADDR_LO + BHT_GHR_SIZE + BTB_BTAG_SIZE +1
val ghr_x_ns = Wire(UInt(BHT_GHR_SIZE.W))
val ghr_d_ns = Wire(UInt(BHT_GHR_SIZE.W))
val ghr_d = Wire(UInt(BHT_GHR_SIZE.W))
@ -18,7 +20,7 @@ class el2_exu extends Module with param{
val data_gate_en =Wire(UInt(1.W))
val csr_rs1_in_d =Wire(UInt(32.W))
val i0_predict_newp_d =Wire(new el2_predict_pkt_t)
val i0_flush_path_d =Wire(UInt(32.W))
val i0_flush_path_d =Wire(UInt(31.W))
val i0_predict_p_d =Wire(new el2_predict_pkt_t)
val i0_pp_r =Wire(new el2_predict_pkt_t)
val i0_predict_p_x =Wire(new el2_predict_pkt_t)
@ -30,6 +32,8 @@ class el2_exu extends Module with param{
io.exu_mp_pkt.br_start_error:=0.U
io.exu_mp_pkt.br_error :=0.U
io.exu_mp_pkt.valid :=0.U
i0_pp_r.toffset := 0.U
val x_data_en = io.dec_data_en(1)
val r_data_en = io.dec_data_en(0)
val x_ctl_en = io.dec_ctl_en(1)
@ -37,31 +41,31 @@ class el2_exu extends Module with param{
val predpipe_d = Cat(io.i0_predict_fghr_d, io.i0_predict_index_d, io.i0_predict_btag_d)
val i0_flush_path_x =rvdffe(i0_flush_path_d,x_data_en.asBool,io.clk,io.scan_mode)
io.exu_csr_rs1_x :=rvdffe(csr_rs1_in_d,x_data_en.asBool,io.clk,io.scan_mode)
i0_predict_p_x :=rvdffe(i0_predict_p_d,x_data_en.asBool,io.clk,io.scan_mode)
val predpipe_x =rvdffe(predpipe_d,x_data_en.asBool,io.clk,io.scan_mode)
val predpipe_r =rvdffe(predpipe_x ,r_data_en.asBool,io.clk,io.scan_mode)
val ghr_x =rvdffe(ghr_x_ns ,x_ctl_en.asBool,io.clk,io.scan_mode)
val i0_pred_correct_upper_x =rvdffe(i0_pred_correct_upper_d ,x_ctl_en.asBool,io.clk,io.scan_mode)
val i0_flush_upper_x =rvdffe(i0_flush_upper_d ,x_ctl_en.asBool,io.clk,io.scan_mode)
val i0_taken_x =rvdffe(i0_taken_d ,x_ctl_en.asBool,io.clk,io.scan_mode)
val i0_valid_x =rvdffe(i0_valid_d ,x_ctl_en.asBool,io.clk,io.scan_mode)
i0_pp_r :=rvdffe(i0_predict_p_x,r_ctl_en.asBool,io.clk,io.scan_mode)
val pred_temp1 =rvdffe(io.pred_correct_npc_x(5,0) ,r_ctl_en.asBool,io.clk,io.scan_mode)
val i0_pred_correct_upper_r =rvdffe(i0_pred_correct_upper_x ,r_ctl_en.asBool,io.clk,io.scan_mode)
val i0_flush_path_upper_r =rvdffe(i0_flush_path_x ,r_data_en.asBool,io.clk,io.scan_mode)
val pred_temp2 =rvdffe(io.pred_correct_npc_x(30,6) ,r_data_en.asBool,io.clk,io.scan_mode)
val i0_flush_path_x =rvdffe(i0_flush_path_d,x_data_en.asBool,clock,io.scan_mode)
io.exu_csr_rs1_x :=rvdffe(csr_rs1_in_d,x_data_en.asBool,clock,io.scan_mode)
i0_predict_p_x :=rvdffe(i0_predict_p_d,x_data_en.asBool,clock,io.scan_mode)
val predpipe_x =rvdffe(predpipe_d,x_data_en.asBool,clock,io.scan_mode)
val predpipe_r =rvdffe(predpipe_x ,r_data_en.asBool,clock,io.scan_mode)
val ghr_x =rvdffe(ghr_x_ns ,x_ctl_en.asBool,clock,io.scan_mode)
val i0_pred_correct_upper_x =rvdffe(i0_pred_correct_upper_d ,x_ctl_en.asBool,clock,io.scan_mode)
val i0_flush_upper_x =rvdffe(i0_flush_upper_d ,x_ctl_en.asBool,clock,io.scan_mode)
val i0_taken_x =rvdffe(i0_taken_d ,x_ctl_en.asBool,clock,io.scan_mode)
val i0_valid_x =rvdffe(i0_valid_d ,x_ctl_en.asBool,clock,io.scan_mode)
i0_pp_r :=rvdffe(i0_predict_p_x,r_ctl_en.asBool,clock,io.scan_mode)
val pred_temp1 =rvdffe(io.pred_correct_npc_x(5,0) ,r_ctl_en.asBool,clock,io.scan_mode)
val i0_pred_correct_upper_r =rvdffe(i0_pred_correct_upper_x ,r_ctl_en.asBool,clock,io.scan_mode)
val i0_flush_path_upper_r =rvdffe(i0_flush_path_x ,r_data_en.asBool,clock,io.scan_mode)
val pred_temp2 =rvdffe(io.pred_correct_npc_x(30,6) ,r_data_en.asBool,clock,io.scan_mode)
pred_correct_npc_r :=Cat(pred_temp2,pred_temp1)
when (BHT_SIZE.asUInt===32.U || BHT_SIZE.asUInt===64.U){
ghr_d :=withClock(io.clk){RegEnable(ghr_d_ns,0.U,data_gate_en.asBool)}
mul_valid_x :=withClock(io.clk){RegEnable(io.mul_p.valid,0.U,data_gate_en.asBool)}
flush_lower_ff :=withClock(io.clk){RegEnable(io.dec_tlu_flush_lower_r,0.U,data_gate_en.asBool)}
ghr_d :=RegEnable(ghr_d_ns,0.U,data_gate_en.asBool)
mul_valid_x :=RegEnable(io.mul_p.valid,0.U,data_gate_en.asBool)
flush_lower_ff :=RegEnable(io.dec_tlu_flush_lower_r,0.U,data_gate_en.asBool)
}.otherwise{
ghr_d :=rvdffe(ghr_d_ns ,data_gate_en.asBool,io.clk,io.scan_mode)
mul_valid_x :=rvdffe(io.mul_p.valid ,data_gate_en.asBool,io.clk,io.scan_mode)
flush_lower_ff :=rvdffe(io.dec_tlu_flush_lower_r ,data_gate_en.asBool,io.clk,io.scan_mode)
ghr_d :=rvdffe(ghr_d_ns ,data_gate_en.asBool,clock,io.scan_mode)
mul_valid_x :=rvdffe(io.mul_p.valid ,data_gate_en.asBool,clock,io.scan_mode)
flush_lower_ff :=rvdffe(io.dec_tlu_flush_lower_r ,data_gate_en.asBool,clock,io.scan_mode)
}
@ -86,11 +90,12 @@ class el2_exu extends Module with param{
(~i0_rs1_bypass_en_d & ~io.dec_debug_wdata_rs1_d & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d
))
val i0_rs2_d=Mux1H(Seq(
val i0_rs2_d = Mux1H(Seq(
(~i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d,
(~i0_rs2_bypass_en_d).asBool -> io.dec_i0_immed_d,
(i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d
))
dontTouch(i0_rs2_d)
io.exu_lsu_rs1_d:=Mux1H(Seq(
(~i0_rs1_bypass_en_d & ~io.dec_extint_stall & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d,
@ -124,7 +129,7 @@ class el2_exu extends Module with param{
i_alu.io.valid_in :=io.dec_i0_alu_decode_d
i_alu.io.flush_upper_x :=i0_flush_upper_x
i_alu.io.flush_lower_r :=io.dec_tlu_flush_lower_r
i_alu.io.a_in :=i0_rs1_d
i_alu.io.a_in :=i0_rs1_d.asSInt
i_alu.io.b_in :=i0_rs2_d
i_alu.io.pc_in :=io.dec_i0_pc_d
i_alu.io.brimm_in :=io.dec_i0_br_immed_d
@ -139,7 +144,6 @@ class el2_exu extends Module with param{
io.exu_i0_pc_x :=i_alu.io.pc_ff
val i_mul=Module(new el2_exu_mul_ctl)
i_mul.io.scan_mode :=io.scan_mode
i_mul.io.mul_p :=io.mul_p
i_mul.io.rs1_in :=muldiv_rs1_d
@ -147,7 +151,6 @@ class el2_exu extends Module with param{
val mul_result_x =i_mul.io.result_x
val i_div=Module(new el2_exu_div_ctl)
i_div.io.scan_mode :=io.scan_mode
i_div.io.cancel :=io.dec_div_cancel
i_div.io.dp :=io.div_p
@ -183,12 +186,12 @@ class el2_exu extends Module with param{
io.exu_i0_br_valid_r := i0_pp_r.valid
io.exu_i0_br_mp_r := i0_pp_r.misp
io.exu_i0_br_way_r := i0_pp_r.way
io.exu_i0_br_hist_r := i0_pp_r.hist
io.exu_i0_br_hist_r := i0_pp_r.hist
io.exu_i0_br_error_r := i0_pp_r.br_error
io.exu_i0_br_middle_r := i0_pp_r.pc4 ^ i0_pp_r.boffset
io.exu_i0_br_start_error_r := i0_pp_r.br_start_error
io.exu_i0_br_fghr_r := predpipe_r(PREDPIPESIZE-1,BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO+1)
io.exu_i0_br_index_r := predpipe_r(BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO,BTB_BTAG_SIZE+1)
io.exu_i0_br_index_r := predpipe_r(BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO,BTB_BTAG_SIZE)
final_predict_mp := Mux(i0_flush_upper_x===1.U,i0_predict_p_x,0.U.asTypeOf(i0_predict_p_x))
val final_predpipe_mp = Mux(i0_flush_upper_x===1.U,predpipe_x,0.U)
@ -213,8 +216,6 @@ class el2_exu extends Module with param{
io.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r)
}
class el2_exu_IO extends Bundle with param{
val clk =Input(Clock()) // Top level clock
val rst_l =Input(Bool()) // Reset
val scan_mode =Input(Bool()) // Scan control
val dec_data_en =Input(UInt(2.W)) // Clock enable {x,r}, one cycle pulse
@ -226,7 +227,7 @@ class el2_exu_IO extends Bundle with param{
val dec_i0_predict_p_d =Input(new el2_predict_pkt_t) // DEC branch predict packet
val i0_predict_fghr_d =Input(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr
val i0_predict_index_d =Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO).W)) // DEC predict index
val i0_predict_index_d =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // DEC predict index
val i0_predict_btag_d =Input(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag
val dec_i0_rs1_en_d =Input(UInt(1.W)) // Qualify GPR RS1 data
@ -272,7 +273,7 @@ class el2_exu_IO extends Bundle with param{
val exu_i0_br_hist_r =Output(UInt(2.W)) // to DEC I0 branch history
val exu_i0_br_error_r =Output(UInt(1.W)) // to DEC I0 branch error
val exu_i0_br_start_error_r =Output(UInt(1.W)) // to DEC I0 branch start error
val exu_i0_br_index_r =Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO).W)) // to DEC I0 branch index
val exu_i0_br_index_r =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // to DEC I0 branch index
val exu_i0_br_valid_r =Output(UInt(1.W)) // to DEC I0 branch valid
val exu_i0_br_mp_r =Output(UInt(1.W)) // to DEC I0 branch mispredict
val exu_i0_br_middle_r =Output(UInt(1.W)) // to DEC I0 branch middle
@ -281,7 +282,7 @@ class el2_exu_IO extends Bundle with param{
val exu_mp_pkt =Output(new el2_predict_pkt_t) // Mispredict branch packet
val exu_mp_eghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict global history
val exu_mp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict fghr
val exu_mp_index =Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO).W)) // Mispredict index
val exu_mp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // Mispredict index
val exu_mp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // Mispredict btag
@ -296,4 +297,4 @@ class el2_exu_IO extends Bundle with param{
object exu_gen extends App{
println(chisel3.Driver.emitVerilog(new el2_exu()))
}
}

22
src/main/scala/exu/el2_exu_alu_ctl.scala
View File

@ -17,7 +17,7 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
val valid_in = Input(UInt(1.W)) // Valid
val ap = Input( new el2_alu_pkt_t ) // predecodes
val csr_ren_in = Input(UInt(1.W)) // extra decode
val a_in = Input(UInt(32.W)) // A operand
val a_in = Input(SInt(32.W)) // A operand
val b_in = Input(UInt(32.W)) // B operand
val pc_in = Input(UInt(31.W)) // for pc=pc+2,4 calculations
val pp_in = Input(new el2_predict_pkt_t) // Predicted branch structure
@ -44,7 +44,7 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
val ov = (~io.a_in(31) & ~bm(31) & aout(31)) | ( io.a_in(31) & bm(31) & ~aout(31) ) //overflow check from last bits
val eq = (io.a_in === io.b_in)
val eq = (io.a_in === io.b_in.asSInt)
val ne = ~eq
val neg = aout(31)// check for the last signed bit (for neg)
val lt = (~io.ap.unsign & (neg ^ ov)) | ( io.ap.unsign & ~cout) //if alu packet sends unsigned and there is no cout(i.e no overflow and unsigned pkt)
@ -52,10 +52,10 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
val lout = Mux1H(Seq(
io.csr_ren_in.asBool -> io.b_in, //read enable read rs2
io.ap.land.asBool -> (io.a_in & io.b_in), //and rs1 and 2
io.ap.lor.asBool -> (io.a_in | io.b_in),
io.ap.lxor.asBool -> (io.a_in ^ io.b_in)))
io.csr_ren_in.asBool -> io.b_in.asSInt, //read enable read rs2
io.ap.land.asBool -> (io.a_in & io.b_in.asSInt), //and rs1 and 2
io.ap.lor.asBool -> (io.a_in | io.b_in.asSInt),
io.ap.lxor.asBool -> (io.a_in ^ io.b_in.asSInt)))
val shift_amount = Mux1H(Seq (
io.ap.sll.asBool -> (32.U(6.W) - Cat(0.U(1.W),io.b_in(4,0))), // [5] unused
@ -69,7 +69,7 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
shift_extend := Cat((repl(31,io.ap.sra) & repl(31,io.a_in(31))) | (repl(31,io.ap.sll) & io.a_in(30,0)),io.a_in)
val shift_long = WireInit(UInt(63.W),0.U)
shift_long := ( shift_extend >> shift_amount ); // 62-32 unused
shift_long := ( shift_extend >> shift_amount(4,0) ); // 62-32 unused
val sout = ( shift_long(31,0) & shift_mask(31,0) ); //incase of sra shift_mask is 1
@ -77,7 +77,7 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
val sel_shift = io.ap.sll | io.ap.srl | io.ap.sra
val sel_adder = (io.ap.add | io.ap.sub) & ~io.ap.slt
val sel_pc = io.ap.jal | io.pp_in.pcall | io.pp_in.pja | io.pp_in.pret
val csr_write_data = Mux(io.ap.csr_imm.asBool, io.b_in, io.a_in)
val csr_write_data = Mux(io.ap.csr_imm.asBool, io.b_in.asSInt, io.a_in)
val slt_one = io.ap.slt & lt
@ -129,5 +129,7 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
}
object alu extends App{
chisel3.Driver execute(args, () =>new el2_exu_alu_ctl())
}
println("Generate Verilog")
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_exu_alu_ctl()))
}

13
src/main/scala/exu/el2_exu_div_ctl.scala
View File

@ -17,8 +17,6 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
val out = Output(UInt(32.W))
val finish_dly = Output(UInt(1.W))
// val out_s = Output(UInt(33.W))
// val test = Output(UInt(6.W))
})
// val exu_div_clk = Wire(Clock())
val run_state = WireInit(0.U(1.W))
@ -48,7 +46,6 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
val count_in = WireInit(0.U(6.W))
val dividend_eff = WireInit(0.U(32.W))
val a_shift = WireInit(0.U(33.W))
// val scan_mode = WireInit(0.U(1.W))
io.out := 0.U
io.finish_dly := 0.U
@ -151,9 +148,6 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
val shortq_enable = valid_ff_x & (m_ff(31,0) =/= 0.U(32.W)) & (shortq_raw =/= 0.U(4.W))
val shortq_shift = Fill(4,shortq_enable) & shortq_raw
// shortq_enable_ff := RegEnable(shortq_enable,0.U,div_clken.asBool)
// shortq_shift_xx := RegEnable(shortq_shift,0.U,div_clken.asBool)
val shortq_shift_ff = Mux1H(Seq (
shortq_shift_xx(3).asBool -> "b11111".U,
shortq_shift_xx(2).asBool -> "b11000".U,
@ -178,7 +172,7 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
(run_state & !(valid_ff_x | shortq_enable_ff)).asBool -> Cat(q_ff(31,0),!a_in(32))
))
val qff_enable = io.dp.valid | (run_state & !shortq_enable)
dividend_eff := Mux((sign_ff & dividend_neg_ff).asBool,rvtwoscomp(q_ff(31,0)),q_ff(31,0))
dividend_eff := Mux((sign_ff & dividend_neg_ff).asBool, rvtwoscomp(q_ff(31,0)),q_ff(31,0))
m_eff := Mux(add.asBool , m_ff, ~m_ff )
@ -223,12 +217,9 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
q_ff := rvdffe(q_in, qff_enable.asBool,clock,io.scan_mode)
a_ff := rvdffe(a_in, aff_enable.asBool,clock,io.scan_mode)
m_ff := rvdffe(Cat(!io.dp.unsign & io.divisor(31), io.divisor), io.dp.valid.asBool,clock,io.scan_mode)
// q_ff := RegEnable (q_in, 0.U, qff_enable.asBool)
// a_ff := RegEnable (a_in, 0.U, aff_enable.asBool)
// m_ff := RegEnable (Cat(!io.dp.unsign & io.divisor(31), io.divisor), 0.U, io.dp.valid.asBool)
}
object div_main extends App{
println("Generate Verilog")
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_exu_div_ctl()))
}
}

12
src/main/scala/exu/el2_exu_mul_ctl.scala
View File

@ -27,12 +27,12 @@ class el2_exu_mul_ctl extends Module with RequireAsyncReset with el2_lib {
rs2_ext_in := Cat(io.mul_p.rs2_sign & io.rs2_in(31),io.rs2_in).asSInt
// --------------------------- Multiply ----------------------------------
// val gated_clock = rvclkhdr(clock,mul_x_enable.asBool(),io.scan_mode)
// withClock(gated_clock) {
// low_x := RegNext(io.mul_p.low, 0.U)
//rs1_x := RegNext(rs1_ext_in, 0.S)
// rs2_x := RegNext(rs2_ext_in, 0.S)
// }
// val gated_clock = rvclkhdr(clock,mul_x_enable.asBool(),io.scan_mode)
// withClock(gated_clock) {
// low_x := RegNext(io.mul_p.low, 0.U)
//rs1_x := RegNext(rs1_ext_in, 0.S)
// rs2_x := RegNext(rs2_ext_in, 0.S)
// }
low_x := rvdffe (io.mul_p.low, mul_x_enable.asBool,clock,io.scan_mode)
rs1_x := rvdffe(rs1_ext_in, mul_x_enable.asBool,clock,io.scan_mode)
rs2_x := rvdffe (rs2_ext_in, mul_x_enable.asBool,clock,io.scan_mode)

344
src/main/scala/ifu/el2_ifu.scala Normal file
View File

@ -0,0 +1,344 @@
package ifu
import chisel3._
import chisel3.internal.naming.chiselName
import chisel3.util._
import lib._
import include._
class el2_ifu extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{
val free_clk = Input(Clock())
val active_clk = Input(Clock())
val dec_i0_decode_d = Input(Bool())
val exu_flush_final = Input(Bool())
val dec_tlu_i0_commit_cmt = Input(Bool())
val dec_tlu_flush_err_wb = Input(Bool())
val dec_tlu_flush_noredir_wb = Input(Bool())
val exu_flush_path_final = Input(UInt(31.W))
val dec_tlu_mrac_ff = Input(UInt(32.W))
val dec_tlu_fence_i_wb = Input(Bool())
val dec_tlu_flush_leak_one_wb = Input(Bool())
val dec_tlu_bpred_disable = Input(Bool())
val dec_tlu_core_ecc_disable = Input(Bool())
val dec_tlu_force_halt = Input(Bool())
// AXI Write Channel
val ifu_axi_awvalid = Output(Bool())
val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_awaddr = Output(UInt(32.W))
val ifu_axi_awregion = Output(UInt(4.W))
val ifu_axi_awlen = Output(UInt(8.W))
val ifu_axi_awsize = Output(UInt(3.W))
val ifu_axi_awburst = Output(UInt(2.W))
val ifu_axi_awlock = Output(Bool())
val ifu_axi_awcache = Output(UInt(4.W))
val ifu_axi_awprot = Output(UInt(3.W))
val ifu_axi_awqos = Output(UInt(4.W))
val ifu_axi_wvalid = Output(Bool())
val ifu_axi_wdata = Output(UInt(64.W))
val ifu_axi_wstrb = Output(UInt(8.W))
val ifu_axi_wlast = Output(Bool())
val ifu_axi_bready = Output(Bool())
// AXI Read Channel
val ifu_axi_arvalid = Output(Bool())
val ifu_axi_arready = Input(Bool())
val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_araddr = Output(UInt(32.W))
val ifu_axi_arregion = Output(UInt(4.W))
val ifu_axi_arlen = Output(UInt(8.W))
val ifu_axi_arsize = Output(UInt(3.W))
val ifu_axi_arburst = Output(UInt(2.W))
val ifu_axi_arlock = Output(Bool())
val ifu_axi_arcache = Output(UInt(4.W))
val ifu_axi_arprot = Output(UInt(3.W))
val ifu_axi_arqos = Output(UInt(4.W))
val ifu_axi_rvalid = Input(Bool())
val ifu_axi_rready = Output(Bool())
val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
val ifu_axi_rdata = Input(UInt(64.W))
val ifu_axi_rresp = Input(UInt(2.W))
val ifu_bus_clk_en = Input(Bool())
// DMA signals
val dma_iccm_req = Input(Bool())
val dma_mem_addr = Input(UInt(32.W))
val dma_mem_sz = Input(UInt(3.W))
val dma_mem_write = Input(Bool())
val dma_mem_wdata = Input(UInt(64.W))
val dma_mem_tag = Input(UInt(3.W))
val dma_iccm_stall_any = Input(Bool())
// ICCM
val iccm_dma_ecc_error = Output(Bool())
val iccm_dma_rvalid = Output(Bool())
val iccm_dma_rdata = Output(UInt(64.W))
val iccm_dma_rtag = Output(UInt(3.W))
val iccm_ready = Output(Bool())
val ifu_pmu_instr_aligned = Output(Bool())
val ifu_pmu_fetch_stall = Output(Bool())
val ifu_ic_error_start = Output(Bool())
// I$
val ic_rw_addr = Output(UInt(31.W))
val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_en = Output(Bool())
val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
val ic_rd_data = Input(UInt(64.W))
val ic_debug_rd_data = Input(UInt(71.W))
val ictag_debug_rd_data = Input(UInt(26.W))
val ic_debug_wr_data = Output(UInt(71.W))
val ifu_ic_debug_rd_data = Output(UInt(71.W))
val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_premux_data = Output(UInt(64.W))
val ic_sel_premux_data = Output(Bool())
val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W))
val ic_debug_rd_en = Output(Bool())
val ic_debug_wr_en = Output(Bool())
val ic_debug_tag_array = Output(Bool())
val ic_debug_way = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_perr = Input(Bool())
// ICCM cont'd
val iccm_rw_addr = Output(UInt((ICCM_BITS-1).W))
val iccm_wren = Output(Bool())
val iccm_rden = Output(Bool())
val iccm_wr_data = Output(UInt(78.W))
val iccm_wr_size = Output(UInt(3.W))
val iccm_rd_data = Input(UInt(64.W))
val iccm_rd_data_ecc = Input(UInt(78.W))
val ifu_iccm_rd_ecc_single_err = Output(Bool())
// Performance counter
val ifu_pmu_ic_miss = Output(Bool())
val ifu_pmu_ic_hit = Output(Bool())
val ifu_pmu_bus_error = Output(Bool())
val ifu_pmu_bus_busy = Output(Bool())
val ifu_pmu_bus_trxn = Output(Bool())
//
val ifu_i0_icaf = Output(Bool())
val ifu_i0_icaf_type = Output(UInt(2.W))
val ifu_i0_valid = Output(Bool())
val ifu_i0_icaf_f1 = Output(Bool())
val ifu_i0_dbecc = Output(Bool())
val iccm_dma_sb_error = Output(Bool())
val ifu_i0_instr = Output(UInt(32.W))
val ifu_i0_pc = Output(UInt(31.W))
val ifu_i0_pc4 = Output(Bool())
val ifu_miss_state_idle = Output(Bool())
// Aligner branch data
val i0_brp = Output(new el2_br_pkt_t)
val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
// BP Inputs
val exu_mp_pkt = Input(new el2_predict_pkt_t)
val exu_mp_eghr = Input(UInt(BHT_GHR_SIZE.W))
val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W))
val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index
val exu_mp_btag = Input(UInt(BTB_BTAG_SIZE.W))
val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t)
val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu
val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
val dec_tlu_flush_lower_wb = Input(Bool())
val ifu_i0_cinst = Output(UInt(16.W))
val dec_tlu_ic_diag_pkt = Input(new el2_cache_debug_pkt_t)
val ifu_ic_debug_rd_data_valid = Output(Bool())
val iccm_buf_correct_ecc = Output(Bool())
val iccm_correction_state = Output(Bool())
val scan_mode = Input(Bool())
})
val mem_ctl_ch = Module(new el2_ifu_mem_ctl)
val bp_ctl_ch = Module(new el2_ifu_bp_ctl)
val aln_ctl_ch = Module(new el2_ifu_aln_ctl)
val ifc_ctl_ch = Module(new el2_ifu_ifc_ctl)
// IFC wiring Inputs
ifc_ctl_ch.io.active_clk := io.active_clk
ifc_ctl_ch.io.free_clk := io.free_clk
ifc_ctl_ch.io.scan_mode := io.scan_mode
ifc_ctl_ch.io.ic_hit_f := mem_ctl_ch.io.ic_hit_f
ifc_ctl_ch.io.ifu_fb_consume1 := aln_ctl_ch.io.ifu_fb_consume1
ifc_ctl_ch.io.ifu_fb_consume2 := aln_ctl_ch.io.ifu_fb_consume2
ifc_ctl_ch.io.dec_tlu_flush_noredir_wb := io.dec_tlu_flush_noredir_wb
ifc_ctl_ch.io.exu_flush_final := io.exu_flush_final
ifc_ctl_ch.io.exu_flush_path_final := io.exu_flush_path_final
ifc_ctl_ch.io.ifu_bp_hit_taken_f := bp_ctl_ch.io.ifu_bp_hit_taken_f
ifc_ctl_ch.io.ifu_bp_btb_target_f := bp_ctl_ch.io.ifu_bp_btb_target_f
ifc_ctl_ch.io.ic_dma_active := mem_ctl_ch.io.ic_dma_active
ifc_ctl_ch.io.ic_write_stall := mem_ctl_ch.io.ic_write_stall
ifc_ctl_ch.io.dma_iccm_stall_any := io.dma_iccm_stall_any
ifc_ctl_ch.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff
ifc_ctl_ch.io.ifu_ic_mb_empty := mem_ctl_ch.io.ifu_ic_mb_empty
// Input complete
// ALN wiring Inputs
aln_ctl_ch.io.scan_mode := io.scan_mode
aln_ctl_ch.io.active_clk := io.active_clk
aln_ctl_ch.io.ifu_async_error_start := mem_ctl_ch.io.ifu_async_error_start
aln_ctl_ch.io.iccm_rd_ecc_double_err := mem_ctl_ch.io.iccm_rd_ecc_double_err
aln_ctl_ch.io.ic_access_fault_f := mem_ctl_ch.io.ic_access_fault_f
aln_ctl_ch.io.ic_access_fault_type_f := mem_ctl_ch.io.ic_access_fault_type_f
aln_ctl_ch.io.ifu_bp_fghr_f := bp_ctl_ch.io.ifu_bp_fghr_f
aln_ctl_ch.io.ifu_bp_btb_target_f := bp_ctl_ch.io.ifu_bp_btb_target_f
aln_ctl_ch.io.ifu_bp_poffset_f := bp_ctl_ch.io.ifu_bp_poffset_f
aln_ctl_ch.io.ifu_bp_hist0_f := bp_ctl_ch.io.ifu_bp_hist0_f
aln_ctl_ch.io.ifu_bp_hist1_f := bp_ctl_ch.io.ifu_bp_hist1_f
aln_ctl_ch.io.ifu_bp_pc4_f := bp_ctl_ch.io.ifu_bp_pc4_f
aln_ctl_ch.io.ifu_bp_way_f := bp_ctl_ch.io.ifu_bp_way_f
aln_ctl_ch.io.ifu_bp_valid_f := bp_ctl_ch.io.ifu_bp_valid_f
aln_ctl_ch.io.ifu_bp_ret_f := bp_ctl_ch.io.ifu_bp_ret_f
aln_ctl_ch.io.exu_flush_final := io.exu_flush_final
aln_ctl_ch.io.dec_i0_decode_d := io.dec_i0_decode_d
aln_ctl_ch.io.ifu_fetch_data_f := mem_ctl_ch.io.ic_data_f
aln_ctl_ch.io.ifu_fetch_val := mem_ctl_ch.io.ifu_fetch_val
aln_ctl_ch.io.ifu_fetch_pc := ifc_ctl_ch.io.ifc_fetch_addr_f
// BP wiring Inputs
bp_ctl_ch.io.scan_mode := io.scan_mode
bp_ctl_ch.io.active_clk := io.active_clk
bp_ctl_ch.io.ic_hit_f := mem_ctl_ch.io.ic_hit_f
bp_ctl_ch.io.ifc_fetch_addr_f := ifc_ctl_ch.io.ifc_fetch_addr_f
bp_ctl_ch.io.ifc_fetch_req_f := ifc_ctl_ch.io.ifc_fetch_req_f
bp_ctl_ch.io.dec_tlu_br0_r_pkt <> io.dec_tlu_br0_r_pkt
bp_ctl_ch.io.exu_i0_br_fghr_r := io.exu_i0_br_fghr_r
bp_ctl_ch.io.exu_i0_br_index_r := io.exu_i0_br_index_r
bp_ctl_ch.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
bp_ctl_ch.io.dec_tlu_flush_leak_one_wb := io.dec_tlu_flush_leak_one_wb
bp_ctl_ch.io.dec_tlu_bpred_disable := io.dec_tlu_bpred_disable
bp_ctl_ch.io.exu_mp_pkt <> io.exu_mp_pkt
bp_ctl_ch.io.exu_mp_eghr := io.exu_mp_eghr
bp_ctl_ch.io.exu_mp_fghr := io.exu_mp_fghr
bp_ctl_ch.io.exu_mp_index := io.exu_mp_index
bp_ctl_ch.io.exu_mp_btag := io.exu_mp_btag
bp_ctl_ch.io.exu_flush_final := io.exu_flush_final
// mem-ctl wiring
mem_ctl_ch.io.free_clk := io.free_clk
mem_ctl_ch.io.active_clk := io.active_clk
mem_ctl_ch.io.exu_flush_final := io.exu_flush_final
mem_ctl_ch.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
mem_ctl_ch.io.dec_tlu_flush_err_wb := io.dec_tlu_flush_err_wb
mem_ctl_ch.io.dec_tlu_i0_commit_cmt := io.dec_tlu_i0_commit_cmt
mem_ctl_ch.io.dec_tlu_force_halt := io.dec_tlu_force_halt
mem_ctl_ch.io.ifc_fetch_addr_bf := ifc_ctl_ch.io.ifc_fetch_addr_bf
mem_ctl_ch.io.ifc_fetch_uncacheable_bf := ifc_ctl_ch.io.ifc_fetch_uncacheable_bf
mem_ctl_ch.io.ifc_fetch_req_bf := ifc_ctl_ch.io.ifc_fetch_req_bf
mem_ctl_ch.io.ifc_fetch_req_bf_raw := ifc_ctl_ch.io.ifc_fetch_req_bf_raw
mem_ctl_ch.io.ifc_iccm_access_bf := ifc_ctl_ch.io.ifc_iccm_access_bf
mem_ctl_ch.io.ifc_region_acc_fault_bf := ifc_ctl_ch.io.ifc_region_acc_fault_bf
mem_ctl_ch.io.ifc_dma_access_ok := ifc_ctl_ch.io.ifc_dma_access_ok
mem_ctl_ch.io.dec_tlu_fence_i_wb := io.dec_tlu_fence_i_wb
mem_ctl_ch.io.ifu_bp_hit_taken_f := bp_ctl_ch.io.ifu_bp_hit_taken_f
mem_ctl_ch.io.ifu_bp_inst_mask_f := bp_ctl_ch.io.ifu_bp_inst_mask_f
mem_ctl_ch.io.ifu_axi_arready := io.ifu_axi_arready
mem_ctl_ch.io.ifu_axi_rvalid := io.ifu_axi_rvalid
mem_ctl_ch.io.ifu_axi_rid := io.ifu_axi_rid
mem_ctl_ch.io.ifu_axi_rdata := io.ifu_axi_rdata
mem_ctl_ch.io.ifu_axi_rresp := io.ifu_axi_rresp
mem_ctl_ch.io.ifu_bus_clk_en := io.ifu_bus_clk_en
mem_ctl_ch.io.dma_iccm_req := io.dma_iccm_req
mem_ctl_ch.io.dma_mem_addr := io.dma_mem_addr
mem_ctl_ch.io.dma_mem_sz := io.dma_mem_sz
mem_ctl_ch.io.dma_mem_write := io.dma_mem_write
mem_ctl_ch.io.dma_mem_wdata := io.dma_mem_wdata
mem_ctl_ch.io.dma_mem_tag := io.dma_mem_tag
mem_ctl_ch.io.ic_rd_data := io.ic_rd_data
mem_ctl_ch.io.ic_debug_rd_data := io.ic_debug_rd_data
mem_ctl_ch.io.ictag_debug_rd_data := io.ictag_debug_rd_data
mem_ctl_ch.io.ic_eccerr := io.ic_eccerr
mem_ctl_ch.io.ic_parerr := io.ic_parerr
mem_ctl_ch.io.ic_rd_hit := io.ic_rd_hit
mem_ctl_ch.io.ic_tag_perr := io.ic_tag_perr
mem_ctl_ch.io.iccm_rd_data := io.iccm_rd_data
mem_ctl_ch.io.iccm_rd_data_ecc := io.iccm_rd_data_ecc
mem_ctl_ch.io.ifu_fetch_val := mem_ctl_ch.io.ic_fetch_val_f
mem_ctl_ch.io.dec_tlu_ic_diag_pkt <> io.dec_tlu_ic_diag_pkt
mem_ctl_ch.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable
mem_ctl_ch.io.scan_mode := io.scan_mode
// Connecting the final outputs
io.ifu_axi_awvalid := mem_ctl_ch.io.ifu_axi_awvalid
io.ifu_axi_awid := mem_ctl_ch.io.ifu_axi_awid
io.ifu_axi_awaddr := mem_ctl_ch.io.ifu_axi_awaddr
io.ifu_axi_awregion := mem_ctl_ch.io.ifu_axi_awregion
io.ifu_axi_awlen := mem_ctl_ch.io.ifu_axi_awlen
io.ifu_axi_awsize := mem_ctl_ch.io.ifu_axi_awsize
io.ifu_axi_awburst := mem_ctl_ch.io.ifu_axi_awburst
io.ifu_axi_awlock := mem_ctl_ch.io.ifu_axi_awlock
io.ifu_axi_awcache := mem_ctl_ch.io.ifu_axi_awcache
io.ifu_axi_awprot := mem_ctl_ch.io.ifu_axi_awprot
io.ifu_axi_awqos := mem_ctl_ch.io.ifu_axi_awqos
io.ifu_axi_wvalid := mem_ctl_ch.io.ifu_axi_wvalid
io.ifu_axi_wdata := mem_ctl_ch.io.ifu_axi_wdata
io.ifu_axi_wstrb := mem_ctl_ch.io.ifu_axi_wstrb
io.ifu_axi_wlast := mem_ctl_ch.io.ifu_axi_wlast
io.ifu_axi_bready := mem_ctl_ch.io.ifu_axi_bready
// AXI Read Channel
io.ifu_axi_arvalid := mem_ctl_ch.io.ifu_axi_arvalid
io.ifu_axi_arid := mem_ctl_ch.io.ifu_axi_arid
io.ifu_axi_araddr := mem_ctl_ch.io.ifu_axi_araddr
io.ifu_axi_arregion := mem_ctl_ch.io.ifu_axi_arregion
io.ifu_axi_arlen := mem_ctl_ch.io.ifu_axi_arlen
io.ifu_axi_arsize := mem_ctl_ch.io.ifu_axi_arsize
io.ifu_axi_arburst := mem_ctl_ch.io.ifu_axi_arburst
io.ifu_axi_arlock := mem_ctl_ch.io.ifu_axi_arlock
io.ifu_axi_arcache := mem_ctl_ch.io.ifu_axi_arcache
io.ifu_axi_arprot := mem_ctl_ch.io.ifu_axi_arprot
io.ifu_axi_arqos := mem_ctl_ch.io.ifu_axi_arqos
io.ifu_axi_rready := mem_ctl_ch.io.ifu_axi_rready
io.iccm_dma_ecc_error := mem_ctl_ch.io.iccm_dma_ecc_error
io.iccm_dma_rvalid := mem_ctl_ch.io.iccm_dma_rvalid
io.iccm_dma_rdata := mem_ctl_ch.io.iccm_dma_rdata
io.iccm_dma_rtag := mem_ctl_ch.io.iccm_dma_rtag
io.iccm_ready := mem_ctl_ch.io.iccm_ready
io.ifu_pmu_instr_aligned := aln_ctl_ch.io.ifu_pmu_instr_aligned
io.ifu_pmu_fetch_stall := ifc_ctl_ch.io.ifu_pmu_fetch_stall
io.ifu_ic_error_start := mem_ctl_ch.io.ic_error_start
// I$
io.ic_rw_addr := mem_ctl_ch.io.ic_rw_addr
io.ic_wr_en := mem_ctl_ch.io.ic_wr_en
io.ic_rd_en := mem_ctl_ch.io.ic_rd_en
io.ic_wr_data := mem_ctl_ch.io.ic_wr_data
io.ic_debug_wr_data := mem_ctl_ch.io.ic_debug_wr_data
io.ifu_ic_debug_rd_data := mem_ctl_ch.io.ifu_ic_debug_rd_data
io.ic_sel_premux_data := mem_ctl_ch.io.ic_sel_premux_data
io.ic_debug_addr := mem_ctl_ch.io.ic_debug_addr
io.ic_debug_rd_en := mem_ctl_ch.io.ic_debug_rd_en
io.ic_debug_wr_en := mem_ctl_ch.io.ic_debug_wr_en
io.ic_debug_tag_array := mem_ctl_ch.io.ic_debug_tag_array
io.ic_debug_way := mem_ctl_ch.io.ic_debug_way
io.ic_tag_valid := mem_ctl_ch.io.ic_tag_valid
io.iccm_rw_addr := mem_ctl_ch.io.iccm_rw_addr
io.iccm_wren := mem_ctl_ch.io.iccm_wren
io.iccm_rden := mem_ctl_ch.io.iccm_rden
io.iccm_wr_data := mem_ctl_ch.io.iccm_wr_data
io.iccm_wr_size := mem_ctl_ch.io.iccm_wr_size
io.ifu_iccm_rd_ecc_single_err := mem_ctl_ch.io.iccm_rd_ecc_single_err
// Performance counter
io.ifu_pmu_ic_miss := mem_ctl_ch.io.ifu_pmu_ic_miss
io.ifu_pmu_ic_hit := mem_ctl_ch.io.ifu_pmu_ic_hit
io.ifu_pmu_bus_error := mem_ctl_ch.io.ifu_pmu_bus_error
io.ifu_pmu_bus_busy := mem_ctl_ch.io.ifu_pmu_bus_busy
io.ifu_pmu_bus_trxn := mem_ctl_ch.io.ifu_pmu_bus_trxn
//
io.ifu_i0_icaf := aln_ctl_ch.io.ifu_i0_icaf
io.ifu_i0_icaf_type := aln_ctl_ch.io.ifu_i0_icaf_type
io.ifu_i0_valid := aln_ctl_ch.io.ifu_i0_valid
io.ifu_i0_icaf_f1 := aln_ctl_ch.io.ifu_i0_icaf_f1
io.ifu_i0_dbecc := aln_ctl_ch.io.ifu_i0_dbecc
io.iccm_dma_sb_error := mem_ctl_ch.io.iccm_dma_sb_error
io.ifu_i0_instr := aln_ctl_ch.io.ifu_i0_instr
io.ifu_i0_pc := aln_ctl_ch.io.ifu_i0_pc
io.ifu_i0_pc4 := aln_ctl_ch.io.ifu_i0_pc4
io.ifu_miss_state_idle := mem_ctl_ch.io.ifu_miss_state_idle
// Aligner branch data
io.i0_brp <> aln_ctl_ch.io.i0_brp
io.ifu_i0_bp_index := aln_ctl_ch.io.ifu_i0_bp_index
io.ifu_i0_bp_fghr := aln_ctl_ch.io.ifu_i0_bp_fghr
io.ifu_i0_bp_btag := aln_ctl_ch.io.ifu_i0_bp_btag
io.ifu_i0_cinst := aln_ctl_ch.io.ifu_i0_cinst
io.ifu_ic_debug_rd_data_valid := mem_ctl_ch.io.ifu_ic_debug_rd_data_valid
io.iccm_buf_correct_ecc := mem_ctl_ch.io.iccm_buf_correct_ecc
io.iccm_correction_state := mem_ctl_ch.io.iccm_correction_state
io.ic_premux_data := mem_ctl_ch.io.ic_premux_data
}
object ifu_comp extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu()))
}

421
src/main/scala/ifu/el2_ifu_aln_ctl.scala Normal file
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package ifu
import lib._
import chisel3._
import chisel3.util._
import include._
class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{
val scan_mode = Input(Bool())
val active_clk = Input(Clock())
val ifu_async_error_start = Input(Bool())
val iccm_rd_ecc_double_err = Input(Bool())
val ic_access_fault_f = Input(Bool())
val ic_access_fault_type_f = Input(UInt(2.W))
val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W))
val ifu_bp_btb_target_f = Input(UInt(31.W))
val ifu_bp_poffset_f = Input(UInt(12.W))
val ifu_bp_hist0_f = Input(UInt(2.W))
val ifu_bp_hist1_f = Input(UInt(2.W))
val ifu_bp_pc4_f = Input(UInt(2.W))
val ifu_bp_way_f = Input(UInt(2.W))
val ifu_bp_valid_f = Input(UInt(2.W))
val ifu_bp_ret_f = Input(UInt(2.W))
val exu_flush_final = Input(Bool())
val dec_i0_decode_d = Input(Bool())
val ifu_fetch_data_f = Input(UInt(32.W))
val ifu_fetch_val = Input(UInt(2.W))
val ifu_fetch_pc = Input(UInt(31.W))
/////////////////////////////////////////////////
val ifu_i0_valid = Output(Bool())
val ifu_i0_icaf = Output(Bool())
val ifu_i0_icaf_type = Output(UInt(2.W))
val ifu_i0_icaf_f1 = Output(Bool())
val ifu_i0_dbecc = Output(Bool())
val ifu_i0_instr = Output(UInt(32.W))
val ifu_i0_pc = Output(UInt(31.W))
val ifu_i0_pc4 = Output(Bool())
val ifu_fb_consume1 = Output(Bool())
val ifu_fb_consume2 = Output(Bool())
val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
val ifu_pmu_instr_aligned = Output(Bool())
val ifu_i0_cinst = Output(UInt(16.W))
val i0_brp = Output(new el2_br_pkt_t)
})
io.ifu_i0_valid := 0.U
io.ifu_i0_icaf := 0.U
io.ifu_i0_icaf_type := 0.U
io.ifu_i0_icaf_f1 := 0.U
io.ifu_i0_dbecc := 0.U
io.ifu_i0_instr := 0.U
io.ifu_i0_pc := 0.U
io.ifu_i0_pc4 := 0.U
io.ifu_fb_consume1 := 0.U
io.ifu_fb_consume2 := 0.U
io.ifu_i0_bp_index := 0.U
io.ifu_i0_bp_fghr := 0.U
io.ifu_i0_bp_btag := 0.U
io.ifu_pmu_instr_aligned := 0.U
io.ifu_i0_cinst := 0.U
val MHI = 46+BHT_GHR_SIZE // 54
val MSIZE = 47+BHT_GHR_SIZE // 55
val BRDATA_SIZE = 12
val error_stall_in = WireInit(Bool(),0.U)
val alignval = WireInit(UInt(2.W), 0.U)
val q0final = WireInit(UInt(32.W), 0.U)
val q1final = WireInit(UInt(16.W), 0.U)
val wrptr_in = WireInit(UInt(2.W), init = 0.U)
val rdptr_in = WireInit(UInt(2.W), init = 0.U)
val f2val_in = WireInit(UInt(2.W), init = 0.U)
val f1val_in = WireInit(UInt(2.W), init = 0.U)
val f0val_in = WireInit(UInt(2.W), init = 0.U)
val q2off_in = WireInit(UInt(1.W), init = 0.U)
val q1off_in = WireInit(UInt(1.W), init = 0.U)
val q0off_in = WireInit(UInt(1.W), init = 0.U)
val sf0_valid = WireInit(Bool(), init = 0.U)
val sf1_valid = WireInit(Bool(), init = 0.U)
val f2_valid = WireInit(Bool(), init = 0.U)
val ifvalid = WireInit(Bool(), init = 0.U)
val shift_f2_f1 = WireInit(Bool(), init = 0.U)
val shift_f2_f0 = WireInit(Bool(), init = 0.U)
val shift_f1_f0 = WireInit(Bool(), init = 0.U)
val f0icaf = WireInit(Bool(), init = 0.U)
val f1icaf = WireInit(Bool(), init = 0.U)
val sf0val = WireInit(UInt(2.W), 0.U)
val sf1val = WireInit(UInt(2.W), 0.U)
val misc0 = WireInit(UInt((MHI+1).W), 0.U)
val misc1 = WireInit(UInt((MHI+1).W), 0.U)
val misc2 = WireInit(UInt((MHI+1).W), 0.U)
val brdata1 = WireInit(UInt(12.W), init = 0.U)
val brdata0 = WireInit(UInt(12.W), init = 0.U)
val brdata2 = WireInit(UInt(12.W), init = 0.U)
val q0 = WireInit(UInt(32.W), init = 0.U)
val q1 = WireInit(UInt(32.W), init = 0.U)
val q2 = WireInit(UInt(32.W), init = 0.U)
val f1pc_in = WireInit(UInt(31.W), 0.U)
val f0pc_in = WireInit(UInt(31.W), 0.U)
val error_stall = WireInit(Bool(), 0.U)
val f2_wr_en = WireInit(Bool(), 0.U)
val shift_4B = WireInit(Bool(), 0.U)
val f1_shift_wr_en = WireInit(Bool(), 0.U)
val f0_shift_wr_en = WireInit(Bool(), 0.U)
val qwen = WireInit(UInt(3.W), 0.U)
val brdata_in = WireInit(UInt(BRDATA_SIZE.W), 0.U)
val misc_data_in = WireInit(UInt((MHI+1).W), 0.U)
val fetch_to_f0 = WireInit(Bool(), 0.U)
val fetch_to_f1 = WireInit(Bool(), 0.U)
val fetch_to_f2 = WireInit(Bool(), 0.U)
val f1_shift_2B = WireInit(Bool(), 0.U)
val first4B = WireInit(Bool(), 0.U)
val shift_2B = WireInit(Bool(), 0.U)
val f0_shift_2B = WireInit(Bool(), 0.U)
error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)}
val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode)
val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode)
val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode)
brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode)
brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode)
brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode)
misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode)
misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode)
misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode)
q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode)
q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode)
q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode)
f2_wr_en := fetch_to_f2
f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B
f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
(qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
(qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U,
(qren(0) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 2.U,
(qren(1) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 0.U,
(qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U,
(!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr))
wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U,
(qwen(1) & !io.exu_flush_final).asBool -> 2.U,
(qwen(2) & !io.exu_flush_final).asBool -> 0.U,
(!ifvalid & !io.exu_flush_final).asBool->wrptr))
q2off_in := Mux1H(Seq((!qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B),
(!qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B),
(!qwen(2) & (rdptr===0.U)).asBool->q2off))
q1off_in := Mux1H(Seq((!qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B),
(!qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B),
(!qwen(1) & (rdptr===2.U)).asBool->q1off))
q0off_in := Mux1H(Seq((!qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B),
(!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B),
(!qwen(0) & (rdptr===1.U)).asBool -> q0off))
val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off,
(rdptr===1.U)->q1off,
(rdptr===2.U)->q2off))
val q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off))
val q0sel = Cat(q0ptr, !q0ptr)
val q1sel = Cat(q1ptr, !q1ptr)
misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f,
io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0),
qren(1).asBool()->Cat(misc2, misc1),
qren(2).asBool()->Cat(misc0, misc2)))
val misc1eff = misceff(misceff.getWidth-1,MHI+1)
val misc0eff = misceff(MHI, 0)
val f1dbecc = misc1eff(misc1eff.getWidth-1)
f1icaf := misc1eff(misc1eff.getWidth-2)
val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0)
val f0dbecc = misc0eff(misc1eff.getWidth-1)
f0icaf := misc0eff(misc1eff.getWidth-2)
val f0ictype = misc0eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
val f0prett = misc0eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0),
qren(1).asBool->Cat(brdata2,brdata1),
qren(2).asBool->Cat(brdata0,brdata2)))
val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
val f0ret = Cat(brdata0final(6),brdata0final(0))
val f0brend = Cat(brdata0final(7),brdata0final(1))
val f0way = Cat(brdata0final(8),brdata0final(2))
val f0pc4 = Cat(brdata0final(9),brdata0final(3))
val f0hist0 = Cat(brdata0final(10),brdata0final(4))
val f0hist1 = Cat(brdata0final(11),brdata0final(5))
val f1ret = Cat(brdata1final(6),brdata1final(0))
val f1brend = Cat(brdata1final(7),brdata1final(1))
val f1way = Cat(brdata1final(8),brdata1final(2))
val f1pc4 = Cat(brdata1final(9),brdata1final(3))
val f1hist0 = Cat(brdata1final(10),brdata1final(4))
val f1hist1 = Cat(brdata1final(11),brdata1final(5))
f2_valid := f2val(0)
sf1_valid := sf1val(0)
sf0_valid := sf0val(0)
val consume_fb0 = !sf0val(0) & f0val(0)
val consume_fb1 = !sf1val(0) & f1val(0)
io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final
io.ifu_fb_consume2 := consume_fb0 & consume_fb1 & !io.exu_flush_final
ifvalid := io.ifu_fetch_val(0)
shift_f1_f0 := !sf0_valid & sf1_valid
shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid
shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid
fetch_to_f0 := !sf0_valid & !sf1_valid & !f2_valid & ifvalid
fetch_to_f1 := (!sf0_valid & !sf1_valid & f2_valid & ifvalid) |
(!sf0_valid & sf1_valid & !f2_valid & ifvalid) |
( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
fetch_to_f2 := (!sf0_valid & sf1_valid & f2_valid & ifvalid) |
( sf0_valid & sf1_valid & !f2_valid & ifvalid)
val f0pc_plus1 = f0pc + 1.U
val f1pc_plus1 = f1pc + 1.U
val sf1pc = (Fill(31, f1_shift_2B) & f1pc_plus1) | (Fill(31, !f1_shift_2B) & f1pc)
f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
shift_f2_f1.asBool->f2pc,
(!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc))
f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
shift_f2_f0.asBool->f2pc,
shift_f1_f0.asBool->sf1pc,
(!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1))
f2val_in := Mux1H(Seq((fetch_to_f2 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
(!fetch_to_f2 & !shift_f2_f1 & !shift_f2_f0 & !io.exu_flush_final).asBool->f2val))
sf1val := Mux1H(Seq(f1_shift_2B.asBool->f1val(1), !f1_shift_2B.asBool->f1val))
f1val_in := Mux1H(Seq(( fetch_to_f1 & !io.exu_flush_final).asBool -> io.ifu_fetch_val,
( shift_f2_f1 & !io.exu_flush_final).asBool->f2val,
(!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1)),
(!shift_2B & !shift_4B).asBool->f0val))
f0val_in := Mux1H(Seq((fetch_to_f0 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
( shift_f2_f0 & !io.exu_flush_final).asBool->f2val,
( shift_f1_f0 & !io.exu_flush_final).asBool->sf1val,
(!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val))
val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
qren(1).asBool->Cat(q2,q1),
qren(2).asBool->Cat(q0,q2)))
val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
q0final := Mux1H(Seq(q0sel(0).asBool->q0eff, q0sel(1).asBool->q0eff(31,16)))
q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16)))
val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0))))
alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U)))
val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
val aligndbecc = Mux1H(Seq(f0val(1).asBool -> Fill(2,f0dbecc), (!f0val(1) & f0val(0)).asBool -> Cat(f1dbecc,f0dbecc)))
val alignbrend = Mux1H(Seq(f0val(1).asBool()->f0brend, (!f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0))))
val alignpc4 = Mux1H(Seq(f0val(1).asBool()->f0pc4, (!f0val(1) & f0val(0)).asBool->Cat(f1pc4(0),f0pc4(0))))
val alignret = Mux1H(Seq(f0val(1).asBool()->f0ret, (!f0val(1) & f0val(0)).asBool->Cat(f1ret(0),f0ret(0))))
val alignway = Mux1H(Seq(f0val(1).asBool()->f0way, (!f0val(1) & f0val(0)).asBool->Cat(f1way(0),f0way(0))))
val alignhist1 = Mux1H(Seq(f0val(1).asBool()->f0hist1, (!f0val(1) & f0val(0)).asBool->Cat(f1hist1(0),f0hist1(0))))
val alignhist0 = Mux1H(Seq(f0val(1).asBool()->f0hist0, (!f0val(1) & f0val(0)).asBool->Cat(f1hist0(0),f0hist0(0))))
val alignfromf1 = !f0val(1) & f0val(0)
val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc))
io.ifu_i0_pc := f0pc
val firstpc = f0pc
io.ifu_i0_pc4 := first4B
io.ifu_i0_cinst := aligndata(15,0)
first4B := aligndata(1,0) === 3.U
val first2B = ~first4B
io.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
io.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
io.ifu_i0_icaf_type := Mux((first4B & !f0val(1) & f0val(0) & !alignicaf(0) & !aligndbecc(0)).asBool, f1ictype, f0ictype)
val icaf_eff = alignicaf(1) | aligndbecc(1)
io.ifu_i0_icaf_f1 := first4B & icaf_eff & alignfromf1
io.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0)))
val ifirst = aligndata
val decompressed = Module(new el2_ifu_compress_ctl())
io.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout))
val firstpc_hash = el2_btb_addr_hash(f0pc)
val secondpc_hash = el2_btb_addr_hash(secondpc)
val firstbrtag_hash = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(firstpc) else el2_btb_tag_hash(firstpc)
val secondbrtag_hash = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(secondpc) else el2_btb_tag_hash(secondpc)
io.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
io.i0_brp.ret := (first2B & alignret(0)) | (first4B & alignret(1))
val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
io.i0_brp.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1))
io.i0_brp.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
(first2B & alignhist0(0)) | (first4B & alignhist0(1)))
val i0_ends_f1 = first4B & alignfromf1
io.i0_brp.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
io.i0_brp.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
io.i0_brp.br_start_error := (first4B & alignval(1) & alignbrend(0))
io.i0_brp.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
io.i0_brp.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B)
io.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
io.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr)
io.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash)
decompressed.io.din := aligndata
val i0_shift = io.dec_i0_decode_d & ~error_stall
io.ifu_pmu_instr_aligned := i0_shift
shift_2B := i0_shift & first2B
shift_4B := i0_shift & first4B
f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (f0val(0) & !f0val(1))))
f1_shift_2B := f0val(0) & !f0val(1) & shift_4B
}
object ifu_aln extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_aln_ctl()))
}

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src/main/scala/ifu/el2_ifu_bp_ctl.scala Normal file
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package ifu
import include._
import lib._
import chisel3._
import chisel3.util._
import chisel3.experimental.chiselName
@chiselName
class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val io = IO (new Bundle {
val active_clk = Input(Clock())
val ic_hit_f = Input(Bool())
val ifc_fetch_addr_f = Input(UInt(31.W))
val ifc_fetch_req_f = Input(Bool()) // Fetch request generated by the IFC
// Decode packet containing information if its a brnach or not
val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t)
val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu
val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Way from where the btb got a hit
val dec_tlu_flush_lower_wb = Input(Bool())
val dec_tlu_flush_leak_one_wb = Input(Bool())
val dec_tlu_bpred_disable = Input(Bool())
// Exu misprediction packet
val exu_mp_pkt = Input(new el2_predict_pkt_t)
val exu_mp_eghr = Input(UInt(BHT_GHR_SIZE.W))
val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W))
val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index
val exu_mp_btag = Input(UInt(BTB_BTAG_SIZE.W))
val exu_flush_final = Input(Bool())
// Signals to the IFU containing information about brnach
val ifu_bp_hit_taken_f = Output(Bool())
val ifu_bp_btb_target_f = Output(UInt(31.W))
val ifu_bp_inst_mask_f = Output(Bool())
val ifu_bp_fghr_f = Output(UInt(BHT_GHR_SIZE.W))
val ifu_bp_way_f = Output(UInt(2.W))
val ifu_bp_ret_f = Output(UInt(2.W))
val ifu_bp_hist1_f = Output(UInt(2.W))
val ifu_bp_hist0_f = Output(UInt(2.W))
val ifu_bp_pc4_f = Output(UInt(2.W))
val ifu_bp_valid_f = Output(UInt(2.W))
val ifu_bp_poffset_f = Output(UInt(12.W))
val scan_mode = Input(Bool())
val test = Output(UInt())
})
val TAG_START = 16+BTB_BTAG_SIZE
val PC4 = 4 // Branch = pc + 4 (BTB Index)
val BOFF = 3 // Branch offset (BTB Index)
val CALL = 2 // Branch CALL (BTB Index)
val RET = 1 // Branch RET (BTB Index)
val BV = 0 // Branch Valid (BTB Index)
val LRU_SIZE = BTB_ARRAY_DEPTH
val NUM_BHT_LOOP = if(BHT_ARRAY_DEPTH > 16) 16 else BHT_ARRAY_DEPTH
val NUM_BHT_LOOP_INNER_HI = if(BHT_ARRAY_DEPTH > 16) BHT_ADDR_LO+3 else BHT_ADDR_HI
val NUM_BHT_LOOP_OUTER_LO = if(BHT_ARRAY_DEPTH > 16) BHT_ADDR_LO+4 else BHT_ADDR_LO
val BHT_NO_ADDR_MATCH = BHT_ARRAY_DEPTH <= 16
/////////////////////////////////////////////////////////
val leak_one_f = WireInit(Bool(), 0.U)
val bht_dir_f = WireInit(UInt(2.W), 0.U)
val dec_tlu_error_wb = WireInit(Bool(), 0.U)
val btb_error_addr_wb = WireInit(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W), 0.U)
val btb_bank0_rd_data_way0_f = WireInit(UInt((TAG_START+1).W), 0.U)
val btb_bank0_rd_data_way1_f = WireInit(UInt((TAG_START+1).W), 0.U)
val btb_bank0_rd_data_way0_p1_f = WireInit(UInt((TAG_START+1).W), 0.U)
val btb_bank0_rd_data_way1_p1_f = WireInit(UInt((TAG_START+1).W), 0.U)
val eoc_mask = WireInit(Bool(), 0.U)
val btb_lru_b0_f = WireInit(UInt(LRU_SIZE.W), init = 0.U)
io.test := btb_lru_b0_f
val dec_tlu_way_wb = WireInit(Bool(), 0.U)
/////////////////////////////////////////////////////////
// Misprediction packet
val exu_mp_valid = io.exu_mp_pkt.misp & !leak_one_f
val exu_mp_boffset = io.exu_mp_pkt.boffset
val exu_mp_pc4 = io.exu_mp_pkt.pc4
val exu_mp_call = io.exu_mp_pkt.pcall
val exu_mp_ret = io.exu_mp_pkt.pret
val exu_mp_ja = io.exu_mp_pkt.pja
val exu_mp_way = io.exu_mp_pkt.way
val exu_mp_hist = io.exu_mp_pkt.hist
val exu_mp_tgt = io.exu_mp_pkt.toffset
val exu_mp_addr = io.exu_mp_index
val exu_mp_ataken = io.exu_mp_pkt.ataken
// Its a commit or update packet
val dec_tlu_br0_v_wb = io.dec_tlu_br0_r_pkt.valid
val dec_tlu_br0_hist_wb = io.dec_tlu_br0_r_pkt.hist
val dec_tlu_br0_addr_wb = io.exu_i0_br_index_r
val dec_tlu_br0_error_wb = io.dec_tlu_br0_r_pkt.br_error
val dec_tlu_br0_middle_wb = io.dec_tlu_br0_r_pkt.middle
val dec_tlu_br0_way_wb = io.dec_tlu_br0_r_pkt.way
val dec_tlu_br0_start_error_wb = io.dec_tlu_br0_r_pkt.br_start_error
val exu_i0_br_fghr_wb = io.exu_i0_br_fghr_r
dec_tlu_error_wb := dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb
btb_error_addr_wb := dec_tlu_br0_addr_wb
dec_tlu_way_wb := dec_tlu_br0_way_wb
// Hash the first PC
val btb_rd_addr_f = el2_btb_addr_hash(io.ifc_fetch_addr_f)
// Second pc = pc +4
val fetch_addr_p1_f = io.ifc_fetch_addr_f(30,1) + 1.U
// Hash the second pc
val btb_rd_addr_p1_f = el2_btb_addr_hash(Cat(fetch_addr_p1_f,0.U))
// TODO
val btb_sel_f = Cat(~bht_dir_f(0),bht_dir_f(0))
// Checking of the pc is a multiple of 4, if it is fetch-start will be "01"
val fetch_start_f = Cat(io.ifc_fetch_addr_f(0),~io.ifc_fetch_addr_f(0))
// If there is an error write-back from the dec check if the current pc is equal to the write-bcak pc
val branch_error_collision_f = dec_tlu_error_wb & (btb_error_addr_wb === btb_rd_addr_f)
val branch_error_collision_p1_f = dec_tlu_error_wb & (btb_error_addr_wb === btb_rd_addr_p1_f)
// If there is an error write back but the address are from different bank
val branch_error_bank_conflict_f = branch_error_collision_f & dec_tlu_error_wb
val branch_error_bank_conflict_p1_f = branch_error_collision_p1_f & dec_tlu_error_wb
// Hashing the PC to generate the index for the btb
val fetch_rd_tag_f = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(io.ifc_fetch_addr_f) else el2_btb_tag_hash(io.ifc_fetch_addr_f)
val fetch_rd_tag_p1_f = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(Cat(fetch_addr_p1_f,0.U)) else el2_btb_tag_hash(Cat(fetch_addr_p1_f,0.U))
// There is a misprediction and the exu is writing back
val fetch_mp_collision_f = (io.exu_mp_btag === fetch_rd_tag_f) & exu_mp_valid & io.ifc_fetch_req_f & (exu_mp_addr === btb_rd_addr_f)
val fetch_mp_collision_p1_f = (io.exu_mp_btag === fetch_rd_tag_p1_f) & exu_mp_valid & io.ifc_fetch_req_f & (exu_mp_addr === btb_rd_addr_p1_f)
val leak_one_f_d1 = withClock(io.active_clk) {RegNext(leak_one_f, init = 0.U)}
val dec_tlu_way_wb_f = withClock(io.active_clk) {RegNext(dec_tlu_way_wb, init = 0.U)}
val exu_mp_way_f = withClock(io.active_clk) {RegNext(exu_mp_way, init = 0.U)}
val exu_flush_final_d1 = withClock(io.active_clk) {RegNext(io.exu_flush_final, init = 0.U)}
// If there is a flush from the lower pipe wait until the flush gets deasserted from the (decode) side
leak_one_f := (io.dec_tlu_flush_leak_one_wb & io.dec_tlu_flush_lower_wb) | (leak_one_f_d1 & io.dec_tlu_flush_lower_wb)
// For a tag to match the branch should be valid tag should match and a fetch request should be generated
// Also there should be no bank conflict or leak-one
val tag_match_way0_f = btb_bank0_rd_data_way0_f(BV) & (btb_bank0_rd_data_way0_f(TAG_START,17) === fetch_rd_tag_f) &
!(dec_tlu_way_wb_f & branch_error_bank_conflict_f) & io.ifc_fetch_req_f & !leak_one_f
// Similar to the way-0 -> way-1
val tag_match_way1_f = btb_bank0_rd_data_way1_f(BV) & (btb_bank0_rd_data_way1_f(TAG_START,17) === fetch_rd_tag_f) &
!(dec_tlu_way_wb_f & branch_error_bank_conflict_f) & io.ifc_fetch_req_f & !leak_one_f
// Similar to above matches
val tag_match_way0_p1_f = btb_bank0_rd_data_way0_p1_f(BV) & (btb_bank0_rd_data_way0_p1_f(TAG_START,17) === fetch_rd_tag_p1_f) &
!(dec_tlu_way_wb_f & branch_error_bank_conflict_f) & io.ifc_fetch_req_f & !leak_one_f
// Similar to above matches
val tag_match_way1_p1_f = btb_bank0_rd_data_way1_p1_f(BV) & (btb_bank0_rd_data_way1_p1_f(TAG_START,17) === fetch_rd_tag_p1_f) &
!(dec_tlu_way_wb_f & branch_error_bank_conflict_f) & io.ifc_fetch_req_f & !leak_one_f
// Reordering to avoid multiple hit
val tag_match_way0_expanded_f = Cat(tag_match_way0_f & (btb_bank0_rd_data_way0_f(BOFF) ^ btb_bank0_rd_data_way0_f(PC4)),
tag_match_way0_f & !(btb_bank0_rd_data_way0_f(BOFF) ^ btb_bank0_rd_data_way0_f(PC4)))
val tag_match_way1_expanded_f = Cat(tag_match_way1_f & (btb_bank0_rd_data_way1_f(BOFF) ^ btb_bank0_rd_data_way1_f(PC4)),
tag_match_way1_f & !(btb_bank0_rd_data_way1_f(BOFF) ^ btb_bank0_rd_data_way1_f(PC4)))
val tag_match_way0_expanded_p1_f = Cat(tag_match_way0_p1_f & (btb_bank0_rd_data_way0_p1_f(BOFF) ^ btb_bank0_rd_data_way0_p1_f(PC4)),
tag_match_way0_p1_f & !(btb_bank0_rd_data_way0_p1_f(BOFF) ^ btb_bank0_rd_data_way0_p1_f(PC4)))
val tag_match_way1_expanded_p1_f = Cat(tag_match_way1_p1_f & (btb_bank0_rd_data_way1_p1_f(BOFF) ^ btb_bank0_rd_data_way1_p1_f(PC4)),
tag_match_way1_p1_f & !(btb_bank0_rd_data_way1_p1_f(BOFF) ^ btb_bank0_rd_data_way1_p1_f(PC4)))
// Final hit calculation
val wayhit_f = tag_match_way0_expanded_f | tag_match_way1_expanded_f
val wayhit_p1_f = tag_match_way0_expanded_p1_f | tag_match_way1_expanded_p1_f
// Chopping off the ways that had a hit btb_vbank0_rd_data_f
// e-> Lower half o-> Upper half
val btb_bank0e_rd_data_f = Mux1H(Seq(tag_match_way0_expanded_f(0).asBool->btb_bank0_rd_data_way0_f,
tag_match_way1_expanded_f(0).asBool->btb_bank0_rd_data_way1_f))
val btb_bank0o_rd_data_f = Mux1H(Seq(tag_match_way0_expanded_f(1).asBool->btb_bank0_rd_data_way0_f,
tag_match_way1_expanded_f(1).asBool->btb_bank0_rd_data_way1_f))
val btb_bank0e_rd_data_p1_f = Mux1H(Seq(tag_match_way0_expanded_p1_f(0).asBool->btb_bank0_rd_data_way0_p1_f,
tag_match_way1_expanded_p1_f(0).asBool->btb_bank0_rd_data_way1_p1_f))
// Making virtual banks, made from pc-bit(1) if it comes from a multiple of 4 we get the lower half of the bank
// and the upper half of the bank-0 in vbank 1
val btb_vbank0_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0)->btb_bank0e_rd_data_f,
io.ifc_fetch_addr_f(0)->btb_bank0o_rd_data_f))
val btb_vbank1_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0)->btb_bank0o_rd_data_f,
io.ifc_fetch_addr_f(0)->btb_bank0e_rd_data_p1_f))
// Branch prediction info is sent with the 2byte lane associated with the end of the branch.
// Cases
// BANK1 BANK0
// -------------------------------
// | : | : |
// -------------------------------
// <------------> : PC4 branch, offset, should be in B1 (indicated on [2])
// <------------> : PC4 branch, no offset, indicate PC4, VALID, HIST on [1]
// <------------> : PC4 branch, offset, indicate PC4, VALID, HIST on [0]
// <------> : PC2 branch, offset, indicate VALID, HIST on [1]
// <------> : PC2 branch, no offset, indicate VALID, HIST on [0]
// Make an LRU value with execution mis-prediction
val mp_wrindex_dec = 1.U << exu_mp_addr
// Make an LRU value with current read pc
val fetch_wrindex_dec = 1.U << btb_rd_addr_f
// Make an LRU value with current read pc + 4
val fetch_wrindex_p1_dec = 1.U << btb_rd_addr_p1_f
// Checking if the mis-prediction was valid or not and make a new LRU value
val mp_wrlru_b0 = mp_wrindex_dec & Fill(LRU_SIZE, exu_mp_valid)
val vwayhit_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->wayhit_f,
io.ifc_fetch_addr_f(0).asBool->Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W))
// Is the update of the lru valid or not
val lru_update_valid_f = (vwayhit_f(0) | vwayhit_f(1)) & io.ifc_fetch_req_f & !leak_one_f
val fetch_wrlru_b0 = fetch_wrindex_dec & Fill(LRU_SIZE, lru_update_valid_f)
val fetch_wrlru_p1_b0 = fetch_wrindex_p1_dec & Fill(LRU_SIZE, lru_update_valid_f)
val btb_lru_b0_hold = ~mp_wrlru_b0 & ~fetch_wrlru_b0
// If there is a collision the use the mis-predicted value as output and update accordingly
val use_mp_way = fetch_mp_collision_f
val use_mp_way_p1 = fetch_mp_collision_p1_f
// Calculate the lru next value and flop it
val btb_lru_b0_ns : UInt = Mux1H(Seq(!exu_mp_way.asBool -> mp_wrlru_b0,
tag_match_way0_f.asBool -> fetch_wrlru_b0,
tag_match_way0_p1_f.asBool -> fetch_wrlru_p1_b0)) | btb_lru_b0_hold & btb_lru_b0_f
val btb_lru_rd_f = Mux(use_mp_way.asBool, exu_mp_way_f, (fetch_wrindex_dec & btb_lru_b0_f).orR)
val btb_lru_rd_p1_f = Mux(use_mp_way_p1.asBool, exu_mp_way_f, (fetch_wrindex_p1_dec & btb_lru_b0_f).orR)
// Similar to the vbank make vlru
val btb_vlru_rd_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0) -> Cat(btb_lru_rd_f, btb_lru_rd_f),
io.ifc_fetch_addr_f(0).asBool -> Cat(btb_lru_rd_p1_f, btb_lru_rd_f)))
// virtual way depending on pc value
val tag_match_vway1_expanded_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->tag_match_way1_expanded_f,
io.ifc_fetch_addr_f(0).asBool->Cat(tag_match_way1_expanded_p1_f(0),tag_match_way1_expanded_f(1))))
io.ifu_bp_way_f := tag_match_vway1_expanded_f | (~vwayhit_f & btb_vlru_rd_f)
// update the lru
btb_lru_b0_f := rvdffe(btb_lru_b0_ns, (io.ifc_fetch_req_f|exu_mp_valid).asBool, clock, io.scan_mode)
//io.test := btb_lru_b0_ns
// Checking if the end of line is near
val eoc_near = io.ifc_fetch_addr_f(ICACHE_BEAT_ADDR_HI-1, 2).andR
// Mask according to eoc-near and make the hit-final
eoc_mask := !eoc_near | (~io.ifc_fetch_addr_f(1,0)).orR()
val btb_sel_data_f = WireInit(UInt(16.W), init = 0.U)
val hist1_raw = WireInit(UInt(2.W), init = 0.U)
// Filteing out portion of BTB read after virtual banking
// Entry -> tag[pt.BTB_BTAG_SIZE-1:0], toffset[11:0], pc4, boffset, call, ret, valid
val btb_rd_tgt_f = btb_sel_data_f(15,4)
val btb_rd_pc4_f = btb_sel_data_f(3)
val btb_rd_call_f = btb_sel_data_f(1)
val btb_rd_ret_f = btb_sel_data_f(0)
// This is 1-index shifted to that of the btb-data-read so we have 1-bit shifted
btb_sel_data_f := Mux1H(Seq(btb_sel_f(1).asBool-> btb_vbank1_rd_data_f(16,1),
btb_sel_f(0).asBool-> btb_vbank0_rd_data_f(16,1)))
// No lower flush or bp-disabple and a fetch request is generated with virtual way hit
io.ifu_bp_hit_taken_f := (vwayhit_f & hist1_raw).orR & io.ifc_fetch_req_f & !leak_one_f_d1 & !io.dec_tlu_bpred_disable
// If the prediction is a call or ret btb entry then do not check the bht just force a taken with data from the RAS
val bht_force_taken_f = Cat( btb_vbank1_rd_data_f(CALL) | btb_vbank1_rd_data_f(RET) ,
btb_vbank0_rd_data_f(CALL) | btb_vbank0_rd_data_f(RET))
val bht_valid_f = vwayhit_f
val bht_bank1_rd_data_f =WireInit(UInt(2.W), 0.U)
val bht_bank0_rd_data_f =WireInit(UInt(2.W), 0.U)
val bht_bank0_rd_data_p1_f =WireInit(UInt(2.W), 0.U)
// Depending on pc make the virtual bank as commented above
val bht_vbank0_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->bht_bank0_rd_data_f,
io.ifc_fetch_addr_f(0).asBool->bht_bank1_rd_data_f))
val bht_vbank1_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->bht_bank1_rd_data_f,
io.ifc_fetch_addr_f(0).asBool->bht_bank0_rd_data_p1_f))
// Direction containing data of both banks direction
bht_dir_f := Cat((bht_force_taken_f(1) | bht_vbank1_rd_data_f(1)) & bht_valid_f(1),
(bht_force_taken_f(0) | bht_vbank0_rd_data_f(1)) & bht_valid_f(0))
// If the branch is taken then pass btb sel else 0
io.ifu_bp_inst_mask_f := (io.ifu_bp_hit_taken_f & btb_sel_f(1)) | !io.ifu_bp_hit_taken_f
// hist 1 shows both banks direction
hist1_raw := bht_force_taken_f | Cat(bht_vbank1_rd_data_f(1), bht_vbank0_rd_data_f(1))
// hist 0 shows the both bank strength
val hist0_raw = Cat(bht_vbank1_rd_data_f(0), bht_vbank0_rd_data_f(0))
// pc4: if the branch is pc+4
val pc4_raw = Cat(vwayhit_f(1) & btb_vbank1_rd_data_f(PC4),
vwayhit_f(0) & btb_vbank0_rd_data_f(PC4))
// Its a call call or ret branch
val pret_raw = Cat(vwayhit_f(1) & !btb_vbank1_rd_data_f(CALL) & btb_vbank1_rd_data_f(RET),
vwayhit_f(0) & !btb_vbank0_rd_data_f(CALL) & btb_vbank0_rd_data_f(RET))
// count number of 1's in bht_valid
val num_valids = bht_valid_f(1) +& bht_valid_f(0)
// To calculate a merged ghr meaning the is a overlapping 1 in sel and dir
val final_h = (btb_sel_f & bht_dir_f).orR
val fghr = WireInit(UInt(BHT_GHR_SIZE.W), 0.U)
val merged_ghr = Mux1H(Seq((num_valids===2.U).asBool->Cat(fghr(BHT_GHR_SIZE-3,0), 0.U, final_h),
(num_valids===1.U).asBool->Cat(fghr(BHT_GHR_SIZE-2,0), final_h),
(num_valids===0.U).asBool->Cat(fghr(BHT_GHR_SIZE-1,0))))
val exu_flush_ghr = io.exu_mp_fghr
val fghr_ns = Wire(UInt(BHT_GHR_SIZE.W))
// If there is a exu-flush use its ghr
// If there is a hit and a fetch then use the merged-ghr
// If there is no hit or fetch then hold value
fghr_ns := Mux1H(Seq(exu_flush_final_d1.asBool->exu_flush_ghr,
(!exu_flush_final_d1 & io.ifc_fetch_req_f & io.ic_hit_f & !leak_one_f_d1).asBool -> merged_ghr,
(!exu_flush_final_d1 & !(io.ifc_fetch_req_f & io.ic_hit_f & !leak_one_f_d1)).asBool -> fghr))
fghr := withClock(io.active_clk) {RegNext(fghr_ns, init = 0.U)}
io.ifu_bp_fghr_f := fghr
io.ifu_bp_hist1_f := hist1_raw
io.ifu_bp_hist0_f := hist0_raw
io.ifu_bp_pc4_f := pc4_raw
io.ifu_bp_valid_f := vwayhit_f & ~Fill(2, io.dec_tlu_bpred_disable)
io.ifu_bp_ret_f := pret_raw
// block fetch to calculate if there is a hit with fetch request and a taken branch then compute the branch offset
val bloc_f = Cat((bht_dir_f(0) & !fetch_start_f(0)) | (!bht_dir_f(0) & fetch_start_f(0)),
(bht_dir_f(0) & fetch_start_f(0)) | (!bht_dir_f(0) & !fetch_start_f(0)))
val use_fa_plus = !bht_dir_f(0) & io.ifc_fetch_addr_f(0) & !btb_rd_pc4_f
val btb_fg_crossing_f = fetch_start_f(0) & btb_sel_f(0) & btb_rd_pc4_f
val bp_total_branch_offset_f = bloc_f(1)^btb_rd_pc4_f
val ifc_fetch_adder_prior = rvdffe(io.ifc_fetch_addr_f(30,1), (io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f).asBool, clock, io.scan_mode)
io.ifu_bp_poffset_f := btb_rd_tgt_f
val adder_pc_in_f = Mux1H(Seq(use_fa_plus.asBool -> fetch_addr_p1_f,
btb_fg_crossing_f.asBool -> ifc_fetch_adder_prior,
(!btb_fg_crossing_f & !use_fa_plus).asBool-> io.ifc_fetch_addr_f(30,1)))
// Calculate the branch target by adding the offset
val bp_btb_target_adder_f = rvbradder(Cat(adder_pc_in_f(29,0),bp_total_branch_offset_f, 0.U), Cat(btb_rd_tgt_f,0.U))
val rets_out = Wire(Vec(RET_STACK_SIZE, UInt(32.W)))
rets_out := (0 until RET_STACK_SIZE).map(i=>0.U)
// Final target if its a RET then pop else take the target pc
io.ifu_bp_btb_target_f := Mux((btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0)).asBool,
rets_out(0)(31,1),bp_btb_target_adder_f(31,1))
// Return stack
val bp_rs_call_target_f = rvbradder(Cat(adder_pc_in_f(29,0),bp_total_branch_offset_f, 0.U), Cat(Fill(11, 0.U),~btb_rd_pc4_f, 0.U))
val rs_push = btb_rd_call_f & !btb_rd_ret_f & io.ifu_bp_hit_taken_f
val rs_pop = btb_rd_ret_f & !btb_rd_call_f & io.ifu_bp_hit_taken_f
val rs_hold = !rs_push & !rs_pop
val rsenable = (0 until RET_STACK_SIZE).map(i=> if(i==0) !rs_hold else if(i==RET_STACK_SIZE-1) rs_push else rs_push | rs_pop)
// Make the input of the RAS
val rets_in = (0 until RET_STACK_SIZE).map(i=> if(i==0)
Mux1H(Seq(rs_push.asBool -> Cat(bp_rs_call_target_f(31,1),1.U),
rs_pop.asBool -> rets_out(1)))
else if(i==RET_STACK_SIZE-1) rets_out(i-1)
else Mux1H(Seq(rs_push.asBool->rets_out(i-1),
rs_pop.asBool ->rets_out(i+1))))
// Make flops for poping the data
rets_out := (0 until RET_STACK_SIZE).map(i=>rvdffe(rets_in(i), rsenable(i).asBool, clock, io.scan_mode))
val btb_valid = exu_mp_valid & (!dec_tlu_error_wb)
val btb_wr_tag = io.exu_mp_btag
// Making the data to write into the BTB according the structure discribed above
val btb_wr_data = Cat(btb_wr_tag, exu_mp_tgt, exu_mp_pc4, exu_mp_boffset, exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid)
val exu_mp_valid_write = exu_mp_valid & exu_mp_ataken
// Enable for write on each way
val btb_wr_en_way0 = ((!exu_mp_way) & exu_mp_valid_write & (!dec_tlu_error_wb)) | ((!dec_tlu_way_wb) & dec_tlu_error_wb)
val btb_wr_en_way1 = (exu_mp_way & exu_mp_valid_write & (!dec_tlu_error_wb)) | (dec_tlu_way_wb & dec_tlu_error_wb)
// Writing is always done from dec or exu check if the dec have a valid data
val btb_wr_addr = Mux(dec_tlu_error_wb.asBool , btb_error_addr_wb, exu_mp_addr)
val middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset
// Enable the clk enable according to the exu misprediction where it is not a RAS
val bht_wr_en0 = Fill(2, exu_mp_valid & !exu_mp_call & !exu_mp_ret & !exu_mp_ja) & Cat(middle_of_bank, ~middle_of_bank)
val bht_wr_en2 = Fill(2, dec_tlu_br0_v_wb) & Cat(dec_tlu_br0_middle_wb, ~dec_tlu_br0_middle_wb)
val bht_wr_data0 = exu_mp_hist
val bht_wr_data2 = dec_tlu_br0_hist_wb
// Hash each read and write address
val mp_hashed = el2_btb_ghr_hash(Cat(exu_mp_addr,0.U(2.W)), io.exu_mp_eghr)
val br0_hashed_wb = el2_btb_ghr_hash(Cat(dec_tlu_br0_addr_wb,0.U(2.W)), exu_i0_br_fghr_wb)
val bht_rd_addr_hashed_f = el2_btb_ghr_hash(Cat(btb_rd_addr_f,0.U(2.W)), fghr)
val bht_rd_addr_hashed_p1_f = el2_btb_ghr_hash(Cat(btb_rd_addr_p1_f,0.U(2.W)), fghr)
val bht_wr_addr0 = mp_hashed
val bht_wr_addr2 = br0_hashed_wb
val bht_rd_addr_f = bht_rd_addr_hashed_f
val bht_rd_addr_p1_f = bht_rd_addr_hashed_p1_f
// BTB
// Entry -> Tag[BTB-BTAG-SIZE], toffset[12], pc4, boffset, call, ret, valid
val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i=>rvdffe(btb_wr_data, ((btb_wr_addr===i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode))
val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i=>rvdffe(btb_wr_data, ((btb_wr_addr===i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode))
btb_bank0_rd_data_way0_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_f===i.U).asBool->btb_bank0_rd_data_way0_out(i)))
btb_bank0_rd_data_way1_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_f===i.U).asBool->btb_bank0_rd_data_way1_out(i)))
// BTB read muxing
btb_bank0_rd_data_way0_p1_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_p1_f===i.U).asBool->btb_bank0_rd_data_way0_out(i)))
btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_p1_f===i.U).asBool->btb_bank0_rd_data_way1_out(i)))
val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool())))
val bht_bank_clk = (0 until 2).map(i=>(0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)).map(k=>rvclkhdr(clock, bht_bank_clken(i)(k), io.scan_mode)))
for(i<-0 until 2; k<- 0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)){
// Checking if there is a write enable with address for the BHT
bht_bank_clken(i)(k) := (bht_wr_en0(i) & ((bht_wr_addr0(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-2)===k.U) | BHT_NO_ADDR_MATCH.B)) |
(bht_wr_en2(i) & ((bht_wr_addr2(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-2)===k.U) | BHT_NO_ADDR_MATCH.B))
}
// Writing data into the BHT (DEC-side) or (EXU-side)
val bht_bank_wr_data = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=>(0 until NUM_BHT_LOOP).map(j=>
Mux((bht_wr_en2(i)&(bht_wr_addr2(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.U)&(bht_wr_addr2(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.U)|BHT_NO_ADDR_MATCH.B).asBool, bht_wr_data2, bht_wr_data0))))
val bht_bank_sel = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Vec(NUM_BHT_LOOP, Bool()))))
// We have a 2 way bht with BHT_ARRAY_DEPTH/NUM_BHT_LOOP blocks and NUM_BHT_LOOP->offset in each block
// Make enables of each flop according to the address dividing the address in 2-blocks upper block for BHT-Block and
// the lower block for the offset and run this on both of the ways
for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<- 0 until NUM_BHT_LOOP){
bht_bank_sel(i)(k)(j) := (bht_wr_en0(i) & (bht_wr_addr0(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt) & ((bht_wr_addr0(BHT_ADDR_HI-BHT_ADDR_LO, NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt) | BHT_NO_ADDR_MATCH.B)) |
(bht_wr_en2(i) & (bht_wr_addr2(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt) & ((bht_wr_addr2(BHT_ADDR_HI-BHT_ADDR_LO, NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt) | BHT_NO_ADDR_MATCH.B))
}
// Reading the BHT with i->way, k->block and the j->offset
val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W))))
for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){
bht_bank_rd_data_out(i)((16*k)+j) := withClock(bht_bank_clk(i)(k)){RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j))}
}
// Make the final read mux
bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(0)(i)))
bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(1)(i)))
bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f===i.U).asBool->bht_bank_rd_data_out(0)(i)))
}
object ifu_bp extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl()))
}

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src/main/scala/ifu/el2_ifu_compress_ctl.scala Normal file
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package ifu
import lib._
import chisel3._
import chisel3.util._
class el2_ifu_compress_ctl extends Module with el2_lib{
val io = IO(new Bundle{
val din = Input(UInt(16.W))
val dout = Output(UInt(32.W))
})
def pat(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0) io.din(y(i)) else !io.din(y(i).abs)).reduce(_&_)
val out = Wire(Vec(32, UInt(1.W)))
out := (0 until 32).map(i=> 0.U.asBool)
out(30) := pat(List(15, -14, -13, 10, -6, -5, 0)) | pat(List(15, -14, -13, -11, 10, 0))
out(20) := pat(List(-14, 12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, 1))
out(14) := pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) | pat(List(15, -14, -13, 6, 0)) | pat(List(15, -14, -13, 5, 0))
out(13) := pat(List(15, -14, -13, 11, -10, 0)) | pat(List(15, -14, -13, 11, 6, 0)) | (io.din(14)&(!io.din(0)))
out(12) := pat(List(15, -14, -13, 6, 5, 0)) | pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) |
pat(List(-15, -14, 1)) | pat(List(15, 14, 13))
out(6) := (pat(List(15, -14, -6, -5, -4, -3, -2)) & !io.din(0)) | pat(List(-14, 13)) | pat(List(15, 14, 0))
out(5) := (io.din(15)&(!io.din(0))) | pat(List(15, 11, 10)) | pat(List(13, -8)) | pat(List(13, 7)) |
pat(List(13, 9)) | pat(List(13, 10)) | pat(List(13, 11)) | pat(List(-14, 13)) | pat(List(15, 14))
out(4) := (pat(List(-14, -11, -10, -9, -8, -7))&(!io.din(0))) | (pat(List(-15, -14))&(!io.din(0))) |
(pat(List(-14, 6))&(!io.din(0))) | pat(List(-15, 14, 0)) | (pat(List(-14, 5))&(!io.din(0))) |
(pat(List(-14, 4))&(!io.din(0))) | (pat(List(-14, 3))&(!io.din(0))) | (pat(List(-14, 2))&(!io.din(0))) |
pat(List(-14, -13, 0))
out(3) := pat(List(-14, 13))
out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) | pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) |
pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) | pat(List(-14, 12, 8, -6,-5,-4, -3, -2,1)) |
pat(List(-14, 12, 7, -6, -5, -4, -3, -2,1)) | (pat(List(15, -14,-12, -6, -5, -4, -3, -2))&(!io.din(0))) |
pat(List(-15,13,-8)) | pat(List(-15,13,7)) | pat(List(-15,13,9)) | pat(List(-15,13,10)) |
pat(List(-15,13,11)) | pat(List(-14,13))
out(1) := 1.U.asBool
out(0) := 1.U.asBool
val rs2d = io.din(6,2)
val rdd = io.din(11,7)
val rdpd = Cat(1.U(2.W), io.din(9,7))
val rs2pd = Cat(1.U(2.W), io.din(4,2))
val rdrd = pat(List(-14,6,1)) | pat(List(-15,14,11,0)) | pat(List(-14,5,1)) | pat(List(-15,14,10,0)) |
pat(List(-14,4,1)) | pat(List(-15,14,9,0)) | pat(List(-14,3,1)) | pat(List(-15,14,-8,0)) |
pat(List(-14,2,1)) | pat(List(-15,14,7,0)) | pat(List(-15,1)) | pat(List(-15,-13,0))
val rdrs1 = pat(List(-14,12,11,1)) | pat(List(-14,12,10,1)) | pat(List(-14,12,9,1)) |
pat(List(-14,12,8,1)) | pat(List(-14,12,7,1)) | pat(List(-14,-12,-6,-5,-4,-3,-2,1)) |
pat(List(-14,12,6,1)) | pat(List(-14,12,5,1)) | pat(List(-14,12,4,1)) | pat(List(-14,12,3,1)) |
pat(List(-14,12,2,1)) | pat(List(-15,-14,-13,0)) | pat(List(-15,-14,1))
val rs2rs2 = pat(List(15,6,1)) | pat(List(15,5,1)) | pat(List(15,4,1)) | pat(List(15,3,1)) | pat(List(15,2,1)) | pat(List(15,14,1))
val rdprd = pat(List(15,-14,-13,0))
val rdprs1 = pat(List(15,-13,0)) | pat(List(15,14,0)) | (pat(List(14,-1))&(!io.din(0)))
val rs2prs2 = pat(List(15,-14,-13,11,10,0)) | (pat(List(15,-1))&(!io.din(0)))
val rs2prd = pat(List(-15,-1))&(!io.din(0))
val uimm9_2 = pat(List(-14,-1))&(!io.din(0))
val ulwimm6_2 = pat(List(-15,14,-1))&(!io.din(0))
val ulwspimm7_2 = pat(List(-15,14,1))
val rdeq2 = pat(List(-15,14,13,-11,-10,-9,8,-7))
val rdeq1 = pat(List(-14,12,11,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,10,-6,-5,-4,-3,-2,1)) |
pat(List(-14,12,9,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,8,-6,-5,-4,-3,-2,1)) |
pat(List(-14,12,7,-6,-5,-4,-3,-2,1)) | pat(List(-15,-14,13))
val rs1eq2 = pat(List(-15,14,13,-11,-10,-9,8,-7)) | pat(List(14,1)) | (pat(List(-14,-1))&(!io.din(0)))
val sbroffset8_1 = pat(List(15,14,0))
val simm9_4 = pat(List(-15,14,13,-11,-10,-9,8,-7))
val simm5_0 = pat(List(-14,-13,11,-10,0)) | pat(List(-15,-13,0))
val sjaloffset11_1 = pat(List(-14,13))
val sluimm17_12 = pat(List(-15,14,13,7)) | pat(List(-15,14,13,-8)) | pat(List(-15,14,13,9)) | pat(List(-15,14,13,10)) | pat(List(-15,14,13,11))
val uimm5_0 = pat(List(15,-14,-13,-11,0)) | pat(List(-15,-14,1))
val uswimm6_2 = pat(List(15,-1))&(!io.din(0))
val uswspimm7_2 = pat(List(15,14,1))
val l1_6 = Cat(out(6),out(5),out(4),out(3),out(2),out(1),out(0)).asUInt()
val l1_11 = Cat(out(11),out(10),out(9),out(8),out(7)).asUInt | Mux1H(Seq(rdrd.asBool->rdd,
rdprd.asBool->rdpd, rs2prd.asBool->rs2pd, rdeq1.asBool->1.U(5.W), rdeq2.asBool->2.U(5.W)))
val l1_14 = Cat(out(14),out(13),out(12))
val l1_19 = Cat(out(19),out(18),out(17),out(16),out(15)).asUInt | Mux1H(Seq(rdrs1.asBool->rdd,
rdprs1.asBool->rdpd, rs1eq2.asBool->2.U(5.W)))
val l1_24 = Cat(out(24),out(23),out(22),out(21),out(20)).asUInt | Mux1H(Seq(rs2rs2.asBool->rs2d,
rs2prs2.asBool->rs2pd))
val l1_31 = Cat(out(31),out(30),out(29),out(28),out(27),out(26),out(25)).asUInt
val l1 = Cat(l1_31,l1_24,l1_19,l1_14,l1_11,l1_6)
val simm5d = Cat(io.din(12), io.din(6,2))
val uimm9d = Cat(io.din(10,7), io.din(12,11), io.din(5), io.din(6))
val simm9d = Cat(io.din(12), io.din(4,3), io.din(5), io.din(2), io.din(6))
val ulwimm6d = Cat(io.din(5), io.din(12,10), io.din(6))
val ulwspimm7d = Cat(io.din(3,2), io.din(12), io.din(6,4))
val uimm5d = Cat(io.din(12), io.din(6,2))
val sjald_1 = Cat(io.din(12), io.din(8), io.din(10,9), io.din(6), io.din(7), io.din(2), io.din(11),
io.din(5,4), io.din(3))
val sjald_12 = repl(9, io.din(12))
val sjald = Cat(sjald_12,sjald_1)
val sluimmd = Cat(repl(15, io.din(12)), io.din(6,2))
val l2_31 = l1(31,20) |
Mux1H(Seq(simm5_0.asBool->Cat(repl(7, simm5d(5)), simm5d(4,0)),
uimm9_2.asBool->Cat(0.U(2.W), uimm9d, 0.U(2.W)),
simm9_4.asBool->Cat(repl(3, simm9d(5)), simm9d(4,0), 0.U(4.W)),
ulwimm6_2.asBool->Cat(0.U(5.W), ulwimm6d, 0.U(2.W)),
ulwspimm7_2.asBool->Cat(0.U(4.W), ulwspimm7d, 0.U(2.W)),
uimm5_0.asBool->Cat(0.U(6.W), uimm5d),
sjaloffset11_1.asBool->Cat(sjald(19), sjald(9,0), sjald(10)),
sluimm17_12.asBool->sluimmd(19,8)))
val l2_19 = l1(19,12) | Mux1H(Seq(sjaloffset11_1.asBool->sjald(19,12),
sluimm17_12.asBool->sluimmd(7,0)))
val l2 = Cat(l2_31, l2_19, l1(11,0))
val sbr8d = Cat(io.din(12),io.din(6),io.din(5),io.din(2),io.din(11),io.din(10),io.din(4),io.din(3),0.U)
val uswimm6d = Cat(io.din(5), io.din(12,10), io.din(6), 0.U(2.W))
val uswspimm7d = Cat(io.din(8,7),io.din(12,9), 0.U(2.W))
val l3_31 = l2(31,25) | Mux1H(Seq(sbroffset8_1.asBool->Cat(repl(4,sbr8d(8)),sbr8d(7,5)),
uswimm6_2.asBool->Cat(0.U(5.W),uswimm6d(6,5)), uswspimm7_2.asBool->Cat(0.U(4.W),uswspimm7d(7,5))))
val l3_24 = l2(24,12)
val l3_11 = l2(11,7) | Mux1H(Seq(sbroffset8_1.asBool->Cat(sbr8d(4,1), sbr8d(8)),
uswimm6_2.asBool->uswimm6d(4,0),
uswspimm7_2.asBool->uswspimm7d(4,0)))
val l3 = Cat(l3_31, l3_24, l3_11, l2(6,0))
val legal = (pat(List(-13,-12,11,1))&(!io.din(0))) | (pat(List(-13,-12,6,1))&(!io.din(0))) |
pat(List(-15,-13,11,-1)) | (pat(List(-13,-12,5,1))&(!io.din(0))) | (pat(List(-13,-12,10,1))&(!io.din(0))) |
pat(List(-15,-13,6,-1)) | pat(List(15,-12,-1,0)) | (pat(List(-13,-12,9,1))&(!io.din(0))) | pat(List(-12,6,-1,0)) | pat(List(-15,-13,5,-1)) |
(pat(List(-13,-12,8,1))&(!io.din(0))) | pat(List(-12,5,-1,0)) | pat(List(-15,-13,10,-1)) |
(pat(List(-13,-12,7,1))&(!io.din(0))) | pat(List(12,11,-10,-1,0)) | pat(List(-15,-13,9,-1)) |
(pat(List(-13,-12,4,1))&(!io.din(0))) | pat(List(13,12,-1,0)) | pat(List(-15,-13,8,-1)) |
(pat(List(-13,-12,3,1))&(!io.din(0))) | pat(List(13,4,-1,0)) | (pat(List(-13,-12,2,1))&(!io.din(0))) |
pat(List(-15,-13,7,-1)) | pat(List(13,3,-1,0)) | pat(List(13,2,-1,0)) | pat(List(14,-13,-1)) |
pat(List(-14,-12,-1,0)) | (pat(List(15,-13,12,1))&(!io.din(0))) | (pat(List(-15,-13,-12,1))&(!io.din(0))) |
pat(List(-15,-13,12,-1)) | (pat(List(14,-13))&(!io.din(0)))
io.dout:= l3 & repl(32, legal)
}
object ifu_compress extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl()))
}

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src/main/scala/ifu/el2_ifu_ic_mem.scala Normal file
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package ifu
import lib._
import chisel3.{util, _}
import chisel3.util._
class el2_ifu_ic_mem extends Module with param{
val io = IO(new Bundle{
val scan_mode = Input(Bool())
val clk_override = Input(Bool())
val dec_tlu_core_ecc_disable = Input(Bool())
val ic_rw_addr = Input(UInt(31.W))
val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_en = Input(Bool())
val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W))
val ic_debug_rd_en = Input(Bool())
val ic_debug_wr_en = Input(Bool())
val ic_debug_tag_array = Input(Bool())
val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_premux_data = Input(UInt(64.W))
val ic_sel_premux_data = Input(Bool())
val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_debug_wr_data = Input(UInt(71.W))
val ic_wr_data = Input(Vec(ICACHE_BANKS_WAY, Input(UInt(71.W))))
val ic_rd_data = Output(UInt(64.W))
val ic_debug_rd_data = Output(UInt(71.W))
val ictag_debug_rd_data = Output(UInt(26.W))
val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W))
val ic_parerr = Output(UInt(ICACHE_BANKS_WAY.W))
val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_perr = Output(Bool())
})
io.ic_tag_perr := 0.U
io.ic_rd_hit := 0.U
io.ic_parerr := 0.U
io.ic_eccerr := 0.U
io.ictag_debug_rd_data := 0.U
io.ic_debug_rd_data := 0.U
io.ic_rd_data := 0.U
val ic_tag_inst = Module(new EL2_IC_TAG())
//ic_tag_inst.io <> io
ic_tag_inst.io.ic_tag_valid := io.ic_tag_valid
ic_tag_inst.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable
ic_tag_inst.io.clk_override := io.clk_override
ic_tag_inst.io.ic_rw_addr := io.ic_rw_addr
ic_tag_inst.io.ic_wr_en := io.ic_wr_en
ic_tag_inst.io.ic_rd_en := io.ic_rd_en
ic_tag_inst.io.ic_debug_addr := io.ic_debug_addr
ic_tag_inst.io.ic_debug_rd_en := io.ic_debug_rd_en
ic_tag_inst.io.ic_debug_wr_en := io.ic_debug_wr_en
ic_tag_inst.io.ic_debug_tag_array := io.ic_debug_tag_array
ic_tag_inst.io.ic_debug_way := io.ic_debug_way
io.ictag_debug_rd_data := ic_tag_inst.io.ictag_debug_rd_data // Output
ic_tag_inst.io.ic_debug_wr_data := io.ic_debug_wr_data
io.ic_rd_hit := ic_tag_inst.io.ic_rd_hit // Output
io.ic_tag_perr := ic_tag_inst.io.ic_tag_perr // Output
ic_tag_inst.io.scan_mode := io.scan_mode
val ic_data_inst = Module(new EL2_IC_DATA())
ic_data_inst.io.clk_override := io.clk_override
ic_data_inst.io.ic_rw_addr :=io.ic_rw_addr
ic_data_inst.io.ic_wr_en := io.ic_wr_en
ic_data_inst.io.ic_rd_en := io.ic_rd_en
ic_data_inst.io.ic_wr_data := io.ic_wr_data
io.ic_rd_data := ic_data_inst.io.ic_rd_data
ic_data_inst.io.ic_debug_wr_data := io.ic_debug_wr_data
io.ic_debug_rd_data := ic_data_inst.io.ic_debug_rd_data
io.ic_parerr := ic_data_inst.io.ic_parerr
io.ic_eccerr := ic_data_inst.io.ic_eccerr
ic_data_inst.io.ic_debug_addr := io.ic_debug_addr
ic_data_inst.io.ic_debug_rd_en := io.ic_debug_rd_en
ic_data_inst.io.ic_debug_wr_en := io.ic_debug_wr_en
ic_data_inst.io.ic_debug_tag_array := io.ic_debug_tag_array
ic_data_inst.io.ic_debug_way := io.ic_debug_way
ic_data_inst.io.ic_premux_data := io.ic_premux_data
ic_data_inst.io.ic_sel_premux_data := io.ic_sel_premux_data
ic_data_inst.io.ic_rd_hit :=io.ic_rd_hit
ic_data_inst.io.scan_mode := io.scan_mode
}
/////////// ICACHE TAG
class EL2_IC_TAG extends Module with el2_lib with param {
val io = IO(new Bundle{
val scan_mode = Input(Bool())
val clk_override = Input(Bool())
val dec_tlu_core_ecc_disable = Input(Bool())
val ic_rw_addr = Input(UInt(29.W)) // 32:3
val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_en = Input(Bool())
val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-2).W)) // 12-2 = 10-bit value
val ic_debug_rd_en = Input(Bool())
val ic_debug_wr_en = Input(Bool())
val ic_debug_tag_array = Input(Bool())
val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
val ictag_debug_rd_data = Output(UInt(26.W))
val ic_debug_wr_data = Input(UInt(71.W))
val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_perr = Output(Bool())
})
io.ictag_debug_rd_data := 0.U
io.ic_rd_hit := 0.U
io.ic_tag_perr := 0.U
val ic_debug_wr_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val ic_debug_rd_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val ic_tag_wren = io.ic_wr_en & Fill(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI-3,1)=== Fill(ICACHE_NUM_WAYS-1, 1.U))
val ic_tag_clken = Fill(ICACHE_NUM_WAYS, io.ic_rd_en|io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | ic_debug_rd_way_en
val ic_rd_en_ff = RegNext(io.ic_rd_en, 0.U)
val ic_rw_addr_ff = RegNext(io.ic_rw_addr(31-ICACHE_TAG_LO, 0), 0.U)
val PAD_BITS = 21 - (32 - ICACHE_TAG_LO)
ic_debug_rd_way_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way
ic_debug_wr_way_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way
val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en
val ic_tag_ecc = if(ICACHE_ECC) rvecc_encode(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3))) else 0.U
val ic_tag_parity = if(ICACHE_ECC) rveven_paritygen(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3))) else 0.U
val ic_tag_wr_data = if(ICACHE_TAG_LO==1)Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, Cat(if(ICACHE_ECC) io.ic_debug_wr_data(68,64) else io.ic_debug_wr_data(64), io.ic_debug_wr_data(31,11)),
Cat(if(ICACHE_ECC) ic_tag_ecc(4,0) else ic_tag_parity, io.ic_rw_addr(31-3,ICACHE_TAG_LO-3)))
else Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, Cat(if(ICACHE_ECC) io.ic_debug_wr_data(68,64) else io.ic_debug_wr_data(64), io.ic_debug_wr_data(31,11)),
Cat(if(ICACHE_ECC) Cat(ic_tag_ecc(4,0),Fill(PAD_BITS,0.U)) else Cat(ic_tag_parity,Fill(PAD_BITS,0.U)), io.ic_rw_addr(31-3,ICACHE_TAG_LO-3)))
val ic_rw_addr_q = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool,io.ic_debug_addr(ICACHE_INDEX_HI-3,ICACHE_TAG_INDEX_LO-3),io.ic_rw_addr)
val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, 0.U)
val tag_mem = Mem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(Tag_Word.W)))
val write_vec = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wren_q(i)&ic_tag_clken(i))
tag_mem.write(ic_rw_addr_q, VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wr_data), write_vec)
val read_enable = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(!ic_tag_wren_q(i))&ic_tag_clken(i))
val ic_tag_data_raw = (0 until ICACHE_NUM_WAYS).map(i=>Fill(Tag_Word,read_enable(i))&tag_mem.read(ic_rw_addr_q)(i))
val w_tout = if(ICACHE_ECC) VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(ic_tag_data_raw(i)(25,21), ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0)))
else VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(ic_tag_data_raw(i)(21), ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0)))
val ic_tag_corrected_ecc_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(7.W)))
val ic_tag_corrected_data_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(32.W)))
val ic_tag_single_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
val ic_tag_double_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
for(i<- 0 until ICACHE_NUM_WAYS){
val decoded_ecc = if(ICACHE_ECC) rvecc_decode(~io.dec_tlu_core_ecc_disable & ic_rd_en_ff, Cat(0.U(11.W),ic_tag_data_raw(i)(20,0)), Cat(0.U(2.W),ic_tag_data_raw(i)(25,21)), 1.U)
else (0.U, 0.U, 0.U, 0.U)
ic_tag_corrected_ecc_unc(i) := decoded_ecc._1
ic_tag_corrected_data_unc(i) := decoded_ecc._2
ic_tag_single_ecc_error(i):= decoded_ecc._3
ic_tag_double_ecc_error(i) := decoded_ecc._4
}
val ic_tag_way_perr = if(ICACHE_ECC)ic_tag_single_ecc_error.reverse.reduce(Cat(_,_)) | ic_tag_double_ecc_error.reverse.reduce(Cat(_,_))
else (0 until ICACHE_NUM_WAYS).map(i=>rveven_paritycheck(ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0), ic_tag_data_raw(i)(21))).reverse.reduce(Cat(_,_))
io.ictag_debug_rd_data := (0 until ICACHE_NUM_WAYS).map(i=> if(ICACHE_ECC) Fill(26, ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i) else Cat(0.U(4.W), Fill(22, ic_debug_rd_way_en_ff(i)),ic_tag_data_raw(i)(21,0))).reduce(_|_)
io.ic_rd_hit := (0 until ICACHE_NUM_WAYS).map(i=>((w_tout(i)(31-ICACHE_TAG_LO,0)===ic_rw_addr_ff)&io.ic_tag_valid(i)).asUInt()).reverse.reduce(Cat(_,_))
io.ic_tag_perr := (ic_tag_way_perr & io.ic_tag_valid).orR()
}
////////////////////////////////////////////////
class EL2_IC_DATA extends Module with el2_lib {
val io = IO (new Bundle{
val clk_override = Input(Bool())
val ic_rw_addr = Input(UInt(ICACHE_INDEX_HI.W))
val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_en = Input(Bool())
val ic_wr_data = Input(Vec(ICACHE_NUM_WAYS, UInt(71.W)))
val ic_rd_data = Output(UInt(64.W))
val ic_debug_wr_data = Input(UInt(71.W))
val ic_debug_rd_data = Output(UInt(71.W))
val ic_parerr = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W))
val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W))
val ic_debug_rd_en = Input(Bool())
val ic_debug_wr_en = Input(Bool())
val ic_debug_tag_array = Input(Bool())
val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_premux_data = Input(UInt(64.W))
val ic_sel_premux_data = Input(Bool())
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
val scan_mode = Input(UInt(1.W))
})
val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & !io.ic_debug_tag_array) & io.ic_debug_way
val ic_debug_wr_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & !io.ic_debug_tag_array) & io.ic_debug_way
val ic_bank_wr_data = Wire(Vec(ICACHE_BANKS_WAY,UInt(71.W)))
val ic_rd_en_with_debug = WireInit(Bool(), 0.U)
val ic_rw_addr_q = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool, Cat(io.ic_debug_addr,0.U(2.W)), io.ic_rw_addr)
val ic_rw_addr_q_inc = ic_rw_addr_q(ICACHE_TAG_LO-2,ICACHE_DATA_INDEX_LO-1) + 1.U
val ic_b_sb_wren = (0 until ICACHE_NUM_WAYS).map(i=>
io.ic_wr_en | ic_debug_wr_way_en & Fill(ICACHE_NUM_WAYS, io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U))
val ic_debug_sel_sb = (0 until ICACHE_NUM_WAYS).map(i=> (io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U).asUInt).reverse.reduce(Cat(_,_))
val ic_sb_wr_data = (0 until ICACHE_NUM_WAYS).map(i=> Mux((ic_debug_sel_sb(i)&io.ic_debug_wr_en).asBool, io.ic_debug_wr_data, ic_bank_wr_data(i)))
val ic_b_rden = (0 until ICACHE_NUM_WAYS).map(i=>
(Mux1H(Seq(!ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 0.U),
(ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U===0.U)),
ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 1.U),
(!ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U === 1.U)))) & ic_rd_en_with_debug).asUInt).reverse.reduce(Cat(_,_))
val ic_b_sb_rden = (0 until ic_b_rden.getWidth).map(i=>Fill(ICACHE_NUM_WAYS, ic_b_rden(i)))
val ic_bank_way_clken = (0 until ICACHE_BANKS_WAY).map(i=>(0 until ICACHE_NUM_WAYS).map(j=>
(ic_b_sb_rden(i)(j) | io.clk_override | ic_b_sb_wren(i)(j)).asUInt).reduce(Cat(_,_)))
ic_rd_en_with_debug := io.ic_rd_en | io.ic_debug_rd_en & (!io.ic_wr_en.orR)
val ic_rw_addr_wrap = ic_rw_addr_q(ICACHE_BANK_HI-1) & (ic_rw_addr_q(1,0) === 3.U) & ic_rd_en_with_debug & !(io.ic_wr_en.orR)
val ic_rw_addr_bank_q = VecInit(Mux((!ic_rw_addr_wrap).asBool,ic_rw_addr_q(ICACHE_INDEX_HI-1,ICACHE_DATA_INDEX_LO-1),
Cat(ic_rw_addr_q(ICACHE_INDEX_HI-1, ICACHE_TAG_INDEX_LO-1) , ic_rw_addr_q_inc(ICACHE_TAG_INDEX_LO-2,ICACHE_DATA_INDEX_LO-1))),
ic_rw_addr_q(ICACHE_INDEX_HI-1,ICACHE_DATA_INDEX_LO-1))
val ic_b_rden_ff = RegNext(ic_b_rden, 0.U)
val ic_rw_addr_ff = RegNext(ic_rw_addr_q(ICACHE_TAG_INDEX_LO-2,0), 0.U)
val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, 0.U)
val ic_debug_rd_en_ff = RegNext(io.ic_debug_rd_en, 0.U)
val ic_cacheline_wrap_ff = ic_rw_addr_ff(ICACHE_TAG_INDEX_LO-2,ICACHE_BANK_LO-1) === Fill(ICACHE_TAG_INDEX_LO-ICACHE_BANK_LO, 1.U)
//////////////////////////////////////////// Memory stated
val (data_mem_word, tag_mem_word, ecc_offset, tag_word) = DATA_MEM_LINE
val wb_dout = Wire(Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
val data_mem = Mem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
for(i<-0 until ICACHE_NUM_WAYS; k<-0 until ICACHE_BANKS_WAY){
wb_dout(i)(k) := 0.U
val WE = if(ICACHE_WAYPACK) ic_b_sb_wren(k).orR else ic_b_sb_wren(k)(i)
val ME = if(ICACHE_WAYPACK) ic_bank_way_clken(k).orR else ic_bank_way_clken(k)(i)
when((ic_b_sb_wren(k)(i) & ic_bank_way_clken(k)(i)).asBool){
data_mem(ic_rw_addr_bank_q(k))(k)(i) := ic_sb_wr_data(k)
}.elsewhen((!ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){
wb_dout(i)(k) := data_mem(ic_rw_addr_bank_q(k))(k)(i)
}
}
val ic_rd_hit_q = Mux(ic_debug_rd_en_ff.asBool, ic_debug_rd_way_en_ff, io.ic_rd_hit)
ic_bank_wr_data := (0 until ICACHE_BANKS_WAY).map(io.ic_wr_data(_))
val wb_dout_way_pre = (0 until ICACHE_BANKS_WAY).map(i=>Cat(
Mux1H((0 until ICACHE_BANKS_WAY).map(j=>(ic_rw_addr_ff(ICACHE_BANK_HI-1, ICACHE_BANK_LO-1)===j.U).asBool->wb_dout(i)(j))),
Mux1H((0 until ICACHE_BANKS_WAY).map(j=>(ic_rw_addr_ff(ICACHE_BANK_HI-1, ICACHE_BANK_LO-1)===(j.U-1.U)).asBool->wb_dout(i)(j)))))
val wb_dout_way = (0 until ICACHE_NUM_WAYS).map(i=>Mux1H(Seq((ic_rw_addr_ff(1,0)===0.U).asBool->wb_dout_way_pre(i)(63,0),
(ic_rw_addr_ff(1,0)===1.U).asBool->Cat(wb_dout_way_pre(i)(data_mem_word+15,data_mem_word),wb_dout_way_pre(i)(63,16)),
(ic_rw_addr_ff(1,0)===2.U).asBool->Cat(wb_dout_way_pre(i)(data_mem_word+31,data_mem_word),wb_dout_way_pre(i)(63,32)),
(ic_rw_addr_ff(1,0)===3.U).asBool->Cat(wb_dout_way_pre(i)(data_mem_word+47,data_mem_word),wb_dout_way_pre(i)(63,48)))))
val wb_dout_way_with_premux = (0 until ICACHE_NUM_WAYS).map(i=>Mux(io.ic_sel_premux_data.asBool,io.ic_premux_data, wb_dout_way(i)))
io.ic_rd_data := Mux1H((0 until ICACHE_NUM_WAYS).map(i=>(ic_rd_hit_q(i) | io.ic_sel_premux_data).asBool->wb_dout_way_with_premux(i)))
io.ic_debug_rd_data := Mux1H((0 until ICACHE_NUM_WAYS).map(i=>ic_rd_hit_q(i).asBool->wb_dout_way_pre(i)(70,0)))
val wb_dout_ecc = Mux1H((0 until ICACHE_NUM_WAYS).map(i=>ic_rd_hit_q(i).asBool->wb_dout_way_pre(i)))
val bank_check_en = for(i<-0 until ICACHE_BANKS_WAY) yield io.ic_rd_hit.orR & ((i.U==0.U).asBool | (!ic_cacheline_wrap_ff & (ic_b_rden_ff(ICACHE_BANKS_WAY-1,0) === Fill(ICACHE_BANKS_WAY,1.U))))
val wb_dout_ecc_bank = (0 until ICACHE_BANKS_WAY).map(i=> wb_dout_ecc((data_mem_word*i)+data_mem_word-1,data_mem_word*i))
// TODO: RVECC
io.ic_eccerr := (0 until ICACHE_NUM_WAYS).map(i=>rvecc_decode_64(bank_check_en(i),wb_dout_ecc_bank(i)(63,0),wb_dout_ecc_bank(i)(70,64)).asUInt).reverse.reduce(Cat(_,_))
val ic_parerr_bank = Wire(Vec(ICACHE_NUM_WAYS, Vec(4, UInt(1.W))))
for(i<-0 until ICACHE_NUM_WAYS; j<-0 until 4){ic_parerr_bank(i)(j):=rveven_paritycheck(wb_dout_ecc_bank(i)(16*(j+1)-1, 16*j), wb_dout_ecc_bank(i)(64+j))}
io.ic_parerr := Cat(ic_parerr_bank(0).reduce(_|_) & bank_check_en(0), ic_parerr_bank(1).reduce(_|_) & bank_check_en(1))
}
object ifu_ic extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ic_mem()))
}

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src/main/scala/ifu/el2_ifu_iccm_mem.scala Normal file
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package ifu
import chisel3._
import chisel3.util._
import lib._
import scala.math.pow
class el2_ifu_iccm_mem extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{
val clk_override = Input(Bool())
val iccm_wren = Input(Bool())
val iccm_rden = Input(Bool())
val iccm_rw_addr = Input(UInt((ICCM_BITS-1).W))
val iccm_buf_correct_ecc = Input(Bool())
val iccm_correction_state = Input(Bool())
val iccm_wr_size = Input(UInt(3.W))
val iccm_wr_data = Input(UInt(78.W))
val iccm_rd_data = Output(UInt(64.W))
val iccm_rd_data_ecc = Output(UInt(78.W))
val scan_mode = Input(Bool())
// val iccm_bank_addr = Output(Vec(ICCM_NUM_BANKS, UInt()))
})
io.iccm_rd_data := 0.U
io.iccm_rd_data_ecc := 0.U
val addr_inc = Mux((io.iccm_wr_size(1,0)===3.U).asBool, 2.U(2.W), 1.U(2.W))
val addr_bank_inc = io.iccm_rw_addr(ICCM_BITS-2,0) + addr_inc
val iccm_bank_wr_data_vec = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W)))
for(i<- 0 until ICCM_NUM_BANKS/2){
iccm_bank_wr_data_vec(2*i) := io.iccm_wr_data(38,0)
iccm_bank_wr_data_vec((2*i)+1) := io.iccm_wr_data(77,39)
}
val wren_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_wren&((io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U)))
val iccm_bank_wr_data = iccm_bank_wr_data_vec
val rden_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_rden&(io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U))
val iccm_clken = for(i<- 0 until ICCM_NUM_BANKS) yield wren_bank(i) | rden_bank(i) | io.clk_override
val addr_bank = Wire(Vec(ICCM_NUM_BANKS, UInt((ICCM_BITS-ICCM_BANK_INDEX_LO).W)))
for(i<-0 until ICCM_NUM_BANKS) {addr_bank(i) := Mux(wren_bank(i).asBool, io.iccm_rw_addr(ICCM_BITS-2, ICCM_BANK_INDEX_LO-1),
Mux((addr_bank_inc(ICCM_BANK_HI-1,1)===i.U),addr_bank_inc(ICCM_BITS-2,ICCM_BANK_INDEX_LO-1),io.iccm_rw_addr(ICCM_BITS-2,ICCM_BANK_INDEX_LO-1)))}
val iccm_mem = new Array[SyncReadMem[UInt]](ICCM_NUM_BANKS)
for(i<-0 until ICCM_NUM_BANKS) iccm_mem(i) = SyncReadMem(pow(2, ICCM_INDEX_BITS).intValue, UInt(39.W))
//val iccm_mem = VecInit.tabulate(ICCM_NUM_BANKS)(i=>Mem(pow(2, ICCM_INDEX_BITS).intValue, UInt(39.W))))
//val iccm_mem = Mem(pow(2, ICCM_INDEX_BITS).intValue, Vec(ICCM_NUM_BANKS, UInt(39.W)))
val write_vec = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&wren_bank(i))
val read_enable = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&(!wren_bank(i)))
val iccm_bank_dout = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W)))
//val inter = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W)))
for(i<-0 until ICCM_NUM_BANKS) when(write_vec(i)) {iccm_mem(i)(addr_bank(i)) := iccm_bank_wr_data(i)}
for(i<-0 until ICCM_NUM_BANKS) {iccm_bank_dout(i) := RegEnable(iccm_mem(i)(addr_bank(i)),0.U,read_enable(i))}
val redundant_valid = WireInit(UInt(2.W), init = 0.U)
val redundant_address = Wire(Vec(2, UInt((ICCM_BITS-2).W)))
redundant_address := (0 until 2).map(i=>0.U)
val sel_red1 = (0 until ICCM_NUM_BANKS).map(i=> (redundant_valid(1) & ((io.iccm_rw_addr(ICCM_BITS-2,1)===redundant_address(1)(ICCM_BITS-3,0)) & (io.iccm_rw_addr(2,1) === i.U)) |
((addr_bank_inc(ICCM_BITS-2,1)===redundant_address(1)(ICCM_BITS-3,0)) & (addr_bank_inc(2,1) === i.U))).asUInt).reverse.reduce(Cat(_,_))
val sel_red0 = (0 until ICCM_NUM_BANKS).map(i=> (redundant_valid(0) & ((io.iccm_rw_addr(ICCM_BITS-2,1)===redundant_address(0)(ICCM_BITS-3,0)) & (io.iccm_rw_addr(2,1) === i.U)) |
((addr_bank_inc(ICCM_BITS-2,1)===redundant_address(0)(ICCM_BITS-3,0)) & (addr_bank_inc(2,1) === i.U))).asUInt).reverse.reduce(Cat(_,_))
val sel_red0_q = RegNext(sel_red0, init = 0.U)
val sel_red1_q = RegNext(sel_red1, init = 0.U)
val redundant_data = Wire(Vec(2, UInt(39.W)))
redundant_data := (0 until 2).map(i=>0.U)
val iccm_bank_dout_fn = (0 until ICCM_NUM_BANKS).map(i=>
Mux1H(Seq(sel_red1_q(i).asBool->redundant_data(1),
sel_red0_q(i).asBool->redundant_data(0),
(~sel_red0_q(i) & ~sel_red1_q(i)).asBool -> iccm_bank_dout(i))))
val redundant_lru = WireInit(Bool(), init = 0.U)
val r0_addr_en = !redundant_lru & io.iccm_buf_correct_ecc
val r1_addr_en = redundant_lru & io.iccm_buf_correct_ecc
val redundant_lru_en = io.iccm_buf_correct_ecc | ((sel_red0.orR | sel_red1.orR) & io.iccm_rden & io.iccm_correction_state)
val redundant_lru_in = Mux(io.iccm_buf_correct_ecc, !redundant_lru, Mux(sel_red0.orR, 1.U, 0.U))
redundant_lru := RegEnable(redundant_lru_in, 0.U, redundant_lru_en)
redundant_address(0) := RegEnable(io.iccm_rw_addr(ICCM_BITS-2,1), 0.U, r0_addr_en)
redundant_address(1) := RegEnable(io.iccm_rw_addr(ICCM_BITS-2,1), 0.U, r1_addr_en.asBool)
redundant_valid := Cat(RegEnable(1.U, 0.U, r1_addr_en.asBool),RegEnable(1.U, 0.U, r0_addr_en))
val redundant_data0_en = ((io.iccm_rw_addr(ICCM_BITS-2,2) === redundant_address(0)(ICCM_BITS-3,1)) &
((io.iccm_rw_addr(1) & redundant_address(0)(0))| (io.iccm_wr_size(1,0)===3.U)) & redundant_valid(0) & io.iccm_wren) |
(!redundant_lru & io.iccm_buf_correct_ecc)
val redundant_data0_in = Mux(((io.iccm_rw_addr(1)&redundant_address(0)(0)) |(redundant_address(0)(0) & (io.iccm_wr_size(1,0)===3.U))).asBool,
io.iccm_wr_data(77,39), io.iccm_wr_data(38,0))
redundant_data(0) := RegEnable(redundant_data0_in, 0.U, redundant_data0_en.asBool)
val redundant_data1_en = ((io.iccm_rw_addr(ICCM_BITS-2,2) === redundant_address(1)(ICCM_BITS-3,1)) &
((io.iccm_rw_addr(1) & redundant_address(1)(0))| (io.iccm_wr_size(1,0)===3.U)) & redundant_valid(1) & io.iccm_wren) |
(!redundant_lru & io.iccm_buf_correct_ecc)
val redundant_data1_in = Mux(((io.iccm_rw_addr(1)&redundant_address(1)(0)) |(redundant_address(1)(0) & (io.iccm_wr_size(1,0)===3.U))).asBool,
io.iccm_wr_data(77,39), io.iccm_wr_data(38,0))
redundant_data(1) := RegEnable(redundant_data1_in, 0.U, redundant_data1_en.asBool)
val iccm_rd_addr_lo_q = RegNext(RegEnable(io.iccm_rw_addr(ICCM_BANK_HI-1,0), 0.U, 1.U.asBool), 0.U)
val iccm_rd_addr_hi_q = RegNext(addr_bank_inc(ICCM_BANK_HI-1,1), 0.U)
//val hig_q_vec = (0 until ICCM_NUM_BANKS)
val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(if(i==3) 0 else i+1)(31,0))),
Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(i)(31,0))))
io.iccm_rd_data := Mux(iccm_rd_addr_lo_q(0).asBool(),Cat(Fill(16,0.U),iccm_rd_data_pre(63,16)) ,iccm_rd_data_pre)
io.iccm_rd_data_ecc :=Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i))),
Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-2,0)===i.U)->iccm_bank_dout_fn(i))))
io.iccm_rd_data_ecc := Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(if(i==3) 0 else i+1)(38,0))),
Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(i)(38,0))))
}
object ifu_iccm extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_iccm_mem()))
}

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src/main/scala/ifu/el2_ifu_ifc_ctl.scala Normal file
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package ifu
import lib._
import chisel3._
import chisel3.util._
class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{
val free_clk = Input(Clock())
val active_clk = Input(Clock())
val scan_mode = Input(Bool())
val ic_hit_f = Input(Bool())
val ifu_ic_mb_empty = Input(Bool())
val ifu_fb_consume1 = Input(Bool())
val ifu_fb_consume2 = Input(Bool())
val dec_tlu_flush_noredir_wb = Input(Bool())
val exu_flush_final = Input(Bool())
val exu_flush_path_final = Input(UInt(31.W))
val ifu_bp_hit_taken_f = Input(Bool())
val ifu_bp_btb_target_f = Input(UInt(31.W))
val ic_dma_active = Input(Bool())
val ic_write_stall = Input(Bool())
val dma_iccm_stall_any = Input(Bool())
val dec_tlu_mrac_ff = Input(UInt(32.W))
val ifc_fetch_addr_f = Output(UInt(31.W))
val ifc_fetch_addr_bf = Output(UInt(31.W))
val ifc_fetch_req_f = Output(Bool())
val ifu_pmu_fetch_stall = Output(Bool())
val ifc_fetch_uncacheable_bf = Output(Bool())
val ifc_fetch_req_bf = Output(Bool())
val ifc_fetch_req_bf_raw = Output(Bool())
val ifc_iccm_access_bf = Output(Bool())
val ifc_region_acc_fault_bf = Output(Bool())
val ifc_dma_access_ok = Output(Bool())
})
val fetch_addr_bf = WireInit(UInt(31.W), init = 0.U)
val fetch_addr_next_0 = WireInit(Bool(), 0.U)
val fetch_addr_next = WireInit(UInt(31.W), init = 0.U)
val fb_write_ns = WireInit(UInt(4.W), init = 0.U)
val fb_write_f = WireInit(UInt(4.W), init = 0.U)
val fb_full_f_ns = WireInit(Bool(), init = 0.U)
val fb_right = WireInit(Bool(), init = 0.U)
val fb_right2 = WireInit(Bool(), init = 0.U)
val fb_left = WireInit(Bool(), init = 0.U)
val wfm = WireInit(Bool(), init = 0.U)
val idle = WireInit(Bool(), init = 0.U)
val miss_f = WireInit(Bool(), init = 0.U)
val miss_a = WireInit(Bool(), init = 0.U)
val flush_fb = WireInit(Bool(), init = 0.U)
val mb_empty_mod = WireInit(Bool(), init = 0.U)
val goto_idle = WireInit(Bool(), init = 0.U)
val leave_idle = WireInit(Bool(), init = 0.U)
val fetch_bf_en = WireInit(Bool(), init = 0.U)
val line_wrap = WireInit(Bool(), init = 0.U)
val state = WireInit(UInt(2.W), init = 0.U)
val dma_iccm_stall_any_f = WireInit(Bool(), init = 0.U)
val idle_E :: fetch_E :: stall_E :: wfm_E :: Nil = Enum(4)
val dma_stall = io.ic_dma_active | dma_iccm_stall_any_f
dma_iccm_stall_any_f := withClock(io.free_clk) {RegNext(io.dma_iccm_stall_any, init=0.U)}
miss_a := withClock(io.free_clk) {RegNext(miss_f, init=0.U)}
val sel_last_addr_bf = !io.exu_flush_final & (!io.ifc_fetch_req_f | !io.ic_hit_f)
val sel_btb_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f
val sel_next_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f
// TODO: Make an assertion for the 1H-Mux under here
io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC
sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC
sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC
sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
val address_upper = io.ifc_fetch_addr_f(30,1)+1.U
fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-2) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
fetch_addr_next := Cat(address_upper, fetch_addr_next_0)
io.ifc_fetch_req_bf_raw := ~idle
io.ifc_fetch_req_bf := io.ifc_fetch_req_bf_raw & !(fb_full_f_ns & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) &
!dma_stall & !io.ic_write_stall & !io.dec_tlu_flush_noredir_wb
fetch_bf_en := io.exu_flush_final | io.ifc_fetch_req_f
miss_f := io.ifc_fetch_req_f & !io.ic_hit_f & !io.exu_flush_final
mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_flush_final) & !dma_stall & !miss_f & !miss_a
goto_idle := io.exu_flush_final & io.dec_tlu_flush_noredir_wb
leave_idle := io.exu_flush_final & !io.dec_tlu_flush_noredir_wb & idle
val next_state_1 = (!state(1) & state(0) & miss_f & !goto_idle) |
(state(1) & !mb_empty_mod & !goto_idle)
val next_state_0 = (!goto_idle & leave_idle) | (state(0) & !goto_idle)
state := withClock(io.active_clk) {RegNext(Cat(next_state_1, next_state_0), init = 0.U)}
flush_fb := io.exu_flush_final
fb_right := ( io.ifu_fb_consume1 & !io.ifu_fb_consume2 & (!io.ifc_fetch_req_f | miss_f)) |
(io.ifu_fb_consume2 & io.ifc_fetch_req_f)
fb_right2 := (io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f))
fb_left := io.ifc_fetch_req_f & !(io.ifu_fb_consume1 | io.ifu_fb_consume2) & !miss_f
fb_write_ns := Mux1H(Seq(flush_fb.asBool -> 1.U(4.W),
(!flush_fb & fb_right).asBool -> Cat(0.U(1.W), fb_write_f(3,1)),
(!flush_fb & fb_right2).asBool -> Cat(0.U(2.W), fb_write_f(3,2)),
(!flush_fb & fb_left).asBool -> Cat(fb_write_f(2,0), 0.U(1.W)),
(!flush_fb & !fb_right & !fb_right2 & !fb_left).asBool -> fb_write_f(3,0)
))
idle := state === 0.U(2.W)
wfm := state === 3.U(2.W)
fb_full_f_ns := fb_write_ns(3)
val fb_full_f = withClock(io.active_clk) {RegNext(fb_full_f_ns, init = 0.U)}
fb_write_f := withClock(io.active_clk) {RegNext(fb_write_ns, 0.U)}
io.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw &
((fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE)
rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U))
else (0.U, 0.U)
io.ifc_iccm_access_bf := iccm_acc_in_range_bf
io.ifc_dma_access_ok := ( (!io.ifc_iccm_access_bf |
(fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) |
(wfm & !io.ifc_fetch_req_bf) | idle ) & !io.exu_flush_final) | dma_iccm_stall_any_f
io.ifc_region_acc_fault_bf := !iccm_acc_in_range_bf & iccm_acc_in_region_bf
io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U))
io.ifc_fetch_req_f := withClock(io.active_clk){RegNext(io.ifc_fetch_req_bf, init=0.U)}
io.ifc_fetch_addr_f := rvdffe(io.ifc_fetch_addr_bf, io.exu_flush_final|io.ifc_fetch_req_f, clock, io.scan_mode)
//rvdffe(io.ifc_fetch_addr_bf,(io.exu_flush_final|io.ifc_fetch_req_f).asBool,clock,io.scan_mode)
}
object ifu_ifc extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctl()))
}

858
src/main/scala/ifu/el2_ifu_mem_ctl.scala Normal file
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package ifu
import chisel3._
import chisel3.internal.naming.chiselName
import chisel3.util._
import lib._
import include._
import scala.math.pow
@chiselName
class mem_ctl_bundle extends Bundle with el2_lib{
val free_clk = Input(Clock())
val active_clk = Input(Clock())
val exu_flush_final = Input(Bool())
val dec_tlu_flush_lower_wb = Input(Bool())
val dec_tlu_flush_err_wb = Input(Bool())
val dec_tlu_i0_commit_cmt = Input(Bool())
val dec_tlu_force_halt = Input(Bool())
val ifc_fetch_addr_bf = Input(UInt(31.W))
val ifc_fetch_uncacheable_bf = Input(Bool())
val ifc_fetch_req_bf = Input(Bool())
val ifc_fetch_req_bf_raw = Input(Bool())
val ifc_iccm_access_bf = Input(Bool())
val ifc_region_acc_fault_bf = Input(Bool())
val ifc_dma_access_ok = Input(Bool())
val dec_tlu_fence_i_wb = Input(Bool())
val ifu_bp_hit_taken_f = Input(Bool())
val ifu_bp_inst_mask_f = Input(Bool())
val ifu_axi_arready = Input(Bool())
val ifu_axi_rvalid = Input(Bool())
val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
val ifu_axi_rdata = Input(UInt(64.W))
val ifu_axi_rresp = Input(UInt(2.W))
val ifu_bus_clk_en = Input(Bool())
val dma_iccm_req = Input(Bool())
val dma_mem_addr = Input(UInt(32.W))
val dma_mem_sz = Input(UInt(3.W))
val dma_mem_write = Input(Bool())
val dma_mem_wdata = Input(UInt(64.W))
val dma_mem_tag = Input(UInt(3.W))
val ic_rd_data = Input(UInt(64.W))
val ic_debug_rd_data = Input(UInt(71.W))
val ictag_debug_rd_data = Input(UInt(26.W))
val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_perr = Input(Bool())
val iccm_rd_data = Input(UInt(64.W))
val iccm_rd_data_ecc = Input(UInt(78.W))
val ifu_fetch_val = Input(UInt(2.W))
val dec_tlu_ic_diag_pkt = Input(new el2_cache_debug_pkt_t)
val ifu_miss_state_idle = Output(Bool())
val ifu_ic_mb_empty = Output(Bool())
val ic_dma_active = Output(Bool())
val ic_write_stall = Output(Bool())
val ifu_pmu_ic_miss = Output(Bool())
val ifu_pmu_ic_hit = Output(Bool())
val ifu_pmu_bus_error = Output(Bool())
val ifu_pmu_bus_busy = Output(Bool())
val ifu_pmu_bus_trxn = Output(Bool())
val ifu_axi_awvalid = Output(Bool())
val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_awaddr = Output(UInt(32.W))
val ifu_axi_awregion = Output(UInt(4.W))
val ifu_axi_awlen = Output(UInt(8.W))
val ifu_axi_awsize = Output(UInt(3.W))
val ifu_axi_awburst = Output(UInt(2.W))
val ifu_axi_awlock = Output(Bool())
val ifu_axi_awcache = Output(UInt(4.W))
val ifu_axi_awprot = Output(UInt(3.W))
val ifu_axi_awqos = Output(UInt(4.W))
val ifu_axi_wvalid = Output(Bool())
val ifu_axi_wdata = Output(UInt(64.W))
val ifu_axi_wstrb = Output(UInt(8.W))
val ifu_axi_wlast = Output(Bool())
val ifu_axi_bready = Output(Bool())
val ifu_axi_arvalid = Output(Bool())
val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_araddr = Output(UInt(32.W))
val ifu_axi_arregion = Output(UInt(4.W))
val ifu_axi_arlen = Output(UInt(8.W))
val ifu_axi_arsize = Output(UInt(3.W))
val ifu_axi_arburst = Output(UInt(2.W))
val ifu_axi_arlock = Output(Bool())
val ifu_axi_arcache = Output(UInt(4.W))
val ifu_axi_arprot = Output(UInt(3.W))
val ifu_axi_arqos = Output(UInt(4.W))
val ifu_axi_rready = Output(Bool())
val iccm_dma_ecc_error = Output(Bool())
val iccm_dma_rvalid = Output(Bool())
val iccm_dma_rdata = Output(UInt(64.W))
val iccm_dma_rtag = Output(UInt(3.W))
val iccm_ready = Output(Bool())
val ic_rw_addr = Output(UInt(31.W))
val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_en = Output(Bool())
val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
val ic_debug_wr_data = Output(UInt(71.W))
val ifu_ic_debug_rd_data = Output(UInt(71.W))
val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W))
val ic_debug_rd_en = Output(Bool())
val ic_debug_wr_en = Output(Bool())
val ic_debug_tag_array = Output(Bool())
val ic_debug_way = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W))
val iccm_rw_addr = Output(UInt((ICCM_BITS-1).W))
val iccm_wren = Output(Bool())
val iccm_rden = Output(Bool())
val iccm_wr_data = Output(UInt(78.W))
val iccm_wr_size = Output(UInt(3.W))
val ic_hit_f = Output(Bool())
val ic_access_fault_f = Output(Bool())
val ic_access_fault_type_f = Output(UInt(2.W))
val iccm_rd_ecc_single_err = Output(Bool())
val iccm_rd_ecc_double_err = Output(Bool())
val ic_error_start = Output(Bool())
val ifu_async_error_start = Output(Bool())
val iccm_dma_sb_error = Output(Bool())
val ic_fetch_val_f = Output(UInt(2.W))
val ic_data_f = Output(UInt(32.W))
val ic_premux_data = Output(UInt(64.W))
val ic_sel_premux_data = Output(Bool())
val dec_tlu_core_ecc_disable = Input(Bool())
val ifu_ic_debug_rd_data_valid = Output(Bool())
val iccm_buf_correct_ecc = Output(Bool())
val iccm_correction_state = Output(Bool())
val scan_mode = Input(Bool())
}
class el2_ifu_mem_ctl extends Module with el2_lib {
val io = IO(new mem_ctl_bundle)
io.ifu_axi_wvalid := 0.U
io.ifu_axi_wdata := 0.U
io.ifu_axi_awqos := 0.U
io.ifu_axi_awaddr := 0.U
io.ifu_axi_awprot := 0.U
io.ifu_axi_awlen := 0.U
io.ifu_axi_arlock := 0.U
io.ifu_axi_awregion := 0.U
io.ifu_axi_awid := 0.U
io.ifu_axi_awvalid := 0.U
io.ifu_axi_wstrb := 0.U
io.ifu_axi_awcache := 0.U
io.ifu_axi_arqos := 0.U
io.ifu_axi_awlock := 0.U
io.ifu_axi_bready := 0.U
io.ifu_axi_arlen := 0.U
io.ifu_axi_awsize := 0.U
io.ifu_axi_arprot := 0.U
io.ifu_axi_awburst := 0.U
io.ifu_axi_wlast := 0.U
val idle_C :: crit_byp_ok_C :: hit_u_miss_C :: miss_wait_C :: crit_wrd_rdy_C :: scnd_miss_C :: stream_C :: stall_scnd_miss_C :: Nil = Enum(8)
val err_stop_idle_C :: err_fetch1_C :: err_fetch2_C :: err_stop_fetch_C :: Nil = Enum(4)
val err_idle_C :: ic_wff_C :: ecc_wff_C :: ecc_cor_C :: dma_sb_err_C :: Nil = Enum(5)
val iccm_single_ecc_error = WireInit(UInt(2.W), 0.U)
val ifc_fetch_req_f = WireInit(Bool(), false.B)
val miss_pending = WireInit(Bool(), false.B)
val scnd_miss_req = WireInit(Bool(), false.B)
val dma_iccm_req_f = WireInit(Bool(), false.B)
val iccm_correct_ecc = WireInit(Bool(), false.B)
val perr_state = WireInit(UInt(3.W), 0.U)
val err_stop_state = WireInit(UInt(2.W), 0.U)
val err_stop_fetch = WireInit(Bool(), false.B)
val miss_state = WireInit(UInt(3.W), 0.U)
val miss_nxtstate = WireInit(UInt(3.W), 0.U)
val miss_state_en = WireInit(Bool(), false.B)
val ifu_bus_rsp_valid = WireInit(Bool(), false.B)
val bus_ifu_bus_clk_en = WireInit(Bool(), false.B)
val ifu_bus_rsp_ready = WireInit(Bool(), false.B)
val uncacheable_miss_ff = WireInit(Bool(), false.B)
val ic_act_miss_f = WireInit(Bool(), false.B)
val ic_byp_hit_f = WireInit(Bool(), false.B)
val bus_new_data_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
val bus_ifu_wr_en_ff = WireInit(Bool(), false.B)
val last_beat = WireInit(Bool(), false.B)
val last_data_recieved_ff = WireInit(Bool(), false.B)
//val flush_final_f = WireInit(Bool(), 0.U)
val stream_eol_f = WireInit(Bool(), false.B)
val ic_miss_under_miss_f = WireInit(Bool(), false.B)
val ic_ignore_2nd_miss_f = WireInit(Bool(), false.B)
val ic_debug_rd_en_ff = WireInit(Bool(), false.B)
val debug_data_clk = rvclkhdr(clock, ic_debug_rd_en_ff, io.scan_mode)
val flush_final_f = RegNext(io.exu_flush_final, 0.U)
val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req
val debug_c1_clken = io.ic_debug_rd_en | io.ic_debug_wr_en
val debug_c1_clk = rvclkhdr(clock, debug_c1_clken, io.scan_mode)
val fetch_bf_f_c1_clk = rvclkhdr(clock, fetch_bf_f_c1_clken, io.scan_mode)
io.iccm_dma_sb_error := iccm_single_ecc_error.orR() & dma_iccm_req_f.asBool()
io.ifu_async_error_start := io.iccm_rd_ecc_single_err | io.ic_error_start
io.ic_dma_active := iccm_correct_ecc | (perr_state === dma_sb_err_C) | (err_stop_state === err_stop_fetch_C) | err_stop_fetch | io.dec_tlu_flush_err_wb
val scnd_miss_req_in = ifu_bus_rsp_valid & bus_ifu_bus_clk_en & ifu_bus_rsp_ready & (bus_new_data_beat_count.andR) &
!uncacheable_miss_ff & ((miss_state === scnd_miss_C)|(miss_nxtstate === scnd_miss_C)) & !io.exu_flush_final
val ifu_bp_hit_taken_q_f = io.ifu_bp_hit_taken_f & io.ic_hit_f
///////////////////////////////// MISS FSM /////////////////////////////////
switch(miss_state){
is (idle_C){
miss_nxtstate := Mux((ic_act_miss_f & !io.exu_flush_final).asBool, crit_byp_ok_C, hit_u_miss_C)
miss_state_en := ic_act_miss_f & !io.dec_tlu_force_halt}
is (crit_byp_ok_C){
miss_nxtstate := Mux((io.dec_tlu_force_halt | (ic_byp_hit_f & (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) & uncacheable_miss_ff)).asBool, idle_C,
Mux((ic_byp_hit_f & !last_data_recieved_ff & uncacheable_miss_ff).asBool, miss_wait_C,
Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & uncacheable_miss_ff).asBool, crit_wrd_rdy_C,
Mux(((bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
Mux((ic_byp_hit_f & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C,
Mux((bus_ifu_wr_en_ff & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C,
Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C))))))))
miss_state_en := io.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff)
}
is (crit_wrd_rdy_C){
miss_nxtstate := idle_C
miss_state_en := io.exu_flush_final | flush_final_f | ic_byp_hit_f | io.dec_tlu_force_halt
}
is (stream_C){
miss_nxtstate := Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f)&(!(bus_ifu_wr_en_ff & last_beat)) & !io.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C)
miss_state_en := io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f | (bus_ifu_wr_en_ff & last_beat) | io.dec_tlu_force_halt
}
is (miss_wait_C){
miss_nxtstate := Mux((io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C)
miss_state_en := io.exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | io.dec_tlu_force_halt
}
is (hit_u_miss_C){
miss_nxtstate := Mux((ic_miss_under_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, scnd_miss_C,
Mux((ic_ignore_2nd_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, stall_scnd_miss_C, idle_C))
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | io.dec_tlu_force_halt
}
is (scnd_miss_C){
miss_nxtstate := Mux(io.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final,
Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), crit_byp_ok_C))
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_tlu_force_halt
}
is (stall_scnd_miss_C){
miss_nxtstate := Mux(io.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final,
Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), idle_C))
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_tlu_force_halt
}
}
miss_state := RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)
val crit_byp_hit_f = WireInit(Bool(), 0.U)
val way_status_mb_scnd_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val tagv_mb_scnd_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val uncacheable_miss_scnd_ff = WireInit(Bool(), 0.U)
val imb_scnd_ff = WireInit(UInt(31.W), 0.U)
val reset_all_tags = WireInit(Bool(), 0.U)
val bus_rd_addr_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
val ifu_bus_rid_ff = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
miss_pending := miss_state =/= idle_C
val crit_wd_byp_ok_ff = (miss_state === crit_byp_ok_C) | ((miss_state === crit_wrd_rdy_C) & !flush_final_f)
val sel_hold_imb = (miss_pending & !(bus_ifu_wr_en_ff & last_beat) & !((miss_state === crit_wrd_rdy_C) & io.exu_flush_final) &
!((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f |
(miss_pending & (miss_nxtstate === crit_wrd_rdy_C))
val sel_hold_imb_scnd = ((miss_state === scnd_miss_C) | ic_miss_under_miss_f) & !flush_final_f
val way_status_mb_scnd_in = Mux(miss_state === scnd_miss_C, way_status_mb_scnd_ff, way_status)
val tagv_mb_scnd_in = Mux(miss_state === scnd_miss_C, tagv_mb_scnd_ff, Fill(ICACHE_NUM_WAYS, !reset_all_tags) & io.ic_tag_valid)
val uncacheable_miss_scnd_in = Mux(sel_hold_imb_scnd.asBool, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf)
uncacheable_miss_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_scnd_in, 0.U)}
val imb_scnd_in = Mux(sel_hold_imb_scnd.asBool, imb_scnd_ff, io.ifc_fetch_addr_bf)
imb_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(imb_scnd_in, 0.U)}
way_status_mb_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(way_status_mb_scnd_in, 0.U)}
tagv_mb_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_scnd_in, 0.U)}
val ic_req_addr_bits_hi_3 = bus_rd_addr_count
val ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & Fill(ICACHE_BEAT_BITS, bus_ifu_wr_en_ff)
val ifc_iccm_access_f = WireInit(Bool(), 0.U)
val ifc_region_acc_fault_final_f = WireInit(Bool(), 0.U)
val fetch_req_icache_f = ifc_fetch_req_f & !ifc_iccm_access_f & !ifc_region_acc_fault_final_f
val fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f
val ic_iccm_hit_f = fetch_req_iccm_f & (!miss_pending | (miss_state === hit_u_miss_C) | (miss_state === stream_C))
val stream_hit_f = WireInit(Bool(), 0.U)
ic_byp_hit_f := (crit_byp_hit_f | stream_hit_f) & fetch_req_icache_f & miss_pending
val sel_mb_addr_ff = WireInit(Bool(), 0.U)
val imb_ff = WireInit(UInt(31.W), 0.U)
val ifu_fetch_addr_int_f = WireInit(UInt(31.W), 0.U)
val ic_act_hit_f = io.ic_rd_hit.orR & fetch_req_icache_f & !reset_all_tags & (!miss_pending | (miss_state===hit_u_miss_C)) & !sel_mb_addr_ff
ic_act_miss_f := (((!io.ic_rd_hit.orR | reset_all_tags) & fetch_req_icache_f & !miss_pending) | scnd_miss_req) & !ifc_region_acc_fault_final_f
ic_miss_under_miss_f := (!io.ic_rd_hit | reset_all_tags) & fetch_req_icache_f & (miss_state===hit_u_miss_C) &
(imb_ff(30,ICACHE_TAG_INDEX_LO-1) =/= ifu_fetch_addr_int_f(30,ICACHE_TAG_INDEX_LO-1)) & !uncacheable_miss_ff & !sel_mb_addr_ff & !ifc_region_acc_fault_final_f
ic_ignore_2nd_miss_f := (!io.ic_rd_hit.orR | reset_all_tags) & fetch_req_icache_f & (miss_state === hit_u_miss_C) &
((imb_ff(30,ICACHE_TAG_INDEX_LO-1)===ifu_fetch_addr_int_f(30,ICACHE_TAG_INDEX_LO-1)) | uncacheable_miss_ff)
// Output
io.ic_hit_f := ic_act_hit_f | ic_byp_hit_f | ic_iccm_hit_f | (ifc_region_acc_fault_final_f & ifc_fetch_req_f)
val uncacheable_miss_in = Mux(scnd_miss_req.asBool, uncacheable_miss_scnd_ff, Mux(sel_hold_imb.asBool, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf))
val imb_in = Mux(scnd_miss_req.asBool, imb_scnd_ff, Mux(sel_hold_imb.asBool, imb_ff, io.ifc_fetch_addr_bf))
val ifu_wr_cumulative_err_data = WireInit(Bool(), 0.U)
val scnd_miss_index_match = (imb_ff(ICACHE_INDEX_HI-1,ICACHE_TAG_INDEX_LO-1)===imb_scnd_ff(ICACHE_INDEX_HI-1,ICACHE_TAG_INDEX_LO-1))& scnd_miss_req & !ifu_wr_cumulative_err_data
val way_status_mb_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status_rep_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status_mb_in = Mux((scnd_miss_req & !scnd_miss_index_match).asBool, way_status_mb_scnd_ff,
Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new,
Mux(miss_pending.asBool, way_status_mb_ff, way_status)))
val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
val tagv_mb_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val tagv_mb_in = Mux(scnd_miss_req.asBool, tagv_mb_scnd_ff | (Fill(ICACHE_NUM_WAYS, scnd_miss_index_match) & replace_way_mb_any.reverse.reduce(Cat(_,_))),
Mux(miss_pending.asBool, tagv_mb_ff, io.ic_tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags)))
val scnd_miss_req_q = WireInit(Bool(), false.B)
val reset_ic_ff = WireInit(Bool(), false.B)
val reset_ic_in = miss_pending & !scnd_miss_req_q & (reset_all_tags | reset_ic_ff)
reset_ic_ff := RegNext(reset_ic_in)
val fetch_uncacheable_ff = RegNext(io.ifc_fetch_uncacheable_bf, 0.U)
ifu_fetch_addr_int_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_fetch_addr_bf, 0.U)}
val vaddr_f = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1, 0)
uncacheable_miss_ff := withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_in, 0.U)}
imb_ff := withClock(fetch_bf_f_c1_clk){RegNext(imb_in)}
val miss_addr = WireInit(UInt((31-ICACHE_BEAT_ADDR_HI).W), 0.U)
val miss_addr_in = Mux(!miss_pending, imb_ff(30, ICACHE_BEAT_ADDR_HI),
Mux(scnd_miss_req_q.asBool, imb_scnd_ff(30, ICACHE_BEAT_ADDR_HI), miss_addr))
val busclk_reset = rvclkhdr(clock, bus_ifu_bus_clk_en | ic_act_miss_f | io.dec_tlu_force_halt, io.scan_mode)
miss_addr := withClock(busclk_reset) {RegNext(miss_addr_in, 0.U)}
way_status_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(way_status_mb_in, 0.U)}
tagv_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_in, 0.U)}
val stream_miss_f = WireInit(Bool(), 0.U)
val ifc_fetch_req_qual_bf = io.ifc_fetch_req_bf & !((miss_state===crit_wrd_rdy_C) & flush_final_f) & !stream_miss_f
val ifc_fetch_req_f_raw = RegNext(ifc_fetch_req_qual_bf, 0.U)
ifc_fetch_req_f := ifc_fetch_req_f_raw & !io.exu_flush_final
ifc_iccm_access_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_iccm_access_bf, 0.U)}
val ifc_region_acc_fault_final_bf = WireInit(Bool(), 0.U)
ifc_region_acc_fault_final_f := withClock(fetch_bf_f_c1_clk){RegNext(ifc_region_acc_fault_final_bf, 0.U)}
val ifc_region_acc_fault_f = withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_region_acc_fault_bf, 0.U)}
val ifu_ic_req_addr_f = Cat(miss_addr, ic_req_addr_bits_hi_3)
io.ifu_ic_mb_empty := (((miss_state===hit_u_miss_C) | (miss_state===stream_C)) & !(bus_ifu_wr_en_ff & last_beat)) | !miss_pending
io.ifu_miss_state_idle := miss_state === idle_C
val write_ic_16_bytes = WireInit(Bool(), false.B)
val reset_tag_valid_for_miss = WireInit(Bool(), false.B)
val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss
val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr -> Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)),
!sel_mb_addr -> io.ifc_fetch_addr_bf))
val bus_ifu_wr_en_ff_q = WireInit(Bool(), false.B)
val sel_mb_status_addr = miss_pending & write_ic_16_bytes & !uncacheable_miss_ff & last_beat & bus_ifu_wr_en_ff_q
val ifu_status_wr_addr = Mux(sel_mb_status_addr, Cat(imb_ff(30, ICACHE_BEAT_ADDR_HI),ic_wr_addr_bits_hi_3, imb_ff(1,0)), ifu_fetch_addr_int_f)
io.ic_rw_addr := ifu_ic_rw_int_addr
sel_mb_addr_ff := withClock(io.free_clk){RegNext(sel_mb_addr, 0.U)}
val ifu_bus_rdata_ff = WireInit(UInt(64.W), 0.U)
val ic_miss_buff_half = WireInit(UInt(64.W), 0.U)
val ic_wr_ecc = rvecc_encode_64(ifu_bus_rdata_ff)
val ic_miss_buff_ecc = rvecc_encode_64(ic_miss_buff_half)
val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U)
io.ic_wr_data := (0 until ICACHE_BANKS_WAY).map(i=>ic_wr_16bytes_data((i*(if(ICACHE_ECC) 71 else 68))+(if(ICACHE_ECC) 70 else 67),(if(ICACHE_ECC) 71 else 68)*i))
io.ic_debug_wr_data := io.dec_tlu_ic_diag_pkt.icache_wrdata
val ic_rd_parity_final_err = WireInit(Bool(), 0.U)
io.ic_error_start := ((if(ICACHE_ECC)io.ic_eccerr.orR()else io.ic_parerr.orR()) & ic_act_hit_f) | ic_rd_parity_final_err
val ic_debug_tag_val_rd_out = WireInit(Bool(), 0.U)
val ic_debug_ict_array_sel_ff = WireInit(Bool(), 0.U)
val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ictag_debug_rd_data(25,21),0.U(32.W),io.ictag_debug_rd_data(20,0), 0.U(7-ICACHE_STATUS_BITS), way_status, 0.U(3.W),ic_debug_tag_val_rd_out)
else Cat(0.U(6.W),io.ictag_debug_rd_data(21),0.U(32.W),io.ictag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) ,
io.ic_debug_rd_data)
io.ifu_ic_debug_rd_data := withClock(debug_data_clk){RegNext(ifu_ic_debug_rd_data_in, 0.U)}
val ic_wr_parity = (0 until 4).map(i=>rveven_paritygen(ifu_bus_rdata_ff((16*i)+15,16*i))).reverse.reduce(Cat(_,_))
val ic_miss_buff_parity = (0 until 4).map(i=>rveven_paritygen(ic_miss_buff_half((16*i)+15,16*i))).reverse.reduce(Cat(_,_))
ic_wr_16bytes_data := Mux(ifu_bus_rid_ff(0).asBool,Cat(if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff, if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half),
Cat(if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half, if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff))
val bus_ifu_wr_data_error_ff = WireInit(Bool(), 0.U)
val ifu_wr_data_comb_err_ff = WireInit(Bool(), 0.U)
val reset_beat_cnt = WireInit(Bool(), 0.U)
val ifu_wr_data_comb_err = bus_ifu_wr_data_error_ff
val ifu_wr_cumulative_err = (ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff) & !reset_beat_cnt
ifu_wr_cumulative_err_data := ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff
ifu_wr_data_comb_err_ff := withClock(io.free_clk) {RegNext(ifu_wr_cumulative_err, 0.U)}
val ic_crit_wd_rdy = WireInit(Bool(), 0.U)
val ifu_byp_data_err_new = WireInit(Bool(), 0.U)
val sel_byp_data = (ic_crit_wd_rdy | (miss_state===stream_C) | (miss_state===crit_byp_ok_C)) & !ifu_byp_data_err_new
val sel_ic_data = !(ic_crit_wd_rdy | (miss_state===stream_C) | (miss_state===crit_byp_ok_C)) & !fetch_req_iccm_f
val sel_iccm_data = fetch_req_iccm_f
val ic_byp_data_only_new = WireInit(UInt(80.W), 0.U)
val ic_final_data = Mux1H(Seq((sel_byp_data | (if(ICCM_ICACHE) (sel_iccm_data | sel_ic_data) else if(ICACHE_ONLY) sel_ic_data else 0.U)).asBool->
(if(ICCM_ICACHE) io.ic_rd_data else ic_byp_data_only_new(63,0))))
val ic_premux_data_temp = if(ICCM_ICACHE) (Fill(64,sel_iccm_data) & io.iccm_rd_data) | (Fill(64, sel_byp_data) & ic_byp_data_only_new)
else if(ICACHE_ONLY) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
val ic_sel_premux_data_temp = if(ICCM_ICACHE) sel_iccm_data | sel_byp_data else if(ICACHE_ONLY) sel_byp_data else 0.U
io.ic_premux_data := ic_premux_data_temp
io.ic_sel_premux_data := ic_sel_premux_data_temp
val ifc_bus_acc_fault_f = ic_byp_hit_f & ifu_byp_data_err_new
io.ic_data_f := ic_final_data
val fetch_req_f_qual = io.ic_hit_f & !io.exu_flush_final
val ifc_region_acc_fault_memory_f = WireInit(Bool(), 0.U)
io.ic_access_fault_f := (ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f) & !io.exu_flush_final
io.ic_access_fault_type_f := Mux(io.iccm_rd_ecc_double_err.asBool, 1.U,
Mux(ifc_region_acc_fault_f.asBool, 2.U,
Mux(ifc_region_acc_fault_memory_f.asBool(), 3.U, 0.U)))
io.ic_fetch_val_f := Cat(fetch_req_f_qual & io.ifu_bp_inst_mask_f & !(vaddr_f===Fill(ICACHE_BEAT_ADDR_HI,1.U)) & (err_stop_state=/=err_fetch2_C), fetch_req_f_qual)
val two_byte_instr = io.ic_data_f(1,0) =/= 3.U
//// Creating full buffer
val ifu_bus_rsp_rdata = WireInit(UInt(64.W), 0.U)
val ic_miss_buff_data_in = ifu_bus_rsp_rdata
val ifu_bus_rsp_tag = WireInit(UInt(IFU_BUS_TAG.W), 0.U)
val bus_ifu_wr_en = WireInit(Bool(), false.B)
val write_fill_data = (0 until ICACHE_NUM_BEATS).map(i=>bus_ifu_wr_en & (ifu_bus_rsp_tag===i.U))
val ic_miss_buff_data = Wire(Vec(2*ICACHE_NUM_BEATS, UInt(32.W)))
for(i<- 0 until ICACHE_NUM_BEATS){
val wr_data_c1_clk = write_fill_data.map(rvclkhdr(clock, _ , io.scan_mode))
ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)}
ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}}
val ic_miss_buff_data_valid = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U)
val ic_miss_buff_data_valid_in = (0 until ICACHE_NUM_BEATS).map(i=>write_fill_data(i)|(ic_miss_buff_data_valid(i)&(!ic_act_miss_f)))
ic_miss_buff_data_valid := withClock(io.free_clk){RegNext(ic_miss_buff_data_valid_in.map(i=>i.asUInt()).reverse.reduce(Cat(_,_)), 0.U)}
val bus_ifu_wr_data_error = WireInit(Bool(), 0.U)
val ic_miss_buff_data_error = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U)
val ic_miss_buff_data_error_in =(0 until ICACHE_NUM_BEATS).map(i=>Mux(write_fill_data(i).asBool,bus_ifu_wr_data_error,
ic_miss_buff_data_error(i) & !ic_act_miss_f))
ic_miss_buff_data_error := withClock(io.free_clk){RegNext(ic_miss_buff_data_error_in.reverse.reduce(Cat(_,_)), 0.U)}
// New Bypass ready
val bypass_index = imb_ff(ICACHE_BEAT_ADDR_HI-1, 0)
val bypass_index_5_3_inc = bypass_index(bypass_index.getWidth-1,2) + 1.U
val bypass_valid_value_check = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(bypass_index.getWidth-1,2)===i.U).asBool->ic_miss_buff_data_valid_in(i)))
val bypass_data_ready_in = (bypass_valid_value_check & !bypass_index(1) & !bypass_index(0)) |
(bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) |
(bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) |
(bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) |
(bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U))
val ic_crit_wd_rdy_new_ff = WireInit(Bool(), 0.U)
val ic_crit_wd_rdy_new_in = (bypass_data_ready_in & crit_wd_byp_ok_ff & uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
(ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final)
ic_crit_wd_rdy_new_ff := withClock(io.free_clk){RegNext(ic_crit_wd_rdy_new_in, 0.U)}
val byp_fetch_index = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,0)
val byp_fetch_index_0 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 0.U)
val byp_fetch_index_1 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 1.U)
val byp_fetch_index_inc = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2) + 1.U
val byp_fetch_index_inc_0 = Cat(byp_fetch_index_inc, 0.U)
val byp_fetch_index_inc_1 = Cat(byp_fetch_index_inc, 1.U)
val ic_miss_buff_data_error_bypass = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===i.U).asBool->ic_miss_buff_data_error(i)))
val ic_miss_buff_data_error_bypass_inc = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc===i.U).asBool->ic_miss_buff_data_error(i)))
when(ifu_fetch_addr_int_f(1)&ifu_fetch_addr_int_f(0)){
ifu_byp_data_err_new := ic_miss_buff_data_error_bypass
} otherwise{ifu_byp_data_err_new := ic_miss_buff_data_error_bypass | ic_miss_buff_data_error_bypass_inc}
val ic_byp_data_only_pre_new = Mux(!ifu_fetch_addr_int_f(1).asBool,
Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_0===i.U).asBool->ic_miss_buff_data(i)(31,0)))),
Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_1===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0)))))
ic_byp_data_only_new := Mux(!ifu_fetch_addr_int_f(0).asBool(),ic_byp_data_only_pre_new,Cat(0.U(16.W),ic_byp_data_only_pre_new(79,16)))
val miss_wrap_f = imb_ff(ICACHE_TAG_INDEX_LO-1) =/= ifu_fetch_addr_int_f(ICACHE_TAG_INDEX_LO-1)
val ic_miss_buff_data_valid_bypass_index = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2)===i.U).asBool->ic_miss_buff_data_valid(i)))
val ic_miss_buff_data_valid_inc_bypass_index = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc===i.U).asBool->ic_miss_buff_data_valid(i)))
val miss_buff_hit_unq_f = (ic_miss_buff_data_valid_bypass_index & !byp_fetch_index(1) & !byp_fetch_index(0)) |
(ic_miss_buff_data_valid_bypass_index & !byp_fetch_index(1) & byp_fetch_index(0)) |
(ic_miss_buff_data_valid_bypass_index & byp_fetch_index(1) & !byp_fetch_index(0)) |
(ic_miss_buff_data_valid_bypass_index & byp_fetch_index(1) & byp_fetch_index(0) & ic_miss_buff_data_valid_inc_bypass_index) |
(ic_miss_buff_data_valid_bypass_index & (byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2) === Fill(ICACHE_BEAT_BITS,1.U)))
stream_hit_f := (miss_state===stream_C) & (miss_buff_hit_unq_f & !miss_wrap_f)
stream_miss_f := (miss_state===stream_C) & !(miss_buff_hit_unq_f & !miss_wrap_f) & ifc_fetch_req_f
stream_eol_f := (byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,1)===Fill(ICACHE_BEAT_BITS+1, 1.U)) & ifc_fetch_req_f & stream_hit_f
crit_byp_hit_f := miss_buff_hit_unq_f & ((miss_state===crit_wrd_rdy_C) | (miss_state===crit_byp_ok_C))
val other_tag = Cat(ifu_bus_rid_ff(IFU_BUS_TAG-1,1),!ifu_bus_rid_ff(0))
val second_half_available = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(other_tag===i.U).asBool->ic_miss_buff_data_valid(i)))
write_ic_16_bytes := second_half_available & bus_ifu_wr_en_ff
ic_miss_buff_half := Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,1.U)===i.U).asBool->ic_miss_buff_data(i))),
Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,0.U)===i.U).asBool->ic_miss_buff_data(i))))
ic_rd_parity_final_err := io.ic_tag_perr & sel_ic_data & !(ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f)
val ifu_ic_rw_int_addr_ff = WireInit(UInt((ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO+1).W), 0.U)
val perr_sb_write_status = WireInit(Bool(), false.B)
val perr_ic_index_ff = withClock(io.active_clk){RegEnable(ifu_ic_rw_int_addr_ff, 0.U, perr_sb_write_status)}
val perr_sel_invalidate = WireInit(Bool(), false.B)
val perr_err_inv_way = Fill(ICACHE_NUM_WAYS, perr_sel_invalidate)
iccm_correct_ecc := perr_state === ecc_cor_C
val dma_sb_err_state = perr_state === dma_sb_err_C
val dma_sb_err_state_ff = Wire(Bool())
io.iccm_buf_correct_ecc := iccm_correct_ecc & !dma_sb_err_state_ff
dma_sb_err_state_ff := withClock(io.active_clk){RegNext(dma_sb_err_state, false.B)}
///////////////////////////////// ERROR FSM /////////////////////////////////
val perr_nxtstate = WireInit(UInt(3.W), 0.U)
val perr_state_en = WireInit(Bool(), false.B)
val iccm_error_start = WireInit(Bool(), false.B)
switch(perr_state){
is(err_idle_C){
perr_nxtstate := Mux(io.iccm_dma_sb_error, dma_sb_err_C, Mux((io.ic_error_start & !io.exu_flush_final).asBool, ic_wff_C, ecc_wff_C))
perr_state_en := (((iccm_error_start | io.ic_error_start) & !io.exu_flush_final) | io.iccm_dma_sb_error) & !io.dec_tlu_force_halt
perr_sb_write_status := perr_state_en
}
is(ic_wff_C){
perr_nxtstate := err_idle_C
perr_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_force_halt
perr_sel_invalidate := io.dec_tlu_flush_lower_wb & io.dec_tlu_force_halt
}
is(ecc_wff_C){
perr_nxtstate := Mux(((io.dec_tlu_flush_err_wb & io.dec_tlu_flush_lower_wb ) | io.dec_tlu_force_halt).asBool(), err_idle_C, ecc_cor_C)
perr_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_force_halt
}
is(dma_sb_err_C){
perr_nxtstate := Mux(io.dec_tlu_force_halt, err_idle_C, ecc_cor_C)
perr_state_en := true.B
}
is(ecc_cor_C){
perr_nxtstate := err_idle_C
perr_state_en := true.B
}
}
perr_state := withClock(io.free_clk){RegEnable(perr_nxtstate, 0.U, perr_state_en)}
///////////////////////////////// STOP FETCH FSM /////////////////////////////////
val err_stop_nxtstate = WireInit(UInt(2.W), 0.U)
val err_stop_state_en = WireInit(Bool(), false.B)
io.iccm_correction_state := false.B
// val err_stop_fetch := WireInit(Bool(), false.B)
switch(err_stop_state){
is(err_stop_idle_C){
err_stop_nxtstate := err_fetch1_C
err_stop_state_en := io.dec_tlu_flush_err_wb & (perr_state === ecc_wff_C) & !io.dec_tlu_force_halt
}
is(err_fetch1_C){
err_stop_nxtstate := Mux((io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.dec_tlu_force_halt).asBool(), err_stop_idle_C,
Mux(((io.ifu_fetch_val===3.U)|(io.ifu_fetch_val(0)&two_byte_instr)).asBool(), err_stop_fetch_C,
Mux(io.ifu_fetch_val(0).asBool(), err_fetch2_C, err_fetch1_C)))
err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | ifu_bp_hit_taken_q_f | io.dec_tlu_force_halt
err_stop_fetch := ((io.ifu_fetch_val(1,0)===3.U) | (io.ifu_fetch_val(0) & two_byte_instr)) & !(io.exu_flush_final | io.dec_tlu_i0_commit_cmt)
io.iccm_correction_state := true.B
}
is(err_fetch2_C){
err_stop_nxtstate := Mux((io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.dec_tlu_force_halt).asBool,
err_stop_idle_C, Mux(io.ifu_fetch_val(0).asBool, err_stop_fetch_C, err_fetch2_C))
err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | io.dec_tlu_force_halt
err_stop_fetch := io.ifu_fetch_val(0) & !io.exu_flush_final & !io.dec_tlu_i0_commit_cmt
io.iccm_correction_state := true.B
}
is(err_stop_fetch_C){
err_stop_nxtstate := Mux(((io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_err_wb) | io.dec_tlu_i0_commit_cmt | io.dec_tlu_force_halt).asBool,
err_stop_idle_C, Mux(io.dec_tlu_flush_err_wb.asBool(), err_fetch1_C, err_stop_fetch_C))
err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.dec_tlu_force_halt
err_stop_fetch := true.B
io.iccm_correction_state := true.B
}
}
err_stop_state := withClock(io.free_clk){RegEnable(err_stop_nxtstate, 0.U, err_stop_state_en)}
bus_ifu_bus_clk_en := io.ifu_bus_clk_en
val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode)
val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_tlu_force_halt , io.scan_mode)
val bus_ifu_bus_clk_en_ff = withClock(io.free_clk){RegNext(bus_ifu_bus_clk_en, 0.U)}
scnd_miss_req_q := withClock(io.free_clk){RegNext(scnd_miss_req_in, 0.U)}
val scnd_miss_req_ff2 = withClock(io.free_clk){RegNext(scnd_miss_req, 0.U)}
scnd_miss_req := scnd_miss_req_q & (!io.exu_flush_final)
val bus_cmd_req_hold = WireInit(Bool(), false.B)
val ifu_bus_cmd_valid = WireInit(Bool(), false.B)
val bus_cmd_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
val ifu_bus_cmd_ready = WireInit(Bool(), false.B)
val ifc_bus_ic_req_ff_in = (ic_act_miss_f | bus_cmd_req_hold | ifu_bus_cmd_valid) & !io.dec_tlu_force_halt & !((bus_cmd_beat_count===Fill(ICACHE_BEAT_BITS,1.U)) & ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending)
ifu_bus_cmd_valid := withClock(busclk_force){RegNext(ifc_bus_ic_req_ff_in, 0.U)}
val bus_cmd_sent = WireInit(Bool(), false.B)
val bus_cmd_req_in = (ic_act_miss_f | bus_cmd_req_hold) & !bus_cmd_sent & !io.dec_tlu_force_halt
bus_cmd_sent := withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)}
// AXI Read-Channel
io.ifu_axi_arvalid := ifu_bus_cmd_valid
io.ifu_axi_arid := bus_rd_addr_count & Fill(IFU_BUS_TAG, ifu_bus_cmd_valid)
io.ifu_axi_araddr := Cat(ifu_ic_req_addr_f, 0.U(3.W)) & Fill(32, ifu_bus_cmd_valid)
io.ifu_axi_arsize := 3.U(3.W)
io.ifu_axi_arcache := 15.U
io.ifu_axi_arregion := ifu_ic_req_addr_f(28,25)
io.ifu_axi_arburst := 1.U
io.ifu_axi_rready := true.B
val ifu_bus_arready_unq = io.ifu_axi_arready
val ifu_bus_rvalid_unq = io.ifu_axi_rvalid
val ifu_bus_arvalid = io.ifu_axi_arvalid
bus_ifu_bus_clk_en
val ifu_bus_arready_unq_ff = withClock(busclk){RegNext(ifu_bus_arready_unq, false.B)}
val ifu_bus_rvalid_unq_ff = withClock(busclk){RegNext(ifu_bus_rvalid_unq, false.B)}
val ifu_bus_arvalid_ff = withClock(busclk){RegNext(ifu_bus_arvalid, false.B)}
val ifu_bus_rresp_ff = withClock(busclk){RegNext(io.ifu_axi_rresp, 0.U)}
ifu_bus_rdata_ff := withClock(busclk){RegNext(io.ifu_axi_rdata, 0.U)}
ifu_bus_rid_ff := withClock(busclk){RegNext(io.ifu_axi_rid, 0.U)}
ifu_bus_cmd_ready := io.ifu_axi_arready
ifu_bus_rsp_valid := io.ifu_axi_rvalid
ifu_bus_rsp_ready := io.ifu_axi_rready
ifu_bus_rsp_tag := io.ifu_axi_rid
ifu_bus_rsp_rdata := io.ifu_axi_rdata
val ifu_bus_rsp_opc = io.ifu_axi_rresp
val ifu_bus_rvalid = ifu_bus_rsp_valid & bus_ifu_bus_clk_en
val ifu_bus_arready = ifu_bus_arready_unq & bus_ifu_bus_clk_en
val ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff
val ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff
bus_cmd_sent := ifu_bus_arvalid & ifu_bus_arready & miss_pending & !io.dec_tlu_force_halt
val bus_last_data_beat = WireInit(Bool(), false.B)
val bus_inc_data_beat_cnt = bus_ifu_wr_en_ff & !bus_last_data_beat & !io.dec_tlu_force_halt
val bus_reset_data_beat_cnt = ic_act_miss_f | (bus_ifu_wr_en_ff & bus_last_data_beat) | io.dec_tlu_force_halt
val bus_hold_data_beat_cnt = !bus_inc_data_beat_cnt & !bus_reset_data_beat_cnt
val bus_data_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
bus_new_data_beat_count := Mux1H(Seq(bus_reset_data_beat_cnt->0.U, bus_inc_data_beat_cnt-> (bus_data_beat_count + 1.U), bus_hold_data_beat_cnt->bus_data_beat_count))
bus_data_beat_count := withClock(io.free_clk){RegNext(bus_new_data_beat_count, 0.U)}
val last_data_recieved_in = (bus_ifu_wr_en_ff & bus_last_data_beat & !scnd_miss_req) | (last_data_recieved_ff & !ic_act_miss_f)
last_data_recieved_ff := withClock(io.free_clk){RegNext(last_data_recieved_in, 0.U)}
// Request Address Count
val bus_new_rd_addr_count = Mux(!miss_pending, imb_ff(ICACHE_BEAT_ADDR_HI-1, 2),
Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2),
Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count)))
bus_rd_addr_count := withClock(busclk_reset){RegNext(bus_new_rd_addr_count, 0.U)}
// Command beat Count
val bus_inc_cmd_beat_cnt = ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending & !io.dec_tlu_force_halt
val bus_reset_cmd_beat_cnt_0 = (ic_act_miss_f & !uncacheable_miss_in) | io.dec_tlu_force_halt
val bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in
val bus_hold_cmd_beat_cnt = !bus_inc_cmd_beat_cnt & !(ic_act_miss_f | scnd_miss_req | io.dec_tlu_force_halt)
val bus_cmd_beat_en = bus_inc_cmd_beat_cnt | ic_act_miss_f | io.dec_tlu_force_halt
val bus_new_cmd_beat_count = Mux1H(Seq(bus_reset_cmd_beat_cnt_0->0.U, bus_reset_cmd_beat_cnt_secondlast.asBool->ICACHE_SCND_LAST.U,
bus_inc_cmd_beat_cnt->(bus_cmd_beat_count+1.U), bus_hold_cmd_beat_cnt->bus_cmd_beat_count))
bus_cmd_beat_count := withClock(busclk_reset){RegEnable(bus_new_cmd_beat_count, 0.U, bus_cmd_beat_en)}
bus_last_data_beat := Mux(uncacheable_miss_ff, bus_data_beat_count===1.U, bus_data_beat_count.andR())
bus_ifu_wr_en := ifu_bus_rvalid & miss_pending
bus_ifu_wr_en_ff := ifu_bus_rvalid_ff & miss_pending
bus_ifu_wr_en_ff_q := ifu_bus_rvalid_ff & miss_pending & !uncacheable_miss_ff & !(ifu_bus_rresp_ff.orR) & write_ic_16_bytes
val bus_ifu_wr_en_ff_wo_err = ifu_bus_rvalid_ff & miss_pending & !uncacheable_miss_ff
val ic_act_miss_f_delayed = withClock(io.free_clk){RegNext(ic_act_miss_f, false.B)}
reset_tag_valid_for_miss := ic_act_miss_f_delayed & (miss_state===crit_byp_ok_C) & !uncacheable_miss_ff
bus_ifu_wr_data_error := ifu_bus_rsp_opc.orR() & ifu_bus_rvalid & miss_pending
bus_ifu_wr_data_error_ff := ifu_bus_rresp_ff.orR & ifu_bus_rvalid_ff & miss_pending
val ifc_dma_access_ok_d = WireInit(Bool(), false.B)
val ifc_dma_access_ok_prev = withClock(io.free_clk){RegNext(ifc_dma_access_ok_d, false.B)}
ic_crit_wd_rdy := ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff
last_beat := bus_last_data_beat & bus_ifu_wr_en_ff
reset_beat_cnt := bus_reset_data_beat_cnt
// DMA
ifc_dma_access_ok_d := io.ifc_dma_access_ok & !iccm_correct_ecc & !io.iccm_dma_sb_error
val ifc_dma_access_q_ok = io.ifc_dma_access_ok & !iccm_correct_ecc & ifc_dma_access_ok_prev & (perr_state===err_idle_C) & !io.iccm_dma_sb_error
io.iccm_ready := ifc_dma_access_q_ok
dma_iccm_req_f := withClock(io.free_clk){RegNext(io.dma_iccm_req, false.B)}
io.iccm_wren := (ifc_dma_access_q_ok & io.dma_iccm_req & io.dma_mem_write) | iccm_correct_ecc
io.iccm_rden := (ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write) | (io.ifc_iccm_access_bf & io.ifc_fetch_req_bf)
val iccm_dma_rden = ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write
io.iccm_wr_size := Fill(3, io.dma_iccm_req) & io.dma_mem_sz
val dma_mem_ecc = Cat(rvecc_encode(io.dma_mem_wdata(63,32)), rvecc_encode(io.dma_mem_wdata(31,0)))
val iccm_ecc_corr_data_ff = WireInit(UInt(39.W), 0.U)
io.iccm_wr_data := Mux(iccm_correct_ecc & !(ifc_dma_access_q_ok & io.dma_iccm_req), Fill(2,iccm_ecc_corr_data_ff),
Cat(dma_mem_ecc(13,7),io.dma_mem_wdata(63,32), dma_mem_ecc(6,0), io.dma_mem_wdata(31,0)))
val iccm_corrected_data = Wire(Vec(2, UInt(32.W)))
iccm_corrected_data(0) := 0.U
iccm_corrected_data(1) := 0.U
val dma_mem_addr_ff = WireInit(UInt(2.W), 0.U)
val iccm_dma_rdata_1_muxed = Mux(dma_mem_addr_ff(0).asBool, iccm_corrected_data(0), iccm_corrected_data(1))
val iccm_double_ecc_error = WireInit(UInt(2.W), 0.U)
val iccm_dma_ecc_error_in = iccm_double_ecc_error.orR
val iccm_dma_rdata_in = Mux(iccm_dma_ecc_error_in, Fill(2, io.dma_mem_addr), Cat(iccm_dma_rdata_1_muxed, iccm_corrected_data(0)))
val dma_mem_tag_ff = withClock(io.free_clk){RegNext(io.dma_mem_tag, 0.U)}
val iccm_dma_rtag_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(dma_mem_tag_ff, 0.U)} else 0.U
io.iccm_dma_rtag := iccm_dma_rtag_temp
dma_mem_addr_ff := withClock(io.free_clk) {RegNext(io.dma_mem_addr(3,2), 0.U)}
val iccm_dma_rvalid_in = withClock(io.free_clk) {RegNext(iccm_dma_rden, false.B)}
val iccm_dma_rvalid_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rvalid_in, false.B)} else 0.U
io.iccm_dma_rvalid := iccm_dma_rvalid_temp
val iccm_dma_ecc_error = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_ecc_error_in, false.B)} else 0.U
io.iccm_dma_ecc_error := iccm_dma_ecc_error_in
val iccm_dma_rdata_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rdata_in, 0.U)} else 0.U
io.iccm_dma_rdata := iccm_dma_rdata_temp
val iccm_ecc_corr_index_ff = WireInit(UInt((ICCM_BITS-2).W), 0.U)
io.iccm_rw_addr := Mux(ifc_dma_access_q_ok & io.dma_iccm_req & !iccm_correct_ecc, io.dma_mem_addr(ICCM_BITS-1,1),
Mux(!(ifc_dma_access_q_ok & io.dma_iccm_req) & iccm_correct_ecc, Cat(iccm_ecc_corr_index_ff, 0.U), io.ifc_fetch_addr_bf(ICCM_BITS-2,0)))
val ic_fetch_val_int_f = Cat(0.U(2.W), io.ic_fetch_val_f)
val ic_fetch_val_shift_right = ic_fetch_val_int_f << ifu_fetch_addr_int_f(0)
val iccm_rdmux_data = io.iccm_rd_data_ecc
val iccm_ecc_word_enable = (0 until 2).map(i=>((ic_fetch_val_shift_right((2*i+1),(2*i)) & !io.exu_flush_final & sel_iccm_data) | iccm_dma_rvalid_in) & !io.dec_tlu_core_ecc_disable).reverse.reduce(Cat(_,_))
val ecc_decoded = (0 until 2).map(i=>rvecc_decode(iccm_ecc_word_enable(i), iccm_rdmux_data((39*i+31),(39*i)), iccm_rdmux_data((39*i+38),(39*i+32)), 0.U))
val iccm_corrected_ecc = Wire(Vec(2, UInt(7.W)))
iccm_corrected_ecc := VecInit(ecc_decoded(0)._1,ecc_decoded(1)._1)
iccm_corrected_data := VecInit(ecc_decoded(0)._2,ecc_decoded(1)._2)
iccm_single_ecc_error := Cat(ecc_decoded(0)._3,ecc_decoded(1)._3)
iccm_double_ecc_error := Cat(ecc_decoded(0)._4,ecc_decoded(1)._4)
io.iccm_rd_ecc_single_err := iccm_single_ecc_error.orR & ifc_iccm_access_f & ifc_fetch_req_f
io.iccm_rd_ecc_double_err := iccm_double_ecc_error.orR & ifc_iccm_access_f
val iccm_corrected_data_f_mux = Mux(iccm_single_ecc_error(0).asBool, iccm_corrected_data(0), iccm_corrected_data(1))
val iccm_corrected_ecc_f_mux = Mux(iccm_single_ecc_error(0).asBool, iccm_corrected_ecc(0), iccm_corrected_ecc(1))
val iccm_rd_ecc_single_err_ff = WireInit(Bool(), false.B)
val iccm_ecc_write_status = if(ICCM_ENABLE)((io.iccm_rd_ecc_single_err & !iccm_rd_ecc_single_err_ff) & !io.exu_flush_final) | io.iccm_dma_sb_error else 0.U
val iccm_rd_ecc_single_err_hold_in = (io.iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff) & !io.exu_flush_final
iccm_error_start := io.iccm_rd_ecc_single_err
val iccm_rw_addr_f = WireInit(UInt((ICCM_BITS-2).W), 0.U)
val iccm_ecc_corr_index_in = Mux(iccm_single_ecc_error(0).asBool(), iccm_rw_addr_f, iccm_rw_addr_f + 1.U)
iccm_rw_addr_f := withClock(io.free_clk){RegNext(io.iccm_rw_addr(ICCM_BITS-2,1), 0.U)}
iccm_rd_ecc_single_err_ff := withClock(io.free_clk){RegNext(iccm_rd_ecc_single_err_hold_in, false.B)}
iccm_ecc_corr_data_ff := withClock(io.free_clk){RegEnable(Cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux), 0.U, iccm_ecc_write_status.asBool())}
iccm_ecc_corr_index_ff := withClock(io.free_clk){RegEnable(iccm_ecc_corr_index_in, 0.U, iccm_ecc_write_status.asBool())}
io.ic_rd_en := (io.ifc_fetch_req_bf & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf &
!(((miss_state===stream_C) & !miss_state_en) |
((miss_state===crit_byp_ok_C) & !miss_state_en) |
((miss_state===stall_scnd_miss_C) & !miss_state_en) |
((miss_state===miss_wait_C) & !miss_state_en) |
((miss_state===crit_wrd_rdy_C) & !miss_state_en) |
((miss_state===crit_byp_ok_C) & miss_state_en & (miss_nxtstate===miss_wait_C)) )) |
(io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf)
val bus_ic_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
io.ic_wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes)
io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff)))
reset_all_tags := withClock(io.active_clk){RegNext(io.dec_tlu_fence_i_wb, false.B)}
val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss
val ifu_status_wr_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array, io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3),
ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
val ifu_status_wr_addr_ff = withClock(io.free_clk) {
RegNext(ifu_status_wr_addr_w_debug, 0.U)
}
val way_status_wr_en = WireInit(Bool(), false.B)
val way_status_wr_en_w_debug = way_status_wr_en | (io.ic_debug_wr_en & io.ic_debug_tag_array)
val way_status_wr_en_ff = withClock(io.free_clk) {
RegNext(way_status_wr_en_w_debug, false.B)
}
val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
if (ICACHE_STATUS_BITS == 1) io.ic_debug_wr_data(4) else io.ic_debug_wr_data(6, 4), way_status_new)
val way_status_new_ff = withClock(io.free_clk) {
RegNext(way_status_new_w_debug, 0.U)
}
val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U)
val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode))
val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W)))
for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8)
way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)}
val test_way_status_out = (0 until ICACHE_TAG_DEPTH).map(i=>way_status_out(i).asUInt).reverse.reduce(Cat(_,_))
// io.test_way_status_out := test_way_status_out
val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_))
//io.test_way_status_clken := test_way_status_clken
way_status := Mux1H((0 until ICACHE_TAG_DEPTH).map(i=>(ifu_ic_rw_int_addr_ff === i.U) -> way_status_out(i)))
val ifu_ic_rw_int_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array,
io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
ifu_ic_rw_int_addr_ff := withClock(io.free_clk) {
RegNext(ifu_ic_rw_int_addr_w_debug, 0.U)
}
val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en
val ifu_tag_wren_ff = withClock(io.free_clk) {
RegNext(ifu_tag_wren_w_debug, 0.U)
}
val ic_valid_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, io.ic_debug_wr_data(0), ic_valid)
val ic_valid_ff = withClock(io.free_clk) {
RegNext(ic_valid_w_debug, false.B)
}
val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j =>
if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags
else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) |
((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) |
reset_all_tags).reverse.reduce(Cat(_, _)))
val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode)))
val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool())))
// io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)),
// (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_)))
for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32)
ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B,
((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)}
val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j =>
Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
// Making a sudo LRU
// val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, Bool()))
val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
if (ICACHE_NUM_WAYS == 4) {
replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
(!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
(!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
(!tagv_mb_ff(1) & tagv_mb_ff(0))
replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0)
way_status_hit_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status(2), 3.U),
io.ic_rd_hit(1) -> Cat(way_status(2), 1.U(2.W)),
io.ic_rd_hit(2) -> Cat(1.U, way_status(1), 0.U),
io.ic_rd_hit(3) -> Cat(0.U, way_status(1), 0.U)))
way_status_rep_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U),
io.ic_rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)),
io.ic_rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U),
io.ic_rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U)))
}
else {
replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0)
replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0)
way_status_hit_new := io.ic_rd_hit(0)
way_status_rep_new := replace_way_mb_any(0)
}
way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new)
way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f
val bus_wren = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending)
val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat)
val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss)
ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _))
bus_ic_wr_en := bus_wren.reverse.reduce(Cat(_,_))
if(!ICACHE_ENABLE){
for(i<- 0 until ICACHE_NUM_WAYS){
bus_wren(i) := 0.U
}
ic_tag_valid_unq := 0.U
way_status := 0.U
replace_way_mb_any := 0.U
way_status_hit_new := 0.U
way_status_rep_new := 0.U
way_status_new := 0.U
way_status_wr_en := 0.U
}
io.ic_tag_valid := ic_tag_valid_unq & Fill(ICACHE_NUM_WAYS, !fetch_uncacheable_ff & ifc_fetch_req_f)
val ic_debug_way_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
ic_debug_tag_val_rd_out := (ic_tag_valid_unq & (ic_debug_way_ff & Fill(ICACHE_NUM_WAYS, ic_debug_rd_en_ff))).orR()
io.ifu_pmu_ic_miss := withClock(io.active_clk){RegNext(ic_act_miss_f, false.B)}
io.ifu_pmu_ic_hit := withClock(io.active_clk){RegNext(ic_act_hit_f, false.B)}
io.ifu_pmu_bus_error := withClock(io.active_clk){RegNext(ifc_bus_acc_fault_f, false.B)}
io.ifu_pmu_bus_busy := withClock(io.active_clk){RegNext(ifu_bus_arvalid_ff & !ifu_bus_arready_ff & miss_pending, false.B)}
io.ifu_pmu_bus_trxn := withClock(io.active_clk){RegNext(bus_cmd_sent, false.B)}
io.ic_debug_addr := io.dec_tlu_ic_diag_pkt.icache_dicawics
io.ic_debug_tag_array := io.dec_tlu_ic_diag_pkt.icache_dicawics(16)
io.ic_debug_rd_en := io.dec_tlu_ic_diag_pkt.icache_rd_valid
io.ic_debug_wr_en := io.dec_tlu_ic_diag_pkt.icache_wr_valid
io.ic_debug_way := Cat(io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===3.U, io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===2.U,
io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===1.U, io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===0.U)
ic_debug_tag_wr_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way
val ic_debug_ict_array_sel_in = io.ic_debug_rd_en & io.ic_debug_tag_array
ic_debug_way_ff := withClock(debug_c1_clk){RegNext(io.ic_debug_way, 0.U)}
ic_debug_ict_array_sel_ff := withClock(debug_c1_clk){RegNext(ic_debug_ict_array_sel_in, 0.U)}
ic_debug_rd_en_ff := withClock(io.free_clk){RegNext(io.ic_debug_rd_en, false.B)}
io.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegEnable(ic_debug_rd_en_ff, 0.U, ic_debug_rd_en_ff.asBool)}
val ifc_region_acc_okay = Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR() |
INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (INST_ACCESS_ADDR0.U | aslong(INST_ACCESS_MASK0).U)) |
INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (INST_ACCESS_ADDR1.U | aslong(INST_ACCESS_MASK1).U)) |
INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (INST_ACCESS_ADDR2.U | aslong(INST_ACCESS_MASK2).U)) |
INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (INST_ACCESS_ADDR3.U | aslong(INST_ACCESS_MASK3).U)) |
INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (INST_ACCESS_ADDR4.U | aslong(INST_ACCESS_MASK4).U)) |
INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (INST_ACCESS_ADDR5.U | aslong(INST_ACCESS_MASK5).U)) |
INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (INST_ACCESS_ADDR6.U | aslong(INST_ACCESS_MASK6).U)) |
INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (INST_ACCESS_ADDR7.U | aslong(INST_ACCESS_MASK7).U))
val ifc_region_acc_fault_memory_bf = !io.ifc_iccm_access_bf & !ifc_region_acc_okay & io.ifc_fetch_req_bf
ifc_region_acc_fault_final_bf := io.ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf
ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)}
}
object ifu_mem extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_mem_ctl()))
}

131
src/main/scala/include/el2_bundle.scala
View File

@ -1,4 +1,5 @@
package include
import chisel3._
// use this for instance declaration val io = IO(Output(new el2_trace_pkt_t))
@ -14,6 +15,7 @@ class el2_trace_pkt_t extends Bundle{
object el2_inst_pkt_t extends Enumeration{
val NULL = "b0000".U(4.W)
val MUL = "b0001".U(4.W)
@ -32,8 +34,27 @@ object el2_inst_pkt_t extends Enumeration{
val JAL = "b1110".U(4.W)
val BITMANIPU = "b1111".U(4.W)
}
/*
class el2_inst_pkt_t extends Bundle{
val NULL = "b0000".U(4.W)
val MUL = "b0001".U(4.W)
val LOAD = "b0010".U(4.W)
val STORE = "b0011".U(4.W)
val ALU = "b0100".U(4.W)
val CSRREAD = "b0101".U(4.W)
val CSRWRITE = "b0110".U(4.W)
val CSRRW = "b0111".U(4.W)
val EBREAK = "b1000".U(4.W)
val ECALL = "b1001".U(4.W)
val FENCE = "b1010".U(4.W)
val FENCEI = "b1011".U(4.W)
val MRET = "b1100".U(4.W)
val CONDBR = "b1101".U(4.W)
val JAL = "b1110".U(4.W)
val BITMANIPU = "b1111".U(4.W)
}
*/
class el2_load_cam_pkt_t extends Bundle {
val valid = UInt(1.W)
val wb = UInt(1.W)
@ -54,7 +75,7 @@ class el2_br_pkt_t extends Bundle {
val br_error = UInt(1.W)
val br_start_error = UInt(1.W)
val bank = UInt(1.W)
val prett = UInt(32.W) // predicted ret target //[31:1] in swerv
val prett = UInt(31.W) // predicted ret target
val way = UInt(1.W)
val ret = UInt(1.W)
}
@ -79,7 +100,7 @@ class el2_predict_pkt_t extends Bundle {
val valid = UInt(1.W)
val br_error = UInt(1.W)
val br_start_error = UInt(1.W)
val prett = UInt(32.W) //[31:1] in swerv
val prett = UInt(31.W)
val pcall = UInt(1.W)
val pret = UInt(1.W)
val pja = UInt(1.W)
@ -94,7 +115,7 @@ class el2_trap_pkt_t extends Bundle {
val icaf_type = UInt(2.W)
val fence_i = UInt(1.W)
val i0trigger = UInt(4.W)
val pmu_i0_itype = el2_inst_pkt_t //pmu-instructiontype
val pmu_i0_itype =UInt(4.W) //new el2_inst_pkt_t //pmu-instructiontype
val pmu_i0_br_unpred = UInt(1.W) //pmu
val pmu_divide = UInt(1.W)
val pmu_lsu_misaligned = UInt(1.W)
@ -148,19 +169,19 @@ class el2_alu_pkt_t extends Bundle {
}
class el2_lsu_pkt_t extends Bundle {
val fast_int = UInt(1.W)
val by = UInt(1.W)
val half = UInt(1.W)
val word = UInt(1.W)
val dword = UInt(1.W) // for dma
val load = UInt(1.W)
val store = UInt(1.W)
val unsign = UInt(1.W)
val dma = UInt(1.W) // dma pkt
val store_data_bypass_d = UInt(1.W)
val load_ldst_bypass_d = UInt(1.W)
val store_data_bypass_m = UInt(1.W)
val valid = UInt(1.W)
val fast_int = Bool()
val by = Bool()
val half = Bool()
val word = Bool()
val dword = Bool() // for dma
val load = Bool()
val store = Bool()
val unsign = Bool()
val dma = Bool() // dma pkt
val store_data_bypass_d = Bool()
val load_ldst_bypass_d = Bool()
val store_data_bypass_m = Bool()
val valid = Bool()
}
class el2_lsu_error_pkt_t extends Bundle {
@ -168,8 +189,8 @@ class el2_lsu_error_pkt_t extends Bundle {
val single_ecc_error = UInt(1.W)
val inst_type = UInt(1.W) //0: Load, 1: Store
val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault
val mscause = UInt(4.W)
val addr = UInt(32.W)
val mscause = UInt(1.W)
val addr = UInt(1.W)
}
class el2_dec_pkt_t extends Bundle {
@ -225,7 +246,6 @@ class el2_dec_pkt_t extends Bundle {
val legal = Bool()
}
class el2_mul_pkt_t extends Bundle {
val valid = UInt(1.W)
val rs1_sign = UInt(1.W)
@ -321,3 +341,74 @@ class el2_cache_debug_pkt_t extends Bundle {
val icache_wr_valid = UInt(1.W)
}
class el2_dec_tlu_csr_pkt extends Bundle{
val csr_misa =UInt(1.W)
val csr_mvendorid =UInt(1.W)
val csr_marchid =UInt(1.W)
val csr_mimpid =UInt(1.W)
val csr_mhartid =UInt(1.W)
val csr_mstatus =UInt(1.W)
val csr_mtvec =UInt(1.W)
val csr_mip =UInt(1.W)
val csr_mie =UInt(1.W)
val csr_mcyclel =UInt(1.W)
val csr_mcycleh =UInt(1.W)
val csr_minstretl =UInt(1.W)
val csr_minstreth =UInt(1.W)
val csr_mscratch =UInt(1.W)
val csr_mepc =UInt(1.W)
val csr_mcause =UInt(1.W)
val csr_mscause =UInt(1.W)
val csr_mtval =UInt(1.W)
val csr_mrac =UInt(1.W)
val csr_dmst =UInt(1.W)
val csr_mdseac =UInt(1.W)
val csr_meihap =UInt(1.W)
val csr_meivt =UInt(1.W)
val csr_meipt =UInt(1.W)
val csr_meicurpl =UInt(1.W)
val csr_meicidpl =UInt(1.W)
val csr_dcsr =UInt(1.W)
val csr_mcgc =UInt(1.W)
val csr_mfdc =UInt(1.W)
val csr_dpc =UInt(1.W)
val csr_mtsel =UInt(1.W)
val csr_mtdata1 =UInt(1.W)
val csr_mtdata2 =UInt(1.W)
val csr_mhpmc3 =UInt(1.W)
val csr_mhpmc4 =UInt(1.W)
val csr_mhpmc5 =UInt(1.W)
val csr_mhpmc6 =UInt(1.W)
val csr_mhpmc3h =UInt(1.W)
val csr_mhpmc4h =UInt(1.W)
val csr_mhpmc5h =UInt(1.W)
val csr_mhpmc6h =UInt(1.W)
val csr_mhpme3 =UInt(1.W)
val csr_mhpme4 =UInt(1.W)
val csr_mhpme5 =UInt(1.W)
val csr_mhpme6 =UInt(1.W)
val csr_mcountinhibit =UInt(1.W)
val csr_mitctl0 =UInt(1.W)
val csr_mitctl1 =UInt(1.W)
val csr_mitb0 =UInt(1.W)
val csr_mitb1 =UInt(1.W)
val csr_mitcnt0 =UInt(1.W)
val csr_mitcnt1 =UInt(1.W)
val csr_mpmc =UInt(1.W)
val csr_mcpc =UInt(1.W)
val csr_meicpct =UInt(1.W)
val csr_mdeau =UInt(1.W)
val csr_micect =UInt(1.W)
val csr_miccmect =UInt(1.W)
val csr_mdccmect =UInt(1.W)
val csr_mfdht =UInt(1.W)
val csr_mfdhs =UInt(1.W)
val csr_dicawics =UInt(1.W)
val csr_dicad0h =UInt(1.W)
val csr_dicad0 =UInt(1.W)
val csr_dicad1 =UInt(1.W)
val csr_dicago =UInt(1.W)
val presync =UInt(1.W)
val postsync =UInt(1.W)
val legal =UInt(1.W)
}

232
src/main/scala/lib/RVC.scala Normal file
View File

@ -0,0 +1,232 @@
// See LICENSE.SiFive for license details.
//package freechips.rocketchip.rocket
package lib
import chisel3._
import chisel3.util._
import chisel3.util.ImplicitConversions
import chisel3.experimental._
import Chisel.ImplicitConversions._
//import freechips.rocketchip.config.Parameters
//import freechips.rocketchip.tile._
//import freechips.rocketchip.util._
class ExpandedInstruction extends Bundle {
val bits = UInt(32.W)
val rd = UInt(5.W)
val rs1 = UInt(5.W)
val rs2 = UInt(5.W)
val rs3 = UInt(5.W)
}
class RVCDecoder(x: UInt, xLen: Int) {
def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = {
val res = Wire(new ExpandedInstruction)
res.bits := bits
res.rd := rd
res.rs1 := rs1
res.rs2 := rs2
res.rs3 := rs3
res
}
def rs1p = Cat(1.U(2.W), x(9,7))
def rs2p = Cat(1.U(2.W), x(4,2))
def rs2 = x(6,2)
def rd = x(11,7)
def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W))
def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W))
def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W))
def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W))
def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W))
def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W))
def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W))
def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W))
def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W))
def addiImm = Cat(Fill(7, x(12)), x(6,2))
def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W))
def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W))
def shamt = Cat(x(12), x(6,2))
def x0 = 0.U(5.W)
def ra = 1.U(5.W)
def sp = 2.U(5.W)
def q0 = {
def addi4spn = {
val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
}
def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
def flw = {
if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
else ld
}
def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
def fsw = {
if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
else sd
}
Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw)
}
def q1 = {
def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p)
def addiw = {
val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W))
inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
}
def jal = {
if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p)
else addiw
}
def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p)
def addi16sp = {
val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W))
inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
}
def lui = {
val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W))
val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p)
Mux(rd === x0 || rd === sp, addi16sp, me)
}
def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p)
def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0)
def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0)
def arith = {
def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W))
def srai = srli | (1 << 30).U
def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W))
def rtype = {
val funct = VecInit(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5)))
val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U)
val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W))
Cat(rs2p, rs1p, funct, rs1p, opc) | sub
}
inst(VecInit(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p)
}
Seq(addi, jal, li, lui, arith, j, beqz, bnez)
}
def q2 = {
val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W))
def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2)
def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2)
def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2)
def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
def flwsp = {
if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
else ldsp
}
def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
def fswsp = {
if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
else sdsp
}
def jalr = {
val mv = inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2)
val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2)
val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W))
val reserved = Cat(jr >> 7, 0x1F.U(7.W))
val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2)
val jr_mv = Mux(rs2.orR, mv, jr_reserved)
val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W))
val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U
val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2)
val jalr_add = Mux(rs2.orR, add, jalr_ebreak)
Mux(x(12), jalr_add, jr_mv)
}
Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp)
}
def q3 = Seq.fill(8)(passthrough)
def passthrough = inst(x)
def decode = {
val s = VecInit(q0 ++ q1 ++ q2 ++ q3)
s(Cat(x(1,0), x(15,13)))
}
def changed_q0 = {
def addi4spn = {
val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
}
def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
def flw = {
if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
else ld
}
def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
def fsw = {
if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
else sd
}
addi4spn
}
def ret_q0 = VecInit(q0)
def ret_q1 = q1
def ret_q2 = q2
def ret_q3 = q3
}
class RVCExpander( val XLen: Int, val usingCompressed: Boolean) extends Module {
val io = IO(new Bundle {
val in = Input(UInt(32.W))
val out = Output(new ExpandedInstruction)
val rvc = Output(Bool())
val legal = Output(Bool())
val waleed_out = Output(UInt(32.W))
//val q1_Out = Output(new ExpandedInstruction)
//val q2_Out = Output(new ExpandedInstruction)
//val q3_Out = Output(new ExpandedInstruction)
})
if (usingCompressed) {
io.rvc := io.in(1,0) =/= 3.U
val inst = new RVCDecoder(io.in, XLen)
io.out := inst.decode
io.legal := (!io.in(13))&(!io.in(12))&(io.in(11))&io.in(1)&(!io.in(0)) |
(!io.in(13))&(!io.in(12))&(io.in(6))&io.in(1)&(!io.in(0)) |
(!io.in(15))&(!io.in(13))&io.in(11)(!io.in(1)) |
(!io.in(13))&(!io.in(12))&io.in(5)&io.in(1)&(!io.in(0)) |
(!io.in(13))&(!io.in(12))&io.in(10)&(!io.in(1))&io.in(0) |
(!io.in(15))&(!io.in(13))&io.in(6)&(!io.in(1)) | io.in(15)&(!io.in(12))&(!io.in(1))&io.in(0) |
(!io.in(13))&(!io.in(12))&io.in(9)&io.in(1)&(!io.in(0)) |
(!io.in(12))&io.in(6)&(!io.in(1))&io.in(0) |
(!io.in(15))&(!io.in(13))&io.in(5)&(!io.in(1)) |
(!io.in(13))&(!io.in(12))&io.in(8)&io.in(1)&(!io.in(0)) |
(!io.in(12))&io.in(5)&(!io.in(1))&io.in(0) |
(!io.in(15))&(!io.in(13))&io.in(10)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(7)&io.in(1)&(!io.in(0)) |
io.in(12)&io.in(11)&(!io.in(10))&(!io.in(1))&io.in(0) | (!io.in(15))&(!io.in(13))&io.in(9)&(!io.in(1)) |
(!io.in(13))&(!io.in(12))&io.in(4)&io.in(1)&(!io.in(0)) | io.in(13)&io.in(12)&(!io.in(1))&io.in(0) |
(!io.in(15))&(!io.in(13))&io.in(8)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(3)&io.in(1)&(!io.in(0)) |
io.in(13)&io.in(4)&(!io.in(1))&io.in(0) | (!io.in(13))&(!io.in(12))&io.in(2)&io.in(1)&(!io.in(0)) |
(!io.in(15))&(!io.in(13))&io.in(7)&(!io.in(1)) | io.in(13)&io.in(3)&(!io.in(1))&io.in(0) |
io.in(13)&io.in(2)&(!io.in(1))&io.in(0) | io.in(14)&(!io.in(13))&(!io.in(1)) |
(!io.in(14))&(!io.in(12))&(!io.in(1))&io.in(0) | io.in(15)&(!io.in(13))&io.in(12)&io.in(1)&(!io.in(0)) |
(!io.in(15))&(!io.in(13))&(!io.in(12))&io.in(1)&(!io.in(0)) | (!io.in(15))&(!io.in(13))&io.in(12)&(!io.in(1)) |
io.in(14)&(!io.in(13))&(!io.in(0))
io.waleed_out := Mux(io.legal,io.out.bits,0.U)
} else {
io.rvc := false.B
io.out := new RVCDecoder(io.in, XLen).passthrough
}
}

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package lib
import chisel3._
import chisel3.util._
import chisel3.experimental.chiselName
@chiselName
class ahb_to_axi4 extends Module with el2_lib with RequireAsyncReset {
val TAG = 1
val io = IO(new Bundle {
val scan_mode = Input(Bool())
val bus_clk_en = Input(Bool())
val clk_override = Input(Bool())
val axi_awready = Input(Bool())
val axi_wready = Input(Bool())
val axi_bvalid = Input(Bool())
val axi_bresp = Input(UInt(2.W))
val axi_bid = Input(UInt(TAG.W))
val axi_arready = Input(Bool())
val axi_rvalid = Input(Bool())
val axi_rid = Input(UInt(TAG.W))
val axi_rdata = Input(UInt(64.W))
val axi_rresp = Input(UInt(2.W))
val ahb_haddr = Input(UInt(32.W)) // ahb bus address
val ahb_hburst = Input(UInt(3.W)) // tied to 0
val ahb_hmastlock = Input(Bool()) // tied to 0
val ahb_hprot = Input(UInt(4.W)) // tied to 4'b0011
val ahb_hsize = Input(UInt(3.W)) // size of bus transaction (possible values 0 =1 =2 =3)
val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now)
val ahb_hwrite = Input(Bool()) // ahb bus write
val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data
val ahb_hsel = Input(Bool()) // this slave was selected
val ahb_hreadyin = Input(Bool()) // previous hready was accepted or not
// outputs
val axi_awvalid = Output(Bool())
val axi_awid = Output(UInt(TAG.W))
val axi_awaddr = Output(UInt(32.W))
val axi_awsize = Output(UInt(3.W))
val axi_awprot = Output(UInt(3.W))
val axi_awlen = Output(UInt(8.W))
val axi_awburst = Output(UInt(2.W))
val axi_wvalid = Output(Bool())
val axi_wdata = Output(UInt(64.W))
val axi_wstrb = Output(UInt(8.W))
val axi_wlast = Output(Bool())
val axi_bready = Output(Bool())
val axi_arvalid = Output(Bool())
val axi_arid = Output(UInt(TAG.W))
val axi_araddr = Output(UInt(32.W))
val axi_arsize = Output(UInt(3.W))
val axi_arprot = Output(UInt(3.W))
val axi_arlen = Output(UInt(8.W))
val axi_arburst = Output(UInt(2.W))
val axi_rready = Output(Bool())
val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data
val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction
val ahb_hresp = Output(Bool()) // slave response (high indicates erro)
})
io.axi_awvalid := 0.U
io.axi_awid := 0.U
io.axi_awaddr := 0.U
io.axi_awsize := 0.U
io.axi_awprot := 0.U
io.axi_awlen := 0.U
io.axi_awburst := 0.U
io.axi_wvalid := 0.U
io.axi_wdata := 0.U
io.axi_wstrb := 0.U
io.axi_wlast := 0.U
io.axi_bready := 0.U
io.axi_arvalid := 0.U
io.axi_arid := 0.U
io.axi_araddr := 0.U
io.axi_arsize := 0.U
io.axi_arprot := 0.U
io.axi_arlen := 0.U
io.axi_arburst := 0.U
io.axi_rready := 0.U
io.ahb_hrdata := 0.U
io.ahb_hreadyout := 0.U
io.ahb_hresp := 0.U
}
object AHB_main extends App {
println("Generate Verilog")
println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4()))
}

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package lib
import chisel3._
import chisel3.util._
trait Config {
val TAG = 1
}
class axi4_to_ahb_IO extends Bundle with Config {
val scan_mode = Input(Bool())
val bus_clk_en = Input(Bool())
val clk_override = Input(Bool())
val axi_awvalid = Input(Bool())
val axi_awid = Input(UInt(TAG.W)) // [TAG-1:0]
val axi_awaddr = Input(UInt(32.W)) // [31:0]
val axi_awsize = Input(UInt(3.W)) // [2:0]
val axi_awprot = Input(UInt(3.W)) // [2:0]
val axi_wvalid = Input(Bool())
val axi_wdata = Input(UInt(64.W)) // [63:0]
val axi_wstrb = Input(UInt(8.W)) // [7:0]
val axi_wlast = Input(Bool())
val axi_bready = Input(Bool())
val axi_arvalid = Input(Bool())
val axi_arid = Input(UInt(TAG.W)) // [TAG-1:0]
val axi_araddr = Input(UInt(32.W)) // [31:0]
val axi_arsize = Input(UInt(3.W)) // [2:0]
val axi_arprot = Input(UInt(3.W)) // [2:0]
val axi_rready = Input(Bool())
val ahb_hrdata = Input(UInt(64.W)) // [63:0] // ahb bus read data
val ahb_hready = Input(Bool()) // slave ready to accept transaction
val ahb_hresp = Input(Bool()) // slave response (high indicates erro)
//----------------------------outputs---------------------------
val axi_awready = Output(Bool())
val axi_wready = Output(Bool())
val axi_bvalid = Output(Bool())
val axi_bresp = Output(UInt(2.W)) // [1:0]]
val axi_bid = Output(UInt(TAG.W)) // [TAG-1:0]
// AXI Read Channels
val axi_arready = Output(Bool())
val axi_rvalid = Output(Bool())
val axi_rid = Output(UInt(TAG.W)) // [TAG-1:0]
val axi_rdata = Output(UInt(32.W)) // [63:0]
val axi_rresp = Output(UInt(2.W)) // 1:0]
val axi_rlast = Output(Bool())
// AHB-Lite signals
val ahb_haddr = Output(UInt(32.W)) // [31:0] // ahb bus address
val ahb_hburst = Output(UInt(3.W)) // [2:0] // tied to 0
val ahb_hmastlock = Output(Bool()) // tied to 0
val ahb_hprot = Output(UInt(4.W)) // [3:0] // tied to 4'b0011
val ahb_hsize = Output(UInt(3.W)) // [2:0] // size of bus transaction (possible values 0,1,2,3)
val ahb_htrans = Output(UInt(2.W))
val ahb_hwrite = Output(Bool()) // ahb bus write
val ahb_hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data
}
class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config {
val io = IO(new axi4_to_ahb_IO)
val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: nil = Enum(8)
val state = RegInit(idle) // typedef enum
val buf_state = RegInit(idle)
val buf_nxtstate = RegInit(idle)
//logic signals
val slave_valid = WireInit(Bool(), init = false.B)
val slave_ready = WireInit(Bool(), init = false.B)
val slave_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
val slave_rdata = WireInit(0.U(64.W)) // [63:0]
val slave_opc = WireInit(0.U(4.W)) // [3:0]
val wrbuf_en = WireInit(Bool(), init = false.B)
val wrbuf_data_en = WireInit(Bool(), init = false.B)
val wrbuf_cmd_sent = WireInit(Bool(), init = false.B)
val wrbuf_rst = WireInit(Bool(), init = false.B)
val wrbuf_vld = WireInit(Bool(), init = false.B)
val wrbuf_data_vld = WireInit(Bool(), init = false.B)
val wrbuf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
val wrbuf_size = WireInit(0.U(3.W)) // [2:0]
val wrbuf_addr = WireInit(0.U(32.W)) // [31:0]
val wrbuf_data = WireInit(0.U(64.W)) // [63:0]
val wrbuf_byteen = WireInit(0.U(8.W)) // [7:0]
val bus_write_clk_en = WireInit(Bool(), init = false.B)
val bus_clk = Wire(Clock())
val bus_write_clk = Wire(Clock())
val master_valid = WireInit(Bool(), init = false.B)
val master_ready = WireInit(0.U(1.W))
val master_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
val master_addr = WireInit(0.U(32.W)) // [31:0]
val master_wdata = WireInit(0.U(64.W)) // [63:0]
val master_size = WireInit(0.U(3.W)) // [2:0]
val master_opc = WireInit(0.U(3.W)) // [2:0]
val master_byteen = WireInit(0.U(8.W)) // [7:0]
// Buffer signals (one entry buffer)
val buf_addr = WireInit(0.U(32.W)) // [31:0]
val buf_size = WireInit(0.U(2.W)) // [1:0]
val buf_write = WireInit(Bool(), init = false.B)
val buf_byteen = WireInit(0.U(8.W)) // [7:0]
val buf_aligned = WireInit(Bool(), init = false.B)
val buf_data = WireInit(0.U(64.W)) // [63:0]
val buf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
//Miscellaneous signals
val buf_rst = WireInit(Bool(), init = false.B)
val buf_tag_in = WireInit(0.U(TAG.W)) // [TAG-1:0]
val buf_addr_in = WireInit(0.U(32.W)) // [31:0]
val buf_byteen_in = WireInit(0.U(8.W)) // [7:0]
val buf_data_in = WireInit(0.U(64.W)) // [63:0]
val buf_write_in = WireInit(Bool(), init = false.B)
val buf_aligned_in = WireInit(Bool(), init = false.B)
val buf_size_in = WireInit(0.U(3.W)) // [2:0]
val buf_state_en = WireInit(Bool(), init = false.B)
val buf_wr_en = WireInit(Bool(), init = false.B)
val buf_data_wr_en = WireInit(Bool(), init = false.B)
val slvbuf_error_en = WireInit(Bool(), init = false.B)
val wr_cmd_vld = WireInit(Bool(), init = false.B)
val cmd_done_rst = WireInit(Bool(), init = false.B)
val cmd_done = WireInit(Bool(), init = false.B)
val cmd_doneQ = WireInit(Bool(), init = false.B)
val trxn_done = WireInit(Bool(), init = false.B)
val buf_cmd_byte_ptr = WireInit(0.U(3.W)) // [2:0]
val buf_cmd_byte_ptrQ = WireInit(0.U(3.W)) // [2:0]
val buf_cmd_nxtbyte_ptr = WireInit(0.U(3.W)) // [2:0]
val buf_cmd_byte_ptr_en = WireInit(Bool(), init = false.B)
val found = WireInit(Bool(), init = false.B)
val slave_valid_pre = WireInit(Bool(), init = false.B)
val ahb_hready_q = WireInit(Bool(), init = false.B)
val ahb_hresp_q = WireInit(Bool(), init = false.B)
val ahb_htrans_q = WireInit(0.U(2.W)) // [1:0]
val ahb_hwrite_q = WireInit(Bool(), init = false.B)
val ahb_hrdata_q = WireInit(0.U(64.W)) // [63:0]
val slvbuf_write = WireInit(Bool(), init = false.B)
val slvbuf_error = WireInit(Bool(), init = false.B)
val slvbuf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
val slvbuf_error_in = WireInit(Bool(), init = false.B)
val slvbuf_wr_en = WireInit(Bool(), init = false.B)
val bypass_en = WireInit(Bool(), init = false.B)
val rd_bypass_idle = WireInit(Bool(), init = false.B)
val last_addr_en = WireInit(Bool(), init = false.B)
val last_bus_addr = WireInit(0.U(32.W)) // [31:0]
// Clocks
val buf_clken = WireInit(Bool(), init = false.B)
val slvbuf_clken = WireInit(Bool(), init = false.B)
val ahbm_addr_clken = WireInit(Bool(), init = false.B)
val ahbm_data_clken = WireInit(Bool(), init = false.B)
val buf_clk = Wire(Clock())
//val slvbuf_clk = Wire(Clock())
val ahbm_clk = Wire(Clock())
val ahbm_addr_clk = Wire(Clock())
val ahbm_data_clk = Wire(Clock())
def get_write_size(byteen: UInt) = {
val byteen = WireInit(0.U(8.W))
val size = ("b11".U & (Fill(2, (byteen(7, 0) === "hff".U))) |
("b10".U & (Fill(2, (byteen(7, 0) === "hf0".U) | (byteen(7, 0) === "h0f".U)))) |
("b01".U & (Fill(2, (byteen(7, 0) === "hc0".U) | (byteen(7, 0) === "h30".U) | (byteen(7, 0) === "h0c".U) | (byteen(7, 0) === "h03".U)))))
size
}
def get_write_addr(byteen_e: UInt) = {
val byteen_e = WireInit(0.U(8.W))
val addr = ("h0".U & (Fill(3, (byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U) | (byteen_e(7, 0) === "h03".U))) |
("h2".U & (Fill(3, (byteen_e(7, 0) === "h0c".U)))) |
("h4".U & (Fill(3, ((byteen_e(7, 0) === "hf0".U) | (byteen_e(7, 0) === "h03".U)))) |
("h6".U & (Fill(3, (byteen_e(7, 0) === "hc0".U))))))
addr
}
def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = {
val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr)
val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U)
MuxCase(0.U, temp)
}
// Write buffer
wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready
wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready
wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U)
wrbuf_rst := wrbuf_cmd_sent & !wrbuf_en
io.axi_awready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready
io.axi_wready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready
io.axi_arready := !(wrbuf_vld & wrbuf_data_vld) & master_ready
io.axi_rlast := true.B
wr_cmd_vld := wrbuf_vld & wrbuf_data_vld
master_valid := wr_cmd_vld | io.axi_arvalid
master_tag := Mux(wr_cmd_vld.asBool(), wrbuf_tag(TAG - 1, 0), io.axi_arid(TAG - 1, 0))
master_opc := Mux(wr_cmd_vld.asBool(), "b011".U, "b0".U)
master_addr := Mux(wr_cmd_vld.asBool(), wrbuf_addr(31, 0), io.axi_araddr(31, 0))
master_size := Mux(wr_cmd_vld.asBool(), wrbuf_size(2, 0), io.axi_arsize(2, 0))
master_byteen := wrbuf_byteen(7, 0)
master_wdata := wrbuf_data(63, 0)
// AXI response channel signals
io.axi_bvalid := slave_valid & slave_ready & slave_opc(3)
io.axi_bresp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U))
io.axi_bid := slave_tag(TAG - 1, 0)
io.axi_rvalid := slave_valid & slave_ready & (slave_opc(3, 2) === "b0".U)
io.axi_rresp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U))
io.axi_rid := slave_tag(TAG - 1, 0)
io.axi_rdata := slave_rdata(63, 0)
slave_ready := io.axi_bready & io.axi_rready
// Clock header logic
bus_write_clk_en := io.bus_clk_en & ((io.axi_awvalid & io.axi_awready) | (io.axi_wvalid & io.axi_wready))
bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
bus_write_clk := rvclkhdr(clock, bus_write_clk_en.asBool(), io.scan_mode)
//State machine
io.ahb_htrans := 0.U
master_ready := 0.U
buf_state_en := 0.U
switch(buf_state) {
is(idle) {
master_ready := 1.U
buf_write_in := (master_opc(2, 1) === "b01".U)
buf_nxtstate := Mux(buf_write_in.asBool(), cmd_wr, cmd_rd)
buf_state_en := master_valid & master_ready
buf_wr_en := buf_state_en
buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr)
buf_cmd_byte_ptr_en := buf_state_en
// ---------------------FROM FUNCTION CHECK LATER
buf_cmd_byte_ptr := Mux(buf_write_in.asBool(), (get_nxtbyte_ptr("b0".U, buf_byteen_in(7, 0), false.B)).asInstanceOf[UInt], master_addr(2, 0))
bypass_en := buf_state_en
rd_bypass_idle := bypass_en & (buf_nxtstate === cmd_rd)
io.ahb_htrans := (Fill(2, bypass_en)) & "b10".U
}
is(cmd_rd) {
buf_nxtstate := Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)
buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q
cmd_done := buf_state_en & !master_valid
slvbuf_wr_en := buf_state_en
master_ready := (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (buf_nxtstate === stream_rd) ////////////TBD////////
buf_wr_en := master_ready
bypass_en := master_ready & master_valid
buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
io.ahb_htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en)))
}
is(stream_rd) {
master_ready := (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U)
buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands
buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux(buf_wr_en.asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away.
buf_state_en := (ahb_hready_q | ahb_hresp_q)
buf_data_wr_en := buf_state_en
slvbuf_error_in := ahb_hresp_q
slvbuf_error_en := buf_state_en
slave_valid_pre := buf_state_en & !ahb_hresp_q // send a response right away if we are not going through an error response.
cmd_done := buf_state_en & !master_valid // last one of the stream should not send a htrans
bypass_en := master_ready & master_valid & (buf_nxtstate === stream_rd) & buf_state_en
buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
io.ahb_htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en)))
slvbuf_wr_en := buf_wr_en // shifting the contents from the buf to slv_buf for streaming cases
}
is(stream_err_rd) {
buf_nxtstate := data_rd
buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q
slave_valid_pre := buf_state_en
slvbuf_wr_en := buf_state_en // Overwrite slvbuf with buffer
buf_cmd_byte_ptr := buf_addr(2, 0)
io.ahb_htrans := "b10".U(2.W) & Fill(2, !buf_state_en)
}
is(data_rd) {
buf_nxtstate := done
buf_state_en := (ahb_hready_q | ahb_hresp_q)
buf_data_wr_en := buf_state_en
slvbuf_error_in := ahb_hresp_q
slvbuf_error_en := buf_state_en
slvbuf_wr_en := buf_state_en
}
is(cmd_wr) {
buf_nxtstate := data_wr
trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U)
buf_state_en := trxn_done
buf_cmd_byte_ptr_en := buf_state_en
slvbuf_wr_en := buf_state_en
buf_cmd_byte_ptr := Mux(trxn_done.asBool(), (get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)).asInstanceOf[UInt], buf_cmd_byte_ptrQ)
cmd_done := trxn_done & (buf_aligned | (buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen((get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B))) === "b0".U))
io.ahb_htrans := Fill(2, !(cmd_done | cmd_doneQ)) & "b10".U
}
is(data_wr) {
buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q
master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error
buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U), cmd_wr, cmd_rd), idle))
slvbuf_error_in := ahb_hresp_q
slvbuf_error_en := buf_state_en
buf_write_in := (master_opc(2, 1) === "b01".U)
buf_wr_en := buf_state_en & ((buf_nxtstate === cmd_wr) | (buf_nxtstate === cmd_rd))
buf_data_wr_en := buf_wr_en
cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & ((buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen((get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B))) === "b0".U))))
bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) // Only bypass for writes for the time being
io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & "b10".U
slave_valid_pre := buf_state_en & (buf_nxtstate =/= done)
trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U)
buf_cmd_byte_ptr_en := trxn_done | bypass_en
//val tmp_func = get_nxtbyte_ptr(Fill(3,0.U),buf_byteen_in(7,0),false.B)
//val tmp_func2 = get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B)
buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(Fill(3, 0.U), buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ))
}
is(done) {
buf_nxtstate := idle
buf_state_en := slave_ready
slvbuf_error_en := true.B
slave_valid_pre := true.B
}
}
buf_rst := false.B
cmd_done_rst := slave_valid_pre
buf_addr_in := Cat(master_addr, Mux((buf_aligned_in & (master_opc(2, 1) === "b01".U)).asBool(), get_write_addr(master_byteen(7, 0)), master_addr(2, 0)))
buf_tag_in := master_tag(TAG - 1, 0)
buf_byteen_in := wrbuf_byteen(7,0)
buf_data_in := Mux((buf_state === data_rd), ahb_hrdata_q(63, 0), master_wdata(63, 0))
buf_size_in := Mux((buf_aligned_in & (master_size(1, 0) === "b11".U) & (master_opc(2, 1) === "b01".U)).asBool(), get_write_size(master_byteen(7, 0)), master_size(1, 0))
buf_aligned_in := (master_opc(2, 0) === "b0".U) | // reads are always aligned since they are either DW or sideeffects
(master_size(1, 0) === "b0".U) | (master_size(1, 0) === "b01".U) | (master_size(1, 0) === "b10".U) | // Always aligned for Byte/HW/Word since they can be only for non-idempotent. IFU/SB are always aligned
((master_size(1, 0) === "b11".U) & ((master_byteen(7, 0) === "h3".U) | (master_byteen(7, 0) === "hc".U) | (master_byteen(7, 0) === "h30".U) | (master_byteen(7, 0) === "hc0".U) |
(master_byteen(7, 0) === "hf".U) | (master_byteen(7, 0) === "hf0".U) | (master_byteen(7, 0) === "hff".U)))
// Generate the ahb signals
io.ahb_haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0)))
io.ahb_hsize := Mux(bypass_en.asBool(), Cat("b0".U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), (Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0)))))
io.ahb_hburst := "b0".U
io.ahb_hmastlock := "b0".U
io.ahb_hprot := Cat("b001".U, ~io.axi_arprot(2))
io.ahb_hwrite := Mux(bypass_en.asBool(), (master_opc(2, 1) === "b01".U), buf_write)
io.ahb_hwdata := buf_data(63, 0)
slave_valid := slave_valid_pre
slave_opc := Cat(Mux(slvbuf_write.asBool(), "b11".U, "b00".U), Fill(2, slvbuf_error) & "b10".U)
slave_rdata := Mux(slvbuf_error.asBool(), Fill(2, last_bus_addr(31, 0)), Mux((buf_state === done), buf_data(63, 0), ahb_hrdata_q(63, 0)))
slave_tag := slvbuf_tag(TAG - 1, 0)
last_addr_en := (io.ahb_htrans(1, 0) =/= "b0".U) & io.ahb_hready & io.ahb_hwrite
//rvdffsc
wrbuf_vld := withClock(bus_clk) {RegEnable("b1".U & Fill("b1".U.getWidth, wrbuf_rst), 0.U, wrbuf_en.asBool())}
wrbuf_data_vld := withClock(bus_clk) {RegEnable("b1".U & Fill("b1".U.getWidth, wrbuf_rst), 0.U, wrbuf_data_en.asBool())}
//rvdffs
wrbuf_tag := withClock(bus_clk) {RegEnable(io.axi_awid(TAG - 1, 0), 0.U, wrbuf_en.asBool())}
wrbuf_size := withClock(bus_clk) {RegEnable(io.axi_awsize(2, 0), 0.U, wrbuf_en.asBool())}
//rvdffe
wrbuf_addr := RegEnable(io.axi_awaddr, 0.U, wrbuf_en.asBool())
wrbuf_data := RegEnable(io.axi_wdata, 0.U, wrbuf_data_en.asBool())
//rvdffs
wrbuf_byteen := withClock(bus_clk) {
RegEnable(io.axi_wstrb(7, 0), 0.U, wrbuf_data_en.asBool())
}
last_bus_addr := withClock(ahbm_clk) {
RegEnable(io.ahb_haddr(31, 0), 0.U, last_addr_en.asBool())
}
//sc
buf_state := withClock(ahbm_clk) {
RegEnable(buf_nxtstate & Fill(buf_nxtstate.getWidth, buf_rst), 0.U, buf_state_en.asBool())
}
//s
buf_write := withClock(buf_clk) {
RegEnable(buf_write_in, 0.U, buf_wr_en.asBool())
}
buf_tag := withClock(buf_clk) {
RegEnable(buf_tag_in(TAG - 1, 0), 0.U, buf_wr_en.asBool())
}
//e
buf_addr := RegEnable(buf_addr_in(31, 0), 0.U, (buf_wr_en & io.bus_clk_en).asBool)
//s
buf_size := withClock(buf_clk) {
RegEnable(buf_size(1, 0), 0.U, buf_wr_en.asBool())
}
buf_aligned := withClock(buf_clk) {
RegEnable(buf_aligned_in, 0.U, buf_wr_en.asBool())
}
buf_byteen := withClock(buf_clk) {
RegEnable(buf_byteen(7, 0), 0.U, buf_wr_en.asBool())
}
//e
buf_data := RegEnable(buf_data_in(63, 0), 0.U, (buf_data_wr_en & io.bus_clk_en).asBool())
//s
slvbuf_write := withClock(buf_clk) {
RegEnable(buf_write, 0.U, slvbuf_wr_en.asBool())
}
slvbuf_tag := withClock(buf_clk) {
RegEnable(buf_tag(TAG - 1, 0), 0.U, slvbuf_wr_en.asBool())
}
slvbuf_error := withClock(ahbm_clk) {
RegEnable(slvbuf_error_in, 0.U, slvbuf_error_en.asBool())
}
//sc
cmd_doneQ := withClock(ahbm_clk) {
RegEnable("b1".U & Fill("b1".U.getWidth, cmd_done_rst), 0.U, cmd_done.asBool())
}
//rvdffs
buf_cmd_byte_ptrQ := withClock(ahbm_clk) {
RegEnable(buf_cmd_byte_ptr(2, 0), 0.U, buf_cmd_byte_ptr_en.asBool())
}
//rvdff
ahb_hready_q := withClock(ahbm_clk) {
RegNext(io.ahb_hready, 0.U)
}
ahb_htrans_q := withClock(ahbm_clk) {
RegNext(io.ahb_htrans(1, 0), 0.U)
}
ahb_hwrite_q := withClock(ahbm_addr_clk) {
RegNext(io.ahb_hwrite, 0.U)
}
ahb_hresp_q := withClock(ahbm_clk) {
RegNext(io.ahb_hresp, 0.U)
}
ahb_hrdata_q := withClock(ahbm_data_clk) {
RegNext(io.ahb_hrdata(63, 0), 0.U)
}
buf_clken := io.bus_clk_en & (buf_wr_en | slvbuf_wr_en | io.clk_override)
ahbm_addr_clken := io.bus_clk_en & ((io.ahb_hready & io.ahb_htrans(1)) | io.clk_override)
ahbm_data_clken := io.bus_clk_en & ((buf_state =/= idle) | io.clk_override)
//Clkhdr
buf_clk := rvclkhdr(clock, buf_clken, io.scan_mode)
ahbm_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode)
ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode)
}
object AXImain extends App {
println("Generate Verilog")
println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb()))
}

217
src/main/scala/lib/beh_ib_func.scala
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@ -1,217 +0,0 @@
package lib
import chisel3._
import chisel3.util._
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
import chisel3.withClock
/*
object beh_ib_func extends RequireAsyncReset {
def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
def rvsyncss(din:UInt,clk:Clock) = withClock(clk){RegNext(RegNext(din,0.U),0.U)}
def rvlsadder(rs1:UInt,offset:UInt) = {
val w1 = Cat(0.U(1.W),rs1(11,0)) + Cat(0.U(1.W),offset(11,0)) //w1[12] =cout offset[11]=sign
val dout_upper = ((Fill(20, ~(offset(11) ^ w1(12)))) & rs1(31,12)) |
((Fill(20, ~offset(11) & w1(12))) & (rs1(31,12)+1.U)) |
((Fill(20, offset(11) & ~w1(12))) & (rs1(31,12)-1.U))
Cat(dout_upper,w1(11,0))
}
def rvbradder(pc:UInt,offset:UInt) = { // lsb is not using in code
val w1 = Cat(0.U(1.W),pc(11,0)) + Cat(0.U(1.W),offset(11,0)) //w1[12] =cout offset[12]=sign
val dout_upper = ((Fill(19, ~(offset(11) ^ w1(12))))& pc(30,12)) |
((Fill(19, ~offset(11) & w1(12))) & (pc(30,12)+1.U)) |
((Fill(19, offset(11) & ~w1(12))) & (pc(30,12)-1.U))
Cat(dout_upper,w1(11,0))}
def rvtwoscomp(din:UInt) = { //Done for verification and testing
val temp = Wire(Vec(din.getWidth-1,UInt(1.W)))
for(i <- 1 to din.getWidth-1){
temp(i-1) := Mux(din(i-1,0).orR ,~din(i),din(i))
}
Cat(temp.asUInt,din(0))
}
//WIDTH will be inferred
def rvmaskandmatch(mask:UInt,data:UInt,masken:UInt) = { //Done for verification and testing
val matchvec = Wire(Vec(data.getWidth,UInt(1.W)))
val masken_or_fullmask = masken.asBool & (~(mask(data.getWidth-1,0).andR))
matchvec(0) := masken_or_fullmask | (mask(0) === data(0)).asUInt
for(i <- 1 to data.getWidth-1)
{matchvec(i) := Mux(mask(i-1,0).andR & masken_or_fullmask,"b1".U,(mask(i) === data(i)).asUInt)}
matchvec.asUInt.andR
}
def rvrangecheck(addr:UInt,CCM_SADR:UInt, CCM_SIZE:Int=128) = {
val REGION_BITS = 4
val MASK_BITS = 10 + log2Ceil(CCM_SIZE)
val start_addr = CCM_SADR
val region = start_addr(31,(32-REGION_BITS))
val in_region = (addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt
val in_range = Wire(UInt(1.W))
if(CCM_SIZE == 48)
in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt)
else
in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt
(in_range,in_region)
}
def rvecc_encode(din:UInt):UInt = {
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1)
val w0 = Wire(Vec(18,UInt(1.W)))
val w1 = Wire(Vec(18,UInt(1.W)))
val w2 = Wire(Vec(18,UInt(1.W)))
val w3 = Wire(Vec(15,UInt(1.W)))
val w4 = Wire(Vec(15,UInt(1.W)))
val w5 = Wire(Vec(6, UInt(1.W)))
var j = 0;var k = 0;var m = 0;
var x = 0;var y = 0;var z = 0
for(i <- 0 to 31)
{
if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := din(i); m = m +1 }
if(mask3(i)==1) {w3(x) := din(i); x = x +1 }
if(mask4(i)==1) {w4(y) := din(i); y = y +1 }
if(mask5(i)==1) {w5(z) := din(i); z = z +1 }
}
val w6 = Cat((w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR))
val ecc_out = Cat(din.xorR ^ w6.xorR, w6)
ecc_out
}
def rveven_paritygen(data_in:UInt):UInt = data_in.xorR.asUInt
def rveven_paritycheck(data_in:UInt,parity_in:UInt) = (data_in.xorR.asUInt) ^ parity_in
def rvecc_decode(en:UInt,din:UInt,ecc_in:UInt,sed_ded:UInt)= {
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1)
val w0 = Wire(Vec(18,UInt(1.W)))
val w1 = Wire(Vec(18,UInt(1.W)))
val w2 = Wire(Vec(18,UInt(1.W)))
val w3 = Wire(Vec(15,UInt(1.W)))
val w4 = Wire(Vec(15,UInt(1.W)))
val w5 = Wire(Vec(6,UInt(1.W)))
var j = 0;var k = 0;var m = 0; var n =0;
var x = 0;var y = 0;
for(i <- 0 to 31)
{
if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := din(i); m = m +1 }
if(mask3(i)==1) {w3(n) := din(i); n = n +1 }
if(mask4(i)==1) {w4(x) := din(i); x = x +1 }
if(mask5(i)==1) {w5(y) := din(i); y = y +1 }
}
val ecc_check = Cat((din.xorR ^ ecc_in.xorR) & ~sed_ded ,ecc_in(5)^(w5.asUInt.xorR),ecc_in(4)^(w4.asUInt.xorR),ecc_in(3)^(w3.asUInt.xorR),ecc_in(2)^(w2.asUInt.xorR),ecc_in(1)^(w1.asUInt.xorR),ecc_in(0)^(w0.asUInt.xorR))
val single_ecc_error = en & (ecc_check=/= 0.U) & ecc_check(6)
val double_ecc_error = en & (ecc_check=/= 0.U) & ~ecc_check(6)
val error_mask = Wire(Vec(39,UInt(1.W)))
for(i <- 1 until 40){
error_mask(i-1) := ecc_check(5,0) === i.asUInt
}
val din_plus_parity = Cat(ecc_in(6), din(31,26), ecc_in(5), din(25,11), ecc_in(4), din(10,4), ecc_in(3), din(3,1), ecc_in(2), din(0), ecc_in(1,0))
val dout_plus_parity = Mux(single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity)
val dout = Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2))
val ecc_out = Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U(7.W)), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
(ecc_out,dout,single_ecc_error,double_ecc_error)
}
def rvecc_encode_64(din:UInt):UInt = {
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
val w0 = Wire(Vec(35,UInt(1.W)))
val w1 = Wire(Vec(35,UInt(1.W)))
val w2 = Wire(Vec(35,UInt(1.W)))
val w3 = Wire(Vec(31,UInt(1.W)))
val w4 = Wire(Vec(31,UInt(1.W)))
val w5 = Wire(Vec(31,UInt(1.W)))
val w6 = Wire(Vec(7, UInt(1.W)))
var j = 0;var k = 0;var m = 0; var n =0;
var x = 0;var y = 0;var z = 0
for(i <- 0 to 63)
{
if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := din(i); m = m +1 }
if(mask3(i)==1) {w3(n) := din(i); n = n +1 }
if(mask4(i)==1) {w4(x) := din(i); x = x +1 }
if(mask5(i)==1) {w5(y) := din(i); y = y +1 }
if(mask6(i)==1) {w6(z) := din(i); z = z +1 }
}
val ecc_out = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR))
ecc_out
}
def rvecc_decode_64(en:UInt,din:UInt,ecc_in:UInt) = {
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
val w0 = Wire(Vec(35,UInt(1.W)))
val w1 = Wire(Vec(35,UInt(1.W)))
val w2 = Wire(Vec(35,UInt(1.W)))
val w3 = Wire(Vec(31,UInt(1.W)))
val w4 = Wire(Vec(31,UInt(1.W)))
val w5 = Wire(Vec(31,UInt(1.W)))
val w6 = Wire(Vec(7, UInt(1.W)))
var j = 0;var k = 0;var m = 0; var n =0;
var x = 0;var y = 0;var z = 0
for(i <- 0 to 63)
{
if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := din(i); m = m +1 }
if(mask3(i)==1) {w3(n) := din(i); n = n +1 }
if(mask4(i)==1) {w4(x) := din(i); x = x +1 }
if(mask5(i)==1) {w5(y) := din(i); y = y +1 }
if(mask6(i)==1) {w6(z) := din(i); z = z +1 }
}
val ecc_check = Cat((ecc_in(6) ^ w6.asUInt.xorR) ,ecc_in(5)^(w5.asUInt.xorR),ecc_in(4)^(w4.asUInt.xorR),ecc_in(3)^(w3.asUInt.xorR),ecc_in(2)^(w2.asUInt.xorR),ecc_in(1)^(w1.asUInt.xorR),ecc_in(0)^(w0.asUInt.xorR))
val ecc_error = en & (ecc_check(6,0) =/= 0.U)
ecc_error
}
}
*/

241
src/main/scala/lib/beh_lib.scala
View File

@ -2,9 +2,7 @@ package lib
import chisel3._
import chisel3.util._
import include._
//import lib.beh_ib_func._
class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{
val io = IO(new Bundle{
@ -19,69 +17,95 @@ class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{
else
{io.dout := flop}
}
//println(getVerilog(new rvdff))
//rvdff => use regnext. with Asynchronous
class rvdffsc extends Module with el2_lib {
val io = IO(new Bundle{
val din = Input(UInt(32.W))
val en = Input(Bool())
val clear = Input(Bool())
val out = Output(UInt())
})
io.out := RegEnable(io.din & Fill(io.din.getWidth, ~io.clear), 0.U, io.en)
}
class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module{ //Done for verification and testing
class rvdffs extends Module with el2_lib {
val io = IO(new Bundle{
val din = Input(UInt(32.W))
val en = Input(Bool())
val clear = Input(Bool())
val out = Output(UInt())
})
io.out := RegEnable(io.din, 0.U, io.en)
}
class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module with RequireAsyncReset{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(WIDTH.W))
val dout = Output(UInt(WIDTH.W))
val clk = Input(Clock())
})
val sync_ff1 = withClock(io.clk){RegNext(io.din,0.U)} //RegNext(io.in,init)
val sync_ff2 = withClock(io.clk){RegNext(sync_ff1,0.U)}
val sync_ff1 = RegNext(io.din,0.U) //RegNext(io.in,init)
val sync_ff2 = RegNext(sync_ff1,0.U)
if(SHORT == 1)
{io.dout := io.din }
{ io.dout := io.din }
else
{io.dout := sync_ff2 }
{ io.dout := sync_ff2 }
}
class rvlsadder extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val rs1 = Input(UInt(32.W))
val offset = Input(UInt(12.W))
val dout = Output(UInt(32.W))
})
val w1 = Cat(0.U(1.W),io.rs1(11,0)) + Cat(0.U(1.W),io.offset(11,0)) //w1[12] =cout offset[11]=sign
val w1 = Cat("b0".U,io.rs1(11,0)) + Cat("b0".U,io.offset(11,0)) //w1[12] =cout offset[11]=sign
val dout_upper = ((Fill(20, ~(io.offset(11) ^ w1(12)))) & io.rs1(31,12)) |
((Fill(20, ~io.offset(11) & w1(12))) & (io.rs1(31,12)+1.U)) |
((Fill(20, io.offset(11) & ~w1(12))) & (io.rs1(31,12)-1.U))
((Fill(20, ~io.offset(11) ^ w1(12))) & (io.rs1(31,12)+1.U)) |
((Fill(20, io.offset(11) ^ ~w1(12))) & (io.rs1(31,12)-1.U))
io.dout := Cat(dout_upper,w1(11,0))
}
class rvbradder extends Module{ //Done for verification and testing
class rvbsadder extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val pc = Input(UInt(31.W)) // 31:1 => 30:0
val offset = Input(UInt(12.W)) // 12:1 => 11:0
val dout = Output(UInt(31.W)) // 31:1 => 30:0
val pc = Input(UInt(32.W)) // lsb is not using in code
val offset = Input(UInt(13.W)) // lsb is not using in code
val dout = Output(UInt(31.W))
})
val w1 = Cat(0.U(1.W),io.pc(11,0)) + Cat(0.U(1.W),io.offset(11,0)) //w1[12] =cout offset[12]=sign
val dout_upper = ((Fill(19, ~(io.offset(11) ^ w1(12))))& io.pc(30,12)) |
((Fill(19, ~io.offset(11) & w1(12))) & (io.pc(30,12)+1.U)) |
((Fill(19, io.offset(11) & ~w1(12))) & (io.pc(30,12)-1.U))
val w1 = Cat("b0".U,io.pc(12,1)) + Cat("b0".U,io.offset(12,1)) //w1[12] =cout offset[12]=sign
val dout_upper = ((Fill(19, ~(io.offset(12) ^ w1(12))))& io.pc(31,13)) |
((Fill(19, ~io.offset(12) ^ w1(12))) & (io.pc(31,13)+1.U)) |
((Fill(19, io.offset(12) ^ ~w1(12))) & (io.pc(31,13)-1.U))
io.dout := Cat(dout_upper,w1(11,0))
}
class rvtwoscomp(WIDTH:Int=32) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(WIDTH.W))
val dout = Output(UInt(WIDTH.W))
})
val temp = Wire(Vec(WIDTH-1,UInt(1.W)))
val i:Int = 1
for(i <- 1 to WIDTH-1){
temp(i-1) := Mux(io.din(i-1,0).orR ,~io.din(i),io.din(i))}
val done = io.din(i-1,0).orR
temp(i-1) := Mux(done ,~io.din(i),io.din(i))
}
io.dout := Cat(temp.asUInt,io.din(0))
}
class rvmaskandmatch(WIDTH:Int=32) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val mask = Input(UInt(WIDTH.W))
@ -91,16 +115,19 @@ class rvmaskandmatch(WIDTH:Int=32) extends Module{ //Done for verification a
})
val matchvec = Wire(Vec(WIDTH,UInt(1.W)))
val masken_or_fullmask = io.masken.asBool & (~(io.mask(WIDTH-1,0).andR))
val masken_or_fullmask = io.masken.asBool & ~io.mask(WIDTH-1,0).andR
matchvec(0) := masken_or_fullmask | (io.mask(0) === io.data(0)).asUInt
for(i <- 1 to WIDTH-1)
{matchvec(i) := Mux(io.mask(i-1,0).andR & masken_or_fullmask,"b1".U,(io.mask(i) === io.data(i)).asUInt)}
io.match_out := matchvec.asUInt.andR
}//ewrfdxgh
io.match_out := matchvec.asUInt
}
class rvrangecheck_ch(CCM_SADR:UInt, CCM_SIZE:Int=128) extends Module{
class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{
val io = IO(new Bundle{
val addr = Input(UInt(32.W))
val in_range = Output(UInt(1.W))
@ -108,7 +135,9 @@ class rvrangecheck_ch(CCM_SADR:UInt, CCM_SIZE:Int=128) extends Module{
})
val REGION_BITS = 4
val MASK_BITS = 10 + log2Ceil(CCM_SIZE)
val start_addr = CCM_SADR
val start_addr = Wire(UInt(32.W))
start_addr := CCM_SIZE.U
val region = start_addr(31,(32-REGION_BITS))
io.in_region := (io.addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt
@ -118,14 +147,19 @@ class rvrangecheck_ch(CCM_SADR:UInt, CCM_SIZE:Int=128) extends Module{
io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt
}
// DONE
class rveven_paritygen(WIDTH:Int= 16) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val data_in = Input (UInt(WIDTH.W))
val parity_out = Output(UInt(1.W))
})
io.parity_out := io.data_in.xorR.asUInt
}
} // DONE
// DONE
class rveven_paritycheck(WIDTH:Int= 16) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val data_in = Input (UInt(WIDTH.W))
@ -133,20 +167,21 @@ class rveven_paritycheck(WIDTH:Int= 16) extends Module{ //Done for verificati
val parity_err = Output(UInt(1.W))
})
io.parity_err := (io.data_in.xorR.asUInt) ^ io.parity_in
}
} // DONE
class rvecc_encode extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(32.W))
val ecc_out = Output(UInt(7.W))
})
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1)
val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1)
val mask1 = Array(1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,1)
val mask2 = Array(1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0)
val mask3 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0)
val mask5 = Array(1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
val w0 = Wire(Vec(18,UInt(1.W)))
val w1 = Wire(Vec(18,UInt(1.W)))
val w2 = Wire(Vec(18,UInt(1.W)))
@ -154,7 +189,7 @@ class rvecc_encode extends Module{ //Done for verification and testing
val w4 = Wire(Vec(15,UInt(1.W)))
val w5 = Wire(Vec(6, UInt(1.W)))
var j = 0;var k = 0;var m = 0;
var x = 0;var y = 0;var z = 0;
var x = 0;var y = 0;var z = 0
for(i <- 0 to 31)
{
@ -165,12 +200,12 @@ class rvecc_encode extends Module{ //Done for verification and testing
if(mask4(i)==1) {w4(y) := io.din(i); y = y +1 }
if(mask5(i)==1) {w5(z) := io.din(i); z = z +1 }
}
val w6 = Cat((w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR))
val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR))
io.ecc_out := Cat(io.din.xorR ^ w6.xorR, w6)
}
// Make generator and then make it a method
class rvecc_decode extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val en = Input(UInt(1.W))
@ -182,7 +217,6 @@ class rvecc_decode extends Module{ //Done for verification and testing
val single_ecc_error = Output(UInt(1.W))
val double_ecc_error = Output(UInt(1.W))
})
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
@ -211,10 +245,10 @@ class rvecc_decode extends Module{ //Done for verification and testing
}
val ecc_check = Cat((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
io.ecc_out := ecc_check
io.single_ecc_error := io.en & (ecc_check =/= 0.U(7.W)) & ecc_check(6)
io.double_ecc_error := io.en & (ecc_check =/= 0.U(7.W)) & ~ecc_check(6)
io.single_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
io.double_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
val error_mask = Wire(Vec(39,UInt(1.W)))
for(i <- 1 until 40){
@ -224,11 +258,14 @@ class rvecc_decode extends Module{ //Done for verification and testing
val dout_plus_parity = Mux(io.single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity)
io.dout := Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2))
io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U(7.W)), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
}
class rvecc_encode_64 extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(64.W))
@ -263,9 +300,13 @@ class rvecc_encode_64 extends Module{ //Done for verification and testing
if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
}
io.ecc_out := Cat((w6.asUInt.xorR),(w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR))
io.ecc_out := Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR))
}
class rvecc_decode_64 extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val en = Input(UInt(1.W))
@ -290,7 +331,7 @@ class rvecc_decode_64 extends Module{ //Done for verification and testing
val w6 = Wire(Vec(7, UInt(1.W)))
var j = 0;var k = 0;var m = 0; var n =0;
var x = 0;var y = 0;var z = 0;
var x = 0;var y = 0;var z = 0
for(i <- 0 to 63)
{
@ -303,110 +344,16 @@ class rvecc_decode_64 extends Module{ //Done for verification and testing
if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
}
val ecc_check = Cat((io.ecc_in(6) ^ w6.asUInt.xorR) ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
io.ecc_error := io.en & (ecc_check(6,0) =/= 0.U(7.W))
}
val ecc_check = Cat((io.ecc_in(6) ^ w5.asUInt.xorR) ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
io.ecc_error := io.en & (ecc_check(6,0) != 0.U)
////////////////////////////TEC_RV_ICG////////////////////////
class TEC_RV_ICG extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val Q = Output(Clock())
val CK = Input(Clock())
val EN = Input(Bool())
val SE = Input(Bool())
})
addResource("/vsrc/TEC_RV_ICG.v")
}
class rvclkhdr extends Module {
val io = IO(new Bundle {
val l1clk = Output(Clock())
val clk = Input(Clock())
val en = Input(Bool())
val scan_mode = Input(Bool())
})
val clkhdr = { Module(new TEC_RV_ICG) }
io.l1clk := clkhdr.io.Q
clkhdr.io.CK := io.clk
clkhdr.io.EN := io.en
clkhdr.io.SE := io.scan_mode
}
object rvclkhdr {
def apply(clk: Clock, en: Bool, scan_mode: Bool): Clock = {
val cg = Module(new rvclkhdr)
cg.io.clk := clk
cg.io.en := en
cg.io.scan_mode := scan_mode
cg.io.l1clk
}
}
////rvdffe ///////////////////////////////////////////////////////////////////////
object rvdffe {
def apply(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = {
val obj = Module(new rvclkhdr())
val l1clk = obj.io.l1clk
obj.io.clk := clk
obj.io.en := en
obj.io.scan_mode := scan_mode
withClock(l1clk) {
RegNext(din, 0.U)
}
}
def apply(din: Bundle, en: Bool, clk: Clock, scan_mode: Bool) = {
val obj = Module(new rvclkhdr())
val l1clk = obj.io.l1clk
obj.io.clk := clk
obj.io.en := en
obj.io.scan_mode := scan_mode
withClock(l1clk) {
RegNext(din,0.U.asTypeOf(din.cloneType))
}
}
def apply(din: SInt, en: Bool, clk: Clock, scan_mode: Bool): Bits with Num[_ >: SInt with UInt <: Bits with Num[_ >: SInt with UInt]] = {
val obj = Module(new rvclkhdr())
val l1clk = obj.io.l1clk
obj.io.clk := clk
obj.io.en := en
obj.io.scan_mode := scan_mode
withClock(l1clk) {
RegNext(din, 0.S)
}
object rvsyncss {
def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)}
}
}
/////////////rvdffe //////////////////////////
/*
class class_rvdffe extends Module with RequireAsyncReset{
val io = IO(new Bundle {
val lsu_pkt_d = Input(new el2_load_cam_pkt_t)
val lsu_pkt_m = Output(new el2_load_cam_pkt_t)
val clk = Input(Clock())
val en = Input(Bool())
val scan_mode = Input(Bool())
})
io.lsu_pkt_m := rvdffe(io.lsu_pkt_d,io.en.asBool,io.clk,io.scan_mode.asBool)
}
object main extends App{
println("Generate Verilog")
chisel3.Driver.execute(args, ()=> new class_rvdffe)
}*/

375
src/main/scala/lib/el2_lib.scala
View File

@ -1,5 +1,4 @@
package lib
import chisel3._
import chisel3.util._
trait param {
@ -26,30 +25,30 @@ trait param {
val BUILD_AXI4 = true
val BUILD_AXI_NATIVE = true
val BUS_PRTY_DEFAULT = 3
val DATA_ACCESS_ADDR0 = "h00000000".U(32.W)
val DATA_ACCESS_ADDR1 = "hC0000000".U(32.W)
val DATA_ACCESS_ADDR2 = "hA0000000".U(32.W)
val DATA_ACCESS_ADDR3 = "h80000000".U(32.W)
val DATA_ACCESS_ADDR4 = "h00000000".U(32.W)
val DATA_ACCESS_ADDR5 = "h00000000".U(32.W)
val DATA_ACCESS_ADDR6 = "h00000000".U(32.W)
val DATA_ACCESS_ADDR7 = "h00000000".U(32.W)
val DATA_ACCESS_ENABLE0 = "h1".U(1.W)
val DATA_ACCESS_ENABLE1 = "h1".U(1.W)
val DATA_ACCESS_ENABLE2 = "h1".U(1.W)
val DATA_ACCESS_ENABLE3 = "h1".U(1.W)
val DATA_ACCESS_ENABLE4 = "h0".U(1.W)
val DATA_ACCESS_ENABLE5 = "h0".U(1.W)
val DATA_ACCESS_ENABLE6 = "h0".U(1.W)
val DATA_ACCESS_ENABLE7 = "h0".U(1.W)
val DATA_ACCESS_MASK0 = "h7FFFFFFF".U(32.W)
val DATA_ACCESS_MASK1 = "h3FFFFFFF".U(32.W)
val DATA_ACCESS_MASK2 = "h1FFFFFFF".U(32.W)
val DATA_ACCESS_MASK3 = "h0FFFFFFF".U(32.W)
val DATA_ACCESS_MASK4 = "hFFFFFFFF".U(32.W)
val DATA_ACCESS_MASK5 = "hFFFFFFFF".U(32.W)
val DATA_ACCESS_MASK6 = "hFFFFFFFF".U(32.W)
val DATA_ACCESS_MASK7 = "hFFFFFFFF".U(32.W)
val DATA_ACCESS_ADDR0 = 0x00000000 //.U(32.W)
val DATA_ACCESS_ADDR1 = 0xC0000000 //.U(32.W)
val DATA_ACCESS_ADDR2 = 0xA0000000 //.U(32.W)
val DATA_ACCESS_ADDR3 = 0x80000000 //.U(32.W)
val DATA_ACCESS_ADDR4 = 0x00000000 //.U(32.W)
val DATA_ACCESS_ADDR5 = 0x00000000 //.U(32.W)
val DATA_ACCESS_ADDR6 = 0x00000000 //.U(32.W)
val DATA_ACCESS_ADDR7 = 0x00000000 //.U(32.W)
val DATA_ACCESS_ENABLE0 = true //.U(1.W)
val DATA_ACCESS_ENABLE1 = true //.U(1.W)
val DATA_ACCESS_ENABLE2 = true //.U(1.W)
val DATA_ACCESS_ENABLE3 = true //.U(1.W)
val DATA_ACCESS_ENABLE4 = false //.U(1.W)
val DATA_ACCESS_ENABLE5 = false //.U(1.W)
val DATA_ACCESS_ENABLE6 = false //.U(1.W)
val DATA_ACCESS_ENABLE7 = false //.U(1.W)
val DATA_ACCESS_MASK0 = 0x7FFFFFFF //.U(32.W)
val DATA_ACCESS_MASK1 = 0x3FFFFFFF //.U(32.W)
val DATA_ACCESS_MASK2 = 0x1FFFFFFF //.U(32.W)
val DATA_ACCESS_MASK3 = 0x0FFFFFFF //.U(32.W)
val DATA_ACCESS_MASK4 = 0xFFFFFFFF //.U(32.W)
val DATA_ACCESS_MASK5 = 0xFFFFFFFF //.U(32.W)
val DATA_ACCESS_MASK6 = 0xFFFFFFFF //.U(32.W)
val DATA_ACCESS_MASK7 = 0xFFFFFFFF //.U(32.W)
val DCCM_BANK_BITS = 2 //.U(3.W)
val DCCM_BITS = 16 //.U(5.W)
val DCCM_BYTE_WIDTH = 4 //.U(3.W)
@ -59,8 +58,8 @@ trait param {
val DCCM_FDATA_WIDTH = 0x27 //.U(6.W)
val DCCM_INDEX_BITS = 0xC //.U(4.W)
val DCCM_NUM_BANKS = 0x04 //.U(5.W)
val DCCM_REGION = 15
val DCCM_SADR = "hF0040000".U(32.W)
val DCCM_REGION = 15 //.U(4.W)
val DCCM_SADR = 0xF0040000
val DCCM_SIZE = 0x040
val DCCM_WIDTH_BITS = 2 //.U(2.W)
val DMA_BUF_DEPTH = 5 //.U(3.W)
@ -102,9 +101,9 @@ trait param {
val ICCM_ICACHE = true //.U(1.W)
val ICCM_INDEX_BITS = 0xC //.U(4.W)
val ICCM_NUM_BANKS = 0x04 //.U(5.W)
val ICCM_ONLY = 0x0 //.U(1.W)
val ICCM_REGION = 0xE //.U(4.W)
val ICCM_SADR = 0xEE000000L //.U(32.W)
val ICCM_ONLY = false //.U(1.W)
val ICCM_REGION = 0xE //.U(4.W)
val ICCM_SADR = 0xEE000000 //.U(32.W)
val ICCM_SIZE = 0x040 //.U(10.W)
val IFU_BUS_ID = 0x1 //.U(1.W)
val IFU_BUS_PRTY = 0x2 //.U(2.W)
@ -142,13 +141,13 @@ trait param {
val LSU_NUM_NBLOAD_WIDTH = 0x2 //.U(3.W)
val LSU_SB_BITS = 0x10 //.U(5.W)
val LSU_STBUF_DEPTH = 0x4 //.U(4.W)
val NO_ICCM_NO_ICACHE = 0x0 //.U(1.W)
val NO_ICCM_NO_ICACHE = false //.U(1.W)
val PIC_2CYCLE = 0x0 //.U(1.W)
val PIC_BASE_ADDR = "hF00C0000".U(32.W)
val PIC_BASE_ADDR = 0xF00C0000 //.U(32.W)
val PIC_BITS = 0x0F //.U(5.W)
val PIC_INT_WORDS = 0x1 //.U(4.W)
val PIC_REGION = 0xF
val PIC_SIZE = 0x020//.U(9.W)
val PIC_REGION = 0xF //.U(4.W)
val PIC_SIZE = 0x020 //.U(9.W)
val PIC_TOTAL_INT = 0x1F //.U(8.W)
val PIC_TOTAL_INT_PLUS1 = 0x020 //.U(9.W)
val RET_STACK_SIZE = 0x8 //.U(4.W)
@ -159,37 +158,75 @@ trait param {
}
trait el2_lib extends param{
// Configuration Methods
def MEM_CAL : (Int, Int, Int)=
def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
def MEM_CAL : (Int, Int, Int, Int)=
(ICACHE_WAYPACK, ICACHE_ECC) match{
case(false,false) => (68,22, 68)
case(false,true) => (71,26, 71)
case(true,false) => (68*ICACHE_NUM_WAYS,22*ICACHE_NUM_WAYS, 68)
case(true,true) => (71*ICACHE_NUM_WAYS,26*ICACHE_NUM_WAYS, 71)
case(false,false) => (68, 22, 68, 22)
case(false,true) => (71, 26, 71, 26)
case(true,false) => (68*ICACHE_NUM_WAYS, 22*ICACHE_NUM_WAYS, 68, 22)
case(true,true) => (71*ICACHE_NUM_WAYS, 26*ICACHE_NUM_WAYS, 71, 26)
}
val DATA_MEM_LINE = MEM_CAL
val Tag_Word = MEM_CAL._4
implicit def bool2int(b:Boolean) = if (b) 1 else 0
implicit def aslong(b:Int) = 0xFFFFFFFFL & b
object rvsyncss {
def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)}
}
///////////////////////////////////////////////////////////////////
def el2_btb_tag_hash(pc : UInt) =
VecInit.tabulate(3)(i => pc(BTB_ADDR_HI+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE)+1)).reduce(_^_)
VecInit.tabulate(3)(i => pc(BTB_ADDR_HI-1+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE))).reduce(_^_)
///////////////////////////////////////////////////////////////////
def el2_btb_tag_hash_fold(pc : UInt) =
pc(BTB_ADDR_HI+(2*BTB_BTAG_SIZE),BTB_ADDR_HI+BTB_BTAG_SIZE+1)^pc(BTB_ADDR_HI+BTB_BTAG_SIZE,BTB_ADDR_HI+1)
///////////////////////////////////////////////////////////////////
def el2_btb_addr_hash(pc : UInt) =
if(BTB_FOLD2_INDEX_HASH) pc(BTB_INDEX1_HI,BTB_INDEX1_LO) ^ pc(BTB_INDEX3_HI,BTB_INDEX3_LO)
else pc(BTB_INDEX1_HI,BTB_INDEX1_LO) ^ pc(BTB_INDEX2_HI,BTB_INDEX2_LO) ^ pc(BTB_INDEX3_HI,BTB_INDEX3_LO)
if(BTB_FOLD2_INDEX_HASH) pc(BTB_INDEX1_HI-1,BTB_INDEX1_LO-1) ^ pc(BTB_INDEX3_HI-1,BTB_INDEX3_LO-1)
else (pc(BTB_INDEX1_HI-1,BTB_INDEX1_LO-1) ^ pc(BTB_INDEX2_HI-1,BTB_INDEX2_LO-1) ^ pc(BTB_INDEX3_HI-1,BTB_INDEX3_LO-1))
///////////////////////////////////////////////////////////////////
def el2_btb_ghr_hash(hashin : UInt, ghr :UInt) =
if(BHT_GHR_HASH_1) Cat(ghr(BHT_GHR_SIZE-1,BTB_INDEX1_HI-1), hashin(BTB_INDEX1_HI,2) ^ ghr(BTB_INDEX1_HI-2,0))
else hashin(BHT_GHR_SIZE+1,2) ^ ghr(BHT_GHR_SIZE-1,0)
def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
///////////////////////////////////////////////////////////////////
def rveven_paritycheck(data_in:UInt, parity_in:UInt) : UInt =
(data_in.xorR.asUInt) ^ parity_in
def Mux1H_LM(a:Seq[Bool], b:Seq[UInt]) = (0 until b.size).map(i=> repl(b(i).getWidth,a(i)) & b(i)).reduce(_|_)
///////////////////////////////////////////////////////////////////
def rveven_paritygen(data_in : UInt) =
data_in.xorR.asUInt
///////////////////////////////////////////////////////////////////
//rvbradder(Cat(pc, 0.U), Cat(offset, 0.U))
def rvbradder (pc:UInt, offset:UInt) = {
val dout_lower = pc(12,1) +& offset(12,1)
val pc_inc = pc(31,13)+1.U
val pc_dec = pc(31,13)-1.U
val sign = offset(12)
Cat(Mux1H(Seq(( sign ^ !dout_lower(dout_lower.getWidth-1)).asBool -> pc(31,13),
(!sign & dout_lower(dout_lower.getWidth-1)).asBool -> pc_inc,
( sign & !dout_lower(dout_lower.getWidth-1)).asBool -> pc_dec)), dout_lower(11,0), 0.U)
}
def rvsyncss(din:UInt,clk:Clock) = withClock(clk){RegNext(RegNext(din,0.U),0.U)}
///////////////////////////////////////////////////////////////////
// RV range
def rvrangecheck(CCM_SADR:Long, CCM_SIZE:Int, addr:UInt) = {
val REGION_BITS = 4;
val MASK_BITS = 10 + log2Ceil(CCM_SIZE)
val start_addr = CCM_SADR.U(32.W)
val region = start_addr(31,32-REGION_BITS)
val in_region = addr(31,(32-REGION_BITS)) === region
val in_range = if(CCM_SIZE==48)
(addr(31, MASK_BITS) === start_addr(31,MASK_BITS)) & ~addr(MASK_BITS-1 , MASK_BITS-2).andR
else addr(31,MASK_BITS) === start_addr(31,MASK_BITS)
(in_region, in_range)
}
def rvlsadder(rs1:UInt,offset:UInt) = {
val w1 = Cat(0.U(1.W),rs1(11,0)) + Cat(0.U(1.W),offset(11,0)) //w1[12] =cout offset[11]=sign
@ -198,73 +235,50 @@ trait el2_lib extends param{
((Fill(20, offset(11) & ~w1(12))) & (rs1(31,12)-1.U))
Cat(dout_upper,w1(11,0))
}
def Encoder(dec_value:UInt) = {
val enc_val = Cat(dec_value(4)| dec_value(5) | dec_value(6)|dec_value(7),
dec_value(2)| dec_value(3) | dec_value(6)|dec_value(7),
dec_value(1)| dec_value(3) | dec_value(5)|dec_value(7))
enc_val }
def rvbradder(pc:UInt,offset:UInt) = { // lsb is not using in code
val w1 = Cat(0.U(1.W),pc(11,0)) + Cat(0.U(1.W),offset(11,0)) //w1[12] =cout offset[12]=sign
val dout_upper = ((Fill(19, ~(offset(11) ^ w1(12))))& pc(30,12)) |
((Fill(19, ~offset(11) & w1(12))) & (pc(30,12)+1.U)) |
((Fill(19, offset(11) & ~w1(12))) & (pc(30,12)-1.U))
Cat(dout_upper,w1(11,0))}
def rvbradder_32 (pc:UInt, offset:UInt) = {
val dout_lower = pc(12,1) +& offset(12,1)
val pc_inc = pc(31,13)+1.U
val pc_dec = pc(31,13)-1.U
val sign = offset(12)
Cat(Mux1H(Seq((sign ^ !dout_lower(dout_lower.getWidth-1)).asBool -> pc(31,13),
(!sign & dout_lower(dout_lower.getWidth-1)).asBool -> pc_inc,
(sign & !dout_lower(dout_lower.getWidth-1)).asBool -> pc_dec)) , dout_lower(11,0), 0.U)
}
def rvtwoscomp(din:UInt) = { //Done for verification and testing
val temp = Wire(Vec(din.getWidth-1,UInt(1.W)))
for(i <- 1 to din.getWidth-1){
temp(i-1) := Mux(din(i-1,0).orR ,~din(i),din(i))
}
Cat(temp.asUInt,din(0))
}
//WIDTH will be inferred
def rvmaskandmatch(mask:UInt,data:UInt,masken:UInt) = { //Done for verification and testing
///////////////////////////////////////////////////////////////////
def rvmaskandmatch(mask:UInt, data:UInt, masken:Bool):UInt={
val matchvec = Wire(Vec(data.getWidth,UInt(1.W)))
val masken_or_fullmask = masken.asBool & (~(mask(data.getWidth-1,0).andR))
val masken_or_fullmask = masken & ~mask.andR
matchvec(0) := masken_or_fullmask | (mask(0) === data(0)).asUInt
for(i <- 1 to data.getWidth-1)
{matchvec(i) := Mux(mask(i-1,0).andR & masken_or_fullmask,"b1".U,(mask(i) === data(i)).asUInt)}
matchvec.asUInt.andR
matchvec(i) := Mux(mask(i-1,0).andR & masken_or_fullmask,"b1".U,(mask(i) === data(i)).asUInt)
matchvec.asUInt
}
def rvrangecheck_ch(addr:UInt,CCM_SADR:UInt, CCM_SIZE:Int=128) = {
val REGION_BITS = 4
val MASK_BITS = 10 + log2Ceil(CCM_SIZE)
val start_addr = CCM_SADR
val region = start_addr(31,(32-REGION_BITS))
val in_region = (addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt
val in_range = Wire(UInt(1.W))
if(CCM_SIZE == 48)
in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt)
else
in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt
(in_range,in_region)
///////////////////////////////////////////////////////////////////
def el2_configurable_gw(clk : Clock, rst:AsyncReset, extintsrc_req_sync : Bool, meigwctrl_polarity: Bool, meigwctrl_type: Bool, meigwclr: Bool) = {
val din = WireInit(Bool(), 0.U)
val dout = withClockAndReset(clk, rst){RegNext(din, false.B)}
din := (extintsrc_req_sync ^ meigwctrl_polarity) | (dout & !meigwclr)
Mux(meigwctrl_type, (extintsrc_req_sync ^ meigwctrl_polarity) | dout, extintsrc_req_sync ^ meigwctrl_polarity)
}
///////////////////////////////////////////////////////////////////
// Move rvecc_encode to a proper trait
def rvecc_encode(din:UInt):UInt = {
def pat(y : List[Int]) = (0 until y.size).map(i=> din(y(i))).reduce(_^_)
val w0 = pat(List(0, 1, 3, 4, 6, 8, 10, 11, 13, 15, 17, 19, 21, 23, 25, 26, 28, 30))
val w1 = pat(List(0, 2, 3, 5, 6, 9, 10, 12, 13, 16, 17, 20, 21, 24, 25, 27, 28, 31))
val w2 = pat(List(1, 2, 3, 7, 8, 9, 10, 14, 15, 16, 17, 22, 23, 24, 25, 29, 30, 31))
val w3 = pat(List(4, 5, 6, 7, 8, 9, 10, 18, 19, 20, 21, 22, 23, 24, 25))
val w4 = pat(List(11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25))
val w5 = pat(List(26, 27, 28, 29, 30, 31))
val w6 = Cat(w5,w4,w3,w2,w1,w0)
Cat(din.xorR ^ w6.xorR, w6)
}
class rvecc_encode extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(32.W))
val ecc_out = Output(UInt(7.W))
})
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1)
val w0 = Wire(Vec(18,UInt(1.W)))
val w1 = Wire(Vec(18,UInt(1.W)))
val w2 = Wire(Vec(18,UInt(1.W)))
@ -272,25 +286,22 @@ trait el2_lib extends param{
val w4 = Wire(Vec(15,UInt(1.W)))
val w5 = Wire(Vec(6, UInt(1.W)))
var j = 0;var k = 0;var m = 0;
var x = 0;var y = 0;var z = 0
var x = 0;var y = 0;var z = 0;
for(i <- 0 to 31)
{
if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := din(i); m = m +1 }
if(mask3(i)==1) {w3(x) := din(i); x = x +1 }
if(mask4(i)==1) {w4(y) := din(i); y = y +1 }
if(mask5(i)==1) {w5(z) := din(i); z = z +1 }
if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
if(mask3(i)==1) {w3(x) := io.din(i); x = x +1 }
if(mask4(i)==1) {w4(y) := io.din(i); y = y +1 }
if(mask5(i)==1) {w5(z) := io.din(i); z = z +1 }
}
val w6 = Cat((w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR))
val ecc_out = Cat(din.xorR ^ w6.xorR, w6)
ecc_out
io.ecc_out := Cat(io.din.xorR ^ w6.xorR, w6)
}
def rveven_paritygen(data_in:UInt):UInt = data_in.xorR.asUInt
def rveven_paritycheck(data_in:UInt,parity_in:UInt) = (data_in.xorR.asUInt) ^ parity_in
def rvecc_decode(en:UInt,din:UInt,ecc_in:UInt,sed_ded:UInt)= {
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
@ -335,6 +346,42 @@ trait el2_lib extends param{
(ecc_out,dout,single_ecc_error,double_ecc_error)
}
class rvecc_encode_64 extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(64.W))
val ecc_out = Output(UInt(7.W))
})
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
val w0 = Wire(Vec(35,UInt(1.W)))
val w1 = Wire(Vec(35,UInt(1.W)))
val w2 = Wire(Vec(35,UInt(1.W)))
val w3 = Wire(Vec(31,UInt(1.W)))
val w4 = Wire(Vec(31,UInt(1.W)))
val w5 = Wire(Vec(31,UInt(1.W)))
val w6 = Wire(Vec(7, UInt(1.W)))
var j = 0;var k = 0;var m = 0; var n =0;
var x = 0;var y = 0;var z = 0
for(i <- 0 to 63)
{
if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
}
io.ecc_out := Cat((w6.asUInt.xorR),(w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR))
}
def rvecc_encode_64(din:UInt):UInt = {
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
@ -345,7 +392,6 @@ trait el2_lib extends param{
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
val w0 = Wire(Vec(35,UInt(1.W)))
val w1 = Wire(Vec(35,UInt(1.W)))
val w2 = Wire(Vec(35,UInt(1.W)))
@ -367,11 +413,9 @@ trait el2_lib extends param{
if(mask5(i)==1) {w5(y) := din(i); y = y +1 }
if(mask6(i)==1) {w6(z) := din(i); z = z +1 }
}
val ecc_out = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR))
ecc_out
Cat((w6.asUInt.xorR),(w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR))
}
def rvecc_decode_64(en:UInt,din:UInt,ecc_in:UInt) = {
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
@ -408,4 +452,97 @@ trait el2_lib extends param{
ecc_error
}
}
class gated_latch extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val Q = Output(Clock())
val CK = Input(Clock())
val EN = Input(Bool())
val SE = Input(Bool())
})
addResource("/vsrc/gated_latch.v")
}
class rvclkhdr extends Module {
val io = IO(new Bundle {
val l1clk = Output(Clock())
val clk = Input(Clock())
val en = Input(Bool())
val scan_mode = Input(Bool())
})
val clkhdr = { Module(new gated_latch) }
io.l1clk := clkhdr.io.Q
clkhdr.io.CK := io.clk
clkhdr.io.EN := io.en
clkhdr.io.SE := io.scan_mode
}
object rvclkhdr {
def apply(clk: Clock, en: Bool, scan_mode: Bool): Clock = {
val cg = Module(new rvclkhdr)
cg.io.clk := clk
cg.io.en := en
cg.io.scan_mode := scan_mode
cg.io.l1clk
}
}
def rvrangecheck_ch(addr:UInt,CCM_SADR:UInt, CCM_SIZE:Int=128) = {
val REGION_BITS = 4
val MASK_BITS = 10 + log2Ceil(CCM_SIZE)
val start_addr = CCM_SADR
val region = start_addr(31,(32-REGION_BITS))
val in_region = (addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt
val in_range = Wire(UInt(1.W))
if(CCM_SIZE == 48)
in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt)
else
in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt
(in_range,in_region)
}
////rvdffe ///////////////////////////////////////////////////////////////////////
object rvdffe {
def apply(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = {
val obj = Module(new rvclkhdr())
val l1clk = obj.io.l1clk
obj.io.clk := clk
obj.io.en := en
obj.io.scan_mode := scan_mode
withClock(l1clk) {
RegNext(din, 0.U)
}
}
def apply(din: Bundle, en: Bool, clk: Clock, scan_mode: Bool) = {
val obj = Module(new rvclkhdr())
val l1clk = obj.io.l1clk
obj.io.clk := clk
obj.io.en := en
obj.io.scan_mode := scan_mode
withClock(l1clk) {
RegNext(din,0.U.asTypeOf(din.cloneType))
}
}
def apply(din: SInt, en: Bool, clk: Clock, scan_mode: Bool): Bits with Num[_ >: SInt with UInt <: Bits with Num[_ >: SInt with UInt]] = {
val obj = Module(new rvclkhdr())
val l1clk = obj.io.l1clk
obj.io.clk := clk
obj.io.en := en
obj.io.scan_mode := scan_mode
withClock(l1clk) {
RegNext(din, 0.S)
}
}
}
/////////////////////////////////////////////////////////
def rvtwoscomp(din:UInt) = { //Done for verification and testing
val temp = Wire(Vec(din.getWidth-1,UInt(1.W)))
for(i <- 1 to din.getWidth-1){
temp(i-1) := Mux(din(i-1,0).orR ,~din(i),din(i))
}
Cat(temp.asUInt,din(0))
}
}

14
src/main/scala/lsu/el2_lsu.scala
View File

@ -27,13 +27,13 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
val dec_tlu_mrac_ff = Input(UInt(32.W))
//Outputs
// val lsu_result_m = Output(UInt(32.W))
// val lsu_result_corr_r = Output(UInt(32.W))
val lsu_result_m = Output(UInt(32.W))
val lsu_result_corr_r = Output(UInt(32.W))
val lsu_load_stall_any = Output(Bool())
val lsu_store_stall_any = Output(Bool())
val lsu_fastint_stall_any = Output(Bool())
val lsu_idle_any = Output(Bool())
val lsu_fir_addr = Output(UInt(32.W))
val lsu_fir_addr = Output(UInt(31.W))
val lsu_fir_error = Output(UInt(2.W))
val lsu_single_ecc_error_incr = Output(Bool())
val lsu_error_pkt_r = Output(new el2_lsu_error_pkt_t)
@ -147,11 +147,13 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
val dma_dccm_wdata = WireInit(0.U(64.W))
val dma_dccm_wdata_lo = WireInit(0.U(32.W))
val dma_dccm_wdata_hi = WireInit(0.U(32.W))
val dma_mem_tag_m = WireInit(0.U(32.W))
val dma_mem_tag_m = WireInit(0.U(3.W))
val lsu_raw_fwd_lo_r = WireInit(0.U(1.W))
val lsu_raw_fwd_hi_r = WireInit(0.U(1.W))
val lsu_lsc_ctl = Module(new el2_lsu_lsc_ctl )
io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m
io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r
val dccm_ctl = Module(new el2_lsu_dccm_ctl )
val stbuf = Module(new el2_lsu_stbuf )
val ecc = Module(new el2_lsu_ecc )
@ -421,7 +423,9 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
bus_intf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d
bus_intf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
bus_intf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
// bus_intf.io.store_data_m := lsu_lsc_ctl.io.store_data_m
bus_intf.io.store_data_r := dccm_ctl.io.store_data_r
bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt
bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m

48
src/main/scala/lsu/el2_lsu_addrcheck.scala
View File

@ -33,9 +33,9 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib
//DCCM check
// Start address check
// Gen_dccm_enable
val (start_addr_in_dccm_d,start_addr_in_dccm_region_d) = if(DCCM_ENABLE) rvrangecheck_ch(io.start_addr_d,DCCM_SADR,DCCM_SIZE) else (0.U,0.U)
// End address check
val (end_addr_in_dccm_d ,end_addr_in_dccm_region_d) = if(DCCM_ENABLE) rvrangecheck_ch(io.end_addr_d,DCCM_SADR,DCCM_SIZE) else (0.U,0.U)
val (start_addr_in_dccm_d,start_addr_in_dccm_region_d) = if(DCCM_ENABLE) rvrangecheck_ch(io.start_addr_d ,aslong(DCCM_SADR).U ,DCCM_SIZE) else (0.U,0.U)
// End address check
val (end_addr_in_dccm_d ,end_addr_in_dccm_region_d) = if(DCCM_ENABLE) rvrangecheck_ch(io.end_addr_d ,aslong(DCCM_SADR).U ,DCCM_SIZE) else (0.U,0.U)
val addr_in_iccm = WireInit(0.U(1.W))
if(ICCM_ENABLE ){ //check_iccm
@ -47,9 +47,9 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib
//PIC memory check
//start address check
val (start_addr_in_pic_d,start_addr_in_pic_region_d) = rvrangecheck_ch(io.start_addr_d(31,0),PIC_BASE_ADDR,PIC_SIZE)
val (start_addr_in_pic_d,start_addr_in_pic_region_d) = rvrangecheck_ch(io.start_addr_d(31,0) ,aslong(PIC_BASE_ADDR).U ,PIC_SIZE)
//End address check
val (end_addr_in_pic_d,end_addr_in_pic_region_d) = rvrangecheck_ch(io.end_addr_d(31,0),PIC_BASE_ADDR,PIC_SIZE)
val (end_addr_in_pic_d,end_addr_in_pic_region_d) = rvrangecheck_ch(io.end_addr_d(31,0) ,aslong(PIC_BASE_ADDR).U ,PIC_SIZE)
val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d
val base_reg_dccm_or_pic = (io.rs1_region_d(3,0) === DCCM_REGION.U) | (io.rs1_region_d(3,0) === PIC_REGION.U) //base region
@ -62,25 +62,25 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib
val is_aligned_d = (io.lsu_pkt_d.word & (io.start_addr_d(1,0) === 0.U)) | (io.lsu_pkt_d.half & (io.start_addr_d(0) === 0.U)) | io.lsu_pkt_d.by
val non_dccm_access_ok = (!(Cat(DATA_ACCESS_ENABLE0,DATA_ACCESS_ENABLE1,DATA_ACCESS_ENABLE2,DATA_ACCESS_ENABLE3,
DATA_ACCESS_ENABLE4,DATA_ACCESS_ENABLE5,DATA_ACCESS_ENABLE6,DATA_ACCESS_ENABLE7)).orR) |
(((DATA_ACCESS_ENABLE0 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK0)) === (DATA_ACCESS_ADDR0 | DATA_ACCESS_MASK0)) | //0111
(DATA_ACCESS_ENABLE1 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK1)) === (DATA_ACCESS_ADDR1 | DATA_ACCESS_MASK1)) | //1111
(DATA_ACCESS_ENABLE2 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK2)) === (DATA_ACCESS_ADDR2 | DATA_ACCESS_MASK2)) | //1011
(DATA_ACCESS_ENABLE3 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK3)) === (DATA_ACCESS_ADDR3 | DATA_ACCESS_MASK3)) | //1000
(DATA_ACCESS_ENABLE4 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK4)) === (DATA_ACCESS_ADDR4 | DATA_ACCESS_MASK4)) |
(DATA_ACCESS_ENABLE5 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK5)) === (DATA_ACCESS_ADDR5 | DATA_ACCESS_MASK5)) |
(DATA_ACCESS_ENABLE6 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK6)) === (DATA_ACCESS_ADDR6 | DATA_ACCESS_MASK6)) |
(DATA_ACCESS_ENABLE7 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK7)) === (DATA_ACCESS_ADDR7 | DATA_ACCESS_MASK7)))
val non_dccm_access_ok = (!(Cat(DATA_ACCESS_ENABLE0.B ,DATA_ACCESS_ENABLE1.B ,DATA_ACCESS_ENABLE2.B ,DATA_ACCESS_ENABLE3.B ,
DATA_ACCESS_ENABLE4.B ,DATA_ACCESS_ENABLE5.B ,DATA_ACCESS_ENABLE6.B ,DATA_ACCESS_ENABLE7.B )).orR) |
(((DATA_ACCESS_ENABLE0.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK0).U)) === (aslong(DATA_ACCESS_ADDR0).U | aslong(DATA_ACCESS_MASK0).U)) | //0111
(DATA_ACCESS_ENABLE1.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK1).U)) === (aslong(DATA_ACCESS_ADDR1).U | aslong(DATA_ACCESS_MASK1).U)) | //1111
(DATA_ACCESS_ENABLE2.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK2).U)) === (aslong(DATA_ACCESS_ADDR2).U | aslong(DATA_ACCESS_MASK2).U)) | //1011
(DATA_ACCESS_ENABLE3.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK3).U)) === (aslong(DATA_ACCESS_ADDR3).U | aslong(DATA_ACCESS_MASK3).U)) | //1000
(DATA_ACCESS_ENABLE4.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK4).U)) === (aslong(DATA_ACCESS_ADDR4).U | aslong(DATA_ACCESS_MASK4).U)) |
(DATA_ACCESS_ENABLE5.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK5).U)) === (aslong(DATA_ACCESS_ADDR5).U | aslong(DATA_ACCESS_MASK5).U)) |
(DATA_ACCESS_ENABLE6.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK6).U)) === (aslong(DATA_ACCESS_ADDR6).U | aslong(DATA_ACCESS_MASK6).U)) |
(DATA_ACCESS_ENABLE7.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK7).U)) === (aslong(DATA_ACCESS_ADDR7).U | aslong(DATA_ACCESS_MASK7).U)))
&
((DATA_ACCESS_ENABLE0 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK0)) === (DATA_ACCESS_ADDR0 | DATA_ACCESS_MASK0)) |
(DATA_ACCESS_ENABLE1 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK1)) === (DATA_ACCESS_ADDR1 | DATA_ACCESS_MASK1)) |
(DATA_ACCESS_ENABLE2 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK2)) === (DATA_ACCESS_ADDR2 | DATA_ACCESS_MASK2)) |
(DATA_ACCESS_ENABLE3 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK3)) === (DATA_ACCESS_ADDR3 | DATA_ACCESS_MASK3)) |
(DATA_ACCESS_ENABLE4 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK4)) === (DATA_ACCESS_ADDR4 | DATA_ACCESS_MASK4)) |
(DATA_ACCESS_ENABLE5 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK5)) === (DATA_ACCESS_ADDR5 | DATA_ACCESS_MASK5)) |
(DATA_ACCESS_ENABLE6 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK6)) === (DATA_ACCESS_ADDR6 | DATA_ACCESS_MASK6)) |
(DATA_ACCESS_ENABLE7 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK7)) === (DATA_ACCESS_ADDR7 | DATA_ACCESS_MASK7))))
((DATA_ACCESS_ENABLE0.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK0).U)) === (aslong(DATA_ACCESS_ADDR0).U | aslong(DATA_ACCESS_MASK0).U)) |
(DATA_ACCESS_ENABLE1.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK1).U)) === (aslong(DATA_ACCESS_ADDR1).U | aslong(DATA_ACCESS_MASK1).U)) |
(DATA_ACCESS_ENABLE2.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK2).U)) === (aslong(DATA_ACCESS_ADDR2).U | aslong(DATA_ACCESS_MASK2).U)) |
(DATA_ACCESS_ENABLE3.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK3).U)) === (aslong(DATA_ACCESS_ADDR3).U | aslong(DATA_ACCESS_MASK3).U)) |
(DATA_ACCESS_ENABLE4.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK4).U)) === (aslong(DATA_ACCESS_ADDR4).U | aslong(DATA_ACCESS_MASK4).U)) |
(DATA_ACCESS_ENABLE5.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK5).U)) === (aslong(DATA_ACCESS_ADDR5).U | aslong(DATA_ACCESS_MASK5).U)) |
(DATA_ACCESS_ENABLE6.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK6).U)) === (aslong(DATA_ACCESS_ADDR6).U | aslong(DATA_ACCESS_MASK6).U)) |
(DATA_ACCESS_ENABLE7.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK7).U)) === (aslong(DATA_ACCESS_ADDR7).U | aslong(DATA_ACCESS_MASK7).U))))
val regpred_access_fault_d = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic)
val picm_access_fault_d = (io.addr_in_pic_d & ((io.start_addr_d(1,0) =/= 0.U(2.W)) | !io.lsu_pkt_d.word))
@ -123,4 +123,4 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib
object address_checker extends App{
println("Generate Verilog")
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_addrcheck()))
}
}

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