obuf_timer corrected

This commit is contained in:
​Laraib Khan 2021-02-02 15:34:19 +05:00
parent 3de7adb50f
commit 33a4c11f1c
4 changed files with 3 additions and 3 deletions

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@ -10798,7 +10798,7 @@ circuit lsu :
obuf_data <= obuf_data_in @[Reg.scala 28:23] obuf_data <= obuf_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
reg _T_1791 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1791 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when obuf_wr_en : @[Reg.scala 28:19] when io.lsu_busm_clken : @[Reg.scala 28:19]
_T_1791 <= obuf_wr_timer_in @[Reg.scala 28:23] _T_1791 <= obuf_wr_timer_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
obuf_wr_timer <= _T_1791 @[lsu_bus_buffer.scala 367:17] obuf_wr_timer <= _T_1791 @[lsu_bus_buffer.scala 367:17]

2
lsu.v
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@ -8929,7 +8929,7 @@ end // initial
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
obuf_wr_timer <= 3'h0; obuf_wr_timer <= 3'h0;
end else if (obuf_wr_en) begin end else if (io_lsu_busm_clken) begin
if (obuf_wr_en) begin if (obuf_wr_en) begin
obuf_wr_timer <= 3'h0; obuf_wr_timer <= 3'h0;
end else if (_T_1058) begin end else if (_T_1058) begin

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@ -364,7 +364,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val obuf_byteen = rvdffs_fpga (obuf_byteen_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) val obuf_byteen = rvdffs_fpga (obuf_byteen_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode) obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode)
val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode) val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode)
obuf_wr_timer := rvdff_fpga (obuf_wr_timer_in,io.lsu_busm_clk,obuf_wr_en,clock) obuf_wr_timer := rvdff_fpga (obuf_wr_timer_in,io.lsu_busm_clk,io.lsu_busm_clken,clock)
val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)