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miss state update

This commit is contained in:
waleed-lm 2020-10-23 12:05:34 +05:00
parent ca546eccb1
commit 33da1ffa79
6 changed files with 126 additions and 124 deletions
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184
el2_ifu_mem_ctl.fir
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@ -13323,68 +13323,68 @@ circuit el2_ifu_mem_ctl :
node _T_10105 = and(ic_tag_valid_unq, _T_10104) @[el2_ifu_mem_ctl.scala 798:48] node _T_10105 = and(ic_tag_valid_unq, _T_10104) @[el2_ifu_mem_ctl.scala 798:48]
node _T_10106 = orr(_T_10105) @[el2_ifu_mem_ctl.scala 798:115] node _T_10106 = orr(_T_10105) @[el2_ifu_mem_ctl.scala 798:115]
ic_debug_tag_val_rd_out <= _T_10106 @[el2_ifu_mem_ctl.scala 798:27] ic_debug_tag_val_rd_out <= _T_10106 @[el2_ifu_mem_ctl.scala 798:27]
reg _T_10107 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 800:58] reg _T_10107 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 800:57]
_T_10107 <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 800:58] _T_10107 <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 800:57]
io.ifu_pmu_bus_trxn <= _T_10107 @[el2_ifu_mem_ctl.scala 800:23] io.ifu_pmu_ic_miss <= _T_10107 @[el2_ifu_mem_ctl.scala 800:22]
reg _T_10108 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 801:58] reg _T_10108 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 801:56]
_T_10108 <= ic_act_hit_f @[el2_ifu_mem_ctl.scala 801:58] _T_10108 <= ic_act_hit_f @[el2_ifu_mem_ctl.scala 801:56]
io.ifu_pmu_bus_busy <= _T_10108 @[el2_ifu_mem_ctl.scala 801:23] io.ifu_pmu_ic_hit <= _T_10108 @[el2_ifu_mem_ctl.scala 801:21]
reg _T_10109 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 802:59] reg _T_10109 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 802:59]
_T_10109 <= ifc_bus_acc_fault_f @[el2_ifu_mem_ctl.scala 802:59] _T_10109 <= ifc_bus_acc_fault_f @[el2_ifu_mem_ctl.scala 802:59]
io.ifu_pmu_bus_error <= _T_10109 @[el2_ifu_mem_ctl.scala 802:24] io.ifu_pmu_bus_error <= _T_10109 @[el2_ifu_mem_ctl.scala 802:24]
node _T_10110 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 803:78] reg _T_10110 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 803:58]
node _T_10111 = and(ifu_bus_arvalid_ff, _T_10110) @[el2_ifu_mem_ctl.scala 803:76] _T_10110 <= bus_cmd_sent @[el2_ifu_mem_ctl.scala 803:58]
node _T_10112 = and(_T_10111, miss_pending) @[el2_ifu_mem_ctl.scala 803:98] io.ifu_pmu_bus_busy <= _T_10110 @[el2_ifu_mem_ctl.scala 803:23]
reg _T_10113 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 803:56] node _T_10111 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 804:80]
_T_10113 <= _T_10112 @[el2_ifu_mem_ctl.scala 803:56] node _T_10112 = and(ifu_bus_arvalid_ff, _T_10111) @[el2_ifu_mem_ctl.scala 804:78]
io.ifu_pmu_ic_hit <= _T_10113 @[el2_ifu_mem_ctl.scala 803:21] node _T_10113 = and(_T_10112, miss_pending) @[el2_ifu_mem_ctl.scala 804:100]
reg _T_10114 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 804:57] reg _T_10114 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 804:58]
_T_10114 <= bus_cmd_sent @[el2_ifu_mem_ctl.scala 804:57] _T_10114 <= _T_10113 @[el2_ifu_mem_ctl.scala 804:58]
io.ifu_pmu_ic_miss <= _T_10114 @[el2_ifu_mem_ctl.scala 804:22] io.ifu_pmu_bus_trxn <= _T_10114 @[el2_ifu_mem_ctl.scala 804:23]
io.ic_debug_addr <= io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_ifu_mem_ctl.scala 805:20] io.ic_debug_addr <= io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_ifu_mem_ctl.scala 807:20]
node _T_10115 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[el2_ifu_mem_ctl.scala 806:66] node _T_10115 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[el2_ifu_mem_ctl.scala 808:66]
io.ic_debug_tag_array <= _T_10115 @[el2_ifu_mem_ctl.scala 806:25] io.ic_debug_tag_array <= _T_10115 @[el2_ifu_mem_ctl.scala 808:25]
io.ic_debug_rd_en <= io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_ifu_mem_ctl.scala 807:21] io.ic_debug_rd_en <= io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_ifu_mem_ctl.scala 809:21]
io.ic_debug_wr_en <= io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_ifu_mem_ctl.scala 808:21] io.ic_debug_wr_en <= io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_ifu_mem_ctl.scala 810:21]
node _T_10116 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 809:64] node _T_10116 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 811:64]
node _T_10117 = eq(_T_10116, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 809:71] node _T_10117 = eq(_T_10116, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 811:71]
node _T_10118 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 809:117] node _T_10118 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 811:117]
node _T_10119 = eq(_T_10118, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 809:124] node _T_10119 = eq(_T_10118, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 811:124]
node _T_10120 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 810:43] node _T_10120 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 812:43]
node _T_10121 = eq(_T_10120, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 810:50] node _T_10121 = eq(_T_10120, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 812:50]
node _T_10122 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 810:96] node _T_10122 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 812:96]
node _T_10123 = eq(_T_10122, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 810:103] node _T_10123 = eq(_T_10122, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 812:103]
node _T_10124 = cat(_T_10121, _T_10123) @[Cat.scala 29:58] node _T_10124 = cat(_T_10121, _T_10123) @[Cat.scala 29:58]
node _T_10125 = cat(_T_10117, _T_10119) @[Cat.scala 29:58] node _T_10125 = cat(_T_10117, _T_10119) @[Cat.scala 29:58]
node _T_10126 = cat(_T_10125, _T_10124) @[Cat.scala 29:58] node _T_10126 = cat(_T_10125, _T_10124) @[Cat.scala 29:58]
io.ic_debug_way <= _T_10126 @[el2_ifu_mem_ctl.scala 809:19] io.ic_debug_way <= _T_10126 @[el2_ifu_mem_ctl.scala 811:19]
node _T_10127 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 811:65] node _T_10127 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 813:65]
node _T_10128 = bits(_T_10127, 0, 0) @[Bitwise.scala 72:15] node _T_10128 = bits(_T_10127, 0, 0) @[Bitwise.scala 72:15]
node _T_10129 = mux(_T_10128, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_10129 = mux(_T_10128, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_10130 = and(_T_10129, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 811:90] node _T_10130 = and(_T_10129, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 813:90]
ic_debug_tag_wr_en <= _T_10130 @[el2_ifu_mem_ctl.scala 811:22] ic_debug_tag_wr_en <= _T_10130 @[el2_ifu_mem_ctl.scala 813:22]
node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 812:53] node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 814:53]
node _T_10131 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 813:72] node _T_10131 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 815:72]
reg _T_10132 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_10132 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_10131 : @[Reg.scala 28:19] when _T_10131 : @[Reg.scala 28:19]
_T_10132 <= io.ic_debug_way @[Reg.scala 28:23] _T_10132 <= io.ic_debug_way @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
ic_debug_way_ff <= _T_10132 @[el2_ifu_mem_ctl.scala 813:19] ic_debug_way_ff <= _T_10132 @[el2_ifu_mem_ctl.scala 815:19]
node _T_10133 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 814:92] node _T_10133 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 816:92]
reg _T_10134 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_10134 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_10133 : @[Reg.scala 28:19] when _T_10133 : @[Reg.scala 28:19]
_T_10134 <= ic_debug_ict_array_sel_in @[Reg.scala 28:23] _T_10134 <= ic_debug_ict_array_sel_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
ic_debug_ict_array_sel_ff <= _T_10134 @[el2_ifu_mem_ctl.scala 814:29] ic_debug_ict_array_sel_ff <= _T_10134 @[el2_ifu_mem_ctl.scala 816:29]
reg _T_10135 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 815:54] reg _T_10135 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 817:54]
_T_10135 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 815:54] _T_10135 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 817:54]
ic_debug_rd_en_ff <= _T_10135 @[el2_ifu_mem_ctl.scala 815:21] ic_debug_rd_en_ff <= _T_10135 @[el2_ifu_mem_ctl.scala 817:21]
node _T_10136 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 816:111] node _T_10136 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 818:111]
reg _T_10137 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_10137 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_10136 : @[Reg.scala 28:19] when _T_10136 : @[Reg.scala 28:19]
_T_10137 <= ic_debug_rd_en_ff @[Reg.scala 28:23] _T_10137 <= ic_debug_rd_en_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
io.ifu_ic_debug_rd_data_valid <= _T_10137 @[el2_ifu_mem_ctl.scala 816:33] io.ifu_ic_debug_rd_data_valid <= _T_10137 @[el2_ifu_mem_ctl.scala 818:33]
node _T_10138 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] node _T_10138 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_10139 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] node _T_10139 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_10140 = cat(_T_10139, _T_10138) @[Cat.scala 29:58] node _T_10140 = cat(_T_10139, _T_10138) @[Cat.scala 29:58]
@ -13392,62 +13392,62 @@ circuit el2_ifu_mem_ctl :
node _T_10142 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] node _T_10142 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_10143 = cat(_T_10142, _T_10141) @[Cat.scala 29:58] node _T_10143 = cat(_T_10142, _T_10141) @[Cat.scala 29:58]
node _T_10144 = cat(_T_10143, _T_10140) @[Cat.scala 29:58] node _T_10144 = cat(_T_10143, _T_10140) @[Cat.scala 29:58]
node _T_10145 = orr(_T_10144) @[el2_ifu_mem_ctl.scala 817:213] node _T_10145 = orr(_T_10144) @[el2_ifu_mem_ctl.scala 819:213]
node _T_10146 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] node _T_10146 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_10147 = or(_T_10146, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 818:62] node _T_10147 = or(_T_10146, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 820:62]
node _T_10148 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 818:110] node _T_10148 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 820:110]
node _T_10149 = eq(_T_10147, _T_10148) @[el2_ifu_mem_ctl.scala 818:85] node _T_10149 = eq(_T_10147, _T_10148) @[el2_ifu_mem_ctl.scala 820:85]
node _T_10150 = and(UInt<1>("h01"), _T_10149) @[el2_ifu_mem_ctl.scala 818:27] node _T_10150 = and(UInt<1>("h01"), _T_10149) @[el2_ifu_mem_ctl.scala 820:27]
node _T_10151 = or(_T_10145, _T_10150) @[el2_ifu_mem_ctl.scala 817:216] node _T_10151 = or(_T_10145, _T_10150) @[el2_ifu_mem_ctl.scala 819:216]
node _T_10152 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] node _T_10152 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_10153 = or(_T_10152, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 819:62] node _T_10153 = or(_T_10152, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 821:62]
node _T_10154 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 819:110] node _T_10154 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 821:110]
node _T_10155 = eq(_T_10153, _T_10154) @[el2_ifu_mem_ctl.scala 819:85] node _T_10155 = eq(_T_10153, _T_10154) @[el2_ifu_mem_ctl.scala 821:85]
node _T_10156 = and(UInt<1>("h01"), _T_10155) @[el2_ifu_mem_ctl.scala 819:27] node _T_10156 = and(UInt<1>("h01"), _T_10155) @[el2_ifu_mem_ctl.scala 821:27]
node _T_10157 = or(_T_10151, _T_10156) @[el2_ifu_mem_ctl.scala 818:134] node _T_10157 = or(_T_10151, _T_10156) @[el2_ifu_mem_ctl.scala 820:134]
node _T_10158 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] node _T_10158 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_10159 = or(_T_10158, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 820:62] node _T_10159 = or(_T_10158, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 822:62]
node _T_10160 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 820:110] node _T_10160 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 822:110]
node _T_10161 = eq(_T_10159, _T_10160) @[el2_ifu_mem_ctl.scala 820:85] node _T_10161 = eq(_T_10159, _T_10160) @[el2_ifu_mem_ctl.scala 822:85]
node _T_10162 = and(UInt<1>("h01"), _T_10161) @[el2_ifu_mem_ctl.scala 820:27] node _T_10162 = and(UInt<1>("h01"), _T_10161) @[el2_ifu_mem_ctl.scala 822:27]
node _T_10163 = or(_T_10157, _T_10162) @[el2_ifu_mem_ctl.scala 819:134] node _T_10163 = or(_T_10157, _T_10162) @[el2_ifu_mem_ctl.scala 821:134]
node _T_10164 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] node _T_10164 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_10165 = or(_T_10164, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 821:62] node _T_10165 = or(_T_10164, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 823:62]
node _T_10166 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 821:110] node _T_10166 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 823:110]
node _T_10167 = eq(_T_10165, _T_10166) @[el2_ifu_mem_ctl.scala 821:85] node _T_10167 = eq(_T_10165, _T_10166) @[el2_ifu_mem_ctl.scala 823:85]
node _T_10168 = and(UInt<1>("h01"), _T_10167) @[el2_ifu_mem_ctl.scala 821:27] node _T_10168 = and(UInt<1>("h01"), _T_10167) @[el2_ifu_mem_ctl.scala 823:27]
node _T_10169 = or(_T_10163, _T_10168) @[el2_ifu_mem_ctl.scala 820:134] node _T_10169 = or(_T_10163, _T_10168) @[el2_ifu_mem_ctl.scala 822:134]
node _T_10170 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] node _T_10170 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_10171 = or(_T_10170, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 822:62] node _T_10171 = or(_T_10170, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 824:62]
node _T_10172 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 822:110] node _T_10172 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 824:110]
node _T_10173 = eq(_T_10171, _T_10172) @[el2_ifu_mem_ctl.scala 822:85] node _T_10173 = eq(_T_10171, _T_10172) @[el2_ifu_mem_ctl.scala 824:85]
node _T_10174 = and(UInt<1>("h00"), _T_10173) @[el2_ifu_mem_ctl.scala 822:27] node _T_10174 = and(UInt<1>("h00"), _T_10173) @[el2_ifu_mem_ctl.scala 824:27]
node _T_10175 = or(_T_10169, _T_10174) @[el2_ifu_mem_ctl.scala 821:134] node _T_10175 = or(_T_10169, _T_10174) @[el2_ifu_mem_ctl.scala 823:134]
node _T_10176 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] node _T_10176 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_10177 = or(_T_10176, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 823:62] node _T_10177 = or(_T_10176, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:62]
node _T_10178 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 823:110] node _T_10178 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:110]
node _T_10179 = eq(_T_10177, _T_10178) @[el2_ifu_mem_ctl.scala 823:85] node _T_10179 = eq(_T_10177, _T_10178) @[el2_ifu_mem_ctl.scala 825:85]
node _T_10180 = and(UInt<1>("h00"), _T_10179) @[el2_ifu_mem_ctl.scala 823:27] node _T_10180 = and(UInt<1>("h00"), _T_10179) @[el2_ifu_mem_ctl.scala 825:27]
node _T_10181 = or(_T_10175, _T_10180) @[el2_ifu_mem_ctl.scala 822:134] node _T_10181 = or(_T_10175, _T_10180) @[el2_ifu_mem_ctl.scala 824:134]
node _T_10182 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] node _T_10182 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_10183 = or(_T_10182, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 824:62] node _T_10183 = or(_T_10182, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 826:62]
node _T_10184 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 824:110] node _T_10184 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 826:110]
node _T_10185 = eq(_T_10183, _T_10184) @[el2_ifu_mem_ctl.scala 824:85] node _T_10185 = eq(_T_10183, _T_10184) @[el2_ifu_mem_ctl.scala 826:85]
node _T_10186 = and(UInt<1>("h00"), _T_10185) @[el2_ifu_mem_ctl.scala 824:27] node _T_10186 = and(UInt<1>("h00"), _T_10185) @[el2_ifu_mem_ctl.scala 826:27]
node _T_10187 = or(_T_10181, _T_10186) @[el2_ifu_mem_ctl.scala 823:134] node _T_10187 = or(_T_10181, _T_10186) @[el2_ifu_mem_ctl.scala 825:134]
node _T_10188 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] node _T_10188 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_10189 = or(_T_10188, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:62] node _T_10189 = or(_T_10188, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 827:62]
node _T_10190 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:110] node _T_10190 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 827:110]
node _T_10191 = eq(_T_10189, _T_10190) @[el2_ifu_mem_ctl.scala 825:85] node _T_10191 = eq(_T_10189, _T_10190) @[el2_ifu_mem_ctl.scala 827:85]
node _T_10192 = and(UInt<1>("h00"), _T_10191) @[el2_ifu_mem_ctl.scala 825:27] node _T_10192 = and(UInt<1>("h00"), _T_10191) @[el2_ifu_mem_ctl.scala 827:27]
node ifc_region_acc_okay = or(_T_10187, _T_10192) @[el2_ifu_mem_ctl.scala 824:134] node ifc_region_acc_okay = or(_T_10187, _T_10192) @[el2_ifu_mem_ctl.scala 826:134]
node _T_10193 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 826:40] node _T_10193 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 828:40]
node _T_10194 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 826:65] node _T_10194 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 828:65]
node _T_10195 = and(_T_10193, _T_10194) @[el2_ifu_mem_ctl.scala 826:63] node _T_10195 = and(_T_10193, _T_10194) @[el2_ifu_mem_ctl.scala 828:63]
node ifc_region_acc_fault_memory_bf = and(_T_10195, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 826:86] node ifc_region_acc_fault_memory_bf = and(_T_10195, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 828:86]
node _T_10196 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 827:63] node _T_10196 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 829:63]
ifc_region_acc_fault_final_bf <= _T_10196 @[el2_ifu_mem_ctl.scala 827:33] ifc_region_acc_fault_final_bf <= _T_10196 @[el2_ifu_mem_ctl.scala 829:33]
reg _T_10197 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 828:66] reg _T_10197 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 830:66]
_T_10197 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 828:66] _T_10197 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 830:66]
ifc_region_acc_fault_memory_f <= _T_10197 @[el2_ifu_mem_ctl.scala 828:33] ifc_region_acc_fault_memory_f <= _T_10197 @[el2_ifu_mem_ctl.scala 830:33]

56
el2_ifu_mem_ctl.v
View File

@ -2974,7 +2974,7 @@ module el2_ifu_mem_ctl(
wire _T_9681 = _T_9680 | _T_9554; // @[el2_ifu_mem_ctl.scala 744:91] wire _T_9681 = _T_9680 | _T_9554; // @[el2_ifu_mem_ctl.scala 744:91]
wire [1:0] ic_tag_valid_unq = {_T_10064,_T_9681}; // @[Cat.scala 29:58] wire [1:0] ic_tag_valid_unq = {_T_10064,_T_9681}; // @[Cat.scala 29:58]
reg [1:0] ic_debug_way_ff; // @[Reg.scala 27:20] reg [1:0] ic_debug_way_ff; // @[Reg.scala 27:20]
reg ic_debug_rd_en_ff; // @[el2_ifu_mem_ctl.scala 815:54] reg ic_debug_rd_en_ff; // @[el2_ifu_mem_ctl.scala 817:54]
wire [1:0] _T_10103 = ic_debug_rd_en_ff ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_10103 = ic_debug_rd_en_ff ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_10104 = ic_debug_way_ff & _T_10103; // @[el2_ifu_mem_ctl.scala 798:67] wire [1:0] _T_10104 = ic_debug_way_ff & _T_10103; // @[el2_ifu_mem_ctl.scala 798:67]
wire [1:0] _T_10105 = ic_tag_valid_unq & _T_10104; // @[el2_ifu_mem_ctl.scala 798:48] wire [1:0] _T_10105 = ic_tag_valid_unq & _T_10104; // @[el2_ifu_mem_ctl.scala 798:48]
@ -3750,7 +3750,7 @@ module el2_ifu_mem_ctl(
wire _T_10094 = bus_wren_last_0 | wren_reset_miss_0; // @[el2_ifu_mem_ctl.scala 780:73] wire _T_10094 = bus_wren_last_0 | wren_reset_miss_0; // @[el2_ifu_mem_ctl.scala 780:73]
wire [1:0] ifu_tag_wren = {_T_10095,_T_10094}; // @[Cat.scala 29:58] wire [1:0] ifu_tag_wren = {_T_10095,_T_10094}; // @[Cat.scala 29:58]
wire [1:0] _T_10129 = _T_3944 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_10129 = _T_3944 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] ic_debug_tag_wr_en = _T_10129 & io_ic_debug_way; // @[el2_ifu_mem_ctl.scala 811:90] wire [1:0] ic_debug_tag_wr_en = _T_10129 & io_ic_debug_way; // @[el2_ifu_mem_ctl.scala 813:90]
wire [1:0] ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en; // @[el2_ifu_mem_ctl.scala 724:45] wire [1:0] ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en; // @[el2_ifu_mem_ctl.scala 724:45]
reg [1:0] ifu_tag_wren_ff; // @[el2_ifu_mem_ctl.scala 726:14] reg [1:0] ifu_tag_wren_ff; // @[el2_ifu_mem_ctl.scala 726:14]
reg ic_valid_ff; // @[el2_ifu_mem_ctl.scala 730:14] reg ic_valid_ff; // @[el2_ifu_mem_ctl.scala 730:14]
@ -4957,30 +4957,30 @@ module el2_ifu_mem_ctl(
wire _T_10097 = ~fetch_uncacheable_ff; // @[el2_ifu_mem_ctl.scala 795:63] wire _T_10097 = ~fetch_uncacheable_ff; // @[el2_ifu_mem_ctl.scala 795:63]
wire _T_10098 = _T_10097 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 795:85] wire _T_10098 = _T_10097 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 795:85]
wire [1:0] _T_10100 = _T_10098 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_10100 = _T_10098 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
reg _T_10107; // @[el2_ifu_mem_ctl.scala 800:58] reg _T_10107; // @[el2_ifu_mem_ctl.scala 800:57]
reg _T_10108; // @[el2_ifu_mem_ctl.scala 801:58] reg _T_10108; // @[el2_ifu_mem_ctl.scala 801:56]
reg _T_10109; // @[el2_ifu_mem_ctl.scala 802:59] reg _T_10109; // @[el2_ifu_mem_ctl.scala 802:59]
wire _T_10110 = ~ifu_bus_arready_ff; // @[el2_ifu_mem_ctl.scala 803:78] reg _T_10110; // @[el2_ifu_mem_ctl.scala 803:58]
wire _T_10111 = ifu_bus_arvalid_ff & _T_10110; // @[el2_ifu_mem_ctl.scala 803:76] wire _T_10111 = ~ifu_bus_arready_ff; // @[el2_ifu_mem_ctl.scala 804:80]
wire _T_10112 = _T_10111 & miss_pending; // @[el2_ifu_mem_ctl.scala 803:98] wire _T_10112 = ifu_bus_arvalid_ff & _T_10111; // @[el2_ifu_mem_ctl.scala 804:78]
reg _T_10113; // @[el2_ifu_mem_ctl.scala 803:56] wire _T_10113 = _T_10112 & miss_pending; // @[el2_ifu_mem_ctl.scala 804:100]
reg _T_10114; // @[el2_ifu_mem_ctl.scala 804:57] reg _T_10114; // @[el2_ifu_mem_ctl.scala 804:58]
wire _T_10117 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[el2_ifu_mem_ctl.scala 809:71] wire _T_10117 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[el2_ifu_mem_ctl.scala 811:71]
wire _T_10119 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[el2_ifu_mem_ctl.scala 809:124] wire _T_10119 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[el2_ifu_mem_ctl.scala 811:124]
wire _T_10121 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[el2_ifu_mem_ctl.scala 810:50] wire _T_10121 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[el2_ifu_mem_ctl.scala 812:50]
wire _T_10123 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[el2_ifu_mem_ctl.scala 810:103] wire _T_10123 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[el2_ifu_mem_ctl.scala 812:103]
wire [3:0] _T_10126 = {_T_10117,_T_10119,_T_10121,_T_10123}; // @[Cat.scala 29:58] wire [3:0] _T_10126 = {_T_10117,_T_10119,_T_10121,_T_10123}; // @[Cat.scala 29:58]
wire ic_debug_ict_array_sel_in = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 812:53] wire ic_debug_ict_array_sel_in = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 814:53]
reg _T_10137; // @[Reg.scala 27:20] reg _T_10137; // @[Reg.scala 27:20]
assign io_ifu_miss_state_idle = miss_state == 3'h0; // @[el2_ifu_mem_ctl.scala 323:26] assign io_ifu_miss_state_idle = miss_state == 3'h0; // @[el2_ifu_mem_ctl.scala 323:26]
assign io_ifu_ic_mb_empty = _T_327 | _T_232; // @[el2_ifu_mem_ctl.scala 322:22] assign io_ifu_ic_mb_empty = _T_327 | _T_232; // @[el2_ifu_mem_ctl.scala 322:22]
assign io_ic_dma_active = _T_11 | io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 187:20] assign io_ic_dma_active = _T_11 | io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 187:20]
assign io_ic_write_stall = write_ic_16_bytes & _T_3932; // @[el2_ifu_mem_ctl.scala 691:21] assign io_ic_write_stall = write_ic_16_bytes & _T_3932; // @[el2_ifu_mem_ctl.scala 691:21]
assign io_ifu_pmu_ic_miss = _T_10114; // @[el2_ifu_mem_ctl.scala 804:22] assign io_ifu_pmu_ic_miss = _T_10107; // @[el2_ifu_mem_ctl.scala 800:22]
assign io_ifu_pmu_ic_hit = _T_10113; // @[el2_ifu_mem_ctl.scala 803:21] assign io_ifu_pmu_ic_hit = _T_10108; // @[el2_ifu_mem_ctl.scala 801:21]
assign io_ifu_pmu_bus_error = _T_10109; // @[el2_ifu_mem_ctl.scala 802:24] assign io_ifu_pmu_bus_error = _T_10109; // @[el2_ifu_mem_ctl.scala 802:24]
assign io_ifu_pmu_bus_busy = _T_10108; // @[el2_ifu_mem_ctl.scala 801:23] assign io_ifu_pmu_bus_busy = _T_10110; // @[el2_ifu_mem_ctl.scala 803:23]
assign io_ifu_pmu_bus_trxn = _T_10107; // @[el2_ifu_mem_ctl.scala 800:23] assign io_ifu_pmu_bus_trxn = _T_10114; // @[el2_ifu_mem_ctl.scala 804:23]
assign io_ifu_axi_awvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 138:22] assign io_ifu_axi_awvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 138:22]
assign io_ifu_axi_awid = 3'h0; // @[el2_ifu_mem_ctl.scala 137:19] assign io_ifu_axi_awid = 3'h0; // @[el2_ifu_mem_ctl.scala 137:19]
assign io_ifu_axi_awaddr = 32'h0; // @[el2_ifu_mem_ctl.scala 132:21] assign io_ifu_axi_awaddr = 32'h0; // @[el2_ifu_mem_ctl.scala 132:21]
@ -5021,11 +5021,11 @@ module el2_ifu_mem_ctl(
assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[el2_ifu_mem_ctl.scala 339:17] assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[el2_ifu_mem_ctl.scala 339:17]
assign io_ic_debug_wr_data = io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_ifu_mem_ctl.scala 340:23] assign io_ic_debug_wr_data = io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_ifu_mem_ctl.scala 340:23]
assign io_ifu_ic_debug_rd_data = _T_1212; // @[el2_ifu_mem_ctl.scala 348:27] assign io_ifu_ic_debug_rd_data = _T_1212; // @[el2_ifu_mem_ctl.scala 348:27]
assign io_ic_debug_addr = io_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[el2_ifu_mem_ctl.scala 805:20] assign io_ic_debug_addr = io_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[el2_ifu_mem_ctl.scala 807:20]
assign io_ic_debug_rd_en = io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_ifu_mem_ctl.scala 807:21] assign io_ic_debug_rd_en = io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_ifu_mem_ctl.scala 809:21]
assign io_ic_debug_wr_en = io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_ifu_mem_ctl.scala 808:21] assign io_ic_debug_wr_en = io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_ifu_mem_ctl.scala 810:21]
assign io_ic_debug_tag_array = io_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[el2_ifu_mem_ctl.scala 806:25] assign io_ic_debug_tag_array = io_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[el2_ifu_mem_ctl.scala 808:25]
assign io_ic_debug_way = _T_10126[1:0]; // @[el2_ifu_mem_ctl.scala 809:19] assign io_ic_debug_way = _T_10126[1:0]; // @[el2_ifu_mem_ctl.scala 811:19]
assign io_ic_tag_valid = ic_tag_valid_unq & _T_10100; // @[el2_ifu_mem_ctl.scala 795:19] assign io_ic_tag_valid = ic_tag_valid_unq & _T_10100; // @[el2_ifu_mem_ctl.scala 795:19]
assign io_iccm_rw_addr = _T_3064[14:0]; // @[el2_ifu_mem_ctl.scala 654:19] assign io_iccm_rw_addr = _T_3064[14:0]; // @[el2_ifu_mem_ctl.scala 654:19]
assign io_iccm_wren = _T_2633 | iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 625:16] assign io_iccm_wren = _T_2633 | iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 625:16]
@ -5044,7 +5044,7 @@ module el2_ifu_mem_ctl(
assign io_ic_data_f = io_ic_rd_data[31:0]; // @[el2_ifu_mem_ctl.scala 376:16] assign io_ic_data_f = io_ic_rd_data[31:0]; // @[el2_ifu_mem_ctl.scala 376:16]
assign io_ic_premux_data = ic_premux_data[63:0]; // @[el2_ifu_mem_ctl.scala 373:21] assign io_ic_premux_data = ic_premux_data[63:0]; // @[el2_ifu_mem_ctl.scala 373:21]
assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[el2_ifu_mem_ctl.scala 374:25] assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[el2_ifu_mem_ctl.scala 374:25]
assign io_ifu_ic_debug_rd_data_valid = _T_10137; // @[el2_ifu_mem_ctl.scala 816:33] assign io_ifu_ic_debug_rd_data_valid = _T_10137; // @[el2_ifu_mem_ctl.scala 818:33]
assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2416; // @[el2_ifu_mem_ctl.scala 472:27] assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2416; // @[el2_ifu_mem_ctl.scala 472:27]
assign io_iccm_correction_state = _T_2444 ? 1'h0 : _GEN_59; // @[el2_ifu_mem_ctl.scala 507:28 el2_ifu_mem_ctl.scala 520:32 el2_ifu_mem_ctl.scala 527:32 el2_ifu_mem_ctl.scala 534:32] assign io_iccm_correction_state = _T_2444 ? 1'h0 : _GEN_59; // @[el2_ifu_mem_ctl.scala 507:28 el2_ifu_mem_ctl.scala 520:32 el2_ifu_mem_ctl.scala 527:32 el2_ifu_mem_ctl.scala 534:32]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
@ -6015,7 +6015,7 @@ initial begin
_RAND_465 = {1{`RANDOM}}; _RAND_465 = {1{`RANDOM}};
_T_10109 = _RAND_465[0:0]; _T_10109 = _RAND_465[0:0];
_RAND_466 = {1{`RANDOM}}; _RAND_466 = {1{`RANDOM}};
_T_10113 = _RAND_466[0:0]; _T_10110 = _RAND_466[0:0];
_RAND_467 = {1{`RANDOM}}; _RAND_467 = {1{`RANDOM}};
_T_10114 = _RAND_467[0:0]; _T_10114 = _RAND_467[0:0];
_RAND_468 = {1{`RANDOM}}; _RAND_468 = {1{`RANDOM}};
@ -8524,14 +8524,14 @@ end // initial
_T_10109 <= ifc_bus_acc_fault_f; _T_10109 <= ifc_bus_acc_fault_f;
end end
if (reset) begin if (reset) begin
_T_10113 <= 1'h0; _T_10110 <= 1'h0;
end else begin end else begin
_T_10113 <= _T_10112; _T_10110 <= bus_cmd_sent;
end end
if (reset) begin if (reset) begin
_T_10114 <= 1'h0; _T_10114 <= 1'h0;
end else begin end else begin
_T_10114 <= bus_cmd_sent; _T_10114 <= _T_10113;
end end
end end
endmodule endmodule

10
src/main/scala/ifu/el2_ifu_mem_ctl.scala
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@ -797,11 +797,13 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
val ic_debug_way_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) val ic_debug_way_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
ic_debug_tag_val_rd_out := (ic_tag_valid_unq & (ic_debug_way_ff & Fill(ICACHE_NUM_WAYS, ic_debug_rd_en_ff))).orR() ic_debug_tag_val_rd_out := (ic_tag_valid_unq & (ic_debug_way_ff & Fill(ICACHE_NUM_WAYS, ic_debug_rd_en_ff))).orR()
io.ifu_pmu_bus_trxn := withClock(io.active_clk){RegNext(ic_act_miss_f, false.B)} io.ifu_pmu_ic_miss := withClock(io.active_clk){RegNext(ic_act_miss_f, false.B)}
io.ifu_pmu_bus_busy := withClock(io.active_clk){RegNext(ic_act_hit_f, false.B)} io.ifu_pmu_ic_hit := withClock(io.active_clk){RegNext(ic_act_hit_f, false.B)}
io.ifu_pmu_bus_error := withClock(io.active_clk){RegNext(ifc_bus_acc_fault_f, false.B)} io.ifu_pmu_bus_error := withClock(io.active_clk){RegNext(ifc_bus_acc_fault_f, false.B)}
io.ifu_pmu_ic_hit := withClock(io.active_clk){RegNext(ifu_bus_arvalid_ff & !ifu_bus_arready_ff & miss_pending, false.B)} io.ifu_pmu_bus_busy := withClock(io.active_clk){RegNext(bus_cmd_sent, false.B)}
io.ifu_pmu_ic_miss := withClock(io.active_clk){RegNext(bus_cmd_sent, false.B)} io.ifu_pmu_bus_trxn := withClock(io.active_clk){RegNext(ifu_bus_arvalid_ff & !ifu_bus_arready_ff & miss_pending, false.B)}
io.ic_debug_addr := io.dec_tlu_ic_diag_pkt.icache_dicawics io.ic_debug_addr := io.dec_tlu_ic_diag_pkt.icache_dicawics
io.ic_debug_tag_array := io.dec_tlu_ic_diag_pkt.icache_dicawics(16) io.ic_debug_tag_array := io.dec_tlu_ic_diag_pkt.icache_dicawics(16)
io.ic_debug_rd_en := io.dec_tlu_ic_diag_pkt.icache_rd_valid io.ic_debug_rd_en := io.dec_tlu_ic_diag_pkt.icache_rd_valid

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target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
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target/scala-2.12/classes/ifu/ifu_mem$.class
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target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class
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