Update el2_ifu_ifc_ctrl.scala
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@ -154,7 +154,7 @@ val io = IO(new Bundle{
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io.ifc_fetch_addr_f := RegEnable(io.ifc_fetch_addr_bf, init = 0.U, io.exu_flush_final|io.ifc_fetch_req_f)
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}
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/*
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object ifu_ifc extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctrl()))
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}
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}*/
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