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| EL2_IC_DATA.anno.json | ||
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| EL2_IC_DATA.v | ||
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| InoutPort.v | ||
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| README.md | ||
| RVCExpander.anno.json | ||
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| TEC_RV_ICG.v | ||
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README.md
EL2 SweRV RISC-V Core Chiselified Version from <> LAMPRO MELLON
This repository contains the SweRV EL2 Core design in CHISEL
Back ground
The project is being made for learning purpose. Copy rights to the SweRV-EL2 belongs to Wrestern Digital
Directory Structure
├── configs # Configurations Dir
│ └── snapshots # Where generated configuration files are created
├── design # Design root dir
│ ├── dbg # Debugger
│ ├── dec # Decode, Registers and Exceptions
│ ├── dmi # DMI block
│ ├── exu # EXU (ALU/MUL/DIV)
│ ├── ifu # Fetch & Branch Prediction
│ ├── include
│ ├── lib
│ └── lsu # Load/Store
├── docs
├── tools # Scripts/Makefiles
└── testbench # (Very) simple testbench
├── asm # Example assembly files
└── hex # Canned demo hex files