IFC
This commit is contained in:
parent
ea5ca86ef6
commit
5b6d41e88b
File diff suppressed because it is too large
Load Diff
|
@ -137,7 +137,7 @@ module el2_ifu_compress_ctl(
|
||||||
wire _T_407 = _T_406 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_407 = _T_406 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_408 = _T_407 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_408 = _T_407 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_409 = _T_408 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_409 = _T_408 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_410 = _T_386 | _T_409; // @[el2_ifu_compress_ctl.scala 37:59]
|
wire _T_410 = _T_386 | _T_409; // @[el2_ifu_compress_ctl.scala 34:59]
|
||||||
wire _T_427 = _T_56 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_427 = _T_56 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_428 = _T_427 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_428 = _T_427 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_429 = _T_428 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_429 = _T_428 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
|
@ -145,7 +145,7 @@ module el2_ifu_compress_ctl(
|
||||||
wire _T_431 = _T_430 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_431 = _T_430 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_432 = _T_431 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_432 = _T_431 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_433 = _T_432 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_433 = _T_432 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_434 = _T_410 | _T_433; // @[el2_ifu_compress_ctl.scala 38:59]
|
wire _T_434 = _T_410 | _T_433; // @[el2_ifu_compress_ctl.scala 34:107]
|
||||||
wire _T_451 = _T_56 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_451 = _T_56 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_452 = _T_451 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_452 = _T_451 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_453 = _T_452 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_453 = _T_452 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
|
@ -153,7 +153,7 @@ module el2_ifu_compress_ctl(
|
||||||
wire _T_455 = _T_454 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_455 = _T_454 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_456 = _T_455 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_456 = _T_455 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_457 = _T_456 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_457 = _T_456 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_458 = _T_434 | _T_457; // @[el2_ifu_compress_ctl.scala 39:58]
|
wire _T_458 = _T_434 | _T_457; // @[el2_ifu_compress_ctl.scala 35:50]
|
||||||
wire _T_475 = _T_56 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_475 = _T_56 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_476 = _T_475 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_476 = _T_475 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_477 = _T_476 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_477 = _T_476 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
|
@ -161,7 +161,7 @@ module el2_ifu_compress_ctl(
|
||||||
wire _T_479 = _T_478 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_479 = _T_478 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_480 = _T_479 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_480 = _T_479 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_481 = _T_480 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_481 = _T_480 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_482 = _T_458 | _T_481; // @[el2_ifu_compress_ctl.scala 40:55]
|
wire _T_482 = _T_458 | _T_481; // @[el2_ifu_compress_ctl.scala 35:94]
|
||||||
wire _T_487 = ~io_din[12]; // @[el2_ifu_compress_ctl.scala 12:83]
|
wire _T_487 = ~io_din[12]; // @[el2_ifu_compress_ctl.scala 12:83]
|
||||||
wire _T_499 = _T_11 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_499 = _T_11 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_500 = _T_499 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_500 = _T_499 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
|
@ -169,62 +169,62 @@ module el2_ifu_compress_ctl(
|
||||||
wire _T_502 = _T_501 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_502 = _T_501 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_503 = _T_502 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_503 = _T_502 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_504 = _T_503 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_504 = _T_503 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_507 = _T_504 & _T_147; // @[el2_ifu_compress_ctl.scala 42:56]
|
wire _T_507 = _T_504 & _T_147; // @[el2_ifu_compress_ctl.scala 36:94]
|
||||||
wire _T_508 = _T_482 | _T_507; // @[el2_ifu_compress_ctl.scala 41:57]
|
wire _T_508 = _T_482 | _T_507; // @[el2_ifu_compress_ctl.scala 36:49]
|
||||||
wire _T_514 = _T_190 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_514 = _T_190 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_515 = _T_514 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_515 = _T_514 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_516 = _T_508 | _T_515; // @[el2_ifu_compress_ctl.scala 42:71]
|
wire _T_516 = _T_508 | _T_515; // @[el2_ifu_compress_ctl.scala 36:109]
|
||||||
wire _T_522 = _T_514 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_522 = _T_514 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_523 = _T_516 | _T_522; // @[el2_ifu_compress_ctl.scala 43:34]
|
wire _T_523 = _T_516 | _T_522; // @[el2_ifu_compress_ctl.scala 37:26]
|
||||||
wire _T_529 = _T_514 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_529 = _T_514 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_530 = _T_523 | _T_529; // @[el2_ifu_compress_ctl.scala 44:33]
|
wire _T_530 = _T_523 | _T_529; // @[el2_ifu_compress_ctl.scala 37:48]
|
||||||
wire _T_536 = _T_514 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_536 = _T_514 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_537 = _T_530 | _T_536; // @[el2_ifu_compress_ctl.scala 45:33]
|
wire _T_537 = _T_530 | _T_536; // @[el2_ifu_compress_ctl.scala 37:70]
|
||||||
wire _T_543 = _T_514 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_543 = _T_514 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_544 = _T_537 | _T_543; // @[el2_ifu_compress_ctl.scala 46:34]
|
wire _T_544 = _T_537 | _T_543; // @[el2_ifu_compress_ctl.scala 37:93]
|
||||||
wire out_2 = _T_544 | _T_228; // @[el2_ifu_compress_ctl.scala 47:34]
|
wire out_2 = _T_544 | _T_228; // @[el2_ifu_compress_ctl.scala 38:26]
|
||||||
wire [4:0] rs2d = io_din[6:2]; // @[el2_ifu_compress_ctl.scala 56:20]
|
wire [4:0] rs2d = io_din[6:2]; // @[el2_ifu_compress_ctl.scala 43:20]
|
||||||
wire [4:0] rdd = io_din[11:7]; // @[el2_ifu_compress_ctl.scala 57:19]
|
wire [4:0] rdd = io_din[11:7]; // @[el2_ifu_compress_ctl.scala 44:19]
|
||||||
wire [4:0] rdpd = {2'h1,io_din[9:7]}; // @[Cat.scala 29:58]
|
wire [4:0] rdpd = {2'h1,io_din[9:7]}; // @[Cat.scala 29:58]
|
||||||
wire [4:0] rs2pd = {2'h1,io_din[4:2]}; // @[Cat.scala 29:58]
|
wire [4:0] rs2pd = {2'h1,io_din[4:2]}; // @[Cat.scala 29:58]
|
||||||
wire _T_557 = _T_308 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_557 = _T_308 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_564 = _T_317 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_564 = _T_317 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_565 = _T_564 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_565 = _T_564 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_566 = _T_557 | _T_565; // @[el2_ifu_compress_ctl.scala 61:33]
|
wire _T_566 = _T_557 | _T_565; // @[el2_ifu_compress_ctl.scala 48:33]
|
||||||
wire _T_572 = _T_323 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_572 = _T_323 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_573 = _T_566 | _T_572; // @[el2_ifu_compress_ctl.scala 61:58]
|
wire _T_573 = _T_566 | _T_572; // @[el2_ifu_compress_ctl.scala 48:58]
|
||||||
wire _T_580 = _T_317 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_580 = _T_317 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_581 = _T_580 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_581 = _T_580 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_582 = _T_573 | _T_581; // @[el2_ifu_compress_ctl.scala 61:79]
|
wire _T_582 = _T_573 | _T_581; // @[el2_ifu_compress_ctl.scala 48:79]
|
||||||
wire _T_588 = _T_331 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_588 = _T_331 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_589 = _T_582 | _T_588; // @[el2_ifu_compress_ctl.scala 61:104]
|
wire _T_589 = _T_582 | _T_588; // @[el2_ifu_compress_ctl.scala 48:104]
|
||||||
wire _T_596 = _T_317 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_596 = _T_317 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_597 = _T_596 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_597 = _T_596 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_598 = _T_589 | _T_597; // @[el2_ifu_compress_ctl.scala 62:24]
|
wire _T_598 = _T_589 | _T_597; // @[el2_ifu_compress_ctl.scala 49:24]
|
||||||
wire _T_604 = _T_339 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_604 = _T_339 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_605 = _T_598 | _T_604; // @[el2_ifu_compress_ctl.scala 62:48]
|
wire _T_605 = _T_598 | _T_604; // @[el2_ifu_compress_ctl.scala 49:48]
|
||||||
wire _T_613 = _T_317 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_613 = _T_317 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_614 = _T_613 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_614 = _T_613 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_615 = _T_605 | _T_614; // @[el2_ifu_compress_ctl.scala 62:69]
|
wire _T_615 = _T_605 | _T_614; // @[el2_ifu_compress_ctl.scala 49:69]
|
||||||
wire _T_621 = _T_347 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_621 = _T_347 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_622 = _T_615 | _T_621; // @[el2_ifu_compress_ctl.scala 62:94]
|
wire _T_622 = _T_615 | _T_621; // @[el2_ifu_compress_ctl.scala 49:94]
|
||||||
wire _T_629 = _T_317 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_629 = _T_317 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_630 = _T_629 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_630 = _T_629 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_631 = _T_622 | _T_630; // @[el2_ifu_compress_ctl.scala 63:22]
|
wire _T_631 = _T_622 | _T_630; // @[el2_ifu_compress_ctl.scala 50:22]
|
||||||
wire _T_635 = _T_190 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_635 = _T_190 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_636 = _T_631 | _T_635; // @[el2_ifu_compress_ctl.scala 63:46]
|
wire _T_636 = _T_631 | _T_635; // @[el2_ifu_compress_ctl.scala 50:46]
|
||||||
wire _T_642 = _T_190 & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_642 = _T_190 & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_643 = _T_642 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_643 = _T_642 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire rdrd = _T_636 | _T_643; // @[el2_ifu_compress_ctl.scala 63:65]
|
wire rdrd = _T_636 | _T_643; // @[el2_ifu_compress_ctl.scala 50:65]
|
||||||
wire _T_651 = _T_380 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_651 = _T_380 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_659 = _T_403 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_659 = _T_403 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_660 = _T_651 | _T_659; // @[el2_ifu_compress_ctl.scala 65:38]
|
wire _T_660 = _T_651 | _T_659; // @[el2_ifu_compress_ctl.scala 52:38]
|
||||||
wire _T_668 = _T_427 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_668 = _T_427 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_669 = _T_660 | _T_668; // @[el2_ifu_compress_ctl.scala 66:28]
|
wire _T_669 = _T_660 | _T_668; // @[el2_ifu_compress_ctl.scala 52:63]
|
||||||
wire _T_677 = _T_451 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_677 = _T_451 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_678 = _T_669 | _T_677; // @[el2_ifu_compress_ctl.scala 67:27]
|
wire _T_678 = _T_669 | _T_677; // @[el2_ifu_compress_ctl.scala 52:87]
|
||||||
wire _T_686 = _T_475 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_686 = _T_475 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_687 = _T_678 | _T_686; // @[el2_ifu_compress_ctl.scala 68:27]
|
wire _T_687 = _T_678 | _T_686; // @[el2_ifu_compress_ctl.scala 53:27]
|
||||||
wire _T_703 = _T_2 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_703 = _T_2 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_704 = _T_703 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_704 = _T_703 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_705 = _T_704 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_705 = _T_704 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
|
@ -232,61 +232,61 @@ module el2_ifu_compress_ctl(
|
||||||
wire _T_707 = _T_706 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_707 = _T_706 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_708 = _T_707 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_708 = _T_707 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_709 = _T_708 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_709 = _T_708 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_710 = _T_687 | _T_709; // @[el2_ifu_compress_ctl.scala 69:27]
|
wire _T_710 = _T_687 | _T_709; // @[el2_ifu_compress_ctl.scala 53:51]
|
||||||
wire _T_717 = _T_56 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_717 = _T_56 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_718 = _T_717 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_718 = _T_717 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_719 = _T_710 | _T_718; // @[el2_ifu_compress_ctl.scala 70:41]
|
wire _T_719 = _T_710 | _T_718; // @[el2_ifu_compress_ctl.scala 53:89]
|
||||||
wire _T_726 = _T_56 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_726 = _T_56 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_727 = _T_726 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_727 = _T_726 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_728 = _T_719 | _T_727; // @[el2_ifu_compress_ctl.scala 71:27]
|
wire _T_728 = _T_719 | _T_727; // @[el2_ifu_compress_ctl.scala 54:27]
|
||||||
wire _T_735 = _T_56 & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_735 = _T_56 & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_736 = _T_735 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_736 = _T_735 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_737 = _T_728 | _T_736; // @[el2_ifu_compress_ctl.scala 72:27]
|
wire _T_737 = _T_728 | _T_736; // @[el2_ifu_compress_ctl.scala 54:51]
|
||||||
wire _T_744 = _T_56 & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_744 = _T_56 & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_745 = _T_744 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_745 = _T_744 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_746 = _T_737 | _T_745; // @[el2_ifu_compress_ctl.scala 73:27]
|
wire _T_746 = _T_737 | _T_745; // @[el2_ifu_compress_ctl.scala 54:75]
|
||||||
wire _T_753 = _T_56 & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_753 = _T_56 & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_754 = _T_753 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_754 = _T_753 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_755 = _T_746 | _T_754; // @[el2_ifu_compress_ctl.scala 74:27]
|
wire _T_755 = _T_746 | _T_754; // @[el2_ifu_compress_ctl.scala 54:99]
|
||||||
wire _T_764 = _T_194 & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_764 = _T_194 & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_765 = _T_764 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_765 = _T_764 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_766 = _T_755 | _T_765; // @[el2_ifu_compress_ctl.scala 75:27]
|
wire _T_766 = _T_755 | _T_765; // @[el2_ifu_compress_ctl.scala 55:27]
|
||||||
wire rdrs1 = _T_766 | _T_195; // @[el2_ifu_compress_ctl.scala 76:30]
|
wire rdrs1 = _T_766 | _T_195; // @[el2_ifu_compress_ctl.scala 55:54]
|
||||||
wire _T_777 = io_din[15] & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_777 = io_din[15] & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_778 = _T_777 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_778 = _T_777 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_782 = io_din[15] & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_782 = io_din[15] & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_783 = _T_782 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_783 = _T_782 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_784 = _T_778 | _T_783; // @[el2_ifu_compress_ctl.scala 79:34]
|
wire _T_784 = _T_778 | _T_783; // @[el2_ifu_compress_ctl.scala 57:34]
|
||||||
wire _T_788 = io_din[15] & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_788 = io_din[15] & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_789 = _T_788 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_789 = _T_788 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_790 = _T_784 | _T_789; // @[el2_ifu_compress_ctl.scala 79:54]
|
wire _T_790 = _T_784 | _T_789; // @[el2_ifu_compress_ctl.scala 57:54]
|
||||||
wire _T_794 = io_din[15] & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_794 = io_din[15] & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_795 = _T_794 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_795 = _T_794 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_796 = _T_790 | _T_795; // @[el2_ifu_compress_ctl.scala 79:74]
|
wire _T_796 = _T_790 | _T_795; // @[el2_ifu_compress_ctl.scala 57:74]
|
||||||
wire _T_800 = io_din[15] & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_800 = io_din[15] & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_801 = _T_800 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_801 = _T_800 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_802 = _T_796 | _T_801; // @[el2_ifu_compress_ctl.scala 79:94]
|
wire _T_802 = _T_796 | _T_801; // @[el2_ifu_compress_ctl.scala 57:94]
|
||||||
wire _T_807 = _T_200 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_807 = _T_200 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire rs2rs2 = _T_802 | _T_807; // @[el2_ifu_compress_ctl.scala 79:114]
|
wire rs2rs2 = _T_802 | _T_807; // @[el2_ifu_compress_ctl.scala 57:114]
|
||||||
wire rdprd = _T_12 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire rdprd = _T_12 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_820 = io_din[15] & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_820 = io_din[15] & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_821 = _T_820 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_821 = _T_820 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_827 = _T_821 | _T_234; // @[el2_ifu_compress_ctl.scala 83:36]
|
wire _T_827 = _T_821 | _T_234; // @[el2_ifu_compress_ctl.scala 61:36]
|
||||||
wire _T_830 = ~io_din[1]; // @[el2_ifu_compress_ctl.scala 12:83]
|
wire _T_830 = ~io_din[1]; // @[el2_ifu_compress_ctl.scala 12:83]
|
||||||
wire _T_831 = io_din[14] & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_831 = io_din[14] & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_834 = _T_831 & _T_147; // @[el2_ifu_compress_ctl.scala 83:76]
|
wire _T_834 = _T_831 & _T_147; // @[el2_ifu_compress_ctl.scala 61:76]
|
||||||
wire rdprs1 = _T_827 | _T_834; // @[el2_ifu_compress_ctl.scala 83:57]
|
wire rdprs1 = _T_827 | _T_834; // @[el2_ifu_compress_ctl.scala 61:57]
|
||||||
wire _T_846 = _T_128 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_846 = _T_128 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_847 = _T_846 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_847 = _T_846 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_851 = io_din[15] & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_851 = io_din[15] & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_854 = _T_851 & _T_147; // @[el2_ifu_compress_ctl.scala 85:66]
|
wire _T_854 = _T_851 & _T_147; // @[el2_ifu_compress_ctl.scala 63:66]
|
||||||
wire rs2prs2 = _T_847 | _T_854; // @[el2_ifu_compress_ctl.scala 85:47]
|
wire rs2prs2 = _T_847 | _T_854; // @[el2_ifu_compress_ctl.scala 63:47]
|
||||||
wire _T_859 = _T_190 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_859 = _T_190 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire rs2prd = _T_859 & _T_147; // @[el2_ifu_compress_ctl.scala 86:33]
|
wire rs2prd = _T_859 & _T_147; // @[el2_ifu_compress_ctl.scala 64:33]
|
||||||
wire _T_866 = _T_2 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_866 = _T_2 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire uimm9_2 = _T_866 & _T_147; // @[el2_ifu_compress_ctl.scala 87:34]
|
wire uimm9_2 = _T_866 & _T_147; // @[el2_ifu_compress_ctl.scala 65:34]
|
||||||
wire _T_875 = _T_317 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_875 = _T_317 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire ulwimm6_2 = _T_875 & _T_147; // @[el2_ifu_compress_ctl.scala 88:39]
|
wire ulwimm6_2 = _T_875 & _T_147; // @[el2_ifu_compress_ctl.scala 66:39]
|
||||||
wire ulwspimm7_2 = _T_317 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire ulwspimm7_2 = _T_317 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_897 = _T_317 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_897 = _T_317 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_898 = _T_897 & _T_23; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_898 = _T_897 & _T_23; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
|
@ -295,24 +295,24 @@ module el2_ifu_compress_ctl(
|
||||||
wire _T_901 = _T_900 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_901 = _T_900 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire rdeq2 = _T_901 & _T_44; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire rdeq2 = _T_901 & _T_44; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1027 = _T_194 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1027 = _T_194 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire rdeq1 = _T_482 | _T_1027; // @[el2_ifu_compress_ctl.scala 93:42]
|
wire rdeq1 = _T_482 | _T_1027; // @[el2_ifu_compress_ctl.scala 71:42]
|
||||||
wire _T_1050 = io_din[14] & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1050 = io_din[14] & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1051 = rdeq2 | _T_1050; // @[el2_ifu_compress_ctl.scala 94:53]
|
wire _T_1051 = rdeq2 | _T_1050; // @[el2_ifu_compress_ctl.scala 72:53]
|
||||||
wire rs1eq2 = _T_1051 | uimm9_2; // @[el2_ifu_compress_ctl.scala 94:71]
|
wire rs1eq2 = _T_1051 | uimm9_2; // @[el2_ifu_compress_ctl.scala 72:71]
|
||||||
wire _T_1092 = _T_357 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1092 = _T_357 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1093 = _T_1092 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1093 = _T_1092 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1094 = _T_1093 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1094 = _T_1093 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire simm5_0 = _T_1094 | _T_643; // @[el2_ifu_compress_ctl.scala 97:45]
|
wire simm5_0 = _T_1094 | _T_643; // @[el2_ifu_compress_ctl.scala 75:45]
|
||||||
wire _T_1112 = _T_897 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1112 = _T_897 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1121 = _T_897 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1121 = _T_897 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1122 = _T_1112 | _T_1121; // @[el2_ifu_compress_ctl.scala 99:44]
|
wire _T_1122 = _T_1112 | _T_1121; // @[el2_ifu_compress_ctl.scala 77:44]
|
||||||
wire _T_1130 = _T_897 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1130 = _T_897 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1131 = _T_1122 | _T_1130; // @[el2_ifu_compress_ctl.scala 100:29]
|
wire _T_1131 = _T_1122 | _T_1130; // @[el2_ifu_compress_ctl.scala 78:29]
|
||||||
wire _T_1139 = _T_897 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1139 = _T_897 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1140 = _T_1131 | _T_1139; // @[el2_ifu_compress_ctl.scala 101:28]
|
wire _T_1140 = _T_1131 | _T_1139; // @[el2_ifu_compress_ctl.scala 79:28]
|
||||||
wire _T_1148 = _T_897 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1148 = _T_897 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire sluimm17_12 = _T_1140 | _T_1148; // @[el2_ifu_compress_ctl.scala 102:29]
|
wire sluimm17_12 = _T_1140 | _T_1148; // @[el2_ifu_compress_ctl.scala 80:29]
|
||||||
wire uimm5_0 = _T_79 | _T_195; // @[el2_ifu_compress_ctl.scala 104:45]
|
wire uimm5_0 = _T_79 | _T_195; // @[el2_ifu_compress_ctl.scala 82:45]
|
||||||
wire [6:0] l1_6 = {out_6,out_5,out_4,_T_228,out_2,1'h1,1'h1}; // @[Cat.scala 29:58]
|
wire [6:0] l1_6 = {out_6,out_5,out_4,_T_228,out_2,1'h1,1'h1}; // @[Cat.scala 29:58]
|
||||||
wire [4:0] _T_1192 = rdrd ? rdd : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1192 = rdrd ? rdd : 5'h0; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1193 = rdprd ? rdpd : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1193 = rdprd ? rdpd : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
@ -332,7 +332,7 @@ module el2_ifu_compress_ctl(
|
||||||
wire [4:0] _T_1222 = rs2rs2 ? rs2d : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1222 = rs2rs2 ? rs2d : 5'h0; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1223 = rs2prs2 ? rs2pd : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1223 = rs2prs2 ? rs2pd : 5'h0; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1224 = _T_1222 | _T_1223; // @[Mux.scala 27:72]
|
wire [4:0] _T_1224 = _T_1222 | _T_1223; // @[Mux.scala 27:72]
|
||||||
wire [4:0] l1_24 = _T_1219 | _T_1224; // @[el2_ifu_compress_ctl.scala 117:67]
|
wire [4:0] l1_24 = _T_1219 | _T_1224; // @[el2_ifu_compress_ctl.scala 95:67]
|
||||||
wire [14:0] _T_1232 = {out_14,out_13,out_12,l1_11,l1_6}; // @[Cat.scala 29:58]
|
wire [14:0] _T_1232 = {out_14,out_13,out_12,l1_11,l1_6}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] l1 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19,_T_1232}; // @[Cat.scala 29:58]
|
wire [31:0] l1 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19,_T_1232}; // @[Cat.scala 29:58]
|
||||||
wire [5:0] simm5d = {io_din[12],rs2d}; // @[Cat.scala 29:58]
|
wire [5:0] simm5d = {io_din[12],rs2d}; // @[Cat.scala 29:58]
|
||||||
|
@ -365,11 +365,11 @@ module el2_ifu_compress_ctl(
|
||||||
wire [11:0] _T_1328 = _T_1327 | _T_1321; // @[Mux.scala 27:72]
|
wire [11:0] _T_1328 = _T_1327 | _T_1321; // @[Mux.scala 27:72]
|
||||||
wire [11:0] _T_1329 = _T_1328 | _T_1322; // @[Mux.scala 27:72]
|
wire [11:0] _T_1329 = _T_1328 | _T_1322; // @[Mux.scala 27:72]
|
||||||
wire [11:0] _T_1330 = _T_1329 | _T_1323; // @[Mux.scala 27:72]
|
wire [11:0] _T_1330 = _T_1329 | _T_1323; // @[Mux.scala 27:72]
|
||||||
wire [11:0] l2_31 = l1[31:20] | _T_1330; // @[el2_ifu_compress_ctl.scala 135:25]
|
wire [11:0] l2_31 = l1[31:20] | _T_1330; // @[el2_ifu_compress_ctl.scala 112:25]
|
||||||
wire [7:0] _T_1337 = _T_228 ? sjald[19:12] : 8'h0; // @[Mux.scala 27:72]
|
wire [7:0] _T_1337 = _T_228 ? sjald[19:12] : 8'h0; // @[Mux.scala 27:72]
|
||||||
wire [7:0] _T_1338 = sluimm17_12 ? sluimmd[7:0] : 8'h0; // @[Mux.scala 27:72]
|
wire [7:0] _T_1338 = sluimm17_12 ? sluimmd[7:0] : 8'h0; // @[Mux.scala 27:72]
|
||||||
wire [7:0] _T_1339 = _T_1337 | _T_1338; // @[Mux.scala 27:72]
|
wire [7:0] _T_1339 = _T_1337 | _T_1338; // @[Mux.scala 27:72]
|
||||||
wire [7:0] l2_19 = l1[19:12] | _T_1339; // @[el2_ifu_compress_ctl.scala 145:25]
|
wire [7:0] l2_19 = l1[19:12] | _T_1339; // @[el2_ifu_compress_ctl.scala 122:25]
|
||||||
wire [31:0] l2 = {l2_31,l2_19,l1[11:0]}; // @[Cat.scala 29:58]
|
wire [31:0] l2 = {l2_31,l2_19,l1[11:0]}; // @[Cat.scala 29:58]
|
||||||
wire [8:0] sbr8d = {io_din[12],io_din[6],io_din[5],io_din[2],io_din[11],io_din[10],io_din[4],io_din[3],1'h0}; // @[Cat.scala 29:58]
|
wire [8:0] sbr8d = {io_din[12],io_din[6],io_din[5],io_din[2],io_din[11],io_din[10],io_din[4],io_din[3],1'h0}; // @[Cat.scala 29:58]
|
||||||
wire [6:0] uswimm6d = {io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
wire [6:0] uswimm6d = {io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
||||||
|
@ -383,129 +383,129 @@ module el2_ifu_compress_ctl(
|
||||||
wire [6:0] _T_1381 = _T_807 ? _T_1378 : 7'h0; // @[Mux.scala 27:72]
|
wire [6:0] _T_1381 = _T_807 ? _T_1378 : 7'h0; // @[Mux.scala 27:72]
|
||||||
wire [6:0] _T_1382 = _T_1379 | _T_1380; // @[Mux.scala 27:72]
|
wire [6:0] _T_1382 = _T_1379 | _T_1380; // @[Mux.scala 27:72]
|
||||||
wire [6:0] _T_1383 = _T_1382 | _T_1381; // @[Mux.scala 27:72]
|
wire [6:0] _T_1383 = _T_1382 | _T_1381; // @[Mux.scala 27:72]
|
||||||
wire [6:0] l3_31 = l2[31:25] | _T_1383; // @[el2_ifu_compress_ctl.scala 153:25]
|
wire [6:0] l3_31 = l2[31:25] | _T_1383; // @[el2_ifu_compress_ctl.scala 129:25]
|
||||||
wire [12:0] l3_24 = l2[24:12]; // @[el2_ifu_compress_ctl.scala 156:17]
|
wire [12:0] l3_24 = l2[24:12]; // @[el2_ifu_compress_ctl.scala 132:17]
|
||||||
wire [4:0] _T_1389 = {sbr8d[4:1],sbr8d[8]}; // @[Cat.scala 29:58]
|
wire [4:0] _T_1389 = {sbr8d[4:1],sbr8d[8]}; // @[Cat.scala 29:58]
|
||||||
wire [4:0] _T_1394 = _T_234 ? _T_1389 : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1394 = _T_234 ? _T_1389 : 5'h0; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1395 = _T_854 ? uswimm6d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1395 = _T_854 ? uswimm6d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1396 = _T_807 ? uswspimm7d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1396 = _T_807 ? uswspimm7d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1397 = _T_1394 | _T_1395; // @[Mux.scala 27:72]
|
wire [4:0] _T_1397 = _T_1394 | _T_1395; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1398 = _T_1397 | _T_1396; // @[Mux.scala 27:72]
|
wire [4:0] _T_1398 = _T_1397 | _T_1396; // @[Mux.scala 27:72]
|
||||||
wire [4:0] l3_11 = l2[11:7] | _T_1398; // @[el2_ifu_compress_ctl.scala 157:24]
|
wire [4:0] l3_11 = l2[11:7] | _T_1398; // @[el2_ifu_compress_ctl.scala 133:24]
|
||||||
wire [31:0] l3 = {l3_31,l3_24,l3_11,l2[6:0]}; // @[Cat.scala 29:58]
|
wire [31:0] l3 = {l3_31,l3_24,l3_11,l2[6:0]}; // @[Cat.scala 29:58]
|
||||||
wire _T_1409 = _T_4 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1409 = _T_4 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1410 = _T_1409 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1410 = _T_1409 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1411 = _T_1410 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1411 = _T_1410 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1414 = _T_1411 & _T_147; // @[el2_ifu_compress_ctl.scala 162:39]
|
wire _T_1414 = _T_1411 & _T_147; // @[el2_ifu_compress_ctl.scala 138:39]
|
||||||
wire _T_1422 = _T_1409 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1422 = _T_1409 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1423 = _T_1422 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1423 = _T_1422 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1426 = _T_1423 & _T_147; // @[el2_ifu_compress_ctl.scala 162:79]
|
wire _T_1426 = _T_1423 & _T_147; // @[el2_ifu_compress_ctl.scala 138:79]
|
||||||
wire _T_1427 = _T_1414 | _T_1426; // @[el2_ifu_compress_ctl.scala 162:54]
|
wire _T_1427 = _T_1414 | _T_1426; // @[el2_ifu_compress_ctl.scala 138:54]
|
||||||
wire _T_1436 = _T_642 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1436 = _T_642 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1437 = _T_1436 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1437 = _T_1436 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1438 = _T_1427 | _T_1437; // @[el2_ifu_compress_ctl.scala 162:94]
|
wire _T_1438 = _T_1427 | _T_1437; // @[el2_ifu_compress_ctl.scala 138:94]
|
||||||
wire _T_1446 = _T_1409 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1446 = _T_1409 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1447 = _T_1446 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1447 = _T_1446 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1450 = _T_1447 & _T_147; // @[el2_ifu_compress_ctl.scala 163:55]
|
wire _T_1450 = _T_1447 & _T_147; // @[el2_ifu_compress_ctl.scala 139:55]
|
||||||
wire _T_1451 = _T_1438 | _T_1450; // @[el2_ifu_compress_ctl.scala 163:30]
|
wire _T_1451 = _T_1438 | _T_1450; // @[el2_ifu_compress_ctl.scala 139:30]
|
||||||
wire _T_1459 = _T_1409 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1459 = _T_1409 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1460 = _T_1459 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1460 = _T_1459 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1463 = _T_1460 & _T_147; // @[el2_ifu_compress_ctl.scala 163:96]
|
wire _T_1463 = _T_1460 & _T_147; // @[el2_ifu_compress_ctl.scala 139:96]
|
||||||
wire _T_1464 = _T_1451 | _T_1463; // @[el2_ifu_compress_ctl.scala 163:70]
|
wire _T_1464 = _T_1451 | _T_1463; // @[el2_ifu_compress_ctl.scala 139:70]
|
||||||
wire _T_1473 = _T_642 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1473 = _T_642 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1474 = _T_1473 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1474 = _T_1473 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1475 = _T_1464 | _T_1474; // @[el2_ifu_compress_ctl.scala 163:111]
|
wire _T_1475 = _T_1464 | _T_1474; // @[el2_ifu_compress_ctl.scala 139:111]
|
||||||
wire _T_1482 = io_din[15] & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1482 = io_din[15] & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1483 = _T_1482 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1483 = _T_1482 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1484 = _T_1483 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1484 = _T_1483 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1485 = _T_1475 | _T_1484; // @[el2_ifu_compress_ctl.scala 164:29]
|
wire _T_1485 = _T_1475 | _T_1484; // @[el2_ifu_compress_ctl.scala 140:29]
|
||||||
wire _T_1493 = _T_1409 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1493 = _T_1409 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1494 = _T_1493 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1494 = _T_1493 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1497 = _T_1494 & _T_147; // @[el2_ifu_compress_ctl.scala 164:79]
|
wire _T_1497 = _T_1494 & _T_147; // @[el2_ifu_compress_ctl.scala 140:79]
|
||||||
wire _T_1498 = _T_1485 | _T_1497; // @[el2_ifu_compress_ctl.scala 164:54]
|
wire _T_1498 = _T_1485 | _T_1497; // @[el2_ifu_compress_ctl.scala 140:54]
|
||||||
wire _T_1505 = _T_487 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1505 = _T_487 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1506 = _T_1505 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1506 = _T_1505 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1507 = _T_1506 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1507 = _T_1506 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1508 = _T_1498 | _T_1507; // @[el2_ifu_compress_ctl.scala 164:94]
|
wire _T_1508 = _T_1498 | _T_1507; // @[el2_ifu_compress_ctl.scala 140:94]
|
||||||
wire _T_1517 = _T_642 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1517 = _T_642 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1518 = _T_1517 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1518 = _T_1517 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1519 = _T_1508 | _T_1518; // @[el2_ifu_compress_ctl.scala 164:118]
|
wire _T_1519 = _T_1508 | _T_1518; // @[el2_ifu_compress_ctl.scala 140:118]
|
||||||
wire _T_1527 = _T_1409 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1527 = _T_1409 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1528 = _T_1527 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1528 = _T_1527 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1531 = _T_1528 & _T_147; // @[el2_ifu_compress_ctl.scala 165:28]
|
wire _T_1531 = _T_1528 & _T_147; // @[el2_ifu_compress_ctl.scala 141:28]
|
||||||
wire _T_1532 = _T_1519 | _T_1531; // @[el2_ifu_compress_ctl.scala 164:144]
|
wire _T_1532 = _T_1519 | _T_1531; // @[el2_ifu_compress_ctl.scala 140:144]
|
||||||
wire _T_1539 = _T_487 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1539 = _T_487 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1540 = _T_1539 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1540 = _T_1539 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1541 = _T_1540 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1541 = _T_1540 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1542 = _T_1532 | _T_1541; // @[el2_ifu_compress_ctl.scala 165:43]
|
wire _T_1542 = _T_1532 | _T_1541; // @[el2_ifu_compress_ctl.scala 141:43]
|
||||||
wire _T_1551 = _T_642 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1551 = _T_642 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1552 = _T_1551 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1552 = _T_1551 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1553 = _T_1542 | _T_1552; // @[el2_ifu_compress_ctl.scala 165:67]
|
wire _T_1553 = _T_1542 | _T_1552; // @[el2_ifu_compress_ctl.scala 141:67]
|
||||||
wire _T_1561 = _T_1409 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1561 = _T_1409 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1562 = _T_1561 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1562 = _T_1561 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1565 = _T_1562 & _T_147; // @[el2_ifu_compress_ctl.scala 166:28]
|
wire _T_1565 = _T_1562 & _T_147; // @[el2_ifu_compress_ctl.scala 142:28]
|
||||||
wire _T_1566 = _T_1553 | _T_1565; // @[el2_ifu_compress_ctl.scala 165:94]
|
wire _T_1566 = _T_1553 | _T_1565; // @[el2_ifu_compress_ctl.scala 141:94]
|
||||||
wire _T_1574 = io_din[12] & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1574 = io_din[12] & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1575 = _T_1574 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1575 = _T_1574 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1576 = _T_1575 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1576 = _T_1575 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1577 = _T_1576 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1577 = _T_1576 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1578 = _T_1566 | _T_1577; // @[el2_ifu_compress_ctl.scala 166:43]
|
wire _T_1578 = _T_1566 | _T_1577; // @[el2_ifu_compress_ctl.scala 142:43]
|
||||||
wire _T_1587 = _T_642 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1587 = _T_642 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1588 = _T_1587 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1588 = _T_1587 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1589 = _T_1578 | _T_1588; // @[el2_ifu_compress_ctl.scala 166:71]
|
wire _T_1589 = _T_1578 | _T_1588; // @[el2_ifu_compress_ctl.scala 142:71]
|
||||||
wire _T_1597 = _T_1409 & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1597 = _T_1409 & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1598 = _T_1597 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1598 = _T_1597 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1601 = _T_1598 & _T_147; // @[el2_ifu_compress_ctl.scala 167:28]
|
wire _T_1601 = _T_1598 & _T_147; // @[el2_ifu_compress_ctl.scala 143:28]
|
||||||
wire _T_1602 = _T_1589 | _T_1601; // @[el2_ifu_compress_ctl.scala 166:97]
|
wire _T_1602 = _T_1589 | _T_1601; // @[el2_ifu_compress_ctl.scala 142:97]
|
||||||
wire _T_1608 = io_din[13] & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1608 = io_din[13] & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1609 = _T_1608 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1609 = _T_1608 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1610 = _T_1609 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1610 = _T_1609 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1611 = _T_1602 | _T_1610; // @[el2_ifu_compress_ctl.scala 167:43]
|
wire _T_1611 = _T_1602 | _T_1610; // @[el2_ifu_compress_ctl.scala 143:43]
|
||||||
wire _T_1620 = _T_642 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1620 = _T_642 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1621 = _T_1620 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1621 = _T_1620 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1622 = _T_1611 | _T_1621; // @[el2_ifu_compress_ctl.scala 167:67]
|
wire _T_1622 = _T_1611 | _T_1621; // @[el2_ifu_compress_ctl.scala 143:67]
|
||||||
wire _T_1630 = _T_1409 & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1630 = _T_1409 & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1631 = _T_1630 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1631 = _T_1630 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1634 = _T_1631 & _T_147; // @[el2_ifu_compress_ctl.scala 168:28]
|
wire _T_1634 = _T_1631 & _T_147; // @[el2_ifu_compress_ctl.scala 144:28]
|
||||||
wire _T_1635 = _T_1622 | _T_1634; // @[el2_ifu_compress_ctl.scala 167:93]
|
wire _T_1635 = _T_1622 | _T_1634; // @[el2_ifu_compress_ctl.scala 143:93]
|
||||||
wire _T_1641 = io_din[13] & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1641 = io_din[13] & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1642 = _T_1641 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1642 = _T_1641 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1643 = _T_1642 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1643 = _T_1642 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1644 = _T_1635 | _T_1643; // @[el2_ifu_compress_ctl.scala 168:43]
|
wire _T_1644 = _T_1635 | _T_1643; // @[el2_ifu_compress_ctl.scala 144:43]
|
||||||
wire _T_1652 = _T_1409 & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1652 = _T_1409 & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1653 = _T_1652 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1653 = _T_1652 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1656 = _T_1653 & _T_147; // @[el2_ifu_compress_ctl.scala 168:91]
|
wire _T_1656 = _T_1653 & _T_147; // @[el2_ifu_compress_ctl.scala 144:91]
|
||||||
wire _T_1657 = _T_1644 | _T_1656; // @[el2_ifu_compress_ctl.scala 168:66]
|
wire _T_1657 = _T_1644 | _T_1656; // @[el2_ifu_compress_ctl.scala 144:66]
|
||||||
wire _T_1666 = _T_642 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1666 = _T_642 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1667 = _T_1666 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1667 = _T_1666 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1668 = _T_1657 | _T_1667; // @[el2_ifu_compress_ctl.scala 168:106]
|
wire _T_1668 = _T_1657 | _T_1667; // @[el2_ifu_compress_ctl.scala 144:106]
|
||||||
wire _T_1674 = io_din[13] & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1674 = io_din[13] & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1675 = _T_1674 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1675 = _T_1674 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1676 = _T_1675 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1676 = _T_1675 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1677 = _T_1668 | _T_1676; // @[el2_ifu_compress_ctl.scala 169:29]
|
wire _T_1677 = _T_1668 | _T_1676; // @[el2_ifu_compress_ctl.scala 145:29]
|
||||||
wire _T_1683 = io_din[13] & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1683 = io_din[13] & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1684 = _T_1683 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1684 = _T_1683 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1685 = _T_1684 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1685 = _T_1684 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1686 = _T_1677 | _T_1685; // @[el2_ifu_compress_ctl.scala 169:52]
|
wire _T_1686 = _T_1677 | _T_1685; // @[el2_ifu_compress_ctl.scala 145:52]
|
||||||
wire _T_1692 = io_din[14] & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1692 = io_din[14] & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1693 = _T_1692 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1693 = _T_1692 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1694 = _T_1686 | _T_1693; // @[el2_ifu_compress_ctl.scala 169:75]
|
wire _T_1694 = _T_1686 | _T_1693; // @[el2_ifu_compress_ctl.scala 145:75]
|
||||||
wire _T_1703 = _T_703 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1703 = _T_703 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1704 = _T_1703 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1704 = _T_1703 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1705 = _T_1694 | _T_1704; // @[el2_ifu_compress_ctl.scala 169:98]
|
wire _T_1705 = _T_1694 | _T_1704; // @[el2_ifu_compress_ctl.scala 145:98]
|
||||||
wire _T_1712 = _T_820 & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1712 = _T_820 & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1713 = _T_1712 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1713 = _T_1712 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1716 = _T_1713 & _T_147; // @[el2_ifu_compress_ctl.scala 170:54]
|
wire _T_1716 = _T_1713 & _T_147; // @[el2_ifu_compress_ctl.scala 146:54]
|
||||||
wire _T_1717 = _T_1705 | _T_1716; // @[el2_ifu_compress_ctl.scala 170:29]
|
wire _T_1717 = _T_1705 | _T_1716; // @[el2_ifu_compress_ctl.scala 146:29]
|
||||||
wire _T_1726 = _T_642 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1726 = _T_642 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1727 = _T_1726 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1727 = _T_1726 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1730 = _T_1727 & _T_147; // @[el2_ifu_compress_ctl.scala 170:96]
|
wire _T_1730 = _T_1727 & _T_147; // @[el2_ifu_compress_ctl.scala 146:96]
|
||||||
wire _T_1731 = _T_1717 | _T_1730; // @[el2_ifu_compress_ctl.scala 170:69]
|
wire _T_1731 = _T_1717 | _T_1730; // @[el2_ifu_compress_ctl.scala 146:69]
|
||||||
wire _T_1740 = _T_642 & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1740 = _T_642 & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1741 = _T_1740 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
wire _T_1741 = _T_1740 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
|
||||||
wire _T_1742 = _T_1731 | _T_1741; // @[el2_ifu_compress_ctl.scala 170:111]
|
wire _T_1742 = _T_1731 | _T_1741; // @[el2_ifu_compress_ctl.scala 146:111]
|
||||||
wire _T_1749 = _T_1692 & _T_147; // @[el2_ifu_compress_ctl.scala 171:50]
|
wire _T_1749 = _T_1692 & _T_147; // @[el2_ifu_compress_ctl.scala 147:50]
|
||||||
wire legal = _T_1742 | _T_1749; // @[el2_ifu_compress_ctl.scala 171:30]
|
wire legal = _T_1742 | _T_1749; // @[el2_ifu_compress_ctl.scala 147:30]
|
||||||
wire [31:0] _T_1751 = legal ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_1751 = legal ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
assign io_dout = l3 & _T_1751; // @[el2_ifu_compress_ctl.scala 173:10]
|
assign io_dout = l3 & _T_1751; // @[el2_ifu_compress_ctl.scala 149:10]
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
@ -1,40 +1,4 @@
|
||||||
[
|
[
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
|
||||||
"sources":[
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_next_addr_bf",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_btb_addr_bf",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_last_addr_bf",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_next_addr_bf",
|
|
||||||
"sources":[
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_btb_addr_bf",
|
|
||||||
"sources":[
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
{
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_pmu_fetch_stall",
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_pmu_fetch_stall",
|
||||||
|
@ -46,6 +10,33 @@
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume1"
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume1"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
||||||
|
"sources":[
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_iccm_access_bf",
|
||||||
|
"sources":[
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
||||||
|
]
|
||||||
|
},
|
||||||
{
|
{
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf",
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf",
|
||||||
|
@ -61,15 +52,6 @@
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f"
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_last_addr_bf",
|
|
||||||
"sources":[
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
{
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_uncacheable_bf",
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_uncacheable_bf",
|
||||||
|
@ -77,32 +59,23 @@
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_dec_tlu_mrac_ff",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_dec_tlu_mrac_ff",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_next_addr_bf",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_btb_addr_bf",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_last_addr_bf",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_iccm_access_bf",
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_mb_empty_mod",
|
||||||
"sources":[
|
"sources":[
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_ic_mb_empty",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_next_addr_bf",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_btb_addr_bf",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_last_addr_bf",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_dma_active",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f"
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
|
|
|
@ -3,10 +3,10 @@ circuit el2_ifu_ifc_ctrl :
|
||||||
module el2_ifu_ifc_ctrl :
|
module el2_ifu_ifc_ctrl :
|
||||||
input clock : Clock
|
input clock : Clock
|
||||||
input reset : UInt<1>
|
input reset : UInt<1>
|
||||||
output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, sel_last_addr_bf : UInt<1>, sel_btb_addr_bf : UInt<1>, sel_next_addr_bf : UInt<1>}
|
output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, mb_empty_mod : UInt<1>}
|
||||||
|
|
||||||
io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 42:30]
|
io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 41:30]
|
||||||
io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 43:24]
|
io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 42:24]
|
||||||
wire fetch_addr_bf : UInt<32>
|
wire fetch_addr_bf : UInt<32>
|
||||||
fetch_addr_bf <= UInt<1>("h00")
|
fetch_addr_bf <= UInt<1>("h00")
|
||||||
wire fetch_addr_next : UInt<32>
|
wire fetch_addr_next : UInt<32>
|
||||||
|
@ -47,206 +47,207 @@ circuit el2_ifu_ifc_ctrl :
|
||||||
state <= UInt<1>("h00")
|
state <= UInt<1>("h00")
|
||||||
wire dma_iccm_stall_any_f : UInt<1>
|
wire dma_iccm_stall_any_f : UInt<1>
|
||||||
dma_iccm_stall_any_f <= UInt<1>("h00")
|
dma_iccm_stall_any_f <= UInt<1>("h00")
|
||||||
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 71:36]
|
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 66:36]
|
||||||
reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 72:34]
|
reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 67:34]
|
||||||
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 72:34]
|
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 67:34]
|
||||||
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctrl.scala 72:24]
|
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctrl.scala 67:24]
|
||||||
reg _T_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 74:20]
|
reg _T_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 69:20]
|
||||||
_T_1 <= miss_f @[el2_ifu_ifc_ctrl.scala 74:20]
|
_T_1 <= miss_f @[el2_ifu_ifc_ctrl.scala 69:20]
|
||||||
miss_a <= _T_1 @[el2_ifu_ifc_ctrl.scala 74:10]
|
miss_a <= _T_1 @[el2_ifu_ifc_ctrl.scala 69:10]
|
||||||
node _T_2 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 76:26]
|
node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 71:26]
|
||||||
node _T_3 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 76:49]
|
node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 71:49]
|
||||||
node _T_4 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 76:71]
|
node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 71:71]
|
||||||
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctrl.scala 76:69]
|
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctrl.scala 71:69]
|
||||||
node _T_6 = and(_T_2, _T_5) @[el2_ifu_ifc_ctrl.scala 76:46]
|
node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctrl.scala 71:46]
|
||||||
io.sel_last_addr_bf <= _T_6 @[el2_ifu_ifc_ctrl.scala 76:23]
|
node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 72:26]
|
||||||
node _T_7 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 77:26]
|
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 72:46]
|
||||||
node _T_8 = and(_T_7, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 77:46]
|
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 72:67]
|
||||||
node _T_9 = and(_T_8, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 77:67]
|
node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 72:92]
|
||||||
node _T_10 = and(_T_9, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 77:91]
|
node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 73:26]
|
||||||
io.sel_btb_addr_bf <= _T_10 @[el2_ifu_ifc_ctrl.scala 77:23]
|
node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 73:46]
|
||||||
node _T_11 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 78:26]
|
node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 73:69]
|
||||||
node _T_12 = and(_T_11, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 78:46]
|
node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctrl.scala 73:67]
|
||||||
node _T_13 = not(io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 78:69]
|
node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 73:92]
|
||||||
node _T_14 = and(_T_12, _T_13) @[el2_ifu_ifc_ctrl.scala 78:67]
|
node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 76:56]
|
||||||
node _T_15 = and(_T_14, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 78:92]
|
node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 77:46]
|
||||||
io.sel_next_addr_bf <= _T_15 @[el2_ifu_ifc_ctrl.scala 78:23]
|
node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 78:45]
|
||||||
node _T_16 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 81:56]
|
node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 79:46]
|
||||||
node _T_17 = bits(io.sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 82:49]
|
node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
node _T_18 = bits(io.sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 83:48]
|
node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
node _T_19 = bits(io.sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 84:49]
|
node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
node _T_20 = mux(_T_16, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_20 = mux(_T_16, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
node _T_21 = mux(_T_17, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
|
||||||
node _T_22 = mux(_T_18, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
|
||||||
node _T_23 = mux(_T_19, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
|
||||||
node _T_24 = or(_T_20, _T_21) @[Mux.scala 27:72]
|
wire _T_24 : UInt<32> @[Mux.scala 27:72]
|
||||||
node _T_25 = or(_T_24, _T_22) @[Mux.scala 27:72]
|
_T_24 <= _T_23 @[Mux.scala 27:72]
|
||||||
node _T_26 = or(_T_25, _T_23) @[Mux.scala 27:72]
|
io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctrl.scala 76:24]
|
||||||
wire _T_27 : UInt<32> @[Mux.scala 27:72]
|
line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 83:13]
|
||||||
_T_27 <= _T_26 @[Mux.scala 27:72]
|
node _T_25 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 84:47]
|
||||||
io.ifc_fetch_addr_bf <= _T_27 @[el2_ifu_ifc_ctrl.scala 81:24]
|
node _T_26 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 84:75]
|
||||||
line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 88:13]
|
node fetch_addr_next_1 = mux(_T_25, UInt<1>("h00"), _T_26) @[el2_ifu_ifc_ctrl.scala 84:30]
|
||||||
node _T_28 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctrl.scala 90:45]
|
node _T_27 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctrl.scala 85:45]
|
||||||
node _T_29 = add(_T_28, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 90:51]
|
node _T_28 = add(_T_27, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 85:51]
|
||||||
node _T_30 = tail(_T_29, 1) @[el2_ifu_ifc_ctrl.scala 90:51]
|
node _T_29 = tail(_T_28, 1) @[el2_ifu_ifc_ctrl.scala 85:51]
|
||||||
node _T_31 = cat(_T_30, UInt<1>("h00")) @[Cat.scala 29:58]
|
node _T_30 = cat(_T_29, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||||
fetch_addr_next <= _T_31 @[el2_ifu_ifc_ctrl.scala 90:19]
|
fetch_addr_next <= _T_30 @[el2_ifu_ifc_ctrl.scala 85:19]
|
||||||
node _T_32 = not(idle) @[el2_ifu_ifc_ctrl.scala 93:30]
|
node _T_31 = not(idle) @[el2_ifu_ifc_ctrl.scala 88:30]
|
||||||
io.ifc_fetch_req_bf_raw <= _T_32 @[el2_ifu_ifc_ctrl.scala 93:27]
|
io.ifc_fetch_req_bf_raw <= _T_31 @[el2_ifu_ifc_ctrl.scala 88:27]
|
||||||
node _T_33 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 95:91]
|
node _T_32 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 90:91]
|
||||||
node _T_34 = not(_T_33) @[el2_ifu_ifc_ctrl.scala 95:70]
|
node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 90:70]
|
||||||
node _T_35 = and(fb_full_f_ns, _T_34) @[el2_ifu_ifc_ctrl.scala 95:68]
|
node _T_34 = and(fb_full_f_ns, _T_33) @[el2_ifu_ifc_ctrl.scala 90:68]
|
||||||
node _T_36 = not(_T_35) @[el2_ifu_ifc_ctrl.scala 95:53]
|
node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 90:53]
|
||||||
node _T_37 = and(io.ifc_fetch_req_bf_raw, _T_36) @[el2_ifu_ifc_ctrl.scala 95:51]
|
node _T_36 = and(io.ifc_fetch_req_bf_raw, _T_35) @[el2_ifu_ifc_ctrl.scala 90:51]
|
||||||
node _T_38 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 96:5]
|
node _T_37 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 91:5]
|
||||||
node _T_39 = and(_T_37, _T_38) @[el2_ifu_ifc_ctrl.scala 95:114]
|
node _T_38 = and(_T_36, _T_37) @[el2_ifu_ifc_ctrl.scala 90:114]
|
||||||
node _T_40 = not(io.ic_write_stall) @[el2_ifu_ifc_ctrl.scala 96:18]
|
node _T_39 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 91:18]
|
||||||
node _T_41 = and(_T_39, _T_40) @[el2_ifu_ifc_ctrl.scala 96:16]
|
node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctrl.scala 91:16]
|
||||||
node _T_42 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 96:39]
|
node _T_41 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 91:39]
|
||||||
node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctrl.scala 96:37]
|
node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctrl.scala 91:37]
|
||||||
io.ifc_fetch_req_bf <= _T_43 @[el2_ifu_ifc_ctrl.scala 95:23]
|
io.ifc_fetch_req_bf <= _T_42 @[el2_ifu_ifc_ctrl.scala 90:23]
|
||||||
node _T_44 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 98:37]
|
node _T_43 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 93:37]
|
||||||
fetch_bf_en <= _T_44 @[el2_ifu_ifc_ctrl.scala 98:15]
|
fetch_bf_en <= _T_43 @[el2_ifu_ifc_ctrl.scala 93:15]
|
||||||
node _T_45 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 100:34]
|
node _T_44 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 95:34]
|
||||||
node _T_46 = and(io.ifc_fetch_req_f, _T_45) @[el2_ifu_ifc_ctrl.scala 100:32]
|
node _T_45 = and(io.ifc_fetch_req_f, _T_44) @[el2_ifu_ifc_ctrl.scala 95:32]
|
||||||
node _T_47 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 100:49]
|
node _T_46 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 95:49]
|
||||||
node _T_48 = and(_T_46, _T_47) @[el2_ifu_ifc_ctrl.scala 100:47]
|
node _T_47 = and(_T_45, _T_46) @[el2_ifu_ifc_ctrl.scala 95:47]
|
||||||
miss_f <= _T_48 @[el2_ifu_ifc_ctrl.scala 100:10]
|
miss_f <= _T_47 @[el2_ifu_ifc_ctrl.scala 95:10]
|
||||||
node _T_49 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 102:39]
|
node _T_48 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 97:39]
|
||||||
node _T_50 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 102:63]
|
node _T_49 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 97:63]
|
||||||
node _T_51 = and(_T_49, _T_50) @[el2_ifu_ifc_ctrl.scala 102:61]
|
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctrl.scala 97:61]
|
||||||
node _T_52 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 102:76]
|
node _T_51 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 97:76]
|
||||||
node _T_53 = and(_T_51, _T_52) @[el2_ifu_ifc_ctrl.scala 102:74]
|
node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctrl.scala 97:74]
|
||||||
node _T_54 = not(miss_a) @[el2_ifu_ifc_ctrl.scala 102:86]
|
node _T_53 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 97:86]
|
||||||
node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctrl.scala 102:84]
|
node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctrl.scala 97:84]
|
||||||
mb_empty_mod <= _T_55 @[el2_ifu_ifc_ctrl.scala 102:16]
|
mb_empty_mod <= _T_54 @[el2_ifu_ifc_ctrl.scala 97:16]
|
||||||
node _T_56 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 104:35]
|
io.mb_empty_mod <= mb_empty_mod @[el2_ifu_ifc_ctrl.scala 98:19]
|
||||||
goto_idle <= _T_56 @[el2_ifu_ifc_ctrl.scala 104:13]
|
node _T_55 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 99:35]
|
||||||
node _T_57 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 106:38]
|
goto_idle <= _T_55 @[el2_ifu_ifc_ctrl.scala 99:13]
|
||||||
node _T_58 = and(io.exu_flush_final, _T_57) @[el2_ifu_ifc_ctrl.scala 106:36]
|
node _T_56 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 101:38]
|
||||||
node _T_59 = and(_T_58, idle) @[el2_ifu_ifc_ctrl.scala 106:67]
|
node _T_57 = and(io.exu_flush_final, _T_56) @[el2_ifu_ifc_ctrl.scala 101:36]
|
||||||
leave_idle <= _T_59 @[el2_ifu_ifc_ctrl.scala 106:14]
|
node _T_58 = and(_T_57, idle) @[el2_ifu_ifc_ctrl.scala 101:67]
|
||||||
node _T_60 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 108:29]
|
leave_idle <= _T_58 @[el2_ifu_ifc_ctrl.scala 101:14]
|
||||||
node _T_61 = not(_T_60) @[el2_ifu_ifc_ctrl.scala 108:23]
|
node _T_59 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 103:29]
|
||||||
node _T_62 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 108:40]
|
node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 103:23]
|
||||||
node _T_63 = and(_T_61, _T_62) @[el2_ifu_ifc_ctrl.scala 108:33]
|
node _T_61 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 103:40]
|
||||||
node _T_64 = and(_T_63, miss_f) @[el2_ifu_ifc_ctrl.scala 108:44]
|
node _T_62 = and(_T_60, _T_61) @[el2_ifu_ifc_ctrl.scala 103:33]
|
||||||
node _T_65 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 108:55]
|
node _T_63 = and(_T_62, miss_f) @[el2_ifu_ifc_ctrl.scala 103:44]
|
||||||
node _T_66 = and(_T_64, _T_65) @[el2_ifu_ifc_ctrl.scala 108:53]
|
node _T_64 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 103:55]
|
||||||
node _T_67 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 109:11]
|
node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctrl.scala 103:53]
|
||||||
node _T_68 = not(mb_empty_mod) @[el2_ifu_ifc_ctrl.scala 109:17]
|
node _T_66 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 104:11]
|
||||||
node _T_69 = and(_T_67, _T_68) @[el2_ifu_ifc_ctrl.scala 109:15]
|
node _T_67 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 104:17]
|
||||||
node _T_70 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 109:33]
|
node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctrl.scala 104:15]
|
||||||
node _T_71 = and(_T_69, _T_70) @[el2_ifu_ifc_ctrl.scala 109:31]
|
node _T_69 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 104:33]
|
||||||
node next_state_1 = or(_T_66, _T_71) @[el2_ifu_ifc_ctrl.scala 108:67]
|
node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctrl.scala 104:31]
|
||||||
node _T_72 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 111:23]
|
node next_state_1 = or(_T_65, _T_70) @[el2_ifu_ifc_ctrl.scala 103:67]
|
||||||
node _T_73 = and(_T_72, leave_idle) @[el2_ifu_ifc_ctrl.scala 111:34]
|
node _T_71 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 106:23]
|
||||||
node _T_74 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 111:56]
|
node _T_72 = and(_T_71, leave_idle) @[el2_ifu_ifc_ctrl.scala 106:34]
|
||||||
node _T_75 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 111:62]
|
node _T_73 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 106:56]
|
||||||
node _T_76 = and(_T_74, _T_75) @[el2_ifu_ifc_ctrl.scala 111:60]
|
node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 106:62]
|
||||||
node next_state_0 = or(_T_73, _T_76) @[el2_ifu_ifc_ctrl.scala 111:48]
|
node _T_75 = and(_T_73, _T_74) @[el2_ifu_ifc_ctrl.scala 106:60]
|
||||||
node _T_77 = cat(next_state_0, next_state_0) @[Cat.scala 29:58]
|
node next_state_0 = or(_T_72, _T_75) @[el2_ifu_ifc_ctrl.scala 106:48]
|
||||||
reg _T_78 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 113:19]
|
node _T_76 = cat(next_state_0, next_state_0) @[Cat.scala 29:58]
|
||||||
_T_78 <= _T_77 @[el2_ifu_ifc_ctrl.scala 113:19]
|
reg _T_77 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 108:19]
|
||||||
state <= _T_78 @[el2_ifu_ifc_ctrl.scala 113:9]
|
_T_77 <= _T_76 @[el2_ifu_ifc_ctrl.scala 108:19]
|
||||||
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 118:12]
|
state <= _T_77 @[el2_ifu_ifc_ctrl.scala 108:9]
|
||||||
node _T_79 = not(io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 120:38]
|
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 110:12]
|
||||||
node _T_80 = and(io.ifu_fb_consume1, _T_79) @[el2_ifu_ifc_ctrl.scala 120:36]
|
node _T_78 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 112:38]
|
||||||
node _T_81 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 120:61]
|
node _T_79 = and(io.ifu_fb_consume1, _T_78) @[el2_ifu_ifc_ctrl.scala 112:36]
|
||||||
node _T_82 = or(_T_81, miss_f) @[el2_ifu_ifc_ctrl.scala 120:81]
|
node _T_80 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 112:61]
|
||||||
node _T_83 = and(_T_80, _T_82) @[el2_ifu_ifc_ctrl.scala 120:58]
|
node _T_81 = or(_T_80, miss_f) @[el2_ifu_ifc_ctrl.scala 112:81]
|
||||||
node _T_84 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 121:25]
|
node _T_82 = and(_T_79, _T_81) @[el2_ifu_ifc_ctrl.scala 112:58]
|
||||||
node _T_85 = or(_T_83, _T_84) @[el2_ifu_ifc_ctrl.scala 120:92]
|
node _T_83 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 113:25]
|
||||||
fb_right <= _T_85 @[el2_ifu_ifc_ctrl.scala 120:12]
|
node _T_84 = or(_T_82, _T_83) @[el2_ifu_ifc_ctrl.scala 112:92]
|
||||||
node _T_86 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 123:39]
|
fb_right <= _T_84 @[el2_ifu_ifc_ctrl.scala 112:12]
|
||||||
node _T_87 = or(_T_86, miss_f) @[el2_ifu_ifc_ctrl.scala 123:59]
|
node _T_85 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 115:39]
|
||||||
node _T_88 = and(io.ifu_fb_consume2, _T_87) @[el2_ifu_ifc_ctrl.scala 123:36]
|
node _T_86 = or(_T_85, miss_f) @[el2_ifu_ifc_ctrl.scala 115:59]
|
||||||
fb_right2 <= _T_88 @[el2_ifu_ifc_ctrl.scala 123:13]
|
node _T_87 = and(io.ifu_fb_consume2, _T_86) @[el2_ifu_ifc_ctrl.scala 115:36]
|
||||||
node _T_89 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 124:56]
|
fb_right2 <= _T_87 @[el2_ifu_ifc_ctrl.scala 115:13]
|
||||||
node _T_90 = not(_T_89) @[el2_ifu_ifc_ctrl.scala 124:35]
|
node _T_88 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 116:56]
|
||||||
node _T_91 = and(io.ifc_fetch_req_f, _T_90) @[el2_ifu_ifc_ctrl.scala 124:33]
|
node _T_89 = eq(_T_88, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 116:35]
|
||||||
node _T_92 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 124:80]
|
node _T_90 = and(io.ifc_fetch_req_f, _T_89) @[el2_ifu_ifc_ctrl.scala 116:33]
|
||||||
node _T_93 = and(_T_91, _T_92) @[el2_ifu_ifc_ctrl.scala 124:78]
|
node _T_91 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 116:80]
|
||||||
fb_left <= _T_93 @[el2_ifu_ifc_ctrl.scala 124:11]
|
node _T_92 = and(_T_90, _T_91) @[el2_ifu_ifc_ctrl.scala 116:78]
|
||||||
node _T_94 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctrl.scala 126:37]
|
fb_left <= _T_92 @[el2_ifu_ifc_ctrl.scala 116:11]
|
||||||
node _T_95 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 127:6]
|
node _T_93 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctrl.scala 118:37]
|
||||||
node _T_96 = and(_T_95, fb_right) @[el2_ifu_ifc_ctrl.scala 127:16]
|
node _T_94 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 119:6]
|
||||||
node _T_97 = bits(_T_96, 0, 0) @[el2_ifu_ifc_ctrl.scala 127:28]
|
node _T_95 = and(_T_94, fb_right) @[el2_ifu_ifc_ctrl.scala 119:16]
|
||||||
node _T_98 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 127:62]
|
node _T_96 = bits(_T_95, 0, 0) @[el2_ifu_ifc_ctrl.scala 119:28]
|
||||||
node _T_99 = cat(UInt<1>("h00"), _T_98) @[Cat.scala 29:58]
|
node _T_97 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 119:62]
|
||||||
node _T_100 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 128:6]
|
node _T_98 = cat(UInt<1>("h00"), _T_97) @[Cat.scala 29:58]
|
||||||
node _T_101 = and(_T_100, fb_right2) @[el2_ifu_ifc_ctrl.scala 128:16]
|
node _T_99 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 120:6]
|
||||||
node _T_102 = bits(_T_101, 0, 0) @[el2_ifu_ifc_ctrl.scala 128:29]
|
node _T_100 = and(_T_99, fb_right2) @[el2_ifu_ifc_ctrl.scala 120:16]
|
||||||
node _T_103 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 128:63]
|
node _T_101 = bits(_T_100, 0, 0) @[el2_ifu_ifc_ctrl.scala 120:29]
|
||||||
node _T_104 = cat(UInt<2>("h00"), _T_103) @[Cat.scala 29:58]
|
node _T_102 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 120:63]
|
||||||
node _T_105 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 129:6]
|
node _T_103 = cat(UInt<2>("h00"), _T_102) @[Cat.scala 29:58]
|
||||||
node _T_106 = and(_T_105, fb_left) @[el2_ifu_ifc_ctrl.scala 129:16]
|
node _T_104 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 121:6]
|
||||||
node _T_107 = bits(_T_106, 0, 0) @[el2_ifu_ifc_ctrl.scala 129:27]
|
node _T_105 = and(_T_104, fb_left) @[el2_ifu_ifc_ctrl.scala 121:16]
|
||||||
node _T_108 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 129:51]
|
node _T_106 = bits(_T_105, 0, 0) @[el2_ifu_ifc_ctrl.scala 121:27]
|
||||||
node _T_109 = cat(_T_108, UInt<1>("h00")) @[Cat.scala 29:58]
|
node _T_107 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 121:51]
|
||||||
node _T_110 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 130:6]
|
node _T_108 = cat(_T_107, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||||
node _T_111 = not(fb_right) @[el2_ifu_ifc_ctrl.scala 130:18]
|
node _T_109 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 122:6]
|
||||||
node _T_112 = and(_T_110, _T_111) @[el2_ifu_ifc_ctrl.scala 130:16]
|
node _T_110 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 122:18]
|
||||||
node _T_113 = not(fb_right2) @[el2_ifu_ifc_ctrl.scala 130:30]
|
node _T_111 = and(_T_109, _T_110) @[el2_ifu_ifc_ctrl.scala 122:16]
|
||||||
node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctrl.scala 130:28]
|
node _T_112 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 122:30]
|
||||||
node _T_115 = not(fb_left) @[el2_ifu_ifc_ctrl.scala 130:43]
|
node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctrl.scala 122:28]
|
||||||
node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctrl.scala 130:41]
|
node _T_114 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 122:43]
|
||||||
node _T_117 = bits(_T_116, 0, 0) @[el2_ifu_ifc_ctrl.scala 130:53]
|
node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctrl.scala 122:41]
|
||||||
node _T_118 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 130:73]
|
node _T_116 = bits(_T_115, 0, 0) @[el2_ifu_ifc_ctrl.scala 122:53]
|
||||||
node _T_119 = mux(_T_94, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_117 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 122:73]
|
||||||
node _T_120 = mux(_T_97, _T_99, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_118 = mux(_T_93, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
node _T_121 = mux(_T_102, _T_104, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_119 = mux(_T_96, _T_98, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
node _T_122 = mux(_T_107, _T_109, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_120 = mux(_T_101, _T_103, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
node _T_123 = mux(_T_117, _T_118, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_121 = mux(_T_106, _T_108, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
node _T_124 = or(_T_119, _T_120) @[Mux.scala 27:72]
|
node _T_122 = mux(_T_116, _T_117, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_123 = or(_T_118, _T_119) @[Mux.scala 27:72]
|
||||||
|
node _T_124 = or(_T_123, _T_120) @[Mux.scala 27:72]
|
||||||
node _T_125 = or(_T_124, _T_121) @[Mux.scala 27:72]
|
node _T_125 = or(_T_124, _T_121) @[Mux.scala 27:72]
|
||||||
node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72]
|
node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72]
|
||||||
node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72]
|
wire _T_127 : UInt<4> @[Mux.scala 27:72]
|
||||||
wire _T_128 : UInt<4> @[Mux.scala 27:72]
|
_T_127 <= _T_126 @[Mux.scala 27:72]
|
||||||
_T_128 <= _T_127 @[Mux.scala 27:72]
|
fb_write_ns <= _T_127 @[el2_ifu_ifc_ctrl.scala 118:15]
|
||||||
fb_write_ns <= _T_128 @[el2_ifu_ifc_ctrl.scala 126:15]
|
node _T_128 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 125:38]
|
||||||
node _T_129 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 133:38]
|
reg _T_129 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 125:26]
|
||||||
reg _T_130 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 133:26]
|
_T_129 <= _T_128 @[el2_ifu_ifc_ctrl.scala 125:26]
|
||||||
_T_130 <= _T_129 @[el2_ifu_ifc_ctrl.scala 133:26]
|
fb_full_f_ns <= _T_129 @[el2_ifu_ifc_ctrl.scala 125:16]
|
||||||
fb_full_f_ns <= _T_130 @[el2_ifu_ifc_ctrl.scala 133:16]
|
node _T_130 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 127:17]
|
||||||
node _T_131 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 135:17]
|
idle <= _T_130 @[el2_ifu_ifc_ctrl.scala 127:8]
|
||||||
idle <= _T_131 @[el2_ifu_ifc_ctrl.scala 135:8]
|
node _T_131 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 128:16]
|
||||||
node _T_132 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 136:16]
|
wfm <= _T_131 @[el2_ifu_ifc_ctrl.scala 128:7]
|
||||||
wfm <= _T_132 @[el2_ifu_ifc_ctrl.scala 136:7]
|
node _T_132 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 130:30]
|
||||||
node _T_133 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 138:30]
|
fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctrl.scala 130:16]
|
||||||
fb_full_f_ns <= _T_133 @[el2_ifu_ifc_ctrl.scala 138:16]
|
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 131:26]
|
||||||
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 139:26]
|
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 131:26]
|
||||||
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 139:26]
|
reg _T_133 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 132:24]
|
||||||
reg _T_134 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 140:24]
|
_T_133 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 132:24]
|
||||||
_T_134 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 140:24]
|
fb_write_f <= _T_133 @[el2_ifu_ifc_ctrl.scala 132:14]
|
||||||
fb_write_f <= _T_134 @[el2_ifu_ifc_ctrl.scala 140:14]
|
node _T_134 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 135:40]
|
||||||
node _T_135 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 143:26]
|
node _T_135 = or(_T_134, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 135:61]
|
||||||
node _T_136 = or(_T_135, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 143:47]
|
node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 135:19]
|
||||||
node _T_137 = not(_T_136) @[el2_ifu_ifc_ctrl.scala 143:5]
|
node _T_137 = and(fb_full_f, _T_136) @[el2_ifu_ifc_ctrl.scala 135:17]
|
||||||
node _T_138 = and(fb_full_f, _T_137) @[el2_ifu_ifc_ctrl.scala 142:75]
|
node _T_138 = or(_T_137, dma_stall) @[el2_ifu_ifc_ctrl.scala 135:84]
|
||||||
node _T_139 = or(_T_138, dma_stall) @[el2_ifu_ifc_ctrl.scala 143:70]
|
node _T_139 = and(io.ifc_fetch_req_bf_raw, _T_138) @[el2_ifu_ifc_ctrl.scala 134:60]
|
||||||
node _T_140 = and(io.ifc_fetch_req_bf_raw, _T_139) @[el2_ifu_ifc_ctrl.scala 142:60]
|
node _T_140 = or(wfm, _T_139) @[el2_ifu_ifc_ctrl.scala 134:33]
|
||||||
node _T_141 = or(wfm, _T_140) @[el2_ifu_ifc_ctrl.scala 142:33]
|
io.ifu_pmu_fetch_stall <= _T_140 @[el2_ifu_ifc_ctrl.scala 134:26]
|
||||||
io.ifu_pmu_fetch_stall <= _T_141 @[el2_ifu_ifc_ctrl.scala 142:26]
|
node _T_141 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||||
node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
node _T_142 = bits(_T_141, 31, 28) @[el2_lib.scala 214:25]
|
||||||
node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 214:25]
|
node iccm_acc_in_region_bf = eq(_T_142, UInt<4>("h0e")) @[el2_lib.scala 214:47]
|
||||||
node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 214:47]
|
node _T_143 = bits(_T_141, 31, 16) @[el2_lib.scala 217:14]
|
||||||
node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 217:14]
|
node iccm_acc_in_range_bf = eq(_T_143, UInt<16>("h0ee00")) @[el2_lib.scala 217:29]
|
||||||
node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 217:29]
|
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 141:25]
|
||||||
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 149:25]
|
node _T_144 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 142:78]
|
||||||
node _T_145 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 150:78]
|
node _T_145 = cat(_T_144, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||||
node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
|
node _T_146 = dshr(io.dec_tlu_mrac_ff, _T_145) @[el2_ifu_ifc_ctrl.scala 142:53]
|
||||||
node _T_147 = dshr(io.dec_tlu_mrac_ff, _T_146) @[el2_ifu_ifc_ctrl.scala 150:53]
|
node _T_147 = bits(_T_146, 0, 0) @[el2_ifu_ifc_ctrl.scala 142:53]
|
||||||
node _T_148 = bits(_T_147, 0, 0) @[el2_ifu_ifc_ctrl.scala 150:53]
|
node _T_148 = not(_T_147) @[el2_ifu_ifc_ctrl.scala 142:34]
|
||||||
node _T_149 = not(_T_148) @[el2_ifu_ifc_ctrl.scala 150:34]
|
io.ifc_fetch_uncacheable_bf <= _T_148 @[el2_ifu_ifc_ctrl.scala 142:31]
|
||||||
io.ifc_fetch_uncacheable_bf <= _T_149 @[el2_ifu_ifc_ctrl.scala 150:31]
|
reg _T_149 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 144:32]
|
||||||
reg _T_150 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 154:32]
|
_T_149 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 144:32]
|
||||||
_T_150 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 154:32]
|
io.ifc_fetch_req_f <= _T_149 @[el2_ifu_ifc_ctrl.scala 144:22]
|
||||||
io.ifc_fetch_req_f <= _T_150 @[el2_ifu_ifc_ctrl.scala 154:22]
|
node _T_150 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 146:88]
|
||||||
node _T_151 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 157:88]
|
reg _T_151 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
reg _T_152 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
when _T_150 : @[Reg.scala 28:19]
|
||||||
when _T_151 : @[Reg.scala 28:19]
|
_T_151 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
|
||||||
_T_152 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
|
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
io.ifc_fetch_addr_f <= _T_152 @[el2_ifu_ifc_ctrl.scala 157:23]
|
io.ifc_fetch_addr_f <= _T_151 @[el2_ifu_ifc_ctrl.scala 146:23]
|
||||||
|
|
||||||
|
|
|
@ -28,9 +28,7 @@ module el2_ifu_ifc_ctrl(
|
||||||
output io_ifc_iccm_access_bf,
|
output io_ifc_iccm_access_bf,
|
||||||
output io_ifc_region_acc_fault_bf,
|
output io_ifc_region_acc_fault_bf,
|
||||||
output io_ifc_dma_access_ok,
|
output io_ifc_dma_access_ok,
|
||||||
output io_sel_last_addr_bf,
|
output io_mb_empty_mod
|
||||||
output io_sel_btb_addr_bf,
|
|
||||||
output io_sel_next_addr_bf
|
|
||||||
);
|
);
|
||||||
`ifdef RANDOMIZE_REG_INIT
|
`ifdef RANDOMIZE_REG_INIT
|
||||||
reg [31:0] _RAND_0;
|
reg [31:0] _RAND_0;
|
||||||
|
@ -39,111 +37,118 @@ module el2_ifu_ifc_ctrl(
|
||||||
reg [31:0] _RAND_3;
|
reg [31:0] _RAND_3;
|
||||||
reg [31:0] _RAND_4;
|
reg [31:0] _RAND_4;
|
||||||
reg [31:0] _RAND_5;
|
reg [31:0] _RAND_5;
|
||||||
|
reg [31:0] _RAND_6;
|
||||||
`endif // RANDOMIZE_REG_INIT
|
`endif // RANDOMIZE_REG_INIT
|
||||||
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 72:34]
|
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 67:34]
|
||||||
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 71:36]
|
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 66:36]
|
||||||
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 76:26]
|
reg miss_a; // @[el2_ifu_ifc_ctrl.scala 69:20]
|
||||||
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 76:49]
|
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 71:26]
|
||||||
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 76:71]
|
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 71:49]
|
||||||
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctrl.scala 76:69]
|
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 71:71]
|
||||||
wire _T_8 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 77:46]
|
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctrl.scala 71:69]
|
||||||
wire _T_9 = _T_8 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 77:67]
|
wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctrl.scala 71:46]
|
||||||
wire _T_13 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 78:69]
|
wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 72:46]
|
||||||
wire _T_14 = _T_8 & _T_13; // @[el2_ifu_ifc_ctrl.scala 78:67]
|
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 72:67]
|
||||||
wire [30:0] _T_20 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
|
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 72:92]
|
||||||
wire [30:0] _T_21 = io_sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
|
wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 73:69]
|
||||||
wire [30:0] _T_22 = io_sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
|
wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctrl.scala 73:67]
|
||||||
wire [29:0] _T_30 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 90:51]
|
wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 73:92]
|
||||||
wire [30:0] _T_31 = {_T_30,1'h0}; // @[Cat.scala 29:58]
|
wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
|
||||||
wire [31:0] fetch_addr_next = {{1'd0}, _T_31}; // @[el2_ifu_ifc_ctrl.scala 90:19]
|
wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
|
||||||
wire [31:0] _T_23 = io_sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72]
|
wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
|
||||||
wire [30:0] _T_24 = _T_20 | _T_21; // @[Mux.scala 27:72]
|
wire [29:0] _T_29 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 85:51]
|
||||||
wire [30:0] _T_25 = _T_24 | _T_22; // @[Mux.scala 27:72]
|
wire [30:0] _T_30 = {_T_29,1'h0}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] _GEN_1 = {{1'd0}, _T_25}; // @[Mux.scala 27:72]
|
wire [31:0] fetch_addr_next = {{1'd0}, _T_30}; // @[el2_ifu_ifc_ctrl.scala 85:19]
|
||||||
wire [31:0] _T_26 = _GEN_1 | _T_23; // @[Mux.scala 27:72]
|
wire [31:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72]
|
||||||
reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 113:19]
|
wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
|
||||||
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 135:17]
|
wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
|
||||||
wire _T_33 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 95:91]
|
wire [31:0] _GEN_1 = {{1'd0}, _T_22}; // @[Mux.scala 27:72]
|
||||||
wire _T_34 = ~_T_33; // @[el2_ifu_ifc_ctrl.scala 95:70]
|
wire [31:0] _T_23 = _GEN_1 | _T_20; // @[Mux.scala 27:72]
|
||||||
wire [3:0] _T_119 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 108:19]
|
||||||
wire _T_79 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 120:38]
|
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 127:17]
|
||||||
wire _T_80 = io_ifu_fb_consume1 & _T_79; // @[el2_ifu_ifc_ctrl.scala 120:36]
|
wire _T_32 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 90:91]
|
||||||
wire _T_46 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctrl.scala 100:32]
|
wire _T_33 = ~_T_32; // @[el2_ifu_ifc_ctrl.scala 90:70]
|
||||||
wire miss_f = _T_46 & _T_2; // @[el2_ifu_ifc_ctrl.scala 100:47]
|
wire [3:0] _T_118 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
||||||
wire _T_82 = _T_3 | miss_f; // @[el2_ifu_ifc_ctrl.scala 120:81]
|
wire _T_78 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 112:38]
|
||||||
wire _T_83 = _T_80 & _T_82; // @[el2_ifu_ifc_ctrl.scala 120:58]
|
wire _T_79 = io_ifu_fb_consume1 & _T_78; // @[el2_ifu_ifc_ctrl.scala 112:36]
|
||||||
wire _T_84 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 121:25]
|
wire _T_45 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctrl.scala 95:32]
|
||||||
wire fb_right = _T_83 | _T_84; // @[el2_ifu_ifc_ctrl.scala 120:92]
|
wire miss_f = _T_45 & _T_2; // @[el2_ifu_ifc_ctrl.scala 95:47]
|
||||||
wire _T_96 = _T_2 & fb_right; // @[el2_ifu_ifc_ctrl.scala 127:16]
|
wire _T_81 = _T_3 | miss_f; // @[el2_ifu_ifc_ctrl.scala 112:81]
|
||||||
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctrl.scala 140:24]
|
wire _T_82 = _T_79 & _T_81; // @[el2_ifu_ifc_ctrl.scala 112:58]
|
||||||
wire [3:0] _T_99 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
|
wire _T_83 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 113:25]
|
||||||
wire [3:0] _T_120 = _T_96 ? _T_99 : 4'h0; // @[Mux.scala 27:72]
|
wire fb_right = _T_82 | _T_83; // @[el2_ifu_ifc_ctrl.scala 112:92]
|
||||||
wire [3:0] _T_124 = _T_119 | _T_120; // @[Mux.scala 27:72]
|
wire _T_95 = _T_2 & fb_right; // @[el2_ifu_ifc_ctrl.scala 119:16]
|
||||||
wire fb_right2 = io_ifu_fb_consume2 & _T_82; // @[el2_ifu_ifc_ctrl.scala 123:36]
|
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctrl.scala 132:24]
|
||||||
wire _T_101 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctrl.scala 128:16]
|
wire [3:0] _T_98 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
|
||||||
wire [3:0] _T_104 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
|
wire [3:0] _T_119 = _T_95 ? _T_98 : 4'h0; // @[Mux.scala 27:72]
|
||||||
wire [3:0] _T_121 = _T_101 ? _T_104 : 4'h0; // @[Mux.scala 27:72]
|
wire [3:0] _T_123 = _T_118 | _T_119; // @[Mux.scala 27:72]
|
||||||
|
wire fb_right2 = io_ifu_fb_consume2 & _T_81; // @[el2_ifu_ifc_ctrl.scala 115:36]
|
||||||
|
wire _T_100 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctrl.scala 120:16]
|
||||||
|
wire [3:0] _T_103 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
|
||||||
|
wire [3:0] _T_120 = _T_100 ? _T_103 : 4'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [3:0] _T_124 = _T_123 | _T_120; // @[Mux.scala 27:72]
|
||||||
|
wire _T_88 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 116:56]
|
||||||
|
wire _T_89 = ~_T_88; // @[el2_ifu_ifc_ctrl.scala 116:35]
|
||||||
|
wire _T_90 = io_ifc_fetch_req_f & _T_89; // @[el2_ifu_ifc_ctrl.scala 116:33]
|
||||||
|
wire _T_91 = ~miss_f; // @[el2_ifu_ifc_ctrl.scala 116:80]
|
||||||
|
wire fb_left = _T_90 & _T_91; // @[el2_ifu_ifc_ctrl.scala 116:78]
|
||||||
|
wire _T_105 = _T_2 & fb_left; // @[el2_ifu_ifc_ctrl.scala 121:16]
|
||||||
|
wire [3:0] _T_108 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
|
||||||
|
wire [3:0] _T_121 = _T_105 ? _T_108 : 4'h0; // @[Mux.scala 27:72]
|
||||||
wire [3:0] _T_125 = _T_124 | _T_121; // @[Mux.scala 27:72]
|
wire [3:0] _T_125 = _T_124 | _T_121; // @[Mux.scala 27:72]
|
||||||
wire _T_89 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 124:56]
|
wire _T_110 = ~fb_right; // @[el2_ifu_ifc_ctrl.scala 122:18]
|
||||||
wire _T_90 = ~_T_89; // @[el2_ifu_ifc_ctrl.scala 124:35]
|
wire _T_111 = _T_2 & _T_110; // @[el2_ifu_ifc_ctrl.scala 122:16]
|
||||||
wire _T_91 = io_ifc_fetch_req_f & _T_90; // @[el2_ifu_ifc_ctrl.scala 124:33]
|
wire _T_112 = ~fb_right2; // @[el2_ifu_ifc_ctrl.scala 122:30]
|
||||||
wire _T_92 = ~miss_f; // @[el2_ifu_ifc_ctrl.scala 124:80]
|
wire _T_113 = _T_111 & _T_112; // @[el2_ifu_ifc_ctrl.scala 122:28]
|
||||||
wire fb_left = _T_91 & _T_92; // @[el2_ifu_ifc_ctrl.scala 124:78]
|
wire _T_114 = ~fb_left; // @[el2_ifu_ifc_ctrl.scala 122:43]
|
||||||
wire _T_106 = _T_2 & fb_left; // @[el2_ifu_ifc_ctrl.scala 129:16]
|
wire _T_115 = _T_113 & _T_114; // @[el2_ifu_ifc_ctrl.scala 122:41]
|
||||||
wire [3:0] _T_109 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
|
wire [3:0] _T_122 = _T_115 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
|
||||||
wire [3:0] _T_122 = _T_106 ? _T_109 : 4'h0; // @[Mux.scala 27:72]
|
wire [3:0] fb_write_ns = _T_125 | _T_122; // @[Mux.scala 27:72]
|
||||||
wire [3:0] _T_126 = _T_125 | _T_122; // @[Mux.scala 27:72]
|
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 130:30]
|
||||||
wire _T_111 = ~fb_right; // @[el2_ifu_ifc_ctrl.scala 130:18]
|
wire _T_34 = fb_full_f_ns & _T_33; // @[el2_ifu_ifc_ctrl.scala 90:68]
|
||||||
wire _T_112 = _T_2 & _T_111; // @[el2_ifu_ifc_ctrl.scala 130:16]
|
wire _T_35 = ~_T_34; // @[el2_ifu_ifc_ctrl.scala 90:53]
|
||||||
wire _T_113 = ~fb_right2; // @[el2_ifu_ifc_ctrl.scala 130:30]
|
wire _T_36 = io_ifc_fetch_req_bf_raw & _T_35; // @[el2_ifu_ifc_ctrl.scala 90:51]
|
||||||
wire _T_114 = _T_112 & _T_113; // @[el2_ifu_ifc_ctrl.scala 130:28]
|
wire _T_37 = ~dma_stall; // @[el2_ifu_ifc_ctrl.scala 91:5]
|
||||||
wire _T_115 = ~fb_left; // @[el2_ifu_ifc_ctrl.scala 130:43]
|
wire _T_38 = _T_36 & _T_37; // @[el2_ifu_ifc_ctrl.scala 90:114]
|
||||||
wire _T_116 = _T_114 & _T_115; // @[el2_ifu_ifc_ctrl.scala 130:41]
|
wire _T_39 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctrl.scala 91:18]
|
||||||
wire [3:0] _T_123 = _T_116 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
|
wire _T_40 = _T_38 & _T_39; // @[el2_ifu_ifc_ctrl.scala 91:16]
|
||||||
wire [3:0] fb_write_ns = _T_126 | _T_123; // @[Mux.scala 27:72]
|
wire _T_41 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 91:39]
|
||||||
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 138:30]
|
wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 93:37]
|
||||||
wire _T_35 = fb_full_f_ns & _T_34; // @[el2_ifu_ifc_ctrl.scala 95:68]
|
wire _T_48 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 97:39]
|
||||||
wire _T_36 = ~_T_35; // @[el2_ifu_ifc_ctrl.scala 95:53]
|
wire _T_50 = _T_48 & _T_37; // @[el2_ifu_ifc_ctrl.scala 97:61]
|
||||||
wire _T_37 = io_ifc_fetch_req_bf_raw & _T_36; // @[el2_ifu_ifc_ctrl.scala 95:51]
|
wire _T_52 = _T_50 & _T_91; // @[el2_ifu_ifc_ctrl.scala 97:74]
|
||||||
wire _T_38 = ~dma_stall; // @[el2_ifu_ifc_ctrl.scala 96:5]
|
wire _T_53 = ~miss_a; // @[el2_ifu_ifc_ctrl.scala 97:86]
|
||||||
wire _T_39 = _T_37 & _T_38; // @[el2_ifu_ifc_ctrl.scala 95:114]
|
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 99:35]
|
||||||
wire _T_40 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctrl.scala 96:18]
|
wire _T_57 = io_exu_flush_final & _T_41; // @[el2_ifu_ifc_ctrl.scala 101:36]
|
||||||
wire _T_41 = _T_39 & _T_40; // @[el2_ifu_ifc_ctrl.scala 96:16]
|
wire leave_idle = _T_57 & idle; // @[el2_ifu_ifc_ctrl.scala 101:67]
|
||||||
wire _T_42 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 96:39]
|
wire _T_64 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 103:55]
|
||||||
wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 98:37]
|
wire _T_72 = _T_64 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 106:34]
|
||||||
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 104:35]
|
wire _T_75 = state[0] & _T_64; // @[el2_ifu_ifc_ctrl.scala 106:60]
|
||||||
wire _T_58 = io_exu_flush_final & _T_42; // @[el2_ifu_ifc_ctrl.scala 106:36]
|
wire next_state_0 = _T_72 | _T_75; // @[el2_ifu_ifc_ctrl.scala 106:48]
|
||||||
wire leave_idle = _T_58 & idle; // @[el2_ifu_ifc_ctrl.scala 106:67]
|
wire [1:0] _T_76 = {next_state_0,next_state_0}; // @[Cat.scala 29:58]
|
||||||
wire _T_65 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 108:55]
|
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 128:16]
|
||||||
wire _T_73 = _T_65 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 111:34]
|
reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 131:26]
|
||||||
wire _T_76 = state[0] & _T_65; // @[el2_ifu_ifc_ctrl.scala 111:60]
|
wire _T_135 = _T_32 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 135:61]
|
||||||
wire next_state_0 = _T_73 | _T_76; // @[el2_ifu_ifc_ctrl.scala 111:48]
|
wire _T_136 = ~_T_135; // @[el2_ifu_ifc_ctrl.scala 135:19]
|
||||||
wire [1:0] _T_77 = {next_state_0,next_state_0}; // @[Cat.scala 29:58]
|
wire _T_137 = fb_full_f & _T_136; // @[el2_ifu_ifc_ctrl.scala 135:17]
|
||||||
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 136:16]
|
wire _T_138 = _T_137 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 135:84]
|
||||||
reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 139:26]
|
wire _T_139 = io_ifc_fetch_req_bf_raw & _T_138; // @[el2_ifu_ifc_ctrl.scala 134:60]
|
||||||
wire _T_136 = _T_33 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 143:47]
|
wire [31:0] _T_141 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
||||||
wire _T_137 = ~_T_136; // @[el2_ifu_ifc_ctrl.scala 143:5]
|
wire [4:0] _T_145 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
||||||
wire _T_138 = fb_full_f & _T_137; // @[el2_ifu_ifc_ctrl.scala 142:75]
|
wire [31:0] _T_146 = io_dec_tlu_mrac_ff >> _T_145; // @[el2_ifu_ifc_ctrl.scala 142:53]
|
||||||
wire _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 143:70]
|
reg _T_149; // @[el2_ifu_ifc_ctrl.scala 144:32]
|
||||||
wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctrl.scala 142:60]
|
reg [30:0] _T_151; // @[Reg.scala 27:20]
|
||||||
wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
assign io_ifc_fetch_addr_f = _T_151; // @[el2_ifu_ifc_ctrl.scala 146:23]
|
||||||
wire [4:0] _T_146 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
assign io_ifc_fetch_addr_bf = _T_23[30:0]; // @[el2_ifu_ifc_ctrl.scala 76:24]
|
||||||
wire [31:0] _T_147 = io_dec_tlu_mrac_ff >> _T_146; // @[el2_ifu_ifc_ctrl.scala 150:53]
|
assign io_ifc_fetch_req_f = _T_149; // @[el2_ifu_ifc_ctrl.scala 144:22]
|
||||||
reg _T_150; // @[el2_ifu_ifc_ctrl.scala 154:32]
|
assign io_ifu_pmu_fetch_stall = wfm | _T_139; // @[el2_ifu_ifc_ctrl.scala 134:26]
|
||||||
reg [30:0] _T_152; // @[Reg.scala 27:20]
|
assign io_ifc_fetch_uncacheable_bf = ~_T_146[0]; // @[el2_ifu_ifc_ctrl.scala 142:31]
|
||||||
assign io_ifc_fetch_addr_f = _T_152; // @[el2_ifu_ifc_ctrl.scala 157:23]
|
assign io_ifc_fetch_req_bf = _T_40 & _T_41; // @[el2_ifu_ifc_ctrl.scala 90:23]
|
||||||
assign io_ifc_fetch_addr_bf = _T_26[30:0]; // @[el2_ifu_ifc_ctrl.scala 81:24]
|
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 88:27]
|
||||||
assign io_ifc_fetch_req_f = _T_150; // @[el2_ifu_ifc_ctrl.scala 154:22]
|
assign io_ifc_iccm_access_bf = _T_141[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 141:25]
|
||||||
assign io_ifu_pmu_fetch_stall = wfm | _T_140; // @[el2_ifu_ifc_ctrl.scala 142:26]
|
assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 41:30]
|
||||||
assign io_ifc_fetch_uncacheable_bf = ~_T_147[0]; // @[el2_ifu_ifc_ctrl.scala 150:31]
|
assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 42:24]
|
||||||
assign io_ifc_fetch_req_bf = _T_41 & _T_42; // @[el2_ifu_ifc_ctrl.scala 95:23]
|
assign io_mb_empty_mod = _T_52 & _T_53; // @[el2_ifu_ifc_ctrl.scala 98:19]
|
||||||
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 93:27]
|
|
||||||
assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 149:25]
|
|
||||||
assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 42:30]
|
|
||||||
assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 43:24]
|
|
||||||
assign io_sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctrl.scala 76:23]
|
|
||||||
assign io_sel_btb_addr_bf = _T_9 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 77:23]
|
|
||||||
assign io_sel_next_addr_bf = _T_14 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 78:23]
|
|
||||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||||
`define RANDOMIZE
|
`define RANDOMIZE
|
||||||
`endif
|
`endif
|
||||||
|
@ -182,15 +187,17 @@ initial begin
|
||||||
_RAND_0 = {1{`RANDOM}};
|
_RAND_0 = {1{`RANDOM}};
|
||||||
dma_iccm_stall_any_f = _RAND_0[0:0];
|
dma_iccm_stall_any_f = _RAND_0[0:0];
|
||||||
_RAND_1 = {1{`RANDOM}};
|
_RAND_1 = {1{`RANDOM}};
|
||||||
state = _RAND_1[1:0];
|
miss_a = _RAND_1[0:0];
|
||||||
_RAND_2 = {1{`RANDOM}};
|
_RAND_2 = {1{`RANDOM}};
|
||||||
fb_write_f = _RAND_2[3:0];
|
state = _RAND_2[1:0];
|
||||||
_RAND_3 = {1{`RANDOM}};
|
_RAND_3 = {1{`RANDOM}};
|
||||||
fb_full_f = _RAND_3[0:0];
|
fb_write_f = _RAND_3[3:0];
|
||||||
_RAND_4 = {1{`RANDOM}};
|
_RAND_4 = {1{`RANDOM}};
|
||||||
_T_150 = _RAND_4[0:0];
|
fb_full_f = _RAND_4[0:0];
|
||||||
_RAND_5 = {1{`RANDOM}};
|
_RAND_5 = {1{`RANDOM}};
|
||||||
_T_152 = _RAND_5[30:0];
|
_T_149 = _RAND_5[0:0];
|
||||||
|
_RAND_6 = {1{`RANDOM}};
|
||||||
|
_T_151 = _RAND_6[30:0];
|
||||||
`endif // RANDOMIZE_REG_INIT
|
`endif // RANDOMIZE_REG_INIT
|
||||||
`endif // RANDOMIZE
|
`endif // RANDOMIZE
|
||||||
end // initial
|
end // initial
|
||||||
|
@ -204,10 +211,15 @@ end // initial
|
||||||
end else begin
|
end else begin
|
||||||
dma_iccm_stall_any_f <= io_dma_iccm_stall_any;
|
dma_iccm_stall_any_f <= io_dma_iccm_stall_any;
|
||||||
end
|
end
|
||||||
|
if (reset) begin
|
||||||
|
miss_a <= 1'h0;
|
||||||
|
end else begin
|
||||||
|
miss_a <= miss_f;
|
||||||
|
end
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
state <= 2'h0;
|
state <= 2'h0;
|
||||||
end else begin
|
end else begin
|
||||||
state <= _T_77;
|
state <= _T_76;
|
||||||
end
|
end
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
fb_write_f <= 4'h0;
|
fb_write_f <= 4'h0;
|
||||||
|
@ -220,14 +232,14 @@ end // initial
|
||||||
fb_full_f <= fb_full_f_ns;
|
fb_full_f <= fb_full_f_ns;
|
||||||
end
|
end
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
_T_150 <= 1'h0;
|
_T_149 <= 1'h0;
|
||||||
end else begin
|
end else begin
|
||||||
_T_150 <= io_ifc_fetch_req_bf;
|
_T_149 <= io_ifc_fetch_req_bf;
|
||||||
end
|
end
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
_T_152 <= 31'h0;
|
_T_151 <= 31'h0;
|
||||||
end else if (fetch_bf_en) begin
|
end else if (fetch_bf_en) begin
|
||||||
_T_152 <= io_ifc_fetch_addr_bf;
|
_T_151 <= io_ifc_fetch_addr_bf;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
@ -30,29 +30,16 @@ class el2_ifu_compress_ctl extends Module {
|
||||||
(pat(List(-14, 4))&(!io.din(0))) | (pat(List(-14, 3))&(!io.din(0))) | (pat(List(-14, 2))&(!io.din(0))) |
|
(pat(List(-14, 4))&(!io.din(0))) | (pat(List(-14, 3))&(!io.din(0))) | (pat(List(-14, 2))&(!io.din(0))) |
|
||||||
pat(List(-14, -13, 0))
|
pat(List(-14, -13, 0))
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
out(3) := pat(List(-14, 13))
|
out(3) := pat(List(-14, 13))
|
||||||
out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) |
|
out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) | pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) |
|
||||||
pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) |
|
pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) | pat(List(-14, 12, 8, -6,-5,-4, -3, -2,1)) |
|
||||||
pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) |
|
pat(List(-14, 12, 7, -6, -5, -4, -3, -2,1)) | (pat(List(15, -14,-12, -6, -5, -4, -3, -2))&(!io.din(0))) |
|
||||||
pat(List(-14, 12, 8, -6,-5,-4, -3, -2,1)) |
|
pat(List(-15,13,-8)) | pat(List(-15,13,7)) | pat(List(-15,13,9)) | pat(List(-15,13,10)) |
|
||||||
pat(List(-14, 12, 7, -6, -5, -4, -3, -2,1)) |
|
pat(List(-15,13,11)) | pat(List(-14,13))
|
||||||
(pat(List(15, -14,-12, -6, -5, -4, -3, -2))&(!io.din(0))) |
|
|
||||||
pat(List(-15,13,-8)) |
|
|
||||||
pat(List(-15,13,7)) |
|
|
||||||
pat(List(-15,13,9)) |
|
|
||||||
pat(List(-15,13,10)) |
|
|
||||||
pat(List(-15,13,11)) |
|
|
||||||
pat(List(-14,13))
|
|
||||||
out(1) := 1.U.asBool
|
out(1) := 1.U.asBool
|
||||||
out(0) := 1.U.asBool
|
out(0) := 1.U.asBool
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
val rs2d = io.din(6,2)
|
val rs2d = io.din(6,2)
|
||||||
val rdd = io.din(11,7)
|
val rdd = io.din(11,7)
|
||||||
val rdpd = Cat(1.U(2.W), io.din(9,7))
|
val rdpd = Cat(1.U(2.W), io.din(9,7))
|
||||||
|
@ -62,19 +49,10 @@ class el2_ifu_compress_ctl extends Module {
|
||||||
pat(List(-14,4,1)) | pat(List(-15,14,9,0)) | pat(List(-14,3,1)) | pat(List(-15,14,-8,0)) |
|
pat(List(-14,4,1)) | pat(List(-15,14,9,0)) | pat(List(-14,3,1)) | pat(List(-15,14,-8,0)) |
|
||||||
pat(List(-14,2,1)) | pat(List(-15,14,7,0)) | pat(List(-15,1)) | pat(List(-15,-13,0))
|
pat(List(-14,2,1)) | pat(List(-15,14,7,0)) | pat(List(-15,1)) | pat(List(-15,-13,0))
|
||||||
|
|
||||||
val rdrs1 = pat(List(-14,12,11,1)) |
|
val rdrs1 = pat(List(-14,12,11,1)) | pat(List(-14,12,10,1)) | pat(List(-14,12,9,1)) |
|
||||||
pat(List(-14,12,10,1)) |
|
pat(List(-14,12,8,1)) | pat(List(-14,12,7,1)) | pat(List(-14,-12,-6,-5,-4,-3,-2,1)) |
|
||||||
pat(List(-14,12,9,1)) |
|
pat(List(-14,12,6,1)) | pat(List(-14,12,5,1)) | pat(List(-14,12,4,1)) | pat(List(-14,12,3,1)) |
|
||||||
pat(List(-14,12,8,1)) |
|
pat(List(-14,12,2,1)) | pat(List(-15,-14,-13,0)) | pat(List(-15,-14,1))
|
||||||
pat(List(-14,12,7,1)) |
|
|
||||||
pat(List(-14,-12,-6,-5,-4,-3,-2,1)) |
|
|
||||||
pat(List(-14,12,6,1)) |
|
|
||||||
pat(List(-14,12,5,1)) |
|
|
||||||
pat(List(-14,12,4,1)) |
|
|
||||||
pat(List(-14,12,3,1)) |
|
|
||||||
pat(List(-14,12,2,1)) |
|
|
||||||
pat(List(-15,-14,-13,0)) |
|
|
||||||
pat(List(-15,-14,1))
|
|
||||||
|
|
||||||
val rs2rs2 = pat(List(15,6,1)) | pat(List(15,5,1)) | pat(List(15,4,1)) | pat(List(15,3,1)) | pat(List(15,2,1)) | pat(List(15,14,1))
|
val rs2rs2 = pat(List(15,6,1)) | pat(List(15,5,1)) | pat(List(15,4,1)) | pat(List(15,3,1)) | pat(List(15,2,1)) | pat(List(15,14,1))
|
||||||
|
|
||||||
|
@ -130,7 +108,6 @@ class el2_ifu_compress_ctl extends Module {
|
||||||
val sjald_12 = Fill(9, io.din(12))
|
val sjald_12 = Fill(9, io.din(12))
|
||||||
val sjald = Cat(sjald_12,sjald_1)
|
val sjald = Cat(sjald_12,sjald_1)
|
||||||
val sluimmd = Cat(Fill(15, io.din(12)), io.din(6,2))
|
val sluimmd = Cat(Fill(15, io.din(12)), io.din(6,2))
|
||||||
//io.sluimmd := sluimmd
|
|
||||||
|
|
||||||
val l2_31 = l1(31,20) |
|
val l2_31 = l1(31,20) |
|
||||||
Mux1H(Seq(simm5_0.asBool->Cat(Fill(7, simm5d(5)), simm5d(4,0)),
|
Mux1H(Seq(simm5_0.asBool->Cat(Fill(7, simm5d(5)), simm5d(4,0)),
|
||||||
|
@ -146,7 +123,6 @@ class el2_ifu_compress_ctl extends Module {
|
||||||
sluimm17_12.asBool->sluimmd(7,0)))
|
sluimm17_12.asBool->sluimmd(7,0)))
|
||||||
val l2 = Cat(l2_31, l2_19, l1(11,0))
|
val l2 = Cat(l2_31, l2_19, l1(11,0))
|
||||||
|
|
||||||
|
|
||||||
val sbr8d = Cat(io.din(12),io.din(6),io.din(5),io.din(2),io.din(11),io.din(10),io.din(4),io.din(3),0.U)
|
val sbr8d = Cat(io.din(12),io.din(6),io.din(5),io.din(2),io.din(11),io.din(10),io.din(4),io.din(3),0.U)
|
||||||
val uswimm6d = Cat(io.din(5), io.din(12,10), io.din(6), 0.U(2.W))
|
val uswimm6d = Cat(io.din(5), io.din(12,10), io.din(6), 0.U(2.W))
|
||||||
val uswspimm7d = Cat(io.din(8,7),io.din(12,9), 0.U(2.W))
|
val uswspimm7d = Cat(io.din(8,7),io.din(12,9), 0.U(2.W))
|
||||||
|
|
|
@ -34,9 +34,8 @@ val io = IO(new Bundle{
|
||||||
val ifc_iccm_access_bf = Output(Bool())
|
val ifc_iccm_access_bf = Output(Bool())
|
||||||
val ifc_region_acc_fault_bf = Output(Bool())
|
val ifc_region_acc_fault_bf = Output(Bool())
|
||||||
val ifc_dma_access_ok = Output(Bool())
|
val ifc_dma_access_ok = Output(Bool())
|
||||||
val sel_last_addr_bf = Output(Bool())
|
val mb_empty_mod = Output(Bool())
|
||||||
val sel_btb_addr_bf = Output(Bool())
|
|
||||||
val sel_next_addr_bf = Output(Bool())
|
|
||||||
})
|
})
|
||||||
|
|
||||||
io.ifc_region_acc_fault_bf := 0.U
|
io.ifc_region_acc_fault_bf := 0.U
|
||||||
|
@ -51,9 +50,6 @@ val io = IO(new Bundle{
|
||||||
val fb_left = WireInit(Bool(), init = 0.U)
|
val fb_left = WireInit(Bool(), init = 0.U)
|
||||||
val wfm = WireInit(Bool(), init = 0.U)
|
val wfm = WireInit(Bool(), init = 0.U)
|
||||||
val idle = WireInit(Bool(), init = 0.U)
|
val idle = WireInit(Bool(), init = 0.U)
|
||||||
// val sel_last_addr_bf = WireInit(Bool(), init = 0.U)
|
|
||||||
// val sel_btb_addr_bf = WireInit(Bool(), init = 0.U)
|
|
||||||
// val sel_next_addr_bf = WireInit(Bool(), init = 0.U)
|
|
||||||
val miss_f = WireInit(Bool(), init = 0.U)
|
val miss_f = WireInit(Bool(), init = 0.U)
|
||||||
val miss_a = WireInit(Bool(), init = 0.U)
|
val miss_a = WireInit(Bool(), init = 0.U)
|
||||||
val flush_fb = WireInit(Bool(), init = 0.U)
|
val flush_fb = WireInit(Bool(), init = 0.U)
|
||||||
|
@ -62,7 +58,6 @@ val io = IO(new Bundle{
|
||||||
val leave_idle = WireInit(Bool(), init = 0.U)
|
val leave_idle = WireInit(Bool(), init = 0.U)
|
||||||
val fetch_bf_en = WireInit(Bool(), init = 0.U)
|
val fetch_bf_en = WireInit(Bool(), init = 0.U)
|
||||||
val line_wrap = WireInit(Bool(), init = 0.U)
|
val line_wrap = WireInit(Bool(), init = 0.U)
|
||||||
//val fetch_addr_next_1 = WireInit(Bool(), init = 0.U)
|
|
||||||
val state = WireInit(UInt(2.W), init = 0.U)
|
val state = WireInit(UInt(2.W), init = 0.U)
|
||||||
val dma_iccm_stall_any_f = WireInit(Bool(), init = 0.U)
|
val dma_iccm_stall_any_f = WireInit(Bool(), init = 0.U)
|
||||||
|
|
||||||
|
@ -73,15 +68,15 @@ val io = IO(new Bundle{
|
||||||
|
|
||||||
miss_a := RegNext(miss_f, init=0.U)
|
miss_a := RegNext(miss_f, init=0.U)
|
||||||
|
|
||||||
io.sel_last_addr_bf := ~io.exu_flush_final & (~io.ifc_fetch_req_f | ~io.ic_hit_f)
|
val sel_last_addr_bf = !io.exu_flush_final & (!io.ifc_fetch_req_f | !io.ic_hit_f)
|
||||||
io.sel_btb_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f
|
val sel_btb_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f
|
||||||
io.sel_next_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & ~io.ifu_bp_hit_taken_f & io.ic_hit_f
|
val sel_next_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f
|
||||||
|
|
||||||
// TODO: Make an assertion for the 1H-Mux under here
|
// TODO: Make an assertion for the 1H-Mux under here
|
||||||
io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC
|
io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC
|
||||||
io.sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC
|
sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC
|
||||||
io.sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC
|
sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC
|
||||||
io.sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
|
sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
|
||||||
|
|
||||||
//io.test_out := io.ifc_fetch_addr_bf
|
//io.test_out := io.ifc_fetch_addr_bf
|
||||||
|
|
||||||
|
@ -92,42 +87,39 @@ val io = IO(new Bundle{
|
||||||
|
|
||||||
io.ifc_fetch_req_bf_raw := ~idle
|
io.ifc_fetch_req_bf_raw := ~idle
|
||||||
|
|
||||||
io.ifc_fetch_req_bf := io.ifc_fetch_req_bf_raw & ~(fb_full_f_ns & ~(io.ifu_fb_consume2 | io.ifu_fb_consume1)) &
|
io.ifc_fetch_req_bf := io.ifc_fetch_req_bf_raw & !(fb_full_f_ns & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) &
|
||||||
~dma_stall & ~io.ic_write_stall & ~io.dec_tlu_flush_noredir_wb
|
!dma_stall & !io.ic_write_stall & !io.dec_tlu_flush_noredir_wb
|
||||||
|
|
||||||
fetch_bf_en := io.exu_flush_final | io.ifc_fetch_req_f
|
fetch_bf_en := io.exu_flush_final | io.ifc_fetch_req_f
|
||||||
|
|
||||||
miss_f := io.ifc_fetch_req_f & ~io.ic_hit_f & ~io.exu_flush_final
|
miss_f := io.ifc_fetch_req_f & !io.ic_hit_f & !io.exu_flush_final
|
||||||
|
|
||||||
mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_flush_final) & ~dma_stall & ~miss_f & ~miss_a
|
|
||||||
|
|
||||||
|
mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_flush_final) & !dma_stall & !miss_f & !miss_a
|
||||||
|
io.mb_empty_mod := mb_empty_mod
|
||||||
goto_idle := io.exu_flush_final & io.dec_tlu_flush_noredir_wb
|
goto_idle := io.exu_flush_final & io.dec_tlu_flush_noredir_wb
|
||||||
|
|
||||||
leave_idle := io.exu_flush_final & ~io.dec_tlu_flush_noredir_wb & idle
|
leave_idle := io.exu_flush_final & !io.dec_tlu_flush_noredir_wb & idle
|
||||||
|
|
||||||
val next_state_1 = (~state(1) & state(0) & miss_f & ~goto_idle) |
|
val next_state_1 = (!state(1) & state(0) & miss_f & !goto_idle) |
|
||||||
(state(1) & ~mb_empty_mod & ~goto_idle)
|
(state(1) & !mb_empty_mod & !goto_idle)
|
||||||
|
|
||||||
val next_state_0 = (~goto_idle & leave_idle) | (state(0) & ~goto_idle)
|
val next_state_0 = (!goto_idle & leave_idle) | (state(0) & !goto_idle)
|
||||||
|
|
||||||
state := RegNext(Cat(next_state_0, next_state_0), init = 0.U)
|
state := RegNext(Cat(next_state_0, next_state_0), init = 0.U)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
flush_fb := io.exu_flush_final
|
flush_fb := io.exu_flush_final
|
||||||
|
|
||||||
fb_right := ( io.ifu_fb_consume1 & ~io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)) |
|
fb_right := ( io.ifu_fb_consume1 & !io.ifu_fb_consume2 & (!io.ifc_fetch_req_f | miss_f)) |
|
||||||
(io.ifu_fb_consume2 & io.ifc_fetch_req_f)
|
(io.ifu_fb_consume2 & io.ifc_fetch_req_f)
|
||||||
|
|
||||||
fb_right2 := (io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f))
|
fb_right2 := (io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f))
|
||||||
fb_left := io.ifc_fetch_req_f & ~(io.ifu_fb_consume1 | io.ifu_fb_consume2) & ~miss_f
|
fb_left := io.ifc_fetch_req_f & !(io.ifu_fb_consume1 | io.ifu_fb_consume2) & !miss_f
|
||||||
|
|
||||||
fb_write_ns := Mux1H(Seq(flush_fb.asBool -> 1.U(4.W),
|
fb_write_ns := Mux1H(Seq(flush_fb.asBool -> 1.U(4.W),
|
||||||
(~flush_fb & fb_right).asBool -> Cat(0.U(1.W), fb_write_f(3,1)),
|
(!flush_fb & fb_right).asBool -> Cat(0.U(1.W), fb_write_f(3,1)),
|
||||||
(~flush_fb & fb_right2).asBool -> Cat(0.U(2.W), fb_write_f(3,2)),
|
(!flush_fb & fb_right2).asBool -> Cat(0.U(2.W), fb_write_f(3,2)),
|
||||||
(~flush_fb & fb_left).asBool -> Cat(fb_write_f(2,0), 0.U(1.W)),
|
(!flush_fb & fb_left).asBool -> Cat(fb_write_f(2,0), 0.U(1.W)),
|
||||||
(~flush_fb & ~fb_right & ~fb_right2 & ~fb_left).asBool -> fb_write_f(3,0)
|
(!flush_fb & !fb_right & !fb_right2 & !fb_left).asBool -> fb_write_f(3,0)
|
||||||
))
|
))
|
||||||
|
|
||||||
fb_full_f_ns := RegNext(fb_write_ns(3), init = 0.U)
|
fb_full_f_ns := RegNext(fb_write_ns(3), init = 0.U)
|
||||||
|
@ -139,8 +131,8 @@ val io = IO(new Bundle{
|
||||||
val fb_full_f = RegNext(fb_full_f_ns, init = 0.U)
|
val fb_full_f = RegNext(fb_full_f_ns, init = 0.U)
|
||||||
fb_write_f := RegNext(fb_write_ns, 0.U)
|
fb_write_f := RegNext(fb_write_ns, 0.U)
|
||||||
|
|
||||||
io.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw & ( (fb_full_f &
|
io.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw &
|
||||||
!(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
|
((fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
|
||||||
|
|
||||||
val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE)
|
val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE)
|
||||||
rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U))
|
rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U))
|
||||||
|
@ -149,11 +141,8 @@ val io = IO(new Bundle{
|
||||||
io.ifc_iccm_access_bf := iccm_acc_in_range_bf
|
io.ifc_iccm_access_bf := iccm_acc_in_range_bf
|
||||||
io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U))
|
io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U))
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
io.ifc_fetch_req_f := RegNext(io.ifc_fetch_req_bf, init=0.U)
|
io.ifc_fetch_req_f := RegNext(io.ifc_fetch_req_bf, init=0.U)
|
||||||
|
|
||||||
|
|
||||||
io.ifc_fetch_addr_f := RegEnable(io.ifc_fetch_addr_bf, init = 0.U, io.exu_flush_final|io.ifc_fetch_req_f)
|
io.ifc_fetch_addr_f := RegEnable(io.ifc_fetch_addr_bf, init = 0.U, io.exu_flush_final|io.ifc_fetch_req_f)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Loading…
Reference in New Issue