pcio clk override updated
This commit is contained in:
Laraib Khan
parent
b9cdbac350
commit
80ac7ee439
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@ -516,49 +516,6 @@
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec|dec>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
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"sources":[
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"~dec|dec>io_lsu_load_stall_any",
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"~dec|dec>io_dec_dma_dctl_dma_dma_dccm_stall_any",
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"~dec|dec>io_lsu_store_stall_any",
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"~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m",
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"~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata",
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"~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid",
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"~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error",
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"~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid",
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"~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid",
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"~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type",
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"~dec|dec>io_mpc_reset_run_req",
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"~dec|dec>io_lsu_fastint_stall_any",
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"~dec|dec>io_lsu_fir_error",
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"~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error",
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"~dec|dec>io_dbg_halt_req",
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"~dec|dec>io_lsu_error_pkt_r_bits_inst_type",
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"~dec|dec>io_lsu_error_pkt_r_valid",
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"~dec|dec>io_dec_pic_mhwakeup",
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"~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r",
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"~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r",
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"~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any",
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"~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any",
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"~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle",
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"~dec|dec>io_lsu_idle_any",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr",
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"~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr",
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"~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist",
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"~dec|dec>io_lsu_result_corr_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sbext",
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@ -654,6 +611,49 @@
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec|dec>io_dec_i0_decode_d",
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"sources":[
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"~dec|dec>io_lsu_load_stall_any",
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"~dec|dec>io_dec_dma_dctl_dma_dma_dccm_stall_any",
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"~dec|dec>io_lsu_store_stall_any",
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"~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m",
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"~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata",
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"~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid",
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"~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error",
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"~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid",
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"~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid",
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"~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type",
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"~dec|dec>io_mpc_reset_run_req",
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"~dec|dec>io_lsu_fastint_stall_any",
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"~dec|dec>io_lsu_fir_error",
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"~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error",
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"~dec|dec>io_dbg_halt_req",
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"~dec|dec>io_lsu_error_pkt_r_bits_inst_type",
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"~dec|dec>io_lsu_error_pkt_r_valid",
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"~dec|dec>io_dec_pic_mhwakeup",
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"~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r",
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"~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r",
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"~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any",
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"~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any",
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"~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle",
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"~dec|dec>io_lsu_idle_any",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr",
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"~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr",
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"~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid",
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"~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist",
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"~dec|dec>io_lsu_result_corr_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_low",
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@ -98,6 +98,8 @@ class dec_IO extends Bundle with lib {
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val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating
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val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating
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val dec_i0_decode_d = Output(Bool())
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val scan_mode = Input(Bool())
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val ifu_dec = Flipped(new ifu_dec)
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val dec_exu = Flipped(new dec_exu)
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@ -143,7 +145,7 @@ class dec extends Module with param with RequireAsyncReset{
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val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
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dontTouch(dec_i0_trigger_match_d)
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decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec
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io.dec_i0_decode_d := decode.io.dec_i0_decode_d
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decode.io.decode_exu<> io.dec_exu.decode_exu
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decode.io.dec_alu<> io.dec_exu.dec_alu
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decode.io.dec_div<> io.dec_exu.dec_div
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@ -257,7 +259,7 @@ class dec extends Module with param with RequireAsyncReset{
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tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
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tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
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tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
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tlu.io.dec_i0_decode_d := decode.io.dec_aln.dec_i0_decode_d
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tlu.io.dec_i0_decode_d := decode.io.dec_i0_decode_d
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tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r
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tlu.io.dbg_halt_req := io.dbg_halt_req
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tlu.io.dbg_resume_req := io.dbg_resume_req
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@ -300,7 +302,7 @@ class dec extends Module with param with RequireAsyncReset{
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io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override
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io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override
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io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override
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io.dec_tlu_picio_clk_override := tlu.io.dec_tlu_icm_clk_override
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io.dec_tlu_picio_clk_override := tlu.io.dec_tlu_picio_clk_override
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io.dec_tlu_core_empty := tlu.io.dec_tlu_core_empty
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io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
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io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
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@ -112,6 +112,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
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val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating
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val dec_div_active = Output(Bool()) // non-block divide is active
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val scan_mode = Input(Bool())
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val dec_i0_decode_d = Output(Bool())
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})
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//packets zero initialization
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io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p)
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@ -201,6 +202,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
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val fa_error_index_ns = WireInit(Bool(),0.B)
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val btb_error_found = WireInit(Bool(),0.B)
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val div_active_in = WireInit(Bool(),0.B)
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//////////////////////////////////////////////////////////////////////
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leak1_i1_stall := rvdffie(leak1_i1_stall_in, io.free_l2clk, reset.asAsyncReset(), io.scan_mode)
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@ -444,7 +446,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
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// can't make this clock active_clock
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leak1_i1_stall_in := (io.dec_tlu_flush_leak_one_r | (leak1_i1_stall & !io.dec_tlu_flush_lower_r))
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leak1_mode := leak1_i1_stall
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leak1_i0_stall_in := ((io.dec_aln.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r))
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leak1_i0_stall_in := ((io.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r))
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// 12b jal's can be predicted - these are calls
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@ -591,7 +593,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
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val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.dec_aln.ifu_i0_cinst))
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// illegal inst handling
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val shift_illegal = io.dec_aln.dec_i0_decode_d & !i0_legal//lm: valid but not legal
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val shift_illegal = io.dec_i0_decode_d & !i0_legal//lm: valid but not legal
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val illegal_inst_en = shift_illegal & !illegal_lockout
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io.dec_illegal_inst := rvdffe(i0_inst_d,illegal_inst_en,clock,io.scan_mode)
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illegal_lockout_in := (shift_illegal | illegal_lockout) & !flush_final_r
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@ -608,13 +610,13 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
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val i0_exublock_d = i0_block_raw_d
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//decode valid
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io.dec_aln.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
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io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
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val i0_exudecode_d = io.dec_ib0_valid_d & !i0_exublock_d & !io.dec_tlu_flush_lower_r & !flush_final_r
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val i0_exulegal_decode_d = i0_exudecode_d & i0_legal
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// performance monitor signals
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io.dec_pmu_instr_decoded := io.dec_aln.dec_i0_decode_d
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io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_aln.dec_i0_decode_d
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io.dec_pmu_instr_decoded := io.dec_i0_decode_d
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io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_i0_decode_d
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io.dec_pmu_postsync_stall := postsync_stall.asBool & io.dec_ib0_valid_d
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io.dec_pmu_presync_stall := presync_stall.asBool & io.dec_ib0_valid_d
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@ -625,7 +627,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
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presync_stall := (i0_presync & prior_inflight_eff)
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// illegals will postsync
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ps_stall_in := (io.dec_aln.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x)
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ps_stall_in := (io.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x)
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io.dec_alu.dec_i0_alu_decode_d := i0_exulegal_decode_d & i0_dp.alu
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io.decode_exu.dec_i0_branch_d := i0_dp.condbr | i0_dp.jal | i0_br_error_all
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@ -649,7 +651,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
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d_t.pmu_divide := 0.U(1.W)
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d_t.pmu_lsu_misaligned := 0.U(1.W)
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d_t.i0trigger := io.dec_i0_trigger_match_d & repl(4,io.dec_aln.dec_i0_decode_d)
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d_t.i0trigger := io.dec_i0_trigger_match_d & repl(4,io.dec_i0_decode_d)
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x_t := rvdfflie(d_t,clock,reset.asAsyncReset,i0_x_ctl_en.asBool,io.scan_mode, elements = 3)
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@ -671,7 +673,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
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// end tlu stuff
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io.dec_aln.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
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io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
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i0r.rs1 := i0(19,15) //H: ing reg packets the instructions bits
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i0r.rs2 := i0(24,20)
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@ -753,7 +755,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
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bitmanip_zbb_zbp_legal := !(i0_dp.zbb & i0_dp.zbp)
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bitmanip_legal := bitmanip_zbb_legal & bitmanip_zbs_legal & bitmanip_zbe_legal & bitmanip_zbc_legal & bitmanip_zbp_legal & bitmanip_zbr_legal & bitmanip_zbf_legal & bitmanip_zba_legal & bitmanip_zbb_zbp_legal
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i0_legal_decode_d := io.dec_aln.dec_i0_decode_d & i0_legal
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i0_legal_decode_d := io.dec_i0_decode_d & i0_legal
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i0_d_c.mul := i0_dp.mul & i0_legal_decode_d
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i0_d_c.load := i0_dp.load & i0_legal_decode_d
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@ -761,7 +763,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
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val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c,0.U.asTypeOf(i0_d_c), i0_x_ctl_en.asBool)}
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val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c,0.U.asTypeOf(i0_x_c), i0_r_ctl_en.asBool)}
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i0_pipe_en := Cat(io.dec_aln.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)})
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i0_pipe_en := Cat(io.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)})
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i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override)
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i0_r_ctl_en := (i0_pipe_en(2,1).orR | io.clk_override)
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@ -775,14 +777,14 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
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d_d.bits.i0rd := i0r.rd
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d_d.bits.i0v := i0_rd_en_d & i0_legal_decode_d
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d_d.valid := io.dec_aln.dec_i0_decode_d // has flush_final_r
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d_d.valid := io.dec_i0_decode_d // has flush_final_r
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d_d.bits.i0load := i0_dp.load & i0_legal_decode_d
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d_d.bits.i0store := i0_dp.store & i0_legal_decode_d
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d_d.bits.i0div := i0_dp.div & i0_legal_decode_d
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d_d.bits.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d
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d_d.bits.csrwonly := i0_csr_write_only_d & io.dec_aln.dec_i0_decode_d
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d_d.bits.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d
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d_d.bits.csrwaddr := Mux(d_d.bits.csrwen, i0(31,20), 0.U)
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x_d := rvdfflie(d_d,clock,reset.asAsyncReset(), i0_x_ctl_en.asBool,io.scan_mode,elements = 4)
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@ -1,405 +1,405 @@
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package ifu
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import lib._
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import chisel3._
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import chisel3.util._
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import include._
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class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
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val io = IO(new Bundle{
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val scan_mode = Input(Bool())
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val active_clk = Input(Clock())
|
||||
val ifu_async_error_start = Input(Bool()) // Error coming from mem-ctl
|
||||
val iccm_rd_ecc_double_err = Input(Bool()) // ICCM double error coming from mem-ctl
|
||||
val ic_access_fault_f = Input(Bool()) // Access fault in I$
|
||||
val ic_access_fault_type_f = Input(UInt(2.W)) // Type of access fault occured
|
||||
val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP
|
||||
val ifu_bp_btb_target_f = Input(UInt(31.W)) // Target for the instruction enqueue in the FP
|
||||
val ifu_bp_poffset_f = Input(UInt(12.W)) // Offset to the current PC for branch
|
||||
val ifu_bp_hist0_f = Input(UInt(2.W)) // History to EXU
|
||||
val ifu_bp_hist1_f = Input(UInt(2.W)) // History to EXU
|
||||
val ifu_bp_pc4_f = Input(UInt(2.W)) // PC4
|
||||
val ifu_bp_way_f = Input(UInt(2.W)) // Way to help in miss prediction
|
||||
val ifu_bp_valid_f = Input(UInt(2.W)) // Valid Branch prediction
|
||||
val ifu_bp_ret_f = Input(UInt(2.W)) // BP ret
|
||||
val exu_flush_final = Input(Bool()) // Miss prediction
|
||||
val dec_aln = new dec_aln() // Data going to the dec from the ALN
|
||||
val ifu_fetch_data_f = Input(UInt(32.W)) // PC of the current instruction in the FP
|
||||
val ifu_fetch_val = Input(UInt(2.W)) // PC boundary i.e 'x' of 2 or 4
|
||||
val ifu_fetch_pc = Input(UInt(31.W)) // Current PC
|
||||
/////////////////////////////////////////////////
|
||||
val ifu_fb_consume1 = Output(Bool()) // FP used 1
|
||||
val ifu_fb_consume2 = Output(Bool()) // FP used 2
|
||||
|
||||
})
|
||||
val MHI = 46+BHT_GHR_SIZE // 54
|
||||
val MSIZE = 47+BHT_GHR_SIZE // 55
|
||||
val BRDATA_SIZE = 12
|
||||
val error_stall_in = WireInit(Bool(),0.U)
|
||||
val alignval = WireInit(UInt(2.W), 0.U)
|
||||
val q0final = WireInit(UInt(32.W), 0.U)
|
||||
val q1final = WireInit(UInt(16.W), 0.U)
|
||||
val wrptr_in = WireInit(UInt(2.W), init = 0.U)
|
||||
val rdptr_in = WireInit(UInt(2.W), init = 0.U)
|
||||
|
||||
val f2val_in = WireInit(UInt(2.W), init = 0.U)
|
||||
val f1val_in = WireInit(UInt(2.W), init = 0.U)
|
||||
val f0val_in = WireInit(UInt(2.W), init = 0.U)
|
||||
|
||||
val q2off_in = WireInit(UInt(1.W), init = 0.U)
|
||||
val q1off_in = WireInit(UInt(1.W), init = 0.U)
|
||||
val q0off_in = WireInit(UInt(1.W), init = 0.U)
|
||||
|
||||
val sf0_valid = WireInit(Bool(), init = 0.U)
|
||||
val sf1_valid = WireInit(Bool(), init = 0.U)
|
||||
|
||||
val f2_valid = WireInit(Bool(), init = 0.U)
|
||||
val ifvalid = WireInit(Bool(), init = 0.U)
|
||||
val shift_f2_f1 = WireInit(Bool(), init = 0.U)
|
||||
val shift_f2_f0 = WireInit(Bool(), init = 0.U)
|
||||
val shift_f1_f0 = WireInit(Bool(), init = 0.U)
|
||||
|
||||
val f0icaf = WireInit(Bool(), init = 0.U)
|
||||
val f1icaf = WireInit(Bool(), init = 0.U)
|
||||
|
||||
val sf0val = WireInit(UInt(2.W), 0.U)
|
||||
val sf1val = WireInit(UInt(2.W), 0.U)
|
||||
|
||||
val misc0 = WireInit(UInt((MHI+1).W), 0.U)
|
||||
val misc1 = WireInit(UInt((MHI+1).W), 0.U)
|
||||
val misc2 = WireInit(UInt((MHI+1).W), 0.U)
|
||||
|
||||
val brdata1 = WireInit(UInt(12.W), init = 0.U)
|
||||
val brdata0 = WireInit(UInt(12.W), init = 0.U)
|
||||
val brdata2 = WireInit(UInt(12.W), init = 0.U)
|
||||
|
||||
val q0 = WireInit(UInt(32.W), init = 0.U)
|
||||
val q1 = WireInit(UInt(32.W), init = 0.U)
|
||||
val q2 = WireInit(UInt(32.W), init = 0.U)
|
||||
|
||||
val f1pc_in = WireInit(UInt(31.W), 0.U)
|
||||
val f0pc_in = WireInit(UInt(31.W), 0.U)
|
||||
val error_stall = WireInit(Bool(), 0.U)
|
||||
val f2_wr_en = WireInit(Bool(), 0.U)
|
||||
val shift_4B = WireInit(Bool(), 0.U)
|
||||
val f1_shift_wr_en = WireInit(Bool(), 0.U)
|
||||
val f0_shift_wr_en = WireInit(Bool(), 0.U)
|
||||
val qwen = WireInit(UInt(3.W), 0.U)
|
||||
val brdata_in = WireInit(UInt(BRDATA_SIZE.W), 0.U)
|
||||
val misc_data_in = WireInit(UInt((MHI+1).W), 0.U)
|
||||
|
||||
val fetch_to_f0 = WireInit(Bool(), 0.U)
|
||||
val fetch_to_f1 = WireInit(Bool(), 0.U)
|
||||
val fetch_to_f2 = WireInit(Bool(), 0.U)
|
||||
val f1_shift_2B = WireInit(Bool(), 0.U)
|
||||
val first4B = WireInit(Bool(), 0.U)
|
||||
val shift_2B = WireInit(Bool(), 0.U)
|
||||
val f0_shift_2B = WireInit(Bool(), 0.U)
|
||||
|
||||
// Stall if there is an error in the instrucion
|
||||
error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
|
||||
|
||||
// Flop the stall until flush
|
||||
error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
|
||||
// Write Ptr of the FP
|
||||
val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
|
||||
// Read Ptr of the FP
|
||||
val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)}
|
||||
// Fetch Instruction boundary
|
||||
val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
|
||||
val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
|
||||
val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
|
||||
|
||||
val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
|
||||
val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
|
||||
val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
|
||||
// Instrution PC to the FP
|
||||
val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode)
|
||||
val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode)
|
||||
val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode)
|
||||
// Branch data to the FP
|
||||
brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode)
|
||||
brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode)
|
||||
brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode)
|
||||
// Miscalanious data to the FP including error's
|
||||
misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode)
|
||||
misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode)
|
||||
misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode)
|
||||
// Instruction in the FP
|
||||
q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode)
|
||||
q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode)
|
||||
q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode)
|
||||
|
||||
// Shift FP logic
|
||||
f2_wr_en := fetch_to_f2
|
||||
f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B
|
||||
f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
|
||||
// FP read enable .. 3-bit for Implemenation of 1HMux
|
||||
val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
|
||||
// FP write enable .. 3-bit for Implemenation of 1HMux
|
||||
qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
|
||||
|
||||
// Read Pointer calculation
|
||||
// Next rdptr = # of consume + current ptr location (Rounding it from 2)
|
||||
rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
|
||||
(qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
|
||||
(qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U,
|
||||
(qren(0) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 2.U,
|
||||
(qren(1) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 0.U,
|
||||
(qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U,
|
||||
(!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr))
|
||||
|
||||
// As there is only 1 enqueue so each time move by 1
|
||||
wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U,
|
||||
(qwen(1) & !io.exu_flush_final).asBool -> 2.U,
|
||||
(qwen(2) & !io.exu_flush_final).asBool -> 0.U,
|
||||
(!ifvalid & !io.exu_flush_final).asBool->wrptr))
|
||||
|
||||
q2off_in := Mux1H(Seq((!qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B),
|
||||
(!qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B),
|
||||
(!qwen(2) & (rdptr===0.U)).asBool->q2off))
|
||||
|
||||
q1off_in := Mux1H(Seq((!qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B),
|
||||
(!qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B),
|
||||
(!qwen(1) & (rdptr===2.U)).asBool->q1off))
|
||||
|
||||
q0off_in := Mux1H(Seq((!qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B),
|
||||
(!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B),
|
||||
(!qwen(0) & (rdptr===1.U)).asBool -> q0off))
|
||||
|
||||
val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off,
|
||||
(rdptr===1.U)->q1off,
|
||||
(rdptr===2.U)->q2off))
|
||||
|
||||
val q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off))
|
||||
|
||||
val q0sel = Cat(q0ptr, !q0ptr)
|
||||
|
||||
val q1sel = Cat(q1ptr, !q1ptr)
|
||||
// Misc data error, access-fault, type of fault, target, offset and ghr value
|
||||
misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f,
|
||||
io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
|
||||
|
||||
val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0),
|
||||
qren(1).asBool()->Cat(misc2, misc1),
|
||||
qren(2).asBool()->Cat(misc0, misc2)))
|
||||
|
||||
val misc1eff = misceff(misceff.getWidth-1,MHI+1)
|
||||
val misc0eff = misceff(MHI, 0)
|
||||
|
||||
|
||||
val f1dbecc = misc1eff(misc1eff.getWidth-1)
|
||||
f1icaf := misc1eff(misc1eff.getWidth-2)
|
||||
val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
|
||||
val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
|
||||
val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
|
||||
val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0)
|
||||
|
||||
val f0dbecc = misc0eff(misc1eff.getWidth-1)
|
||||
f0icaf := misc0eff(misc1eff.getWidth-2)
|
||||
val f0ictype = misc0eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
|
||||
val f0prett = misc0eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
|
||||
val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
|
||||
val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
|
||||
|
||||
// Branch information
|
||||
brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
|
||||
io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
|
||||
io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
|
||||
// Effective branch information
|
||||
val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0),
|
||||
qren(1).asBool->Cat(brdata2,brdata1),
|
||||
qren(2).asBool->Cat(brdata0,brdata2)))
|
||||
|
||||
val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
|
||||
|
||||
val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
|
||||
val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
|
||||
|
||||
val f0ret = Cat(brdata0final(6),brdata0final(0))
|
||||
val f0brend = Cat(brdata0final(7),brdata0final(1))
|
||||
val f0way = Cat(brdata0final(8),brdata0final(2))
|
||||
val f0pc4 = Cat(brdata0final(9),brdata0final(3))
|
||||
val f0hist0 = Cat(brdata0final(10),brdata0final(4))
|
||||
val f0hist1 = Cat(brdata0final(11),brdata0final(5))
|
||||
|
||||
val f1ret = Cat(brdata1final(6),brdata1final(0))
|
||||
val f1brend = Cat(brdata1final(7),brdata1final(1))
|
||||
val f1way = Cat(brdata1final(8),brdata1final(2))
|
||||
val f1pc4 = Cat(brdata1final(9),brdata1final(3))
|
||||
val f1hist0 = Cat(brdata1final(10),brdata1final(4))
|
||||
val f1hist1 = Cat(brdata1final(11),brdata1final(5))
|
||||
|
||||
|
||||
f2_valid := f2val(0)
|
||||
sf1_valid := sf1val(0)
|
||||
sf0_valid := sf0val(0)
|
||||
|
||||
val consume_fb0 = !sf0val(0) & f0val(0)
|
||||
val consume_fb1 = !sf1val(0) & f1val(0)
|
||||
|
||||
// Depending on type of instruction and boundary determine how many FP to consume
|
||||
io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final
|
||||
io.ifu_fb_consume2 := consume_fb0 & consume_fb1 & !io.exu_flush_final
|
||||
|
||||
ifvalid := io.ifu_fetch_val(0)
|
||||
|
||||
// Shift logic for each dequeue
|
||||
shift_f1_f0 := !sf0_valid & sf1_valid
|
||||
shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid
|
||||
shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid
|
||||
|
||||
fetch_to_f0 := !sf0_valid & !sf1_valid & !f2_valid & ifvalid
|
||||
fetch_to_f1 := (!sf0_valid & !sf1_valid & f2_valid & ifvalid) |
|
||||
(!sf0_valid & sf1_valid & !f2_valid & ifvalid) |
|
||||
( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
|
||||
|
||||
fetch_to_f2 := (!sf0_valid & sf1_valid & f2_valid & ifvalid) |
|
||||
( sf0_valid & sf1_valid & !f2_valid & ifvalid)
|
||||
|
||||
val f0pc_plus1 = f0pc + 1.U
|
||||
|
||||
val f1pc_plus1 = f1pc + 1.U
|
||||
|
||||
val sf1pc = (Fill(31, f1_shift_2B) & f1pc_plus1) | (Fill(31, !f1_shift_2B) & f1pc)
|
||||
|
||||
f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
|
||||
shift_f2_f1.asBool->f2pc,
|
||||
(!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc))
|
||||
|
||||
f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
|
||||
shift_f2_f0.asBool->f2pc,
|
||||
shift_f1_f0.asBool->sf1pc,
|
||||
(!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1))
|
||||
|
||||
f2val_in := Mux1H(Seq((fetch_to_f2 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
|
||||
(!fetch_to_f2 & !shift_f2_f1 & !shift_f2_f0 & !io.exu_flush_final).asBool->f2val))
|
||||
|
||||
sf1val := Mux1H(Seq(f1_shift_2B.asBool->f1val(1), !f1_shift_2B.asBool->f1val))
|
||||
|
||||
f1val_in := Mux1H(Seq(( fetch_to_f1 & !io.exu_flush_final).asBool -> io.ifu_fetch_val,
|
||||
( shift_f2_f1 & !io.exu_flush_final).asBool->f2val,
|
||||
(!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
|
||||
|
||||
sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1)),
|
||||
(!shift_2B & !shift_4B).asBool->f0val))
|
||||
|
||||
f0val_in := Mux1H(Seq((fetch_to_f0 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
|
||||
( shift_f2_f0 & !io.exu_flush_final).asBool->f2val,
|
||||
( shift_f1_f0 & !io.exu_flush_final).asBool->sf1val,
|
||||
(!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val))
|
||||
|
||||
val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
|
||||
qren(1).asBool->Cat(q2,q1),
|
||||
qren(2).asBool->Cat(q0,q2)))
|
||||
val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
|
||||
|
||||
q0final := Mux1H(Seq(q0sel(0).asBool->q0eff, q0sel(1).asBool->q0eff(31,16)))
|
||||
|
||||
q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16)))
|
||||
|
||||
// Alinging the data according to the boundary of PC
|
||||
val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0))))
|
||||
|
||||
alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U)))
|
||||
|
||||
val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
|
||||
|
||||
val aligndbecc = Mux1H(Seq(f0val(1).asBool -> Fill(2,f0dbecc), (!f0val(1) & f0val(0)).asBool -> Cat(f1dbecc,f0dbecc)))
|
||||
|
||||
val alignbrend = Mux1H(Seq(f0val(1).asBool()->f0brend, (!f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0))))
|
||||
|
||||
val alignpc4 = Mux1H(Seq(f0val(1).asBool()->f0pc4, (!f0val(1) & f0val(0)).asBool->Cat(f1pc4(0),f0pc4(0))))
|
||||
|
||||
val alignret = Mux1H(Seq(f0val(1).asBool()->f0ret, (!f0val(1) & f0val(0)).asBool->Cat(f1ret(0),f0ret(0))))
|
||||
|
||||
val alignway = Mux1H(Seq(f0val(1).asBool()->f0way, (!f0val(1) & f0val(0)).asBool->Cat(f1way(0),f0way(0))))
|
||||
|
||||
val alignhist1 = Mux1H(Seq(f0val(1).asBool()->f0hist1, (!f0val(1) & f0val(0)).asBool->Cat(f1hist1(0),f0hist1(0))))
|
||||
|
||||
val alignhist0 = Mux1H(Seq(f0val(1).asBool()->f0hist0, (!f0val(1) & f0val(0)).asBool->Cat(f1hist0(0),f0hist0(0))))
|
||||
|
||||
val alignfromf1 = !f0val(1) & f0val(0)
|
||||
|
||||
val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc))
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_pc := f0pc
|
||||
|
||||
val firstpc = f0pc
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_pc4 := first4B
|
||||
|
||||
io.dec_aln.aln_dec.ifu_i0_cinst := aligndata(15,0)
|
||||
|
||||
// Instruction is compressed or not
|
||||
first4B := aligndata(1,0) === 3.U
|
||||
|
||||
val first2B = ~first4B
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_icaf_type := Mux((first4B & !f0val(1) & f0val(0) & !alignicaf(0) & !aligndbecc(0)).asBool, f1ictype, f0ictype)
|
||||
|
||||
val icaf_eff = alignicaf(1) | aligndbecc(1)
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_icaf_second := first4B & icaf_eff & alignfromf1
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0)))
|
||||
|
||||
val ifirst = aligndata
|
||||
// Expander from 16-bit to 32-bit
|
||||
val decompressed = Module(new ifu_compress_ctl())
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout))
|
||||
|
||||
// Hashing the PC
|
||||
val firstpc_hash = btb_addr_hash(f0pc)
|
||||
|
||||
val secondpc_hash = btb_addr_hash(secondpc)
|
||||
|
||||
val firstbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(firstpc) else btb_tag_hash(firstpc)
|
||||
|
||||
val secondbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(secondpc) else btb_tag_hash(secondpc)
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1))
|
||||
|
||||
val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1))
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
|
||||
(first2B & alignhist0(0)) | (first4B & alignhist0(1)))
|
||||
|
||||
val i0_ends_f1 = first4B & alignfromf1
|
||||
io.dec_aln.aln_ib.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.bits.br_start_error := (first4B & alignval(1) & alignbrend(0))
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.bits.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.bits.br_error := (io.dec_aln.aln_ib.i0_brp.valid & i0_brp_pc4 & first2B) | (io.dec_aln.aln_ib.i0_brp.valid & !i0_brp_pc4 & first4B)
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr)
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash)
|
||||
|
||||
decompressed.io.din := aligndata
|
||||
|
||||
val i0_shift = io.dec_aln.aln_dec.dec_i0_decode_d & ~error_stall
|
||||
|
||||
io.dec_aln.ifu_pmu_instr_aligned := i0_shift
|
||||
|
||||
shift_2B := i0_shift & first2B
|
||||
shift_4B := i0_shift & first4B
|
||||
|
||||
f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (f0val(0) & !f0val(1))))
|
||||
f1_shift_2B := f0val(0) & !f0val(1) & shift_4B
|
||||
|
||||
}
|
||||
//package ifu
|
||||
//import lib._
|
||||
//import chisel3._
|
||||
//import chisel3.util._
|
||||
//import include._
|
||||
//
|
||||
//class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
||||
// val io = IO(new Bundle{
|
||||
// val scan_mode = Input(Bool())
|
||||
// val active_clk = Input(Clock())
|
||||
// val ifu_async_error_start = Input(Bool()) // Error coming from mem-ctl
|
||||
// val iccm_rd_ecc_double_err = Input(Bool()) // ICCM double error coming from mem-ctl
|
||||
// val ic_access_fault_f = Input(Bool()) // Access fault in I$
|
||||
// val ic_access_fault_type_f = Input(UInt(2.W)) // Type of access fault occured
|
||||
// val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP
|
||||
// val ifu_bp_btb_target_f = Input(UInt(31.W)) // Target for the instruction enqueue in the FP
|
||||
// val ifu_bp_poffset_f = Input(UInt(12.W)) // Offset to the current PC for branch
|
||||
// val ifu_bp_hist0_f = Input(UInt(2.W)) // History to EXU
|
||||
// val ifu_bp_hist1_f = Input(UInt(2.W)) // History to EXU
|
||||
// val ifu_bp_pc4_f = Input(UInt(2.W)) // PC4
|
||||
// val ifu_bp_way_f = Input(UInt(2.W)) // Way to help in miss prediction
|
||||
// val ifu_bp_valid_f = Input(UInt(2.W)) // Valid Branch prediction
|
||||
// val ifu_bp_ret_f = Input(UInt(2.W)) // BP ret
|
||||
// val exu_flush_final = Input(Bool()) // Miss prediction
|
||||
// val dec_aln = new dec_aln() // Data going to the dec from the ALN
|
||||
// val ifu_fetch_data_f = Input(UInt(32.W)) // PC of the current instruction in the FP
|
||||
// val ifu_fetch_val = Input(UInt(2.W)) // PC boundary i.e 'x' of 2 or 4
|
||||
// val ifu_fetch_pc = Input(UInt(31.W)) // Current PC
|
||||
// /////////////////////////////////////////////////
|
||||
// val ifu_fb_consume1 = Output(Bool()) // FP used 1
|
||||
// val ifu_fb_consume2 = Output(Bool()) // FP used 2
|
||||
//
|
||||
// })
|
||||
// val MHI = 46+BHT_GHR_SIZE // 54
|
||||
// val MSIZE = 47+BHT_GHR_SIZE // 55
|
||||
// val BRDATA_SIZE = 12
|
||||
// val error_stall_in = WireInit(Bool(),0.U)
|
||||
// val alignval = WireInit(UInt(2.W), 0.U)
|
||||
// val q0final = WireInit(UInt(32.W), 0.U)
|
||||
// val q1final = WireInit(UInt(16.W), 0.U)
|
||||
// val wrptr_in = WireInit(UInt(2.W), init = 0.U)
|
||||
// val rdptr_in = WireInit(UInt(2.W), init = 0.U)
|
||||
//
|
||||
// val f2val_in = WireInit(UInt(2.W), init = 0.U)
|
||||
// val f1val_in = WireInit(UInt(2.W), init = 0.U)
|
||||
// val f0val_in = WireInit(UInt(2.W), init = 0.U)
|
||||
//
|
||||
// val q2off_in = WireInit(UInt(1.W), init = 0.U)
|
||||
// val q1off_in = WireInit(UInt(1.W), init = 0.U)
|
||||
// val q0off_in = WireInit(UInt(1.W), init = 0.U)
|
||||
//
|
||||
// val sf0_valid = WireInit(Bool(), init = 0.U)
|
||||
// val sf1_valid = WireInit(Bool(), init = 0.U)
|
||||
//
|
||||
// val f2_valid = WireInit(Bool(), init = 0.U)
|
||||
// val ifvalid = WireInit(Bool(), init = 0.U)
|
||||
// val shift_f2_f1 = WireInit(Bool(), init = 0.U)
|
||||
// val shift_f2_f0 = WireInit(Bool(), init = 0.U)
|
||||
// val shift_f1_f0 = WireInit(Bool(), init = 0.U)
|
||||
//
|
||||
// val f0icaf = WireInit(Bool(), init = 0.U)
|
||||
// val f1icaf = WireInit(Bool(), init = 0.U)
|
||||
//
|
||||
// val sf0val = WireInit(UInt(2.W), 0.U)
|
||||
// val sf1val = WireInit(UInt(2.W), 0.U)
|
||||
//
|
||||
// val misc0 = WireInit(UInt((MHI+1).W), 0.U)
|
||||
// val misc1 = WireInit(UInt((MHI+1).W), 0.U)
|
||||
// val misc2 = WireInit(UInt((MHI+1).W), 0.U)
|
||||
//
|
||||
// val brdata1 = WireInit(UInt(12.W), init = 0.U)
|
||||
// val brdata0 = WireInit(UInt(12.W), init = 0.U)
|
||||
// val brdata2 = WireInit(UInt(12.W), init = 0.U)
|
||||
//
|
||||
// val q0 = WireInit(UInt(32.W), init = 0.U)
|
||||
// val q1 = WireInit(UInt(32.W), init = 0.U)
|
||||
// val q2 = WireInit(UInt(32.W), init = 0.U)
|
||||
//
|
||||
// val f1pc_in = WireInit(UInt(31.W), 0.U)
|
||||
// val f0pc_in = WireInit(UInt(31.W), 0.U)
|
||||
// val error_stall = WireInit(Bool(), 0.U)
|
||||
// val f2_wr_en = WireInit(Bool(), 0.U)
|
||||
// val shift_4B = WireInit(Bool(), 0.U)
|
||||
// val f1_shift_wr_en = WireInit(Bool(), 0.U)
|
||||
// val f0_shift_wr_en = WireInit(Bool(), 0.U)
|
||||
// val qwen = WireInit(UInt(3.W), 0.U)
|
||||
// val brdata_in = WireInit(UInt(BRDATA_SIZE.W), 0.U)
|
||||
// val misc_data_in = WireInit(UInt((MHI+1).W), 0.U)
|
||||
//
|
||||
// val fetch_to_f0 = WireInit(Bool(), 0.U)
|
||||
// val fetch_to_f1 = WireInit(Bool(), 0.U)
|
||||
// val fetch_to_f2 = WireInit(Bool(), 0.U)
|
||||
// val f1_shift_2B = WireInit(Bool(), 0.U)
|
||||
// val first4B = WireInit(Bool(), 0.U)
|
||||
// val shift_2B = WireInit(Bool(), 0.U)
|
||||
// val f0_shift_2B = WireInit(Bool(), 0.U)
|
||||
//
|
||||
// // Stall if there is an error in the instrucion
|
||||
// error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
|
||||
//
|
||||
// // Flop the stall until flush
|
||||
// error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
|
||||
// // Write Ptr of the FP
|
||||
// val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
|
||||
// // Read Ptr of the FP
|
||||
// val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)}
|
||||
// // Fetch Instruction boundary
|
||||
// val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
|
||||
// val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
|
||||
// val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
|
||||
//
|
||||
// val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
|
||||
// val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
|
||||
// val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
|
||||
// // Instrution PC to the FP
|
||||
// val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode)
|
||||
// val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode)
|
||||
// val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode)
|
||||
// // Branch data to the FP
|
||||
// brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode)
|
||||
// brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode)
|
||||
// brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode)
|
||||
// // Miscalanious data to the FP including error's
|
||||
// misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode)
|
||||
// misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode)
|
||||
// misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode)
|
||||
// // Instruction in the FP
|
||||
// q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode)
|
||||
// q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode)
|
||||
// q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode)
|
||||
//
|
||||
// // Shift FP logic
|
||||
// f2_wr_en := fetch_to_f2
|
||||
// f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B
|
||||
// f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
|
||||
// // FP read enable .. 3-bit for Implemenation of 1HMux
|
||||
// val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
|
||||
// // FP write enable .. 3-bit for Implemenation of 1HMux
|
||||
// qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
|
||||
//
|
||||
// // Read Pointer calculation
|
||||
// // Next rdptr = # of consume + current ptr location (Rounding it from 2)
|
||||
// rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
|
||||
// (qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
|
||||
// (qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U,
|
||||
// (qren(0) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 2.U,
|
||||
// (qren(1) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 0.U,
|
||||
// (qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U,
|
||||
// (!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr))
|
||||
//
|
||||
// // As there is only 1 enqueue so each time move by 1
|
||||
// wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U,
|
||||
// (qwen(1) & !io.exu_flush_final).asBool -> 2.U,
|
||||
// (qwen(2) & !io.exu_flush_final).asBool -> 0.U,
|
||||
// (!ifvalid & !io.exu_flush_final).asBool->wrptr))
|
||||
//
|
||||
// q2off_in := Mux1H(Seq((!qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B),
|
||||
// (!qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B),
|
||||
// (!qwen(2) & (rdptr===0.U)).asBool->q2off))
|
||||
//
|
||||
// q1off_in := Mux1H(Seq((!qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B),
|
||||
// (!qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B),
|
||||
// (!qwen(1) & (rdptr===2.U)).asBool->q1off))
|
||||
//
|
||||
// q0off_in := Mux1H(Seq((!qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B),
|
||||
// (!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B),
|
||||
// (!qwen(0) & (rdptr===1.U)).asBool -> q0off))
|
||||
//
|
||||
// val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off,
|
||||
// (rdptr===1.U)->q1off,
|
||||
// (rdptr===2.U)->q2off))
|
||||
//
|
||||
// val q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off))
|
||||
//
|
||||
// val q0sel = Cat(q0ptr, !q0ptr)
|
||||
//
|
||||
// val q1sel = Cat(q1ptr, !q1ptr)
|
||||
// // Misc data error, access-fault, type of fault, target, offset and ghr value
|
||||
// misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f,
|
||||
// io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
|
||||
//
|
||||
// val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0),
|
||||
// qren(1).asBool()->Cat(misc2, misc1),
|
||||
// qren(2).asBool()->Cat(misc0, misc2)))
|
||||
//
|
||||
// val misc1eff = misceff(misceff.getWidth-1,MHI+1)
|
||||
// val misc0eff = misceff(MHI, 0)
|
||||
//
|
||||
//
|
||||
// val f1dbecc = misc1eff(misc1eff.getWidth-1)
|
||||
// f1icaf := misc1eff(misc1eff.getWidth-2)
|
||||
// val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
|
||||
// val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
|
||||
// val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
|
||||
// val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0)
|
||||
//
|
||||
// val f0dbecc = misc0eff(misc1eff.getWidth-1)
|
||||
// f0icaf := misc0eff(misc1eff.getWidth-2)
|
||||
// val f0ictype = misc0eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
|
||||
// val f0prett = misc0eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
|
||||
// val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
|
||||
// val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
|
||||
//
|
||||
// // Branch information
|
||||
// brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
|
||||
// io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
|
||||
// io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
|
||||
// // Effective branch information
|
||||
// val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0),
|
||||
// qren(1).asBool->Cat(brdata2,brdata1),
|
||||
// qren(2).asBool->Cat(brdata0,brdata2)))
|
||||
//
|
||||
// val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
|
||||
//
|
||||
// val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
|
||||
// val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
|
||||
//
|
||||
// val f0ret = Cat(brdata0final(6),brdata0final(0))
|
||||
// val f0brend = Cat(brdata0final(7),brdata0final(1))
|
||||
// val f0way = Cat(brdata0final(8),brdata0final(2))
|
||||
// val f0pc4 = Cat(brdata0final(9),brdata0final(3))
|
||||
// val f0hist0 = Cat(brdata0final(10),brdata0final(4))
|
||||
// val f0hist1 = Cat(brdata0final(11),brdata0final(5))
|
||||
//
|
||||
// val f1ret = Cat(brdata1final(6),brdata1final(0))
|
||||
// val f1brend = Cat(brdata1final(7),brdata1final(1))
|
||||
// val f1way = Cat(brdata1final(8),brdata1final(2))
|
||||
// val f1pc4 = Cat(brdata1final(9),brdata1final(3))
|
||||
// val f1hist0 = Cat(brdata1final(10),brdata1final(4))
|
||||
// val f1hist1 = Cat(brdata1final(11),brdata1final(5))
|
||||
//
|
||||
//
|
||||
// f2_valid := f2val(0)
|
||||
// sf1_valid := sf1val(0)
|
||||
// sf0_valid := sf0val(0)
|
||||
//
|
||||
// val consume_fb0 = !sf0val(0) & f0val(0)
|
||||
// val consume_fb1 = !sf1val(0) & f1val(0)
|
||||
//
|
||||
// // Depending on type of instruction and boundary determine how many FP to consume
|
||||
// io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final
|
||||
// io.ifu_fb_consume2 := consume_fb0 & consume_fb1 & !io.exu_flush_final
|
||||
//
|
||||
// ifvalid := io.ifu_fetch_val(0)
|
||||
//
|
||||
// // Shift logic for each dequeue
|
||||
// shift_f1_f0 := !sf0_valid & sf1_valid
|
||||
// shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid
|
||||
// shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid
|
||||
//
|
||||
// fetch_to_f0 := !sf0_valid & !sf1_valid & !f2_valid & ifvalid
|
||||
// fetch_to_f1 := (!sf0_valid & !sf1_valid & f2_valid & ifvalid) |
|
||||
// (!sf0_valid & sf1_valid & !f2_valid & ifvalid) |
|
||||
// ( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
|
||||
//
|
||||
// fetch_to_f2 := (!sf0_valid & sf1_valid & f2_valid & ifvalid) |
|
||||
// ( sf0_valid & sf1_valid & !f2_valid & ifvalid)
|
||||
//
|
||||
// val f0pc_plus1 = f0pc + 1.U
|
||||
//
|
||||
// val f1pc_plus1 = f1pc + 1.U
|
||||
//
|
||||
// val sf1pc = (Fill(31, f1_shift_2B) & f1pc_plus1) | (Fill(31, !f1_shift_2B) & f1pc)
|
||||
//
|
||||
// f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
|
||||
// shift_f2_f1.asBool->f2pc,
|
||||
// (!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc))
|
||||
//
|
||||
// f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
|
||||
// shift_f2_f0.asBool->f2pc,
|
||||
// shift_f1_f0.asBool->sf1pc,
|
||||
// (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1))
|
||||
//
|
||||
// f2val_in := Mux1H(Seq((fetch_to_f2 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
|
||||
// (!fetch_to_f2 & !shift_f2_f1 & !shift_f2_f0 & !io.exu_flush_final).asBool->f2val))
|
||||
//
|
||||
// sf1val := Mux1H(Seq(f1_shift_2B.asBool->f1val(1), !f1_shift_2B.asBool->f1val))
|
||||
//
|
||||
// f1val_in := Mux1H(Seq(( fetch_to_f1 & !io.exu_flush_final).asBool -> io.ifu_fetch_val,
|
||||
// ( shift_f2_f1 & !io.exu_flush_final).asBool->f2val,
|
||||
// (!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
|
||||
//
|
||||
// sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1)),
|
||||
// (!shift_2B & !shift_4B).asBool->f0val))
|
||||
//
|
||||
// f0val_in := Mux1H(Seq((fetch_to_f0 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
|
||||
// ( shift_f2_f0 & !io.exu_flush_final).asBool->f2val,
|
||||
// ( shift_f1_f0 & !io.exu_flush_final).asBool->sf1val,
|
||||
// (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val))
|
||||
//
|
||||
// val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
|
||||
// qren(1).asBool->Cat(q2,q1),
|
||||
// qren(2).asBool->Cat(q0,q2)))
|
||||
// val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
|
||||
//
|
||||
// q0final := Mux1H(Seq(q0sel(0).asBool->q0eff, q0sel(1).asBool->q0eff(31,16)))
|
||||
//
|
||||
// q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16)))
|
||||
//
|
||||
// // Alinging the data according to the boundary of PC
|
||||
// val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0))))
|
||||
//
|
||||
// alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U)))
|
||||
//
|
||||
// val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
|
||||
//
|
||||
// val aligndbecc = Mux1H(Seq(f0val(1).asBool -> Fill(2,f0dbecc), (!f0val(1) & f0val(0)).asBool -> Cat(f1dbecc,f0dbecc)))
|
||||
//
|
||||
// val alignbrend = Mux1H(Seq(f0val(1).asBool()->f0brend, (!f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0))))
|
||||
//
|
||||
// val alignpc4 = Mux1H(Seq(f0val(1).asBool()->f0pc4, (!f0val(1) & f0val(0)).asBool->Cat(f1pc4(0),f0pc4(0))))
|
||||
//
|
||||
// val alignret = Mux1H(Seq(f0val(1).asBool()->f0ret, (!f0val(1) & f0val(0)).asBool->Cat(f1ret(0),f0ret(0))))
|
||||
//
|
||||
// val alignway = Mux1H(Seq(f0val(1).asBool()->f0way, (!f0val(1) & f0val(0)).asBool->Cat(f1way(0),f0way(0))))
|
||||
//
|
||||
// val alignhist1 = Mux1H(Seq(f0val(1).asBool()->f0hist1, (!f0val(1) & f0val(0)).asBool->Cat(f1hist1(0),f0hist1(0))))
|
||||
//
|
||||
// val alignhist0 = Mux1H(Seq(f0val(1).asBool()->f0hist0, (!f0val(1) & f0val(0)).asBool->Cat(f1hist0(0),f0hist0(0))))
|
||||
//
|
||||
// val alignfromf1 = !f0val(1) & f0val(0)
|
||||
//
|
||||
// val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc))
|
||||
//
|
||||
// io.dec_aln.aln_ib.ifu_i0_pc := f0pc
|
||||
//
|
||||
// val firstpc = f0pc
|
||||
//
|
||||
// io.dec_aln.aln_ib.ifu_i0_pc4 := first4B
|
||||
//
|
||||
// io.dec_aln.aln_dec.ifu_i0_cinst := aligndata(15,0)
|
||||
//
|
||||
// // Instruction is compressed or not
|
||||
// first4B := aligndata(1,0) === 3.U
|
||||
//
|
||||
// val first2B = ~first4B
|
||||
//
|
||||
// io.dec_aln.aln_ib.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
|
||||
//
|
||||
// io.dec_aln.aln_ib.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
|
||||
//
|
||||
// io.dec_aln.aln_ib.ifu_i0_icaf_type := Mux((first4B & !f0val(1) & f0val(0) & !alignicaf(0) & !aligndbecc(0)).asBool, f1ictype, f0ictype)
|
||||
//
|
||||
// val icaf_eff = alignicaf(1) | aligndbecc(1)
|
||||
//
|
||||
// io.dec_aln.aln_ib.ifu_i0_icaf_second := first4B & icaf_eff & alignfromf1
|
||||
//
|
||||
// io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0)))
|
||||
//
|
||||
// val ifirst = aligndata
|
||||
// // Expander from 16-bit to 32-bit
|
||||
// val decompressed = Module(new ifu_compress_ctl())
|
||||
//
|
||||
// io.dec_aln.aln_ib.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout))
|
||||
//
|
||||
// // Hashing the PC
|
||||
// val firstpc_hash = btb_addr_hash(f0pc)
|
||||
//
|
||||
// val secondpc_hash = btb_addr_hash(secondpc)
|
||||
//
|
||||
// val firstbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(firstpc) else btb_tag_hash(firstpc)
|
||||
//
|
||||
// val secondbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(secondpc) else btb_tag_hash(secondpc)
|
||||
//
|
||||
// io.dec_aln.aln_ib.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
|
||||
//
|
||||
// io.dec_aln.aln_ib.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1))
|
||||
//
|
||||
// val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
|
||||
//
|
||||
// io.dec_aln.aln_ib.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1))
|
||||
//
|
||||
// io.dec_aln.aln_ib.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
|
||||
// (first2B & alignhist0(0)) | (first4B & alignhist0(1)))
|
||||
//
|
||||
// val i0_ends_f1 = first4B & alignfromf1
|
||||
// io.dec_aln.aln_ib.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
|
||||
//
|
||||
// io.dec_aln.aln_ib.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
|
||||
//
|
||||
// io.dec_aln.aln_ib.i0_brp.bits.br_start_error := (first4B & alignval(1) & alignbrend(0))
|
||||
//
|
||||
// io.dec_aln.aln_ib.i0_brp.bits.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
|
||||
//
|
||||
// io.dec_aln.aln_ib.i0_brp.bits.br_error := (io.dec_aln.aln_ib.i0_brp.valid & i0_brp_pc4 & first2B) | (io.dec_aln.aln_ib.i0_brp.valid & !i0_brp_pc4 & first4B)
|
||||
//
|
||||
// io.dec_aln.aln_ib.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
|
||||
//
|
||||
// io.dec_aln.aln_ib.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr)
|
||||
//
|
||||
// io.dec_aln.aln_ib.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash)
|
||||
//
|
||||
// decompressed.io.din := aligndata
|
||||
//
|
||||
// val i0_shift = io.dec_aln.aln_dec.dec_i0_decode_d & ~error_stall
|
||||
//
|
||||
// io.dec_aln.ifu_pmu_instr_aligned := i0_shift
|
||||
//
|
||||
// shift_2B := i0_shift & first2B
|
||||
// shift_4B := i0_shift & first4B
|
||||
//
|
||||
// f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (f0val(0) & !f0val(1))))
|
||||
// f1_shift_2B := f0val(0) & !f0val(1) & shift_4B
|
||||
//
|
||||
//}
|
||||
|
|
|
|||
|
|
@ -258,7 +258,7 @@ class aln_ib extends Bundle with lib{
|
|||
val i0_brp = Valid(new br_pkt_t)
|
||||
}
|
||||
class aln_dec extends Bundle{
|
||||
val dec_i0_decode_d = Input(Bool()) // Dec
|
||||
//val dec_i0_decode_d = Input(Bool()) // Dec
|
||||
val ifu_i0_cinst = Output(UInt(16.W)) // Dec
|
||||
}
|
||||
class dec_aln extends Bundle with lib {
|
||||
|
|
|
|||
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Reference in New Issue