obuf_timer corrected
This commit is contained in:
Laraib Khan
parent
9da7df3623
commit
92b7b00a3a
412
lsu.fir
412
lsu.fir
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@ -10809,7 +10809,7 @@ circuit lsu :
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skip @[Reg.scala 28:19]
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reg _T_1791 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when obuf_wr_en : @[Reg.scala 28:19]
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_T_1791 <= obuf_data_done_in @[Reg.scala 28:23]
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_T_1791 <= obuf_wr_timer_in @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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obuf_wr_timer <= _T_1791 @[lsu_bus_buffer.scala 365:17]
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wire WrPtr0_m : UInt<2>
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@ -14886,56 +14886,56 @@ circuit lsu :
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bus_buffer.io.lsu_pkt_r.bits.stack <= io.lsu_pkt_r.bits.stack @[lsu_bus_intf.scala 118:27]
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bus_buffer.io.lsu_pkt_r.bits.fast_int <= io.lsu_pkt_r.bits.fast_int @[lsu_bus_intf.scala 118:27]
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bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[lsu_bus_intf.scala 118:27]
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bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[lsu_bus_intf.scala 121:51]
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bus_buffer.io.end_addr_m <= io.end_addr_m @[lsu_bus_intf.scala 122:51]
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bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[lsu_bus_intf.scala 123:51]
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bus_buffer.io.end_addr_r <= io.end_addr_r @[lsu_bus_intf.scala 124:51]
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bus_buffer.io.store_data_r <= io.store_data_r @[lsu_bus_intf.scala 125:51]
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bus_buffer.io.lsu_busreq_m <= io.lsu_busreq_m @[lsu_bus_intf.scala 127:51]
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bus_buffer.io.flush_m_up <= io.flush_m_up @[lsu_bus_intf.scala 128:51]
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bus_buffer.io.flush_r <= io.flush_r @[lsu_bus_intf.scala 129:51]
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bus_buffer.io.lsu_commit_r <= io.lsu_commit_r @[lsu_bus_intf.scala 130:51]
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bus_buffer.io.lsu_axi.r.bits.last <= io.axi.r.bits.last @[lsu_bus_intf.scala 131:51]
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bus_buffer.io.lsu_axi.r.bits.resp <= io.axi.r.bits.resp @[lsu_bus_intf.scala 131:51]
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bus_buffer.io.lsu_axi.r.bits.data <= io.axi.r.bits.data @[lsu_bus_intf.scala 131:51]
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bus_buffer.io.lsu_axi.r.bits.id <= io.axi.r.bits.id @[lsu_bus_intf.scala 131:51]
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bus_buffer.io.lsu_axi.r.valid <= io.axi.r.valid @[lsu_bus_intf.scala 131:51]
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io.axi.r.ready <= bus_buffer.io.lsu_axi.r.ready @[lsu_bus_intf.scala 131:51]
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io.axi.ar.bits.qos <= bus_buffer.io.lsu_axi.ar.bits.qos @[lsu_bus_intf.scala 131:51]
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io.axi.ar.bits.prot <= bus_buffer.io.lsu_axi.ar.bits.prot @[lsu_bus_intf.scala 131:51]
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io.axi.ar.bits.cache <= bus_buffer.io.lsu_axi.ar.bits.cache @[lsu_bus_intf.scala 131:51]
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io.axi.ar.bits.lock <= bus_buffer.io.lsu_axi.ar.bits.lock @[lsu_bus_intf.scala 131:51]
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io.axi.ar.bits.burst <= bus_buffer.io.lsu_axi.ar.bits.burst @[lsu_bus_intf.scala 131:51]
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io.axi.ar.bits.size <= bus_buffer.io.lsu_axi.ar.bits.size @[lsu_bus_intf.scala 131:51]
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io.axi.ar.bits.len <= bus_buffer.io.lsu_axi.ar.bits.len @[lsu_bus_intf.scala 131:51]
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io.axi.ar.bits.region <= bus_buffer.io.lsu_axi.ar.bits.region @[lsu_bus_intf.scala 131:51]
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io.axi.ar.bits.addr <= bus_buffer.io.lsu_axi.ar.bits.addr @[lsu_bus_intf.scala 131:51]
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io.axi.ar.bits.id <= bus_buffer.io.lsu_axi.ar.bits.id @[lsu_bus_intf.scala 131:51]
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io.axi.ar.valid <= bus_buffer.io.lsu_axi.ar.valid @[lsu_bus_intf.scala 131:51]
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bus_buffer.io.lsu_axi.ar.ready <= io.axi.ar.ready @[lsu_bus_intf.scala 131:51]
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bus_buffer.io.lsu_axi.b.bits.id <= io.axi.b.bits.id @[lsu_bus_intf.scala 131:51]
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bus_buffer.io.lsu_axi.b.bits.resp <= io.axi.b.bits.resp @[lsu_bus_intf.scala 131:51]
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bus_buffer.io.lsu_axi.b.valid <= io.axi.b.valid @[lsu_bus_intf.scala 131:51]
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io.axi.b.ready <= bus_buffer.io.lsu_axi.b.ready @[lsu_bus_intf.scala 131:51]
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io.axi.w.bits.last <= bus_buffer.io.lsu_axi.w.bits.last @[lsu_bus_intf.scala 131:51]
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io.axi.w.bits.strb <= bus_buffer.io.lsu_axi.w.bits.strb @[lsu_bus_intf.scala 131:51]
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io.axi.w.bits.data <= bus_buffer.io.lsu_axi.w.bits.data @[lsu_bus_intf.scala 131:51]
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io.axi.w.valid <= bus_buffer.io.lsu_axi.w.valid @[lsu_bus_intf.scala 131:51]
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bus_buffer.io.lsu_axi.w.ready <= io.axi.w.ready @[lsu_bus_intf.scala 131:51]
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io.axi.aw.bits.qos <= bus_buffer.io.lsu_axi.aw.bits.qos @[lsu_bus_intf.scala 131:51]
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io.axi.aw.bits.prot <= bus_buffer.io.lsu_axi.aw.bits.prot @[lsu_bus_intf.scala 131:51]
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io.axi.aw.bits.cache <= bus_buffer.io.lsu_axi.aw.bits.cache @[lsu_bus_intf.scala 131:51]
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io.axi.aw.bits.lock <= bus_buffer.io.lsu_axi.aw.bits.lock @[lsu_bus_intf.scala 131:51]
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io.axi.aw.bits.burst <= bus_buffer.io.lsu_axi.aw.bits.burst @[lsu_bus_intf.scala 131:51]
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io.axi.aw.bits.size <= bus_buffer.io.lsu_axi.aw.bits.size @[lsu_bus_intf.scala 131:51]
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io.axi.aw.bits.len <= bus_buffer.io.lsu_axi.aw.bits.len @[lsu_bus_intf.scala 131:51]
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io.axi.aw.bits.region <= bus_buffer.io.lsu_axi.aw.bits.region @[lsu_bus_intf.scala 131:51]
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io.axi.aw.bits.addr <= bus_buffer.io.lsu_axi.aw.bits.addr @[lsu_bus_intf.scala 131:51]
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io.axi.aw.bits.id <= bus_buffer.io.lsu_axi.aw.bits.id @[lsu_bus_intf.scala 131:51]
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io.axi.aw.valid <= bus_buffer.io.lsu_axi.aw.valid @[lsu_bus_intf.scala 131:51]
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bus_buffer.io.lsu_axi.aw.ready <= io.axi.aw.ready @[lsu_bus_intf.scala 131:51]
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bus_buffer.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 132:51]
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io.lsu_nonblock_load_data <= bus_buffer.io.lsu_nonblock_load_data @[lsu_bus_intf.scala 133:29]
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bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[lsu_bus_intf.scala 121:38]
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bus_buffer.io.end_addr_m <= io.end_addr_m @[lsu_bus_intf.scala 122:38]
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bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[lsu_bus_intf.scala 123:38]
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bus_buffer.io.end_addr_r <= io.end_addr_r @[lsu_bus_intf.scala 124:38]
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bus_buffer.io.store_data_r <= io.store_data_r @[lsu_bus_intf.scala 125:38]
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bus_buffer.io.lsu_busreq_m <= io.lsu_busreq_m @[lsu_bus_intf.scala 127:38]
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bus_buffer.io.flush_m_up <= io.flush_m_up @[lsu_bus_intf.scala 128:38]
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bus_buffer.io.flush_r <= io.flush_r @[lsu_bus_intf.scala 129:38]
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bus_buffer.io.lsu_commit_r <= io.lsu_commit_r @[lsu_bus_intf.scala 130:38]
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bus_buffer.io.lsu_axi.r.bits.last <= io.axi.r.bits.last @[lsu_bus_intf.scala 131:38]
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bus_buffer.io.lsu_axi.r.bits.resp <= io.axi.r.bits.resp @[lsu_bus_intf.scala 131:38]
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bus_buffer.io.lsu_axi.r.bits.data <= io.axi.r.bits.data @[lsu_bus_intf.scala 131:38]
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bus_buffer.io.lsu_axi.r.bits.id <= io.axi.r.bits.id @[lsu_bus_intf.scala 131:38]
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bus_buffer.io.lsu_axi.r.valid <= io.axi.r.valid @[lsu_bus_intf.scala 131:38]
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io.axi.r.ready <= bus_buffer.io.lsu_axi.r.ready @[lsu_bus_intf.scala 131:38]
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io.axi.ar.bits.qos <= bus_buffer.io.lsu_axi.ar.bits.qos @[lsu_bus_intf.scala 131:38]
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io.axi.ar.bits.prot <= bus_buffer.io.lsu_axi.ar.bits.prot @[lsu_bus_intf.scala 131:38]
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io.axi.ar.bits.cache <= bus_buffer.io.lsu_axi.ar.bits.cache @[lsu_bus_intf.scala 131:38]
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io.axi.ar.bits.lock <= bus_buffer.io.lsu_axi.ar.bits.lock @[lsu_bus_intf.scala 131:38]
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io.axi.ar.bits.burst <= bus_buffer.io.lsu_axi.ar.bits.burst @[lsu_bus_intf.scala 131:38]
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io.axi.ar.bits.size <= bus_buffer.io.lsu_axi.ar.bits.size @[lsu_bus_intf.scala 131:38]
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io.axi.ar.bits.len <= bus_buffer.io.lsu_axi.ar.bits.len @[lsu_bus_intf.scala 131:38]
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io.axi.ar.bits.region <= bus_buffer.io.lsu_axi.ar.bits.region @[lsu_bus_intf.scala 131:38]
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io.axi.ar.bits.addr <= bus_buffer.io.lsu_axi.ar.bits.addr @[lsu_bus_intf.scala 131:38]
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io.axi.ar.bits.id <= bus_buffer.io.lsu_axi.ar.bits.id @[lsu_bus_intf.scala 131:38]
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io.axi.ar.valid <= bus_buffer.io.lsu_axi.ar.valid @[lsu_bus_intf.scala 131:38]
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bus_buffer.io.lsu_axi.ar.ready <= io.axi.ar.ready @[lsu_bus_intf.scala 131:38]
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bus_buffer.io.lsu_axi.b.bits.id <= io.axi.b.bits.id @[lsu_bus_intf.scala 131:38]
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bus_buffer.io.lsu_axi.b.bits.resp <= io.axi.b.bits.resp @[lsu_bus_intf.scala 131:38]
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bus_buffer.io.lsu_axi.b.valid <= io.axi.b.valid @[lsu_bus_intf.scala 131:38]
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io.axi.b.ready <= bus_buffer.io.lsu_axi.b.ready @[lsu_bus_intf.scala 131:38]
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io.axi.w.bits.last <= bus_buffer.io.lsu_axi.w.bits.last @[lsu_bus_intf.scala 131:38]
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io.axi.w.bits.strb <= bus_buffer.io.lsu_axi.w.bits.strb @[lsu_bus_intf.scala 131:38]
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io.axi.w.bits.data <= bus_buffer.io.lsu_axi.w.bits.data @[lsu_bus_intf.scala 131:38]
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io.axi.w.valid <= bus_buffer.io.lsu_axi.w.valid @[lsu_bus_intf.scala 131:38]
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bus_buffer.io.lsu_axi.w.ready <= io.axi.w.ready @[lsu_bus_intf.scala 131:38]
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io.axi.aw.bits.qos <= bus_buffer.io.lsu_axi.aw.bits.qos @[lsu_bus_intf.scala 131:38]
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io.axi.aw.bits.prot <= bus_buffer.io.lsu_axi.aw.bits.prot @[lsu_bus_intf.scala 131:38]
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io.axi.aw.bits.cache <= bus_buffer.io.lsu_axi.aw.bits.cache @[lsu_bus_intf.scala 131:38]
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io.axi.aw.bits.lock <= bus_buffer.io.lsu_axi.aw.bits.lock @[lsu_bus_intf.scala 131:38]
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io.axi.aw.bits.burst <= bus_buffer.io.lsu_axi.aw.bits.burst @[lsu_bus_intf.scala 131:38]
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io.axi.aw.bits.size <= bus_buffer.io.lsu_axi.aw.bits.size @[lsu_bus_intf.scala 131:38]
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io.axi.aw.bits.len <= bus_buffer.io.lsu_axi.aw.bits.len @[lsu_bus_intf.scala 131:38]
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io.axi.aw.bits.region <= bus_buffer.io.lsu_axi.aw.bits.region @[lsu_bus_intf.scala 131:38]
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io.axi.aw.bits.addr <= bus_buffer.io.lsu_axi.aw.bits.addr @[lsu_bus_intf.scala 131:38]
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io.axi.aw.bits.id <= bus_buffer.io.lsu_axi.aw.bits.id @[lsu_bus_intf.scala 131:38]
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io.axi.aw.valid <= bus_buffer.io.lsu_axi.aw.valid @[lsu_bus_intf.scala 131:38]
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bus_buffer.io.lsu_axi.aw.ready <= io.axi.aw.ready @[lsu_bus_intf.scala 131:38]
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bus_buffer.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 132:38]
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io.lsu_nonblock_load_data <= bus_buffer.io.lsu_nonblock_load_data @[lsu_bus_intf.scala 133:38]
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io.lsu_busreq_r <= bus_buffer.io.lsu_busreq_r @[lsu_bus_intf.scala 134:38]
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io.lsu_bus_buffer_pend_any <= bus_buffer.io.lsu_bus_buffer_pend_any @[lsu_bus_intf.scala 135:38]
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io.lsu_bus_buffer_full_any <= bus_buffer.io.lsu_bus_buffer_full_any @[lsu_bus_intf.scala 136:38]
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@ -15440,35 +15440,35 @@ circuit lsu :
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bus_intf.reset <= reset
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node lsu_raw_fwd_lo_m = orr(stbuf.io.stbuf_fwdbyteen_lo_m) @[lsu.scala 83:56]
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node lsu_raw_fwd_hi_m = orr(stbuf.io.stbuf_fwdbyteen_hi_m) @[lsu.scala 84:56]
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node _T = or(stbuf.io.lsu_stbuf_full_any, bus_intf.io.lsu_bus_buffer_full_any) @[lsu.scala 87:57]
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node _T_1 = or(_T, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 87:95]
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io.lsu_store_stall_any <= _T_1 @[lsu.scala 87:26]
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node _T_2 = or(bus_intf.io.lsu_bus_buffer_full_any, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 88:64]
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io.lsu_load_stall_any <= _T_2 @[lsu.scala 88:25]
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io.lsu_fastint_stall_any <= dccm_ctl.io.ld_single_ecc_error_r @[lsu.scala 89:28]
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node _T_3 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 94:58]
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node _T_4 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_3) @[lsu.scala 94:56]
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node _T_5 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 94:126]
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node _T_6 = and(_T_4, _T_5) @[lsu.scala 94:93]
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node ldst_nodma_mtor = and(_T_6, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 94:158]
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node _T_7 = or(io.dec_lsu_valid_raw_d, ldst_nodma_mtor) @[lsu.scala 95:53]
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node _T_8 = or(_T_7, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 95:71]
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node _T_9 = eq(_T_8, UInt<1>("h00")) @[lsu.scala 95:28]
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io.lsu_dma.dccm_ready <= _T_9 @[lsu.scala 95:25]
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node _T_10 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 96:58]
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node _T_11 = and(_T_10, lsu_lsc_ctl.io.addr_in_dccm_d) @[lsu.scala 96:97]
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node _T_12 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_sz, 1, 1) @[lsu.scala 96:164]
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node dma_dccm_wen = and(_T_11, _T_12) @[lsu.scala 96:129]
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node _T_13 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 97:58]
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node dma_pic_wen = and(_T_13, lsu_lsc_ctl.io.addr_in_pic_d) @[lsu.scala 97:97]
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node _T_14 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu.scala 98:100]
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node _T = or(stbuf.io.lsu_stbuf_full_any, bus_intf.io.lsu_bus_buffer_full_any) @[lsu.scala 87:60]
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node _T_1 = or(_T, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 87:98]
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io.lsu_store_stall_any <= _T_1 @[lsu.scala 87:29]
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node _T_2 = or(bus_intf.io.lsu_bus_buffer_full_any, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 88:68]
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io.lsu_load_stall_any <= _T_2 @[lsu.scala 88:29]
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io.lsu_fastint_stall_any <= dccm_ctl.io.ld_single_ecc_error_r @[lsu.scala 89:29]
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node _T_3 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 94:62]
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node _T_4 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_3) @[lsu.scala 94:60]
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node _T_5 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 94:130]
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node _T_6 = and(_T_4, _T_5) @[lsu.scala 94:97]
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node ldst_nodma_mtor = and(_T_6, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 94:162]
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node _T_7 = or(io.dec_lsu_valid_raw_d, ldst_nodma_mtor) @[lsu.scala 95:55]
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node _T_8 = or(_T_7, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 95:73]
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node _T_9 = eq(_T_8, UInt<1>("h00")) @[lsu.scala 95:30]
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io.lsu_dma.dccm_ready <= _T_9 @[lsu.scala 95:27]
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node _T_10 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 96:65]
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node _T_11 = and(_T_10, lsu_lsc_ctl.io.addr_in_dccm_d) @[lsu.scala 96:104]
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node _T_12 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_sz, 1, 1) @[lsu.scala 96:171]
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node dma_dccm_wen = and(_T_11, _T_12) @[lsu.scala 96:136]
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node _T_13 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 97:65]
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node dma_pic_wen = and(_T_13, lsu_lsc_ctl.io.addr_in_pic_d) @[lsu.scala 97:104]
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node _T_14 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu.scala 98:109]
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node _T_15 = cat(_T_14, UInt<3>("h00")) @[Cat.scala 29:58]
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node _T_16 = dshr(io.lsu_dma.dma_lsc_ctl.dma_mem_wdata, _T_15) @[lsu.scala 98:58]
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dma_dccm_wdata <= _T_16 @[lsu.scala 98:18]
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node _T_17 = bits(dma_dccm_wdata, 63, 32) @[lsu.scala 99:38]
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dma_dccm_wdata_hi <= _T_17 @[lsu.scala 99:21]
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node _T_18 = bits(dma_dccm_wdata, 31, 0) @[lsu.scala 100:38]
|
||||
dma_dccm_wdata_lo <= _T_18 @[lsu.scala 100:21]
|
||||
node _T_16 = dshr(io.lsu_dma.dma_lsc_ctl.dma_mem_wdata, _T_15) @[lsu.scala 98:67]
|
||||
dma_dccm_wdata <= _T_16 @[lsu.scala 98:27]
|
||||
node _T_17 = bits(dma_dccm_wdata, 63, 32) @[lsu.scala 99:44]
|
||||
dma_dccm_wdata_hi <= _T_17 @[lsu.scala 99:27]
|
||||
node _T_18 = bits(dma_dccm_wdata, 31, 0) @[lsu.scala 100:44]
|
||||
dma_dccm_wdata_lo <= _T_18 @[lsu.scala 100:27]
|
||||
node _T_19 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 109:58]
|
||||
node _T_20 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_19) @[lsu.scala 109:56]
|
||||
node _T_21 = eq(lsu_lsc_ctl.io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu.scala 109:130]
|
||||
|
|
@ -15477,11 +15477,11 @@ circuit lsu :
|
|||
node _T_24 = eq(_T_23, UInt<1>("h00")) @[lsu.scala 109:22]
|
||||
node _T_25 = and(_T_24, bus_intf.io.lsu_bus_buffer_empty_any) @[lsu.scala 109:167]
|
||||
io.lsu_idle_any <= _T_25 @[lsu.scala 109:19]
|
||||
node _T_26 = or(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_r.valid) @[lsu.scala 110:53]
|
||||
node _T_27 = or(_T_26, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 110:86]
|
||||
node _T_28 = eq(bus_intf.io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu.scala 110:128]
|
||||
node _T_29 = or(_T_27, _T_28) @[lsu.scala 110:126]
|
||||
io.lsu_active <= _T_29 @[lsu.scala 110:18]
|
||||
node _T_26 = or(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_r.valid) @[lsu.scala 110:54]
|
||||
node _T_27 = or(_T_26, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 110:87]
|
||||
node _T_28 = eq(bus_intf.io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu.scala 110:129]
|
||||
node _T_29 = or(_T_27, _T_28) @[lsu.scala 110:127]
|
||||
io.lsu_active <= _T_29 @[lsu.scala 110:19]
|
||||
node _T_30 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, lsu_lsc_ctl.io.lsu_pkt_r.bits.store) @[lsu.scala 112:61]
|
||||
node _T_31 = and(_T_30, lsu_lsc_ctl.io.addr_in_dccm_r) @[lsu.scala 112:99]
|
||||
node _T_32 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[lsu.scala 112:133]
|
||||
|
|
@ -15492,27 +15492,27 @@ circuit lsu :
|
|||
node _T_37 = and(_T_35, _T_36) @[lsu.scala 112:255]
|
||||
node _T_38 = or(_T_34, _T_37) @[lsu.scala 112:180]
|
||||
node store_stbuf_reqvld_r = and(_T_33, _T_38) @[lsu.scala 112:142]
|
||||
node _T_39 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 114:90]
|
||||
node _T_40 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_39) @[lsu.scala 114:52]
|
||||
node _T_41 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 114:162]
|
||||
node lsu_cmpen_m = and(_T_40, _T_41) @[lsu.scala 114:129]
|
||||
node _T_42 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 116:92]
|
||||
node _T_43 = and(_T_42, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 116:131]
|
||||
node _T_44 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_43) @[lsu.scala 116:53]
|
||||
node _T_45 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[lsu.scala 116:167]
|
||||
node _T_46 = and(_T_44, _T_45) @[lsu.scala 116:165]
|
||||
node _T_47 = eq(lsu_lsc_ctl.io.lsu_exc_m, UInt<1>("h00")) @[lsu.scala 116:181]
|
||||
node _T_48 = and(_T_46, _T_47) @[lsu.scala 116:179]
|
||||
node _T_49 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu.scala 116:209]
|
||||
node lsu_busreq_m = and(_T_48, _T_49) @[lsu.scala 116:207]
|
||||
node _T_50 = bits(lsu_lsc_ctl.io.lsu_addr_m, 0, 0) @[lsu.scala 120:127]
|
||||
node _T_51 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.half, _T_50) @[lsu.scala 120:100]
|
||||
node _T_52 = bits(lsu_lsc_ctl.io.lsu_addr_m, 1, 0) @[lsu.scala 120:197]
|
||||
node _T_53 = orr(_T_52) @[lsu.scala 120:203]
|
||||
node _T_54 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.word, _T_53) @[lsu.scala 120:170]
|
||||
node _T_55 = or(_T_51, _T_54) @[lsu.scala 120:132]
|
||||
node _T_56 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_55) @[lsu.scala 120:61]
|
||||
io.lsu_pmu_misaligned_m <= _T_56 @[lsu.scala 120:27]
|
||||
node _T_39 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 114:92]
|
||||
node _T_40 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_39) @[lsu.scala 114:54]
|
||||
node _T_41 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 114:164]
|
||||
node lsu_cmpen_m = and(_T_40, _T_41) @[lsu.scala 114:131]
|
||||
node _T_42 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 116:93]
|
||||
node _T_43 = and(_T_42, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 116:132]
|
||||
node _T_44 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_43) @[lsu.scala 116:54]
|
||||
node _T_45 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[lsu.scala 116:168]
|
||||
node _T_46 = and(_T_44, _T_45) @[lsu.scala 116:166]
|
||||
node _T_47 = eq(lsu_lsc_ctl.io.lsu_exc_m, UInt<1>("h00")) @[lsu.scala 116:182]
|
||||
node _T_48 = and(_T_46, _T_47) @[lsu.scala 116:180]
|
||||
node _T_49 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu.scala 116:210]
|
||||
node lsu_busreq_m = and(_T_48, _T_49) @[lsu.scala 116:208]
|
||||
node _T_50 = bits(lsu_lsc_ctl.io.lsu_addr_m, 0, 0) @[lsu.scala 120:139]
|
||||
node _T_51 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.half, _T_50) @[lsu.scala 120:112]
|
||||
node _T_52 = bits(lsu_lsc_ctl.io.lsu_addr_m, 1, 0) @[lsu.scala 120:209]
|
||||
node _T_53 = orr(_T_52) @[lsu.scala 120:215]
|
||||
node _T_54 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.word, _T_53) @[lsu.scala 120:182]
|
||||
node _T_55 = or(_T_51, _T_54) @[lsu.scala 120:144]
|
||||
node _T_56 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_55) @[lsu.scala 120:73]
|
||||
io.lsu_pmu_misaligned_m <= _T_56 @[lsu.scala 120:39]
|
||||
node _T_57 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.bits.load) @[lsu.scala 121:73]
|
||||
node _T_58 = and(_T_57, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 121:110]
|
||||
io.lsu_tlu.lsu_pmu_load_external_m <= _T_58 @[lsu.scala 121:39]
|
||||
|
|
@ -15724,52 +15724,52 @@ circuit lsu :
|
|||
stbuf.io.ldst_dual_r <= _T_88 @[lsu.scala 229:50]
|
||||
stbuf.io.lsu_stbuf_c1_clk <= clkdomain.io.lsu_stbuf_c1_clk @[lsu.scala 230:54]
|
||||
stbuf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 231:54]
|
||||
stbuf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 232:48]
|
||||
stbuf.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 233:48]
|
||||
stbuf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 233:48]
|
||||
stbuf.io.store_stbuf_reqvld_r <= store_stbuf_reqvld_r @[lsu.scala 234:48]
|
||||
stbuf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 235:49]
|
||||
stbuf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 236:49]
|
||||
stbuf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 232:50]
|
||||
stbuf.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 233:50]
|
||||
stbuf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 233:50]
|
||||
stbuf.io.store_stbuf_reqvld_r <= store_stbuf_reqvld_r @[lsu.scala 234:50]
|
||||
stbuf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 235:50]
|
||||
stbuf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 236:50]
|
||||
stbuf.io.store_data_hi_r <= dccm_ctl.io.store_data_hi_r @[lsu.scala 237:62]
|
||||
stbuf.io.store_data_lo_r <= dccm_ctl.io.store_data_lo_r @[lsu.scala 238:62]
|
||||
stbuf.io.store_datafn_hi_r <= dccm_ctl.io.store_datafn_hi_r @[lsu.scala 239:49]
|
||||
stbuf.io.store_datafn_hi_r <= dccm_ctl.io.store_datafn_hi_r @[lsu.scala 239:50]
|
||||
stbuf.io.store_datafn_lo_r <= dccm_ctl.io.store_datafn_lo_r @[lsu.scala 240:56]
|
||||
stbuf.io.lsu_stbuf_commit_any <= dccm_ctl.io.lsu_stbuf_commit_any @[lsu.scala 241:52]
|
||||
stbuf.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 242:64]
|
||||
stbuf.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 243:64]
|
||||
stbuf.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 244:64]
|
||||
stbuf.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[lsu.scala 245:64]
|
||||
stbuf.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 246:64]
|
||||
stbuf.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 247:64]
|
||||
stbuf.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 248:49]
|
||||
stbuf.io.lsu_stbuf_commit_any <= dccm_ctl.io.lsu_stbuf_commit_any @[lsu.scala 241:54]
|
||||
stbuf.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 242:66]
|
||||
stbuf.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 243:66]
|
||||
stbuf.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 244:66]
|
||||
stbuf.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[lsu.scala 245:66]
|
||||
stbuf.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 246:66]
|
||||
stbuf.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 247:66]
|
||||
stbuf.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 248:50]
|
||||
stbuf.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 249:56]
|
||||
stbuf.io.lsu_cmpen_m <= lsu_cmpen_m @[lsu.scala 250:54]
|
||||
stbuf.io.scan_mode <= io.scan_mode @[lsu.scala 251:49]
|
||||
stbuf.io.lsu_cmpen_m <= lsu_cmpen_m @[lsu.scala 250:56]
|
||||
stbuf.io.scan_mode <= io.scan_mode @[lsu.scala 251:50]
|
||||
ecc.io.clk_override <= io.clk_override @[lsu.scala 255:50]
|
||||
ecc.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 256:52]
|
||||
ecc.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 257:52]
|
||||
|
|
@ -15939,16 +15939,16 @@ circuit lsu :
|
|||
clkdomain.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 310:50]
|
||||
clkdomain.io.scan_mode <= io.scan_mode @[lsu.scala 311:50]
|
||||
bus_intf.io.scan_mode <= io.scan_mode @[lsu.scala 315:49]
|
||||
io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu.scala 316:26]
|
||||
io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu.scala 316:26]
|
||||
io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu.scala 316:26]
|
||||
bus_intf.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu.scala 316:26]
|
||||
bus_intf.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu.scala 316:26]
|
||||
bus_intf.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu.scala 316:26]
|
||||
io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu.scala 316:26]
|
||||
io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_error @[lsu.scala 316:26]
|
||||
io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu.scala 316:26]
|
||||
io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu.scala 316:26]
|
||||
io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu.scala 316:49]
|
||||
io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu.scala 316:49]
|
||||
io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu.scala 316:49]
|
||||
bus_intf.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu.scala 316:49]
|
||||
bus_intf.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu.scala 316:49]
|
||||
bus_intf.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu.scala 316:49]
|
||||
io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu.scala 316:49]
|
||||
io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_error @[lsu.scala 316:49]
|
||||
io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu.scala 316:49]
|
||||
io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu.scala 316:49]
|
||||
bus_intf.io.clk_override <= io.clk_override @[lsu.scala 317:49]
|
||||
bus_intf.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 318:49]
|
||||
bus_intf.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 319:49]
|
||||
|
|
@ -16029,55 +16029,55 @@ circuit lsu :
|
|||
bus_intf.io.is_sideeffects_m <= lsu_lsc_ctl.io.is_sideeffects_m @[lsu.scala 342:49]
|
||||
bus_intf.io.flush_m_up <= io.dec_tlu_flush_lower_r @[lsu.scala 343:49]
|
||||
bus_intf.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[lsu.scala 344:49]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu.scala 346:27]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu.scala 346:27]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu.scala 346:27]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu.scala 346:27]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu.scala 346:27]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu.scala 346:27]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu.scala 346:27]
|
||||
io.lsu_nonblock_load_data <= bus_intf.io.lsu_nonblock_load_data @[lsu.scala 347:29]
|
||||
lsu_busreq_r <= bus_intf.io.lsu_busreq_r @[lsu.scala 348:16]
|
||||
bus_intf.io.axi.r.bits.last <= io.axi.r.bits.last @[lsu.scala 349:49]
|
||||
bus_intf.io.axi.r.bits.resp <= io.axi.r.bits.resp @[lsu.scala 349:49]
|
||||
bus_intf.io.axi.r.bits.data <= io.axi.r.bits.data @[lsu.scala 349:49]
|
||||
bus_intf.io.axi.r.bits.id <= io.axi.r.bits.id @[lsu.scala 349:49]
|
||||
bus_intf.io.axi.r.valid <= io.axi.r.valid @[lsu.scala 349:49]
|
||||
io.axi.r.ready <= bus_intf.io.axi.r.ready @[lsu.scala 349:49]
|
||||
io.axi.ar.bits.qos <= bus_intf.io.axi.ar.bits.qos @[lsu.scala 349:49]
|
||||
io.axi.ar.bits.prot <= bus_intf.io.axi.ar.bits.prot @[lsu.scala 349:49]
|
||||
io.axi.ar.bits.cache <= bus_intf.io.axi.ar.bits.cache @[lsu.scala 349:49]
|
||||
io.axi.ar.bits.lock <= bus_intf.io.axi.ar.bits.lock @[lsu.scala 349:49]
|
||||
io.axi.ar.bits.burst <= bus_intf.io.axi.ar.bits.burst @[lsu.scala 349:49]
|
||||
io.axi.ar.bits.size <= bus_intf.io.axi.ar.bits.size @[lsu.scala 349:49]
|
||||
io.axi.ar.bits.len <= bus_intf.io.axi.ar.bits.len @[lsu.scala 349:49]
|
||||
io.axi.ar.bits.region <= bus_intf.io.axi.ar.bits.region @[lsu.scala 349:49]
|
||||
io.axi.ar.bits.addr <= bus_intf.io.axi.ar.bits.addr @[lsu.scala 349:49]
|
||||
io.axi.ar.bits.id <= bus_intf.io.axi.ar.bits.id @[lsu.scala 349:49]
|
||||
io.axi.ar.valid <= bus_intf.io.axi.ar.valid @[lsu.scala 349:49]
|
||||
bus_intf.io.axi.ar.ready <= io.axi.ar.ready @[lsu.scala 349:49]
|
||||
bus_intf.io.axi.b.bits.id <= io.axi.b.bits.id @[lsu.scala 349:49]
|
||||
bus_intf.io.axi.b.bits.resp <= io.axi.b.bits.resp @[lsu.scala 349:49]
|
||||
bus_intf.io.axi.b.valid <= io.axi.b.valid @[lsu.scala 349:49]
|
||||
io.axi.b.ready <= bus_intf.io.axi.b.ready @[lsu.scala 349:49]
|
||||
io.axi.w.bits.last <= bus_intf.io.axi.w.bits.last @[lsu.scala 349:49]
|
||||
io.axi.w.bits.strb <= bus_intf.io.axi.w.bits.strb @[lsu.scala 349:49]
|
||||
io.axi.w.bits.data <= bus_intf.io.axi.w.bits.data @[lsu.scala 349:49]
|
||||
io.axi.w.valid <= bus_intf.io.axi.w.valid @[lsu.scala 349:49]
|
||||
bus_intf.io.axi.w.ready <= io.axi.w.ready @[lsu.scala 349:49]
|
||||
io.axi.aw.bits.qos <= bus_intf.io.axi.aw.bits.qos @[lsu.scala 349:49]
|
||||
io.axi.aw.bits.prot <= bus_intf.io.axi.aw.bits.prot @[lsu.scala 349:49]
|
||||
io.axi.aw.bits.cache <= bus_intf.io.axi.aw.bits.cache @[lsu.scala 349:49]
|
||||
io.axi.aw.bits.lock <= bus_intf.io.axi.aw.bits.lock @[lsu.scala 349:49]
|
||||
io.axi.aw.bits.burst <= bus_intf.io.axi.aw.bits.burst @[lsu.scala 349:49]
|
||||
io.axi.aw.bits.size <= bus_intf.io.axi.aw.bits.size @[lsu.scala 349:49]
|
||||
io.axi.aw.bits.len <= bus_intf.io.axi.aw.bits.len @[lsu.scala 349:49]
|
||||
io.axi.aw.bits.region <= bus_intf.io.axi.aw.bits.region @[lsu.scala 349:49]
|
||||
io.axi.aw.bits.addr <= bus_intf.io.axi.aw.bits.addr @[lsu.scala 349:49]
|
||||
io.axi.aw.bits.id <= bus_intf.io.axi.aw.bits.id @[lsu.scala 349:49]
|
||||
io.axi.aw.valid <= bus_intf.io.axi.aw.valid @[lsu.scala 349:49]
|
||||
bus_intf.io.axi.aw.ready <= io.axi.aw.ready @[lsu.scala 349:49]
|
||||
bus_intf.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 350:49]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu.scala 346:31]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu.scala 346:31]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu.scala 346:31]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu.scala 346:31]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu.scala 346:31]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu.scala 346:31]
|
||||
io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu.scala 346:31]
|
||||
io.lsu_nonblock_load_data <= bus_intf.io.lsu_nonblock_load_data @[lsu.scala 347:31]
|
||||
lsu_busreq_r <= bus_intf.io.lsu_busreq_r @[lsu.scala 348:31]
|
||||
bus_intf.io.axi.r.bits.last <= io.axi.r.bits.last @[lsu.scala 349:31]
|
||||
bus_intf.io.axi.r.bits.resp <= io.axi.r.bits.resp @[lsu.scala 349:31]
|
||||
bus_intf.io.axi.r.bits.data <= io.axi.r.bits.data @[lsu.scala 349:31]
|
||||
bus_intf.io.axi.r.bits.id <= io.axi.r.bits.id @[lsu.scala 349:31]
|
||||
bus_intf.io.axi.r.valid <= io.axi.r.valid @[lsu.scala 349:31]
|
||||
io.axi.r.ready <= bus_intf.io.axi.r.ready @[lsu.scala 349:31]
|
||||
io.axi.ar.bits.qos <= bus_intf.io.axi.ar.bits.qos @[lsu.scala 349:31]
|
||||
io.axi.ar.bits.prot <= bus_intf.io.axi.ar.bits.prot @[lsu.scala 349:31]
|
||||
io.axi.ar.bits.cache <= bus_intf.io.axi.ar.bits.cache @[lsu.scala 349:31]
|
||||
io.axi.ar.bits.lock <= bus_intf.io.axi.ar.bits.lock @[lsu.scala 349:31]
|
||||
io.axi.ar.bits.burst <= bus_intf.io.axi.ar.bits.burst @[lsu.scala 349:31]
|
||||
io.axi.ar.bits.size <= bus_intf.io.axi.ar.bits.size @[lsu.scala 349:31]
|
||||
io.axi.ar.bits.len <= bus_intf.io.axi.ar.bits.len @[lsu.scala 349:31]
|
||||
io.axi.ar.bits.region <= bus_intf.io.axi.ar.bits.region @[lsu.scala 349:31]
|
||||
io.axi.ar.bits.addr <= bus_intf.io.axi.ar.bits.addr @[lsu.scala 349:31]
|
||||
io.axi.ar.bits.id <= bus_intf.io.axi.ar.bits.id @[lsu.scala 349:31]
|
||||
io.axi.ar.valid <= bus_intf.io.axi.ar.valid @[lsu.scala 349:31]
|
||||
bus_intf.io.axi.ar.ready <= io.axi.ar.ready @[lsu.scala 349:31]
|
||||
bus_intf.io.axi.b.bits.id <= io.axi.b.bits.id @[lsu.scala 349:31]
|
||||
bus_intf.io.axi.b.bits.resp <= io.axi.b.bits.resp @[lsu.scala 349:31]
|
||||
bus_intf.io.axi.b.valid <= io.axi.b.valid @[lsu.scala 349:31]
|
||||
io.axi.b.ready <= bus_intf.io.axi.b.ready @[lsu.scala 349:31]
|
||||
io.axi.w.bits.last <= bus_intf.io.axi.w.bits.last @[lsu.scala 349:31]
|
||||
io.axi.w.bits.strb <= bus_intf.io.axi.w.bits.strb @[lsu.scala 349:31]
|
||||
io.axi.w.bits.data <= bus_intf.io.axi.w.bits.data @[lsu.scala 349:31]
|
||||
io.axi.w.valid <= bus_intf.io.axi.w.valid @[lsu.scala 349:31]
|
||||
bus_intf.io.axi.w.ready <= io.axi.w.ready @[lsu.scala 349:31]
|
||||
io.axi.aw.bits.qos <= bus_intf.io.axi.aw.bits.qos @[lsu.scala 349:31]
|
||||
io.axi.aw.bits.prot <= bus_intf.io.axi.aw.bits.prot @[lsu.scala 349:31]
|
||||
io.axi.aw.bits.cache <= bus_intf.io.axi.aw.bits.cache @[lsu.scala 349:31]
|
||||
io.axi.aw.bits.lock <= bus_intf.io.axi.aw.bits.lock @[lsu.scala 349:31]
|
||||
io.axi.aw.bits.burst <= bus_intf.io.axi.aw.bits.burst @[lsu.scala 349:31]
|
||||
io.axi.aw.bits.size <= bus_intf.io.axi.aw.bits.size @[lsu.scala 349:31]
|
||||
io.axi.aw.bits.len <= bus_intf.io.axi.aw.bits.len @[lsu.scala 349:31]
|
||||
io.axi.aw.bits.region <= bus_intf.io.axi.aw.bits.region @[lsu.scala 349:31]
|
||||
io.axi.aw.bits.addr <= bus_intf.io.axi.aw.bits.addr @[lsu.scala 349:31]
|
||||
io.axi.aw.bits.id <= bus_intf.io.axi.aw.bits.id @[lsu.scala 349:31]
|
||||
io.axi.aw.valid <= bus_intf.io.axi.aw.valid @[lsu.scala 349:31]
|
||||
bus_intf.io.axi.aw.ready <= io.axi.aw.ready @[lsu.scala 349:31]
|
||||
bus_intf.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 350:31]
|
||||
reg _T_115 : UInt, clkdomain.io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 352:67]
|
||||
_T_115 <= io.lsu_dma.dma_mem_tag @[lsu.scala 352:67]
|
||||
dma_mem_tag_m <= _T_115 @[lsu.scala 352:57]
|
||||
|
|
|
|||
296
lsu.v
296
lsu.v
|
|
@ -5852,8 +5852,7 @@ module lsu_bus_buffer(
|
|||
wire [3:0] buf_numvld_cmd_any = _T_4460 + _GEN_379; // @[lsu_bus_buffer.scala 534:126]
|
||||
wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 267:72]
|
||||
wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 267:51]
|
||||
reg _T_1791; // @[Reg.scala 27:20]
|
||||
wire [2:0] obuf_wr_timer = {{2'd0}, _T_1791}; // @[lsu_bus_buffer.scala 365:17]
|
||||
reg [2:0] obuf_wr_timer; // @[Reg.scala 27:20]
|
||||
wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 267:97]
|
||||
wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 267:80]
|
||||
wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 267:114]
|
||||
|
|
@ -5926,6 +5925,10 @@ module lsu_bus_buffer(
|
|||
wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 271:101]
|
||||
wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 269:119]
|
||||
wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 269:117]
|
||||
wire _T_1056 = |buf_numvld_cmd_any; // @[lsu_bus_buffer.scala 270:75]
|
||||
wire _T_1057 = obuf_wr_timer < 3'h7; // @[lsu_bus_buffer.scala 270:95]
|
||||
wire _T_1058 = _T_1056 & _T_1057; // @[lsu_bus_buffer.scala 270:79]
|
||||
wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[lsu_bus_buffer.scala 270:123]
|
||||
wire _T_4477 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 535:63]
|
||||
wire _T_4481 = _T_4477 | _T_2590; // @[lsu_bus_buffer.scala 535:74]
|
||||
wire _T_4472 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 535:63]
|
||||
|
|
@ -6117,9 +6120,6 @@ module lsu_bus_buffer(
|
|||
wire _T_2039 = _T_2037 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:104]
|
||||
wire [2:0] _T_2041 = {_T_2025,_T_2032,_T_2039}; // @[Cat.scala 29:58]
|
||||
wire [1:0] CmdPtr1 = _T_2041[1:0]; // @[lsu_bus_buffer.scala 398:11]
|
||||
wire _T_1302 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 310:39]
|
||||
wire _T_1303 = ~_T_1302; // @[lsu_bus_buffer.scala 310:26]
|
||||
wire obuf_data_done_in = _T_1303 & bus_wdata_sent; // @[lsu_bus_buffer.scala 313:52]
|
||||
wire _T_1309 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 314:72]
|
||||
wire _T_1312 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 314:98]
|
||||
wire _T_1313 = obuf_sz_in[0] & _T_1312; // @[lsu_bus_buffer.scala 314:96]
|
||||
|
|
@ -7581,7 +7581,7 @@ initial begin
|
|||
_RAND_40 = {1{`RANDOM}};
|
||||
ibuf_sz = _RAND_40[1:0];
|
||||
_RAND_41 = {1{`RANDOM}};
|
||||
_T_1791 = _RAND_41[0:0];
|
||||
obuf_wr_timer = _RAND_41[2:0];
|
||||
_RAND_42 = {1{`RANDOM}};
|
||||
buf_nomerge_0 = _RAND_42[0:0];
|
||||
_RAND_43 = {1{`RANDOM}};
|
||||
|
|
@ -7807,7 +7807,7 @@ initial begin
|
|||
ibuf_sz = 2'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_1791 = 1'h0;
|
||||
obuf_wr_timer = 3'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
buf_nomerge_0 = 1'h0;
|
||||
|
|
@ -8628,9 +8628,13 @@ end // initial
|
|||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_1791 <= 1'h0;
|
||||
obuf_wr_timer <= 3'h0;
|
||||
end else if (obuf_wr_en) begin
|
||||
_T_1791 <= obuf_data_done_in;
|
||||
if (obuf_wr_en) begin
|
||||
obuf_wr_timer <= 3'h0;
|
||||
end else if (_T_1058) begin
|
||||
obuf_wr_timer <= _T_1060;
|
||||
end
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
||||
|
|
@ -9484,18 +9488,18 @@ module lsu_bus_intf(
|
|||
assign io_tlu_busbuff_lsu_imprecise_error_load_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 103:18]
|
||||
assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 103:18]
|
||||
assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 103:18]
|
||||
assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 131:51]
|
||||
assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 131:51]
|
||||
assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 131:51]
|
||||
assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 131:51]
|
||||
assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 131:51]
|
||||
assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 131:51]
|
||||
assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 131:38]
|
||||
assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 131:38]
|
||||
assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 131:38]
|
||||
assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 131:38]
|
||||
assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 131:38]
|
||||
assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 131:38]
|
||||
assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 134:38]
|
||||
assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 135:38]
|
||||
assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 136:38]
|
||||
assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 137:38]
|
||||
assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[lsu_bus_intf.scala 192:27]
|
||||
assign io_lsu_nonblock_load_data = bus_buffer_io_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 133:29]
|
||||
assign io_lsu_nonblock_load_data = bus_buffer_io_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 133:38]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_valid_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 143:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_tag_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 143:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_inv_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 143:19]
|
||||
|
|
@ -9522,34 +9526,34 @@ module lsu_bus_intf(
|
|||
assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 118:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 118:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 118:27]
|
||||
assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[lsu_bus_intf.scala 121:51]
|
||||
assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[lsu_bus_intf.scala 122:51]
|
||||
assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[lsu_bus_intf.scala 123:51]
|
||||
assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[lsu_bus_intf.scala 124:51]
|
||||
assign bus_buffer_io_store_data_r = io_store_data_r; // @[lsu_bus_intf.scala 125:51]
|
||||
assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[lsu_bus_intf.scala 121:38]
|
||||
assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[lsu_bus_intf.scala 122:38]
|
||||
assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[lsu_bus_intf.scala 123:38]
|
||||
assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[lsu_bus_intf.scala 124:38]
|
||||
assign bus_buffer_io_store_data_r = io_store_data_r; // @[lsu_bus_intf.scala 125:38]
|
||||
assign bus_buffer_io_no_word_merge_r = _T_19 & _T_21; // @[lsu_bus_intf.scala 144:51]
|
||||
assign bus_buffer_io_no_dword_merge_r = _T_19 & _T_27; // @[lsu_bus_intf.scala 145:51]
|
||||
assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[lsu_bus_intf.scala 127:51]
|
||||
assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[lsu_bus_intf.scala 127:38]
|
||||
assign bus_buffer_io_ld_full_hit_m = _T_369 & _T_370; // @[lsu_bus_intf.scala 151:51]
|
||||
assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[lsu_bus_intf.scala 128:51]
|
||||
assign bus_buffer_io_flush_r = io_flush_r; // @[lsu_bus_intf.scala 129:51]
|
||||
assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[lsu_bus_intf.scala 130:51]
|
||||
assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[lsu_bus_intf.scala 128:38]
|
||||
assign bus_buffer_io_flush_r = io_flush_r; // @[lsu_bus_intf.scala 129:38]
|
||||
assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[lsu_bus_intf.scala 130:38]
|
||||
assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[lsu_bus_intf.scala 146:51]
|
||||
assign bus_buffer_io_ldst_dual_d = io_ldst_dual_d; // @[lsu_bus_intf.scala 147:51]
|
||||
assign bus_buffer_io_ldst_dual_m = io_ldst_dual_m; // @[lsu_bus_intf.scala 148:51]
|
||||
assign bus_buffer_io_ldst_dual_r = io_ldst_dual_r; // @[lsu_bus_intf.scala 149:51]
|
||||
assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_31}; // @[lsu_bus_intf.scala 150:51]
|
||||
assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 131:51]
|
||||
assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 131:51]
|
||||
assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 131:51]
|
||||
assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 131:51]
|
||||
assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 131:51]
|
||||
assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 131:51]
|
||||
assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 131:51]
|
||||
assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 131:51]
|
||||
assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 131:51]
|
||||
assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 131:51]
|
||||
assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 132:51]
|
||||
assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 131:38]
|
||||
assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 131:38]
|
||||
assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 131:38]
|
||||
assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 131:38]
|
||||
assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 131:38]
|
||||
assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 131:38]
|
||||
assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 131:38]
|
||||
assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 131:38]
|
||||
assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 131:38]
|
||||
assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 131:38]
|
||||
assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 132:38]
|
||||
assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 152:51]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
|
|
@ -10218,25 +10222,25 @@ module lsu(
|
|||
wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 81:30]
|
||||
wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 81:30]
|
||||
wire bus_intf_io_lsu_bus_clk_en; // @[lsu.scala 81:30]
|
||||
wire _T = stbuf_io_lsu_stbuf_full_any | bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 87:57]
|
||||
wire _T_3 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 94:58]
|
||||
wire _T_4 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_3; // @[lsu.scala 94:56]
|
||||
wire _T_5 = lsu_lsc_ctl_io_addr_in_dccm_m | lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 94:126]
|
||||
wire _T_6 = _T_4 & _T_5; // @[lsu.scala 94:93]
|
||||
wire ldst_nodma_mtor = _T_6 & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 94:158]
|
||||
wire _T_7 = io_dec_lsu_valid_raw_d | ldst_nodma_mtor; // @[lsu.scala 95:53]
|
||||
wire _T_8 = _T_7 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 95:71]
|
||||
wire _T_10 = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 96:58]
|
||||
wire _T_11 = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 96:97]
|
||||
wire _T = stbuf_io_lsu_stbuf_full_any | bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 87:60]
|
||||
wire _T_3 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 94:62]
|
||||
wire _T_4 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_3; // @[lsu.scala 94:60]
|
||||
wire _T_5 = lsu_lsc_ctl_io_addr_in_dccm_m | lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 94:130]
|
||||
wire _T_6 = _T_4 & _T_5; // @[lsu.scala 94:97]
|
||||
wire ldst_nodma_mtor = _T_6 & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 94:162]
|
||||
wire _T_7 = io_dec_lsu_valid_raw_d | ldst_nodma_mtor; // @[lsu.scala 95:55]
|
||||
wire _T_8 = _T_7 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 95:73]
|
||||
wire _T_10 = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 96:65]
|
||||
wire _T_11 = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 96:104]
|
||||
wire [5:0] _T_15 = {io_lsu_dma_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [63:0] dma_dccm_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata >> _T_15; // @[lsu.scala 98:58]
|
||||
wire [63:0] dma_dccm_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata >> _T_15; // @[lsu.scala 98:67]
|
||||
wire _T_21 = ~lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 109:130]
|
||||
wire _T_22 = lsu_lsc_ctl_io_lsu_pkt_r_valid & _T_21; // @[lsu.scala 109:128]
|
||||
wire _T_23 = _T_4 | _T_22; // @[lsu.scala 109:94]
|
||||
wire _T_24 = ~_T_23; // @[lsu.scala 109:22]
|
||||
wire _T_26 = lsu_lsc_ctl_io_lsu_pkt_m_valid | lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 110:53]
|
||||
wire _T_27 = _T_26 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 110:86]
|
||||
wire _T_28 = ~bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 110:128]
|
||||
wire _T_26 = lsu_lsc_ctl_io_lsu_pkt_m_valid | lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 110:54]
|
||||
wire _T_27 = _T_26 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 110:87]
|
||||
wire _T_28 = ~bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 110:129]
|
||||
wire _T_30 = lsu_lsc_ctl_io_lsu_pkt_r_valid & lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 112:61]
|
||||
wire _T_31 = _T_30 & lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 112:99]
|
||||
wire _T_32 = ~io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 112:133]
|
||||
|
|
@ -10245,23 +10249,23 @@ module lsu(
|
|||
wire _T_36 = ~ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 112:257]
|
||||
wire _T_37 = _T_35 & _T_36; // @[lsu.scala 112:255]
|
||||
wire _T_38 = _T_21 | _T_37; // @[lsu.scala 112:180]
|
||||
wire _T_39 = lsu_lsc_ctl_io_lsu_pkt_m_bits_load | lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 114:90]
|
||||
wire _T_43 = _T_39 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 116:131]
|
||||
wire _T_44 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_43; // @[lsu.scala 116:53]
|
||||
wire _T_45 = ~io_dec_tlu_flush_lower_r; // @[lsu.scala 116:167]
|
||||
wire _T_46 = _T_44 & _T_45; // @[lsu.scala 116:165]
|
||||
wire _T_47 = ~lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 116:181]
|
||||
wire _T_48 = _T_46 & _T_47; // @[lsu.scala 116:179]
|
||||
wire _T_49 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 116:209]
|
||||
wire _T_51 = lsu_lsc_ctl_io_lsu_pkt_m_bits_half & lsu_lsc_ctl_io_lsu_addr_m[0]; // @[lsu.scala 120:100]
|
||||
wire _T_53 = |lsu_lsc_ctl_io_lsu_addr_m[1:0]; // @[lsu.scala 120:203]
|
||||
wire _T_54 = lsu_lsc_ctl_io_lsu_pkt_m_bits_word & _T_53; // @[lsu.scala 120:170]
|
||||
wire _T_55 = _T_51 | _T_54; // @[lsu.scala 120:132]
|
||||
wire _T_39 = lsu_lsc_ctl_io_lsu_pkt_m_bits_load | lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 114:92]
|
||||
wire _T_43 = _T_39 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 116:132]
|
||||
wire _T_44 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_43; // @[lsu.scala 116:54]
|
||||
wire _T_45 = ~io_dec_tlu_flush_lower_r; // @[lsu.scala 116:168]
|
||||
wire _T_46 = _T_44 & _T_45; // @[lsu.scala 116:166]
|
||||
wire _T_47 = ~lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 116:182]
|
||||
wire _T_48 = _T_46 & _T_47; // @[lsu.scala 116:180]
|
||||
wire _T_49 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 116:210]
|
||||
wire _T_51 = lsu_lsc_ctl_io_lsu_pkt_m_bits_half & lsu_lsc_ctl_io_lsu_addr_m[0]; // @[lsu.scala 120:112]
|
||||
wire _T_53 = |lsu_lsc_ctl_io_lsu_addr_m[1:0]; // @[lsu.scala 120:215]
|
||||
wire _T_54 = lsu_lsc_ctl_io_lsu_pkt_m_bits_word & _T_53; // @[lsu.scala 120:182]
|
||||
wire _T_55 = _T_51 | _T_54; // @[lsu.scala 120:144]
|
||||
wire _T_57 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 121:73]
|
||||
wire _T_59 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 122:73]
|
||||
wire _T_98 = lsu_lsc_ctl_io_addr_external_m & lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 333:119]
|
||||
wire [31:0] _T_100 = _T_98 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[lsu.scala 348:16]
|
||||
wire lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[lsu.scala 348:31]
|
||||
wire [31:0] _T_103 = lsu_busreq_r ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
reg [2:0] dma_mem_tag_m; // @[lsu.scala 352:67]
|
||||
reg lsu_raw_fwd_hi_r; // @[lsu.scala 353:67]
|
||||
|
|
@ -10701,7 +10705,7 @@ module lsu(
|
|||
assign io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 222:27]
|
||||
assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 222:27]
|
||||
assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 222:27]
|
||||
assign io_lsu_dma_dccm_ready = ~_T_8; // @[lsu.scala 95:25]
|
||||
assign io_lsu_dma_dccm_ready = ~_T_8; // @[lsu.scala 95:27]
|
||||
assign io_lsu_pic_picm_wren = dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 224:14]
|
||||
assign io_lsu_pic_picm_rden = dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 224:14]
|
||||
assign io_lsu_pic_picm_mken = dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 224:14]
|
||||
|
|
@ -10709,20 +10713,20 @@ module lsu(
|
|||
assign io_lsu_pic_picm_wraddr = dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 224:14]
|
||||
assign io_lsu_pic_picm_wr_data = dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 224:14]
|
||||
assign io_lsu_exu_lsu_result_m = lsu_lsc_ctl_io_lsu_exu_lsu_result_m; // @[lsu.scala 144:46]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 316:26]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 316:26]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 316:26]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 316:26]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 316:26]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 316:26]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 316:26]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 346:27]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 346:27]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 346:27]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 346:27]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 346:27]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 346:27]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 346:27]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 316:49]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 316:49]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 316:49]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 316:49]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 316:49]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 316:49]
|
||||
assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 316:49]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 346:31]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 346:31]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 346:31]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 346:31]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 346:31]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 346:31]
|
||||
assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 346:31]
|
||||
assign io_dccm_wren = dccm_ctl_io_dccm_wren; // @[lsu.scala 223:11]
|
||||
assign io_dccm_rden = dccm_ctl_io_dccm_rden; // @[lsu.scala 223:11]
|
||||
assign io_dccm_wr_addr_lo = dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 223:11]
|
||||
|
|
@ -10733,40 +10737,40 @@ module lsu(
|
|||
assign io_dccm_wr_data_hi = dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 223:11]
|
||||
assign io_lsu_tlu_lsu_pmu_load_external_m = _T_57 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 121:39]
|
||||
assign io_lsu_tlu_lsu_pmu_store_external_m = _T_59 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 122:39]
|
||||
assign io_axi_aw_valid = 1'h0; // @[lsu.scala 349:49]
|
||||
assign io_axi_aw_bits_id = 3'h0; // @[lsu.scala 349:49]
|
||||
assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 349:49]
|
||||
assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 349:49]
|
||||
assign io_axi_aw_bits_len = 8'h0; // @[lsu.scala 349:49]
|
||||
assign io_axi_aw_bits_size = 3'h3; // @[lsu.scala 349:49]
|
||||
assign io_axi_aw_bits_burst = 2'h1; // @[lsu.scala 349:49]
|
||||
assign io_axi_aw_bits_lock = 1'h0; // @[lsu.scala 349:49]
|
||||
assign io_axi_aw_bits_cache = 4'hf; // @[lsu.scala 349:49]
|
||||
assign io_axi_aw_bits_prot = 3'h1; // @[lsu.scala 349:49]
|
||||
assign io_axi_aw_bits_qos = 4'h0; // @[lsu.scala 349:49]
|
||||
assign io_axi_w_valid = 1'h0; // @[lsu.scala 349:49]
|
||||
assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 349:49]
|
||||
assign io_axi_w_bits_strb = 8'h0; // @[lsu.scala 349:49]
|
||||
assign io_axi_w_bits_last = 1'h1; // @[lsu.scala 349:49]
|
||||
assign io_axi_b_ready = 1'h1; // @[lsu.scala 349:49]
|
||||
assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 349:49]
|
||||
assign io_axi_ar_bits_id = 3'h0; // @[lsu.scala 349:49]
|
||||
assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 349:49]
|
||||
assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 349:49]
|
||||
assign io_axi_ar_bits_len = 8'h0; // @[lsu.scala 349:49]
|
||||
assign io_axi_ar_bits_size = 3'h3; // @[lsu.scala 349:49]
|
||||
assign io_axi_ar_bits_burst = 2'h1; // @[lsu.scala 349:49]
|
||||
assign io_axi_ar_bits_lock = 1'h0; // @[lsu.scala 349:49]
|
||||
assign io_axi_ar_bits_cache = 4'hf; // @[lsu.scala 349:49]
|
||||
assign io_axi_ar_bits_prot = 3'h1; // @[lsu.scala 349:49]
|
||||
assign io_axi_ar_bits_qos = 4'h0; // @[lsu.scala 349:49]
|
||||
assign io_axi_r_ready = 1'h1; // @[lsu.scala 349:49]
|
||||
assign io_axi_aw_valid = 1'h0; // @[lsu.scala 349:31]
|
||||
assign io_axi_aw_bits_id = 3'h0; // @[lsu.scala 349:31]
|
||||
assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 349:31]
|
||||
assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 349:31]
|
||||
assign io_axi_aw_bits_len = 8'h0; // @[lsu.scala 349:31]
|
||||
assign io_axi_aw_bits_size = 3'h3; // @[lsu.scala 349:31]
|
||||
assign io_axi_aw_bits_burst = 2'h1; // @[lsu.scala 349:31]
|
||||
assign io_axi_aw_bits_lock = 1'h0; // @[lsu.scala 349:31]
|
||||
assign io_axi_aw_bits_cache = 4'hf; // @[lsu.scala 349:31]
|
||||
assign io_axi_aw_bits_prot = 3'h1; // @[lsu.scala 349:31]
|
||||
assign io_axi_aw_bits_qos = 4'h0; // @[lsu.scala 349:31]
|
||||
assign io_axi_w_valid = 1'h0; // @[lsu.scala 349:31]
|
||||
assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 349:31]
|
||||
assign io_axi_w_bits_strb = 8'h0; // @[lsu.scala 349:31]
|
||||
assign io_axi_w_bits_last = 1'h1; // @[lsu.scala 349:31]
|
||||
assign io_axi_b_ready = 1'h1; // @[lsu.scala 349:31]
|
||||
assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 349:31]
|
||||
assign io_axi_ar_bits_id = 3'h0; // @[lsu.scala 349:31]
|
||||
assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 349:31]
|
||||
assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 349:31]
|
||||
assign io_axi_ar_bits_len = 8'h0; // @[lsu.scala 349:31]
|
||||
assign io_axi_ar_bits_size = 3'h3; // @[lsu.scala 349:31]
|
||||
assign io_axi_ar_bits_burst = 2'h1; // @[lsu.scala 349:31]
|
||||
assign io_axi_ar_bits_lock = 1'h0; // @[lsu.scala 349:31]
|
||||
assign io_axi_ar_bits_cache = 4'hf; // @[lsu.scala 349:31]
|
||||
assign io_axi_ar_bits_prot = 3'h1; // @[lsu.scala 349:31]
|
||||
assign io_axi_ar_bits_qos = 4'h0; // @[lsu.scala 349:31]
|
||||
assign io_axi_r_ready = 1'h1; // @[lsu.scala 349:31]
|
||||
assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 75:24]
|
||||
assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 88:25]
|
||||
assign io_lsu_store_stall_any = _T | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 87:26]
|
||||
assign io_lsu_fastint_stall_any = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 89:28]
|
||||
assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 88:29]
|
||||
assign io_lsu_store_stall_any = _T | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 87:29]
|
||||
assign io_lsu_fastint_stall_any = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 89:29]
|
||||
assign io_lsu_idle_any = _T_24 & bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 109:19]
|
||||
assign io_lsu_active = _T_27 | _T_28; // @[lsu.scala 110:18]
|
||||
assign io_lsu_active = _T_27 | _T_28; // @[lsu.scala 110:19]
|
||||
assign io_lsu_fir_addr = lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 162:49]
|
||||
assign io_lsu_fir_error = lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 163:49]
|
||||
assign io_lsu_single_ecc_error_incr = lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 160:49]
|
||||
|
|
@ -10776,9 +10780,9 @@ module lsu(
|
|||
assign io_lsu_error_pkt_r_bits_exc_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 161:49]
|
||||
assign io_lsu_error_pkt_r_bits_mscause = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 161:49]
|
||||
assign io_lsu_error_pkt_r_bits_addr = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 161:49]
|
||||
assign io_lsu_pmu_misaligned_m = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_55; // @[lsu.scala 120:27]
|
||||
assign io_lsu_pmu_misaligned_m = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_55; // @[lsu.scala 120:39]
|
||||
assign io_lsu_trigger_match_m = trigger_io_lsu_trigger_match_m; // @[lsu.scala 291:50]
|
||||
assign io_lsu_nonblock_load_data = bus_intf_io_lsu_nonblock_load_data; // @[lsu.scala 347:29]
|
||||
assign io_lsu_nonblock_load_data = bus_intf_io_lsu_nonblock_load_data; // @[lsu.scala 347:31]
|
||||
assign lsu_lsc_ctl_clock = clock;
|
||||
assign lsu_lsc_ctl_reset = reset;
|
||||
assign lsu_lsc_ctl_io_clk_override = io_clk_override; // @[lsu.scala 126:46]
|
||||
|
|
@ -10898,32 +10902,32 @@ module lsu(
|
|||
assign stbuf_reset = reset;
|
||||
assign stbuf_io_lsu_stbuf_c1_clk = clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 230:54]
|
||||
assign stbuf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 231:54]
|
||||
assign stbuf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 232:48]
|
||||
assign stbuf_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 232:48]
|
||||
assign stbuf_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 232:48]
|
||||
assign stbuf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 233:48]
|
||||
assign stbuf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 233:48]
|
||||
assign stbuf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 233:48]
|
||||
assign stbuf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 233:48]
|
||||
assign stbuf_io_lsu_pkt_r_bits_dword = lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 233:48]
|
||||
assign stbuf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 233:48]
|
||||
assign stbuf_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 233:48]
|
||||
assign stbuf_io_store_stbuf_reqvld_r = _T_33 & _T_38; // @[lsu.scala 234:48]
|
||||
assign stbuf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 235:49]
|
||||
assign stbuf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 236:49]
|
||||
assign stbuf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 232:50]
|
||||
assign stbuf_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 232:50]
|
||||
assign stbuf_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 232:50]
|
||||
assign stbuf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 233:50]
|
||||
assign stbuf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 233:50]
|
||||
assign stbuf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 233:50]
|
||||
assign stbuf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 233:50]
|
||||
assign stbuf_io_lsu_pkt_r_bits_dword = lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 233:50]
|
||||
assign stbuf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 233:50]
|
||||
assign stbuf_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 233:50]
|
||||
assign stbuf_io_store_stbuf_reqvld_r = _T_33 & _T_38; // @[lsu.scala 234:50]
|
||||
assign stbuf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 235:50]
|
||||
assign stbuf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 236:50]
|
||||
assign stbuf_io_store_data_hi_r = dccm_ctl_io_store_data_hi_r; // @[lsu.scala 237:62]
|
||||
assign stbuf_io_store_data_lo_r = dccm_ctl_io_store_data_lo_r; // @[lsu.scala 238:62]
|
||||
assign stbuf_io_store_datafn_hi_r = dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 239:49]
|
||||
assign stbuf_io_store_datafn_hi_r = dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 239:50]
|
||||
assign stbuf_io_store_datafn_lo_r = dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 240:56]
|
||||
assign stbuf_io_lsu_stbuf_commit_any = dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 241:52]
|
||||
assign stbuf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 243:64]
|
||||
assign stbuf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 244:64]
|
||||
assign stbuf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 246:64]
|
||||
assign stbuf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 247:64]
|
||||
assign stbuf_io_lsu_stbuf_commit_any = dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 241:54]
|
||||
assign stbuf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 243:66]
|
||||
assign stbuf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 244:66]
|
||||
assign stbuf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 246:66]
|
||||
assign stbuf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 247:66]
|
||||
assign stbuf_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 227:50]
|
||||
assign stbuf_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != lsu_lsc_ctl_io_end_addr_m[2]; // @[lsu.scala 228:50]
|
||||
assign stbuf_io_ldst_dual_r = lsu_lsc_ctl_io_lsu_addr_r[2] != lsu_lsc_ctl_io_end_addr_r[2]; // @[lsu.scala 229:50]
|
||||
assign stbuf_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 248:49]
|
||||
assign stbuf_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 248:50]
|
||||
assign stbuf_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 249:56]
|
||||
assign ecc_clock = clock;
|
||||
assign ecc_reset = reset;
|
||||
|
|
@ -10988,25 +10992,25 @@ module lsu(
|
|||
assign clkdomain_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 306:50]
|
||||
assign bus_intf_clock = clock;
|
||||
assign bus_intf_reset = reset;
|
||||
assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 316:26]
|
||||
assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 316:26]
|
||||
assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 316:26]
|
||||
assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 316:49]
|
||||
assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 316:49]
|
||||
assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 316:49]
|
||||
assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 318:49]
|
||||
assign bus_intf_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 319:49]
|
||||
assign bus_intf_io_lsu_bus_ibuf_c1_clk = clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 322:49]
|
||||
assign bus_intf_io_lsu_bus_buf_c1_clk = clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 324:49]
|
||||
assign bus_intf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 325:49]
|
||||
assign bus_intf_io_active_clk = io_active_clk; // @[lsu.scala 326:49]
|
||||
assign bus_intf_io_axi_aw_ready = io_axi_aw_ready; // @[lsu.scala 349:49]
|
||||
assign bus_intf_io_axi_w_ready = io_axi_w_ready; // @[lsu.scala 349:49]
|
||||
assign bus_intf_io_axi_b_valid = io_axi_b_valid; // @[lsu.scala 349:49]
|
||||
assign bus_intf_io_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu.scala 349:49]
|
||||
assign bus_intf_io_axi_b_bits_id = io_axi_b_bits_id; // @[lsu.scala 349:49]
|
||||
assign bus_intf_io_axi_ar_ready = io_axi_ar_ready; // @[lsu.scala 349:49]
|
||||
assign bus_intf_io_axi_r_valid = io_axi_r_valid; // @[lsu.scala 349:49]
|
||||
assign bus_intf_io_axi_r_bits_id = io_axi_r_bits_id; // @[lsu.scala 349:49]
|
||||
assign bus_intf_io_axi_r_bits_data = io_axi_r_bits_data; // @[lsu.scala 349:49]
|
||||
assign bus_intf_io_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu.scala 349:49]
|
||||
assign bus_intf_io_axi_aw_ready = io_axi_aw_ready; // @[lsu.scala 349:31]
|
||||
assign bus_intf_io_axi_w_ready = io_axi_w_ready; // @[lsu.scala 349:31]
|
||||
assign bus_intf_io_axi_b_valid = io_axi_b_valid; // @[lsu.scala 349:31]
|
||||
assign bus_intf_io_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu.scala 349:31]
|
||||
assign bus_intf_io_axi_b_bits_id = io_axi_b_bits_id; // @[lsu.scala 349:31]
|
||||
assign bus_intf_io_axi_ar_ready = io_axi_ar_ready; // @[lsu.scala 349:31]
|
||||
assign bus_intf_io_axi_r_valid = io_axi_r_valid; // @[lsu.scala 349:31]
|
||||
assign bus_intf_io_axi_r_bits_id = io_axi_r_bits_id; // @[lsu.scala 349:31]
|
||||
assign bus_intf_io_axi_r_bits_data = io_axi_r_bits_data; // @[lsu.scala 349:31]
|
||||
assign bus_intf_io_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu.scala 349:31]
|
||||
assign bus_intf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 328:49]
|
||||
assign bus_intf_io_lsu_busreq_m = _T_48 & _T_49; // @[lsu.scala 329:49]
|
||||
assign bus_intf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 338:49]
|
||||
|
|
@ -11034,7 +11038,7 @@ module lsu(
|
|||
assign bus_intf_io_is_sideeffects_m = lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 342:49]
|
||||
assign bus_intf_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 343:49]
|
||||
assign bus_intf_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 344:49]
|
||||
assign bus_intf_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 350:49]
|
||||
assign bus_intf_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 350:31]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,183 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_hi",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_valid",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_lo",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_busy",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_nonblock_load_data",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_tag_m",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_buffer_full_any",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_d",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_valid_m",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ld_full_hit_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_bits_load",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_flush_m_up",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_misaligned",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_trxn",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_lo",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_addr_any",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_hi",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_inv_r",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_error",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"lsu_bus_buffer.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.sv"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"lsu_bus_buffer"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
256
lsu_lsc_ctl.fir
256
lsu_lsc_ctl.fir
|
|
@ -783,45 +783,45 @@ circuit lsu_lsc_ctl :
|
|||
node _T_151 = bits(io.lsu_exu.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:103]
|
||||
node _T_152 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:122]
|
||||
node store_data_m_in = mux(_T_150, _T_151, _T_152) @[lsu_lsc_ctl.scala 223:34]
|
||||
node _T_153 = bits(io.lsu_addr_d, 2, 2) @[lsu_lsc_ctl.scala 225:61]
|
||||
reg _T_154 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:47]
|
||||
_T_154 <= _T_153 @[lsu_lsc_ctl.scala 225:47]
|
||||
node _T_155 = bits(io.end_addr_d, 2, 2) @[lsu_lsc_ctl.scala 225:123]
|
||||
reg _T_156 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:109]
|
||||
_T_156 <= _T_155 @[lsu_lsc_ctl.scala 225:109]
|
||||
node int = neq(_T_154, _T_156) @[lsu_lsc_ctl.scala 225:71]
|
||||
node _T_157 = bits(io.lsu_addr_m, 2, 2) @[lsu_lsc_ctl.scala 226:62]
|
||||
reg _T_158 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:48]
|
||||
_T_158 <= _T_157 @[lsu_lsc_ctl.scala 226:48]
|
||||
node _T_159 = bits(io.end_addr_m, 2, 2) @[lsu_lsc_ctl.scala 226:124]
|
||||
reg _T_160 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:110]
|
||||
_T_160 <= _T_159 @[lsu_lsc_ctl.scala 226:110]
|
||||
node int1 = neq(_T_158, _T_160) @[lsu_lsc_ctl.scala 226:72]
|
||||
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:72]
|
||||
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 229:72]
|
||||
reg _T_161 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:62]
|
||||
_T_161 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 230:62]
|
||||
io.lsu_addr_m <= _T_161 @[lsu_lsc_ctl.scala 230:24]
|
||||
reg _T_162 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 231:62]
|
||||
_T_162 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 231:62]
|
||||
io.lsu_addr_r <= _T_162 @[lsu_lsc_ctl.scala 231:24]
|
||||
node _T_163 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:60]
|
||||
node _T_164 = mux(int, end_addr_pre_m, _T_163) @[lsu_lsc_ctl.scala 232:27]
|
||||
node _T_165 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 232:117]
|
||||
reg _T_166 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:103]
|
||||
_T_166 <= _T_165 @[lsu_lsc_ctl.scala 232:103]
|
||||
node _T_153 = bits(io.lsu_addr_d, 2, 2) @[lsu_lsc_ctl.scala 224:62]
|
||||
reg _T_154 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 224:48]
|
||||
_T_154 <= _T_153 @[lsu_lsc_ctl.scala 224:48]
|
||||
node _T_155 = bits(io.end_addr_d, 2, 2) @[lsu_lsc_ctl.scala 224:124]
|
||||
reg _T_156 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 224:110]
|
||||
_T_156 <= _T_155 @[lsu_lsc_ctl.scala 224:110]
|
||||
node int = neq(_T_154, _T_156) @[lsu_lsc_ctl.scala 224:72]
|
||||
node _T_157 = bits(io.lsu_addr_m, 2, 2) @[lsu_lsc_ctl.scala 225:62]
|
||||
reg _T_158 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:48]
|
||||
_T_158 <= _T_157 @[lsu_lsc_ctl.scala 225:48]
|
||||
node _T_159 = bits(io.end_addr_m, 2, 2) @[lsu_lsc_ctl.scala 225:124]
|
||||
reg _T_160 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:110]
|
||||
_T_160 <= _T_159 @[lsu_lsc_ctl.scala 225:110]
|
||||
node int1 = neq(_T_158, _T_160) @[lsu_lsc_ctl.scala 225:72]
|
||||
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:72]
|
||||
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 226:72]
|
||||
reg _T_161 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62]
|
||||
_T_161 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 227:62]
|
||||
io.lsu_addr_m <= _T_161 @[lsu_lsc_ctl.scala 227:24]
|
||||
reg _T_162 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:62]
|
||||
_T_162 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 228:62]
|
||||
io.lsu_addr_r <= _T_162 @[lsu_lsc_ctl.scala 228:24]
|
||||
node _T_163 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:60]
|
||||
node _T_164 = mux(int, end_addr_pre_m, _T_163) @[lsu_lsc_ctl.scala 229:27]
|
||||
node _T_165 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:117]
|
||||
reg _T_166 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:103]
|
||||
_T_166 <= _T_165 @[lsu_lsc_ctl.scala 229:103]
|
||||
node _T_167 = cat(_T_164, _T_166) @[Cat.scala 29:58]
|
||||
io.end_addr_m <= _T_167 @[lsu_lsc_ctl.scala 232:17]
|
||||
node _T_168 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 233:61]
|
||||
node _T_169 = mux(int1, end_addr_pre_r, _T_168) @[lsu_lsc_ctl.scala 233:27]
|
||||
node _T_170 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 233:118]
|
||||
reg _T_171 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:104]
|
||||
_T_171 <= _T_170 @[lsu_lsc_ctl.scala 233:104]
|
||||
io.end_addr_m <= _T_167 @[lsu_lsc_ctl.scala 229:17]
|
||||
node _T_168 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:61]
|
||||
node _T_169 = mux(int1, end_addr_pre_r, _T_168) @[lsu_lsc_ctl.scala 230:27]
|
||||
node _T_170 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:118]
|
||||
reg _T_171 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:104]
|
||||
_T_171 <= _T_170 @[lsu_lsc_ctl.scala 230:104]
|
||||
node _T_172 = cat(_T_169, _T_171) @[Cat.scala 29:58]
|
||||
io.end_addr_r <= _T_172 @[lsu_lsc_ctl.scala 233:17]
|
||||
node _T_173 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 234:41]
|
||||
node _T_174 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 234:69]
|
||||
node _T_175 = or(_T_174, io.clk_override) @[lsu_lsc_ctl.scala 234:87]
|
||||
io.end_addr_r <= _T_172 @[lsu_lsc_ctl.scala 230:17]
|
||||
node _T_173 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 231:41]
|
||||
node _T_174 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 231:69]
|
||||
node _T_175 = or(_T_174, io.clk_override) @[lsu_lsc_ctl.scala 231:87]
|
||||
node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23]
|
||||
rvclkhdr_1.clock <= clock
|
||||
|
|
@ -833,10 +833,10 @@ circuit lsu_lsc_ctl :
|
|||
when _T_175 : @[Reg.scala 28:19]
|
||||
_T_177 <= _T_173 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
end_addr_pre_m <= _T_177 @[lsu_lsc_ctl.scala 234:18]
|
||||
node _T_178 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 235:41]
|
||||
node _T_179 = and(io.lsu_pkt_m.valid, int) @[lsu_lsc_ctl.scala 235:69]
|
||||
node _T_180 = or(_T_179, io.clk_override) @[lsu_lsc_ctl.scala 235:76]
|
||||
end_addr_pre_m <= _T_177 @[lsu_lsc_ctl.scala 231:18]
|
||||
node _T_178 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:41]
|
||||
node _T_179 = and(io.lsu_pkt_m.valid, int) @[lsu_lsc_ctl.scala 232:69]
|
||||
node _T_180 = or(_T_179, io.clk_override) @[lsu_lsc_ctl.scala 232:76]
|
||||
node _T_181 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23]
|
||||
rvclkhdr_2.clock <= clock
|
||||
|
|
@ -848,25 +848,25 @@ circuit lsu_lsc_ctl :
|
|||
when _T_180 : @[Reg.scala 28:19]
|
||||
_T_182 <= _T_178 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
end_addr_pre_r <= _T_182 @[lsu_lsc_ctl.scala 235:18]
|
||||
reg _T_183 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
|
||||
_T_183 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 236:62]
|
||||
io.addr_in_dccm_m <= _T_183 @[lsu_lsc_ctl.scala 236:24]
|
||||
reg _T_184 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62]
|
||||
_T_184 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 237:62]
|
||||
io.addr_in_dccm_r <= _T_184 @[lsu_lsc_ctl.scala 237:24]
|
||||
reg _T_185 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:62]
|
||||
_T_185 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 238:62]
|
||||
io.addr_in_pic_m <= _T_185 @[lsu_lsc_ctl.scala 238:24]
|
||||
reg _T_186 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 239:62]
|
||||
_T_186 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 239:62]
|
||||
io.addr_in_pic_r <= _T_186 @[lsu_lsc_ctl.scala 239:24]
|
||||
reg _T_187 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 240:62]
|
||||
_T_187 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 240:62]
|
||||
io.addr_external_m <= _T_187 @[lsu_lsc_ctl.scala 240:24]
|
||||
reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 241:66]
|
||||
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 241:66]
|
||||
node _T_188 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 242:77]
|
||||
end_addr_pre_r <= _T_182 @[lsu_lsc_ctl.scala 232:18]
|
||||
reg _T_183 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62]
|
||||
_T_183 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 233:62]
|
||||
io.addr_in_dccm_m <= _T_183 @[lsu_lsc_ctl.scala 233:24]
|
||||
reg _T_184 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62]
|
||||
_T_184 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 234:62]
|
||||
io.addr_in_dccm_r <= _T_184 @[lsu_lsc_ctl.scala 234:24]
|
||||
reg _T_185 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62]
|
||||
_T_185 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 235:62]
|
||||
io.addr_in_pic_m <= _T_185 @[lsu_lsc_ctl.scala 235:24]
|
||||
reg _T_186 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
|
||||
_T_186 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 236:62]
|
||||
io.addr_in_pic_r <= _T_186 @[lsu_lsc_ctl.scala 236:24]
|
||||
reg _T_187 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62]
|
||||
_T_187 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 237:62]
|
||||
io.addr_external_m <= _T_187 @[lsu_lsc_ctl.scala 237:24]
|
||||
reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:66]
|
||||
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 238:66]
|
||||
node _T_188 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 239:77]
|
||||
node _T_189 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23]
|
||||
rvclkhdr_3.clock <= clock
|
||||
|
|
@ -878,110 +878,110 @@ circuit lsu_lsc_ctl :
|
|||
when _T_188 : @[Reg.scala 28:19]
|
||||
bus_read_data_r <= io.bus_read_data_m @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_190 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 245:52]
|
||||
io.lsu_fir_addr <= _T_190 @[lsu_lsc_ctl.scala 245:28]
|
||||
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 247:28]
|
||||
node _T_191 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 249:68]
|
||||
node _T_192 = and(io.lsu_pkt_r.valid, _T_191) @[lsu_lsc_ctl.scala 249:41]
|
||||
node _T_193 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 249:96]
|
||||
node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 249:94]
|
||||
node _T_195 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 249:110]
|
||||
node _T_196 = and(_T_194, _T_195) @[lsu_lsc_ctl.scala 249:108]
|
||||
io.lsu_commit_r <= _T_196 @[lsu_lsc_ctl.scala 249:19]
|
||||
node _T_197 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 250:52]
|
||||
node _T_198 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 250:69]
|
||||
node _T_190 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 242:52]
|
||||
io.lsu_fir_addr <= _T_190 @[lsu_lsc_ctl.scala 242:28]
|
||||
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 244:28]
|
||||
node _T_191 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 246:68]
|
||||
node _T_192 = and(io.lsu_pkt_r.valid, _T_191) @[lsu_lsc_ctl.scala 246:41]
|
||||
node _T_193 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:96]
|
||||
node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 246:94]
|
||||
node _T_195 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:110]
|
||||
node _T_196 = and(_T_194, _T_195) @[lsu_lsc_ctl.scala 246:108]
|
||||
io.lsu_commit_r <= _T_196 @[lsu_lsc_ctl.scala 246:19]
|
||||
node _T_197 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 247:52]
|
||||
node _T_198 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 247:69]
|
||||
node _T_199 = bits(_T_198, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_200 = mux(_T_199, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_201 = or(_T_197, _T_200) @[lsu_lsc_ctl.scala 250:59]
|
||||
node _T_202 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 250:133]
|
||||
node _T_203 = mux(_T_202, io.lsu_exu.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 250:94]
|
||||
node _T_204 = and(_T_201, _T_203) @[lsu_lsc_ctl.scala 250:89]
|
||||
io.store_data_m <= _T_204 @[lsu_lsc_ctl.scala 250:29]
|
||||
node _T_205 = mux(io.addr_external_m, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 271:33]
|
||||
lsu_ld_datafn_m <= _T_205 @[lsu_lsc_ctl.scala 271:27]
|
||||
node _T_206 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 272:49]
|
||||
node _T_207 = mux(_T_206, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 272:33]
|
||||
lsu_ld_datafn_corr_r <= _T_207 @[lsu_lsc_ctl.scala 272:27]
|
||||
node _T_208 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 273:74]
|
||||
node _T_201 = or(_T_197, _T_200) @[lsu_lsc_ctl.scala 247:59]
|
||||
node _T_202 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 247:133]
|
||||
node _T_203 = mux(_T_202, io.lsu_exu.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 247:94]
|
||||
node _T_204 = and(_T_201, _T_203) @[lsu_lsc_ctl.scala 247:89]
|
||||
io.store_data_m <= _T_204 @[lsu_lsc_ctl.scala 247:29]
|
||||
node _T_205 = mux(io.addr_external_m, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 268:33]
|
||||
lsu_ld_datafn_m <= _T_205 @[lsu_lsc_ctl.scala 268:27]
|
||||
node _T_206 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 269:49]
|
||||
node _T_207 = mux(_T_206, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 269:33]
|
||||
lsu_ld_datafn_corr_r <= _T_207 @[lsu_lsc_ctl.scala 269:27]
|
||||
node _T_208 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 270:74]
|
||||
node _T_209 = bits(_T_208, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_210 = mux(_T_209, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_211 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 273:133]
|
||||
node _T_211 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 270:133]
|
||||
node _T_212 = cat(UInt<24>("h00"), _T_211) @[Cat.scala 29:58]
|
||||
node _T_213 = and(_T_210, _T_212) @[lsu_lsc_ctl.scala 273:102]
|
||||
node _T_214 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 274:43]
|
||||
node _T_213 = and(_T_210, _T_212) @[lsu_lsc_ctl.scala 270:102]
|
||||
node _T_214 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 271:43]
|
||||
node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_216 = mux(_T_215, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_217 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 274:102]
|
||||
node _T_217 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 271:102]
|
||||
node _T_218 = cat(UInt<16>("h00"), _T_217) @[Cat.scala 29:58]
|
||||
node _T_219 = and(_T_216, _T_218) @[lsu_lsc_ctl.scala 274:71]
|
||||
node _T_220 = or(_T_213, _T_219) @[lsu_lsc_ctl.scala 273:141]
|
||||
node _T_221 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 275:17]
|
||||
node _T_222 = and(_T_221, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 275:43]
|
||||
node _T_219 = and(_T_216, _T_218) @[lsu_lsc_ctl.scala 271:71]
|
||||
node _T_220 = or(_T_213, _T_219) @[lsu_lsc_ctl.scala 270:141]
|
||||
node _T_221 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 272:17]
|
||||
node _T_222 = and(_T_221, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 272:43]
|
||||
node _T_223 = bits(_T_222, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_224 = mux(_T_223, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_225 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 275:102]
|
||||
node _T_225 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 272:102]
|
||||
node _T_226 = bits(_T_225, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_227 = mux(_T_226, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_228 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 275:125]
|
||||
node _T_228 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 272:125]
|
||||
node _T_229 = cat(_T_227, _T_228) @[Cat.scala 29:58]
|
||||
node _T_230 = and(_T_224, _T_229) @[lsu_lsc_ctl.scala 275:71]
|
||||
node _T_231 = or(_T_220, _T_230) @[lsu_lsc_ctl.scala 274:114]
|
||||
node _T_232 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 276:17]
|
||||
node _T_233 = and(_T_232, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 276:43]
|
||||
node _T_230 = and(_T_224, _T_229) @[lsu_lsc_ctl.scala 272:71]
|
||||
node _T_231 = or(_T_220, _T_230) @[lsu_lsc_ctl.scala 271:114]
|
||||
node _T_232 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 273:17]
|
||||
node _T_233 = and(_T_232, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 273:43]
|
||||
node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_236 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 276:101]
|
||||
node _T_236 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 273:101]
|
||||
node _T_237 = bits(_T_236, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_238 = mux(_T_237, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_239 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 276:125]
|
||||
node _T_239 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 273:125]
|
||||
node _T_240 = cat(_T_238, _T_239) @[Cat.scala 29:58]
|
||||
node _T_241 = and(_T_235, _T_240) @[lsu_lsc_ctl.scala 276:71]
|
||||
node _T_242 = or(_T_231, _T_241) @[lsu_lsc_ctl.scala 275:134]
|
||||
node _T_241 = and(_T_235, _T_240) @[lsu_lsc_ctl.scala 273:71]
|
||||
node _T_242 = or(_T_231, _T_241) @[lsu_lsc_ctl.scala 272:134]
|
||||
node _T_243 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_244 = mux(_T_243, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_245 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 277:60]
|
||||
node _T_246 = and(_T_244, _T_245) @[lsu_lsc_ctl.scala 277:43]
|
||||
node _T_247 = or(_T_242, _T_246) @[lsu_lsc_ctl.scala 276:134]
|
||||
io.lsu_exu.lsu_result_m <= _T_247 @[lsu_lsc_ctl.scala 273:35]
|
||||
node _T_248 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 278:66]
|
||||
node _T_245 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 274:60]
|
||||
node _T_246 = and(_T_244, _T_245) @[lsu_lsc_ctl.scala 274:43]
|
||||
node _T_247 = or(_T_242, _T_246) @[lsu_lsc_ctl.scala 273:134]
|
||||
io.lsu_exu.lsu_result_m <= _T_247 @[lsu_lsc_ctl.scala 270:35]
|
||||
node _T_248 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 275:66]
|
||||
node _T_249 = bits(_T_248, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_250 = mux(_T_249, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_251 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 278:130]
|
||||
node _T_251 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 275:130]
|
||||
node _T_252 = cat(UInt<24>("h00"), _T_251) @[Cat.scala 29:58]
|
||||
node _T_253 = and(_T_250, _T_252) @[lsu_lsc_ctl.scala 278:94]
|
||||
node _T_254 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 279:43]
|
||||
node _T_253 = and(_T_250, _T_252) @[lsu_lsc_ctl.scala 275:94]
|
||||
node _T_254 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 276:43]
|
||||
node _T_255 = bits(_T_254, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_256 = mux(_T_255, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_257 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 279:107]
|
||||
node _T_257 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 276:107]
|
||||
node _T_258 = cat(UInt<16>("h00"), _T_257) @[Cat.scala 29:58]
|
||||
node _T_259 = and(_T_256, _T_258) @[lsu_lsc_ctl.scala 279:71]
|
||||
node _T_260 = or(_T_253, _T_259) @[lsu_lsc_ctl.scala 278:138]
|
||||
node _T_261 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 280:17]
|
||||
node _T_262 = and(_T_261, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 280:43]
|
||||
node _T_259 = and(_T_256, _T_258) @[lsu_lsc_ctl.scala 276:71]
|
||||
node _T_260 = or(_T_253, _T_259) @[lsu_lsc_ctl.scala 275:138]
|
||||
node _T_261 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17]
|
||||
node _T_262 = and(_T_261, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 277:43]
|
||||
node _T_263 = bits(_T_262, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_264 = mux(_T_263, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 280:107]
|
||||
node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 277:107]
|
||||
node _T_266 = bits(_T_265, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_267 = mux(_T_266, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_268 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 280:135]
|
||||
node _T_268 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 277:135]
|
||||
node _T_269 = cat(_T_267, _T_268) @[Cat.scala 29:58]
|
||||
node _T_270 = and(_T_264, _T_269) @[lsu_lsc_ctl.scala 280:71]
|
||||
node _T_271 = or(_T_260, _T_270) @[lsu_lsc_ctl.scala 279:119]
|
||||
node _T_272 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 281:17]
|
||||
node _T_273 = and(_T_272, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 281:43]
|
||||
node _T_270 = and(_T_264, _T_269) @[lsu_lsc_ctl.scala 277:71]
|
||||
node _T_271 = or(_T_260, _T_270) @[lsu_lsc_ctl.scala 276:119]
|
||||
node _T_272 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 278:17]
|
||||
node _T_273 = and(_T_272, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 278:43]
|
||||
node _T_274 = bits(_T_273, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 281:106]
|
||||
node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 278:106]
|
||||
node _T_277 = bits(_T_276, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_278 = mux(_T_277, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_279 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 281:135]
|
||||
node _T_279 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 278:135]
|
||||
node _T_280 = cat(_T_278, _T_279) @[Cat.scala 29:58]
|
||||
node _T_281 = and(_T_275, _T_280) @[lsu_lsc_ctl.scala 281:71]
|
||||
node _T_282 = or(_T_271, _T_281) @[lsu_lsc_ctl.scala 280:144]
|
||||
node _T_281 = and(_T_275, _T_280) @[lsu_lsc_ctl.scala 278:71]
|
||||
node _T_282 = or(_T_271, _T_281) @[lsu_lsc_ctl.scala 277:144]
|
||||
node _T_283 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_284 = mux(_T_283, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_285 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 282:65]
|
||||
node _T_286 = and(_T_284, _T_285) @[lsu_lsc_ctl.scala 282:43]
|
||||
node _T_287 = or(_T_282, _T_286) @[lsu_lsc_ctl.scala 281:144]
|
||||
io.lsu_result_corr_r <= _T_287 @[lsu_lsc_ctl.scala 278:27]
|
||||
node _T_285 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 279:65]
|
||||
node _T_286 = and(_T_284, _T_285) @[lsu_lsc_ctl.scala 279:43]
|
||||
node _T_287 = or(_T_282, _T_286) @[lsu_lsc_ctl.scala 278:144]
|
||||
io.lsu_result_corr_r <= _T_287 @[lsu_lsc_ctl.scala 275:27]
|
||||
|
||||
|
|
|
|||
150
lsu_lsc_ctl.v
150
lsu_lsc_ctl.v
|
|
@ -526,92 +526,92 @@ module lsu_lsc_ctl(
|
|||
reg _T_143; // @[lsu_lsc_ctl.scala 219:65]
|
||||
wire [5:0] _T_146 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_146; // @[lsu_lsc_ctl.scala 221:66]
|
||||
reg _T_154; // @[lsu_lsc_ctl.scala 225:47]
|
||||
reg _T_156; // @[lsu_lsc_ctl.scala 225:109]
|
||||
wire int_ = _T_154 != _T_156; // @[lsu_lsc_ctl.scala 225:71]
|
||||
reg _T_158; // @[lsu_lsc_ctl.scala 226:48]
|
||||
reg _T_160; // @[lsu_lsc_ctl.scala 226:110]
|
||||
wire int1 = _T_158 != _T_160; // @[lsu_lsc_ctl.scala 226:72]
|
||||
reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 229:72]
|
||||
reg [31:0] _T_161; // @[lsu_lsc_ctl.scala 230:62]
|
||||
reg [31:0] _T_162; // @[lsu_lsc_ctl.scala 231:62]
|
||||
reg _T_154; // @[lsu_lsc_ctl.scala 224:48]
|
||||
reg _T_156; // @[lsu_lsc_ctl.scala 224:110]
|
||||
wire int_ = _T_154 != _T_156; // @[lsu_lsc_ctl.scala 224:72]
|
||||
reg _T_158; // @[lsu_lsc_ctl.scala 225:48]
|
||||
reg _T_160; // @[lsu_lsc_ctl.scala 225:110]
|
||||
wire int1 = _T_158 != _T_160; // @[lsu_lsc_ctl.scala 225:72]
|
||||
reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 226:72]
|
||||
reg [31:0] _T_161; // @[lsu_lsc_ctl.scala 227:62]
|
||||
reg [31:0] _T_162; // @[lsu_lsc_ctl.scala 228:62]
|
||||
reg [28:0] end_addr_pre_m; // @[Reg.scala 27:20]
|
||||
wire [28:0] _T_164 = int_ ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 232:27]
|
||||
reg [2:0] _T_166; // @[lsu_lsc_ctl.scala 232:103]
|
||||
wire [28:0] _T_164 = int_ ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 229:27]
|
||||
reg [2:0] _T_166; // @[lsu_lsc_ctl.scala 229:103]
|
||||
reg [28:0] end_addr_pre_r; // @[Reg.scala 27:20]
|
||||
wire [28:0] _T_169 = int1 ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 233:27]
|
||||
reg [2:0] _T_171; // @[lsu_lsc_ctl.scala 233:104]
|
||||
wire _T_174 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 234:69]
|
||||
wire _T_175 = _T_174 | io_clk_override; // @[lsu_lsc_ctl.scala 234:87]
|
||||
wire _T_179 = io_lsu_pkt_m_valid & int_; // @[lsu_lsc_ctl.scala 235:69]
|
||||
wire _T_180 = _T_179 | io_clk_override; // @[lsu_lsc_ctl.scala 235:76]
|
||||
reg _T_183; // @[lsu_lsc_ctl.scala 236:62]
|
||||
reg _T_184; // @[lsu_lsc_ctl.scala 237:62]
|
||||
reg _T_185; // @[lsu_lsc_ctl.scala 238:62]
|
||||
reg _T_186; // @[lsu_lsc_ctl.scala 239:62]
|
||||
reg _T_187; // @[lsu_lsc_ctl.scala 240:62]
|
||||
reg addr_external_r; // @[lsu_lsc_ctl.scala 241:66]
|
||||
wire _T_188 = io_addr_external_m | io_clk_override; // @[lsu_lsc_ctl.scala 242:77]
|
||||
wire [28:0] _T_169 = int1 ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 230:27]
|
||||
reg [2:0] _T_171; // @[lsu_lsc_ctl.scala 230:104]
|
||||
wire _T_174 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 231:69]
|
||||
wire _T_175 = _T_174 | io_clk_override; // @[lsu_lsc_ctl.scala 231:87]
|
||||
wire _T_179 = io_lsu_pkt_m_valid & int_; // @[lsu_lsc_ctl.scala 232:69]
|
||||
wire _T_180 = _T_179 | io_clk_override; // @[lsu_lsc_ctl.scala 232:76]
|
||||
reg _T_183; // @[lsu_lsc_ctl.scala 233:62]
|
||||
reg _T_184; // @[lsu_lsc_ctl.scala 234:62]
|
||||
reg _T_185; // @[lsu_lsc_ctl.scala 235:62]
|
||||
reg _T_186; // @[lsu_lsc_ctl.scala 236:62]
|
||||
reg _T_187; // @[lsu_lsc_ctl.scala 237:62]
|
||||
reg addr_external_r; // @[lsu_lsc_ctl.scala 238:66]
|
||||
wire _T_188 = io_addr_external_m | io_clk_override; // @[lsu_lsc_ctl.scala 239:77]
|
||||
reg [31:0] bus_read_data_r; // @[Reg.scala 27:20]
|
||||
wire _T_191 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 249:68]
|
||||
wire _T_192 = io_lsu_pkt_r_valid & _T_191; // @[lsu_lsc_ctl.scala 249:41]
|
||||
wire _T_193 = ~io_flush_r; // @[lsu_lsc_ctl.scala 249:96]
|
||||
wire _T_194 = _T_192 & _T_193; // @[lsu_lsc_ctl.scala 249:94]
|
||||
wire _T_195 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 249:110]
|
||||
wire _T_198 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 250:69]
|
||||
wire _T_191 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 246:68]
|
||||
wire _T_192 = io_lsu_pkt_r_valid & _T_191; // @[lsu_lsc_ctl.scala 246:41]
|
||||
wire _T_193 = ~io_flush_r; // @[lsu_lsc_ctl.scala 246:96]
|
||||
wire _T_194 = _T_192 & _T_193; // @[lsu_lsc_ctl.scala 246:94]
|
||||
wire _T_195 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 246:110]
|
||||
wire _T_198 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 247:69]
|
||||
wire [31:0] _T_200 = _T_198 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_201 = io_picm_mask_data_m | _T_200; // @[lsu_lsc_ctl.scala 250:59]
|
||||
wire [31:0] _T_203 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_exu_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 250:94]
|
||||
wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 271:33]
|
||||
wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 272:33]
|
||||
wire _T_208 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 273:74]
|
||||
wire [31:0] _T_201 = io_picm_mask_data_m | _T_200; // @[lsu_lsc_ctl.scala 247:59]
|
||||
wire [31:0] _T_203 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_exu_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 247:94]
|
||||
wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 268:33]
|
||||
wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 269:33]
|
||||
wire _T_208 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 270:74]
|
||||
wire [31:0] _T_210 = _T_208 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_212 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_213 = _T_210 & _T_212; // @[lsu_lsc_ctl.scala 273:102]
|
||||
wire _T_214 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 274:43]
|
||||
wire [31:0] _T_213 = _T_210 & _T_212; // @[lsu_lsc_ctl.scala 270:102]
|
||||
wire _T_214 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 271:43]
|
||||
wire [31:0] _T_216 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_218 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_219 = _T_216 & _T_218; // @[lsu_lsc_ctl.scala 274:71]
|
||||
wire [31:0] _T_220 = _T_213 | _T_219; // @[lsu_lsc_ctl.scala 273:141]
|
||||
wire _T_221 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 275:17]
|
||||
wire _T_222 = _T_221 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 275:43]
|
||||
wire [31:0] _T_219 = _T_216 & _T_218; // @[lsu_lsc_ctl.scala 271:71]
|
||||
wire [31:0] _T_220 = _T_213 | _T_219; // @[lsu_lsc_ctl.scala 270:141]
|
||||
wire _T_221 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 272:17]
|
||||
wire _T_222 = _T_221 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 272:43]
|
||||
wire [31:0] _T_224 = _T_222 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [23:0] _T_227 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_229 = {_T_227,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_230 = _T_224 & _T_229; // @[lsu_lsc_ctl.scala 275:71]
|
||||
wire [31:0] _T_231 = _T_220 | _T_230; // @[lsu_lsc_ctl.scala 274:114]
|
||||
wire _T_233 = _T_221 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 276:43]
|
||||
wire [31:0] _T_230 = _T_224 & _T_229; // @[lsu_lsc_ctl.scala 272:71]
|
||||
wire [31:0] _T_231 = _T_220 | _T_230; // @[lsu_lsc_ctl.scala 271:114]
|
||||
wire _T_233 = _T_221 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 273:43]
|
||||
wire [31:0] _T_235 = _T_233 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [15:0] _T_238 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_240 = {_T_238,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_241 = _T_235 & _T_240; // @[lsu_lsc_ctl.scala 276:71]
|
||||
wire [31:0] _T_242 = _T_231 | _T_241; // @[lsu_lsc_ctl.scala 275:134]
|
||||
wire [31:0] _T_241 = _T_235 & _T_240; // @[lsu_lsc_ctl.scala 273:71]
|
||||
wire [31:0] _T_242 = _T_231 | _T_241; // @[lsu_lsc_ctl.scala 272:134]
|
||||
wire [31:0] _T_244 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_246 = _T_244 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 277:43]
|
||||
wire _T_248 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 278:66]
|
||||
wire [31:0] _T_246 = _T_244 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 274:43]
|
||||
wire _T_248 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 275:66]
|
||||
wire [31:0] _T_250 = _T_248 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_252 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_253 = _T_250 & _T_252; // @[lsu_lsc_ctl.scala 278:94]
|
||||
wire _T_254 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 279:43]
|
||||
wire [31:0] _T_253 = _T_250 & _T_252; // @[lsu_lsc_ctl.scala 275:94]
|
||||
wire _T_254 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 276:43]
|
||||
wire [31:0] _T_256 = _T_254 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_258 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_259 = _T_256 & _T_258; // @[lsu_lsc_ctl.scala 279:71]
|
||||
wire [31:0] _T_260 = _T_253 | _T_259; // @[lsu_lsc_ctl.scala 278:138]
|
||||
wire _T_261 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 280:17]
|
||||
wire _T_262 = _T_261 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 280:43]
|
||||
wire [31:0] _T_259 = _T_256 & _T_258; // @[lsu_lsc_ctl.scala 276:71]
|
||||
wire [31:0] _T_260 = _T_253 | _T_259; // @[lsu_lsc_ctl.scala 275:138]
|
||||
wire _T_261 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 277:17]
|
||||
wire _T_262 = _T_261 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 277:43]
|
||||
wire [31:0] _T_264 = _T_262 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [23:0] _T_267 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_269 = {_T_267,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_270 = _T_264 & _T_269; // @[lsu_lsc_ctl.scala 280:71]
|
||||
wire [31:0] _T_271 = _T_260 | _T_270; // @[lsu_lsc_ctl.scala 279:119]
|
||||
wire _T_273 = _T_261 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 281:43]
|
||||
wire [31:0] _T_270 = _T_264 & _T_269; // @[lsu_lsc_ctl.scala 277:71]
|
||||
wire [31:0] _T_271 = _T_260 | _T_270; // @[lsu_lsc_ctl.scala 276:119]
|
||||
wire _T_273 = _T_261 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 278:43]
|
||||
wire [31:0] _T_275 = _T_273 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [15:0] _T_278 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_280 = {_T_278,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_281 = _T_275 & _T_280; // @[lsu_lsc_ctl.scala 281:71]
|
||||
wire [31:0] _T_282 = _T_271 | _T_281; // @[lsu_lsc_ctl.scala 280:144]
|
||||
wire [31:0] _T_281 = _T_275 & _T_280; // @[lsu_lsc_ctl.scala 278:71]
|
||||
wire [31:0] _T_282 = _T_271 | _T_281; // @[lsu_lsc_ctl.scala 277:144]
|
||||
wire [31:0] _T_284 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_286 = _T_284 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 282:43]
|
||||
wire [31:0] _T_286 = _T_284 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 279:43]
|
||||
lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 117:25]
|
||||
.reset(addrcheck_reset),
|
||||
.io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk),
|
||||
|
|
@ -653,18 +653,18 @@ module lsu_lsc_ctl(
|
|||
.io_clk(rvclkhdr_3_io_clk),
|
||||
.io_en(rvclkhdr_3_io_en)
|
||||
);
|
||||
assign io_lsu_exu_lsu_result_m = _T_242 | _T_246; // @[lsu_lsc_ctl.scala 273:35]
|
||||
assign io_lsu_result_corr_r = _T_282 | _T_286; // @[lsu_lsc_ctl.scala 278:27]
|
||||
assign io_lsu_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 247:28]
|
||||
assign io_lsu_addr_m = _T_161; // @[lsu_lsc_ctl.scala 230:24]
|
||||
assign io_lsu_addr_r = _T_162; // @[lsu_lsc_ctl.scala 231:24]
|
||||
assign io_lsu_exu_lsu_result_m = _T_242 | _T_246; // @[lsu_lsc_ctl.scala 270:35]
|
||||
assign io_lsu_result_corr_r = _T_282 | _T_286; // @[lsu_lsc_ctl.scala 275:27]
|
||||
assign io_lsu_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 244:28]
|
||||
assign io_lsu_addr_m = _T_161; // @[lsu_lsc_ctl.scala 227:24]
|
||||
assign io_lsu_addr_r = _T_162; // @[lsu_lsc_ctl.scala 228:24]
|
||||
assign io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 114:24]
|
||||
assign io_end_addr_m = {_T_164,_T_166}; // @[lsu_lsc_ctl.scala 232:17]
|
||||
assign io_end_addr_r = {_T_169,_T_171}; // @[lsu_lsc_ctl.scala 233:17]
|
||||
assign io_store_data_m = _T_201 & _T_203; // @[lsu_lsc_ctl.scala 250:29]
|
||||
assign io_end_addr_m = {_T_164,_T_166}; // @[lsu_lsc_ctl.scala 229:17]
|
||||
assign io_end_addr_r = {_T_169,_T_171}; // @[lsu_lsc_ctl.scala 230:17]
|
||||
assign io_store_data_m = _T_201 & _T_203; // @[lsu_lsc_ctl.scala 247:29]
|
||||
assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:16]
|
||||
assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 127:42]
|
||||
assign io_lsu_commit_r = _T_194 & _T_195; // @[lsu_lsc_ctl.scala 249:19]
|
||||
assign io_lsu_commit_r = _T_194 & _T_195; // @[lsu_lsc_ctl.scala 246:19]
|
||||
assign io_lsu_single_ecc_error_incr = _T_74 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 155:32]
|
||||
assign io_lsu_error_pkt_r_valid = _T_112; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 186:30]
|
||||
assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_111; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 185:46]
|
||||
|
|
@ -672,15 +672,15 @@ module lsu_lsc_ctl(
|
|||
assign io_lsu_error_pkt_r_bits_exc_type = _T_110_bits_exc_type; // @[lsu_lsc_ctl.scala 184:24]
|
||||
assign io_lsu_error_pkt_r_bits_mscause = _T_110_bits_mscause; // @[lsu_lsc_ctl.scala 184:24]
|
||||
assign io_lsu_error_pkt_r_bits_addr = _T_110_bits_addr; // @[lsu_lsc_ctl.scala 184:24]
|
||||
assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 245:28]
|
||||
assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 242:28]
|
||||
assign io_lsu_fir_error = _T_113; // @[lsu_lsc_ctl.scala 187:38]
|
||||
assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 128:42]
|
||||
assign io_addr_in_dccm_m = _T_183; // @[lsu_lsc_ctl.scala 236:24]
|
||||
assign io_addr_in_dccm_r = _T_184; // @[lsu_lsc_ctl.scala 237:24]
|
||||
assign io_addr_in_dccm_m = _T_183; // @[lsu_lsc_ctl.scala 233:24]
|
||||
assign io_addr_in_dccm_r = _T_184; // @[lsu_lsc_ctl.scala 234:24]
|
||||
assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 129:42]
|
||||
assign io_addr_in_pic_m = _T_185; // @[lsu_lsc_ctl.scala 238:24]
|
||||
assign io_addr_in_pic_r = _T_186; // @[lsu_lsc_ctl.scala 239:24]
|
||||
assign io_addr_external_m = _T_187; // @[lsu_lsc_ctl.scala 240:24]
|
||||
assign io_addr_in_pic_m = _T_185; // @[lsu_lsc_ctl.scala 235:24]
|
||||
assign io_addr_in_pic_r = _T_186; // @[lsu_lsc_ctl.scala 236:24]
|
||||
assign io_addr_external_m = _T_187; // @[lsu_lsc_ctl.scala 237:24]
|
||||
assign io_lsu_pkt_d_valid = _T_128 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24]
|
||||
assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_stack = io_dec_lsu_valid_raw_d & io_lsu_p_bits_stack; // @[lsu_lsc_ctl.scala 208:20]
|
||||
|
|
|
|||
|
|
@ -84,20 +84,20 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
val lsu_raw_fwd_hi_m = stbuf.io.stbuf_fwdbyteen_hi_m.orR
|
||||
|
||||
// block stores in decode - for either bus or stbuf reasons
|
||||
io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||
io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||
io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage
|
||||
io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||
io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||
io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage
|
||||
|
||||
// Ready to accept dma trxns
|
||||
// There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m
|
||||
val dma_mem_tag_d = io.lsu_dma.dma_mem_tag
|
||||
val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store
|
||||
io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff)
|
||||
val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1)
|
||||
val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d
|
||||
dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
|
||||
dma_dccm_wdata_hi := dma_dccm_wdata(63,32)
|
||||
dma_dccm_wdata_lo := dma_dccm_wdata(31,0)
|
||||
val dma_mem_tag_d = io.lsu_dma.dma_mem_tag
|
||||
val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store
|
||||
io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff)
|
||||
val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1)
|
||||
val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d
|
||||
dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
|
||||
dma_dccm_wdata_hi := dma_dccm_wdata(63,32)
|
||||
dma_dccm_wdata_lo := dma_dccm_wdata(31,0)
|
||||
|
||||
val flush_m_up = io.dec_tlu_flush_lower_r
|
||||
val flush_r = io.dec_tlu_i0_kill_writeb_r
|
||||
|
|
@ -107,17 +107,17 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
// Store buffer now have only non-dma dccm stores
|
||||
// stbuf_empty not needed since it has only dccm stores
|
||||
io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any
|
||||
io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock
|
||||
io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock
|
||||
// Instantiate the store buffer
|
||||
val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & (!lsu_lsc_ctl.io.lsu_pkt_r.bits.dma | ((lsu_lsc_ctl.io.lsu_pkt_r.bits.by | lsu_lsc_ctl.io.lsu_pkt_r.bits.half) & !ecc.io.lsu_double_ecc_error_r))
|
||||
// Disable Forwarding for now
|
||||
val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m)
|
||||
val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m)
|
||||
// Bus signals
|
||||
val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int
|
||||
val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int
|
||||
// Dual signals
|
||||
|
||||
// PMU signals
|
||||
io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR))
|
||||
io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR))
|
||||
io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m
|
||||
io.lsu_tlu.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m
|
||||
|
||||
|
|
@ -229,26 +229,26 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
stbuf.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
|
||||
stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk
|
||||
stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
|
||||
stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r
|
||||
stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
|
||||
stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r
|
||||
stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
|
||||
stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
stbuf.io.store_data_hi_r := dccm_ctl.io.store_data_hi_r
|
||||
stbuf.io.store_data_lo_r := dccm_ctl.io.store_data_lo_r
|
||||
stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r
|
||||
stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r
|
||||
stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r
|
||||
stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any
|
||||
stbuf.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d
|
||||
stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||
stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
|
||||
stbuf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d
|
||||
stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
|
||||
stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
|
||||
stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||
stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any
|
||||
stbuf.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d
|
||||
stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||
stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
|
||||
stbuf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d
|
||||
stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
|
||||
stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
|
||||
stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||
stbuf.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
|
||||
stbuf.io.lsu_cmpen_m := lsu_cmpen_m
|
||||
stbuf.io.scan_mode := io.scan_mode
|
||||
stbuf.io.lsu_cmpen_m := lsu_cmpen_m
|
||||
stbuf.io.scan_mode := io.scan_mode
|
||||
|
||||
// ECC
|
||||
//Inputs
|
||||
|
|
@ -313,7 +313,7 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
//Bus Interface
|
||||
//Inputs
|
||||
bus_intf.io.scan_mode := io.scan_mode
|
||||
io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff
|
||||
io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff
|
||||
bus_intf.io.clk_override := io.clk_override
|
||||
bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
|
||||
bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||
|
|
@ -343,11 +343,11 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
bus_intf.io.flush_m_up := flush_m_up
|
||||
bus_intf.io.flush_r := flush_r
|
||||
//Outputs
|
||||
io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff
|
||||
io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data
|
||||
lsu_busreq_r := bus_intf.io.lsu_busreq_r
|
||||
io.axi <> bus_intf.io.axi
|
||||
bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff
|
||||
io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data
|
||||
lsu_busreq_r := bus_intf.io.lsu_busreq_r
|
||||
io.axi <> bus_intf.io.axi
|
||||
bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
|
||||
withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)}
|
||||
withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)}
|
||||
|
|
|
|||
|
|
@ -362,7 +362,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
|
|||
val obuf_byteen = rvdffs_fpga (obuf_byteen_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
|
||||
obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode)
|
||||
val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode)
|
||||
obuf_wr_timer := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,obuf_wr_en,clock)
|
||||
obuf_wr_timer := rvdff_fpga (obuf_wr_timer_in,io.lsu_busm_clk,obuf_wr_en,clock)
|
||||
val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -118,19 +118,19 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
|
|||
bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r
|
||||
//
|
||||
|
||||
bus_buffer.io.lsu_addr_m := io.lsu_addr_m
|
||||
bus_buffer.io.end_addr_m := io.end_addr_m
|
||||
bus_buffer.io.lsu_addr_r := io.lsu_addr_r
|
||||
bus_buffer.io.end_addr_r := io.end_addr_r
|
||||
bus_buffer.io.store_data_r := io.store_data_r
|
||||
bus_buffer.io.lsu_addr_m := io.lsu_addr_m
|
||||
bus_buffer.io.end_addr_m := io.end_addr_m
|
||||
bus_buffer.io.lsu_addr_r := io.lsu_addr_r
|
||||
bus_buffer.io.end_addr_r := io.end_addr_r
|
||||
bus_buffer.io.store_data_r := io.store_data_r
|
||||
|
||||
bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m
|
||||
bus_buffer.io.flush_m_up := io.flush_m_up
|
||||
bus_buffer.io.flush_r := io.flush_r
|
||||
bus_buffer.io.lsu_commit_r := io.lsu_commit_r
|
||||
bus_buffer.io.lsu_axi <> io.axi
|
||||
bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
io.lsu_nonblock_load_data := bus_buffer.io.lsu_nonblock_load_data
|
||||
bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m
|
||||
bus_buffer.io.flush_m_up := io.flush_m_up
|
||||
bus_buffer.io.flush_r := io.flush_r
|
||||
bus_buffer.io.lsu_commit_r := io.lsu_commit_r
|
||||
bus_buffer.io.lsu_axi <> io.axi
|
||||
bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
io.lsu_nonblock_load_data := bus_buffer.io.lsu_nonblock_load_data
|
||||
io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r
|
||||
io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any
|
||||
io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any
|
||||
|
|
|
|||
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Reference in New Issue