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LSU Added

This commit is contained in:
​Laraib Khan 2021-01-28 17:36:33 +05:00
parent 60faa36fe5
commit 9da7df3623
91 changed files with 45020 additions and 1890 deletions
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34
exu.anno.json
View File

@ -11,7 +11,7 @@
"sink":"~exu|exu>io_lsu_exu_exu_lsu_rs2_d", "sink":"~exu|exu>io_lsu_exu_exu_lsu_rs2_d",
"sources":[ "sources":[
"~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs2_d", "~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs2_d",
"~exu|exu>io_dec_qual_lsu_d", "~exu|exu>io_dec_exu_decode_exu_dec_qual_lsu_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs2_en_d", "~exu|exu>io_dec_exu_decode_exu_dec_i0_rs2_en_d",
"~exu|exu>io_lsu_exu_lsu_nonblock_load_data", "~exu|exu>io_lsu_exu_lsu_nonblock_load_data",
"~exu|exu>io_dec_exu_decode_exu_dec_extint_stall", "~exu|exu>io_dec_exu_decode_exu_dec_extint_stall",
@ -66,22 +66,6 @@
"~exu|exu>io_dec_exu_tlu_exu_exu_i0_br_index_r" "~exu|exu>io_dec_exu_tlu_exu_exu_i0_br_index_r"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu|exu>io_lsu_exu_exu_lsu_rs1_d",
"sources":[
"~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs1_d",
"~exu|exu>io_dec_exu_tlu_exu_dec_tlu_meihap",
"~exu|exu>io_dec_exu_decode_exu_dec_extint_stall",
"~exu|exu>io_dec_qual_lsu_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_en_d",
"~exu|exu>io_lsu_exu_lsu_nonblock_load_data",
"~exu|exu>io_dec_exu_decode_exu_exu_i0_result_x",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_result_r",
"~exu|exu>io_lsu_exu_lsu_result_m"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~exu|exu>io_exu_flush_final", "sink":"~exu|exu>io_exu_flush_final",
@ -132,6 +116,22 @@
"~exu|exu>io_dec_exu_dec_div_dec_div_cancel" "~exu|exu>io_dec_exu_dec_div_dec_div_cancel"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu|exu>io_lsu_exu_exu_lsu_rs1_d",
"sources":[
"~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs1_d",
"~exu|exu>io_dec_exu_tlu_exu_dec_tlu_meihap",
"~exu|exu>io_dec_exu_decode_exu_dec_extint_stall",
"~exu|exu>io_dec_exu_decode_exu_dec_qual_lsu_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_en_d",
"~exu|exu>io_lsu_exu_lsu_nonblock_load_data",
"~exu|exu>io_dec_exu_decode_exu_exu_i0_result_x",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_result_r",
"~exu|exu>io_lsu_exu_lsu_result_m"
]
},
{ {
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"

782
exu.fir
View File

@ -219,7 +219,7 @@ circuit exu :
module exu_alu_ctl : module exu_alu_ctl :
input clock : Clock input clock : Clock
input reset : AsyncReset input reset : AsyncReset
output io : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_i0_pc_d : UInt<31>, flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip enable : UInt<1>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}} output io : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip csr_rddata_in : UInt<32>, flip dec_i0_pc_d : UInt<31>, flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip enable : UInt<1>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}}
wire ap_clz : UInt<1> wire ap_clz : UInt<1>
ap_clz <= UInt<1>("h00") ap_clz <= UInt<1>("h00")
@ -429,7 +429,7 @@ circuit exu :
node _T_92 = and(io.i0_ap.unsign, _T_91) @[exu_alu_ctl.scala 154:82] node _T_92 = and(io.i0_ap.unsign, _T_91) @[exu_alu_ctl.scala 154:82]
node lt = or(_T_90, _T_92) @[exu_alu_ctl.scala 154:61] node lt = or(_T_90, _T_92) @[exu_alu_ctl.scala 154:61]
node ge = eq(lt, UInt<1>("h00")) @[exu_alu_ctl.scala 155:29] node ge = eq(lt, UInt<1>("h00")) @[exu_alu_ctl.scala 155:29]
node _T_93 = asSInt(io.dec_alu.dec_csr_rddata_d) @[exu_alu_ctl.scala 159:73] node _T_93 = asSInt(io.csr_rddata_in) @[exu_alu_ctl.scala 159:62]
node _T_94 = eq(ap_zbb, UInt<1>("h00")) @[exu_alu_ctl.scala 160:22] node _T_94 = eq(ap_zbb, UInt<1>("h00")) @[exu_alu_ctl.scala 160:22]
node _T_95 = and(io.i0_ap.land, _T_94) @[exu_alu_ctl.scala 160:20] node _T_95 = and(io.i0_ap.land, _T_94) @[exu_alu_ctl.scala 160:20]
node _T_96 = bits(_T_95, 0, 0) @[exu_alu_ctl.scala 160:31] node _T_96 = bits(_T_95, 0, 0) @[exu_alu_ctl.scala 160:31]
@ -44537,49 +44537,49 @@ circuit exu :
module exu : module exu :
input clock : Clock input clock : Clock
input reset : AsyncReset input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}, exu_flush_final : UInt<1>, exu_div_result : UInt<32>, exu_div_wren : UInt<1>, flip dbg_cmd_wrdata : UInt<32>, flip lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>, lsu_nonblock_load_data : UInt<32>}, exu_flush_path_final : UInt<31>, flip dec_qual_lsu_d : UInt<1>} output io : {flip scan_mode : UInt<1>, dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_qual_lsu_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}, exu_flush_final : UInt<1>, exu_div_result : UInt<32>, exu_div_wren : UInt<1>, flip dbg_cmd_wrdata : UInt<32>, flip dec_csr_rddata_d : UInt<32>, flip lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>, lsu_nonblock_load_data : UInt<32>}, exu_flush_path_final : UInt<31>}
wire ghr_x_ns : UInt<8> @[exu.scala 33:57] wire ghr_x_ns : UInt<8> @[exu.scala 32:57]
wire ghr_d_ns : UInt<8> @[exu.scala 34:57] wire ghr_d_ns : UInt<8> @[exu.scala 33:57]
wire ghr_d : UInt<8> @[exu.scala 35:67] wire ghr_d : UInt<8> @[exu.scala 34:67]
wire i0_taken_d : UInt<1> @[exu.scala 36:63] wire i0_taken_d : UInt<1> @[exu.scala 35:63]
wire mul_valid_x : UInt<1> @[exu.scala 37:63] wire mul_valid_x : UInt<1> @[exu.scala 36:63]
wire i0_valid_d : UInt<1> @[exu.scala 38:63] wire i0_valid_d : UInt<1> @[exu.scala 37:63]
wire i0_branch_x : UInt<1> @[exu.scala 39:39] wire i0_branch_x : UInt<1> @[exu.scala 38:39]
wire i0_predict_newp_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 40:51] wire i0_predict_newp_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 39:51]
wire i0_flush_path_d : UInt<31> @[exu.scala 41:53] wire i0_flush_path_d : UInt<31> @[exu.scala 40:53]
wire i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 42:53] wire i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 41:53]
wire i0_pp_r : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 43:65] wire i0_pp_r : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 42:65]
wire i0_predict_p_x : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 44:53] wire i0_predict_p_x : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 43:53]
wire final_predict_mp : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 45:45] wire final_predict_mp : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 44:45]
wire pred_correct_npc_r : UInt<32> @[exu.scala 46:51] wire pred_correct_npc_r : UInt<32> @[exu.scala 45:51]
wire i0_pred_correct_upper_d : UInt<1> @[exu.scala 47:41] wire i0_pred_correct_upper_d : UInt<1> @[exu.scala 46:41]
wire i0_flush_upper_d : UInt<1> @[exu.scala 48:45] wire i0_flush_upper_d : UInt<1> @[exu.scala 47:45]
io.exu_bp.exu_mp_pkt.bits.prett <= UInt<1>("h00") @[exu.scala 49:57] io.exu_bp.exu_mp_pkt.bits.prett <= UInt<1>("h00") @[exu.scala 48:57]
io.exu_bp.exu_mp_pkt.bits.br_start_error <= UInt<1>("h00") @[exu.scala 50:44] io.exu_bp.exu_mp_pkt.bits.br_start_error <= UInt<1>("h00") @[exu.scala 49:44]
io.exu_bp.exu_mp_pkt.bits.br_error <= UInt<1>("h00") @[exu.scala 51:39] io.exu_bp.exu_mp_pkt.bits.br_error <= UInt<1>("h00") @[exu.scala 50:39]
io.exu_bp.exu_mp_pkt.valid <= UInt<1>("h00") @[exu.scala 52:53] io.exu_bp.exu_mp_pkt.valid <= UInt<1>("h00") @[exu.scala 51:53]
i0_pp_r.bits.toffset <= UInt<1>("h00") @[exu.scala 53:39] i0_pp_r.bits.toffset <= UInt<1>("h00") @[exu.scala 52:39]
node x_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 55:69] node x_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 54:69]
node _T = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 56:69] node _T = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 55:69]
node x_data_en_q1 = and(_T, io.dec_exu.dec_alu.dec_csr_ren_d) @[exu.scala 56:73] node x_data_en_q1 = and(_T, io.dec_exu.dec_alu.dec_csr_ren_d) @[exu.scala 55:73]
node _T_1 = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 57:69] node _T_1 = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 56:69]
node x_data_en_q2 = and(_T_1, io.dec_exu.decode_exu.dec_i0_branch_d) @[exu.scala 57:73] node x_data_en_q2 = and(_T_1, io.dec_exu.decode_exu.dec_i0_branch_d) @[exu.scala 56:73]
node r_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 58:69] node r_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 57:69]
node _T_2 = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 59:69] node _T_2 = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 58:69]
node r_data_en_q2 = and(_T_2, i0_branch_x) @[exu.scala 59:73] node r_data_en_q2 = and(_T_2, i0_branch_x) @[exu.scala 58:73]
node x_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 1, 1) @[exu.scala 60:68] node x_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 1, 1) @[exu.scala 59:68]
node r_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 0, 0) @[exu.scala 61:68] node r_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 0, 0) @[exu.scala 60:68]
node _T_3 = cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d) @[Cat.scala 29:58] node _T_3 = cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d) @[Cat.scala 29:58]
node predpipe_d = cat(_T_3, io.dec_exu.decode_exu.i0_predict_btag_d) @[Cat.scala 29:58] node predpipe_d = cat(_T_3, io.dec_exu.decode_exu.i0_predict_btag_d) @[Cat.scala 29:58]
node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 64:68] node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 63:68]
wire _T_5 : UInt<31> @[lib.scala 648:38] wire _T_5 : UInt<31> @[lib.scala 648:38]
_T_5 <= UInt<1>("h00") @[lib.scala 648:38] _T_5 <= UInt<1>("h00") @[lib.scala 648:38]
reg i0_flush_path_x : UInt, clock with : (reset => (reset, _T_5)) @[Reg.scala 27:20] reg i0_flush_path_x : UInt, clock with : (reset => (reset, _T_5)) @[Reg.scala 27:20]
when _T_4 : @[Reg.scala 28:19] when _T_4 : @[Reg.scala 28:19]
i0_flush_path_x <= i0_flush_path_d @[Reg.scala 28:23] i0_flush_path_x <= i0_flush_path_d @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_6 = bits(x_data_en, 0, 0) @[exu.scala 65:116] node _T_6 = bits(x_data_en, 0, 0) @[exu.scala 64:116]
node _T_7 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44] node _T_7 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44]
wire _T_8 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37] wire _T_8 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37]
_T_8.bits.prett <= UInt<31>("h00") @[lib.scala 598:37] _T_8.bits.prett <= UInt<31>("h00") @[lib.scala 598:37]
@ -44613,21 +44613,21 @@ circuit exu :
_T_9.bits.misp <= i0_predict_p_d.bits.misp @[Reg.scala 28:23] _T_9.bits.misp <= i0_predict_p_d.bits.misp @[Reg.scala 28:23]
_T_9.valid <= i0_predict_p_d.valid @[Reg.scala 28:23] _T_9.valid <= i0_predict_p_d.valid @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
i0_predict_p_x.bits.prett <= _T_9.bits.prett @[exu.scala 65:55] i0_predict_p_x.bits.prett <= _T_9.bits.prett @[exu.scala 64:55]
i0_predict_p_x.bits.pret <= _T_9.bits.pret @[exu.scala 65:55] i0_predict_p_x.bits.pret <= _T_9.bits.pret @[exu.scala 64:55]
i0_predict_p_x.bits.way <= _T_9.bits.way @[exu.scala 65:55] i0_predict_p_x.bits.way <= _T_9.bits.way @[exu.scala 64:55]
i0_predict_p_x.bits.pja <= _T_9.bits.pja @[exu.scala 65:55] i0_predict_p_x.bits.pja <= _T_9.bits.pja @[exu.scala 64:55]
i0_predict_p_x.bits.pcall <= _T_9.bits.pcall @[exu.scala 65:55] i0_predict_p_x.bits.pcall <= _T_9.bits.pcall @[exu.scala 64:55]
i0_predict_p_x.bits.br_start_error <= _T_9.bits.br_start_error @[exu.scala 65:55] i0_predict_p_x.bits.br_start_error <= _T_9.bits.br_start_error @[exu.scala 64:55]
i0_predict_p_x.bits.br_error <= _T_9.bits.br_error @[exu.scala 65:55] i0_predict_p_x.bits.br_error <= _T_9.bits.br_error @[exu.scala 64:55]
i0_predict_p_x.bits.toffset <= _T_9.bits.toffset @[exu.scala 65:55] i0_predict_p_x.bits.toffset <= _T_9.bits.toffset @[exu.scala 64:55]
i0_predict_p_x.bits.hist <= _T_9.bits.hist @[exu.scala 65:55] i0_predict_p_x.bits.hist <= _T_9.bits.hist @[exu.scala 64:55]
i0_predict_p_x.bits.pc4 <= _T_9.bits.pc4 @[exu.scala 65:55] i0_predict_p_x.bits.pc4 <= _T_9.bits.pc4 @[exu.scala 64:55]
i0_predict_p_x.bits.boffset <= _T_9.bits.boffset @[exu.scala 65:55] i0_predict_p_x.bits.boffset <= _T_9.bits.boffset @[exu.scala 64:55]
i0_predict_p_x.bits.ataken <= _T_9.bits.ataken @[exu.scala 65:55] i0_predict_p_x.bits.ataken <= _T_9.bits.ataken @[exu.scala 64:55]
i0_predict_p_x.bits.misp <= _T_9.bits.misp @[exu.scala 65:55] i0_predict_p_x.bits.misp <= _T_9.bits.misp @[exu.scala 64:55]
i0_predict_p_x.valid <= _T_9.valid @[exu.scala 65:55] i0_predict_p_x.valid <= _T_9.valid @[exu.scala 64:55]
node _T_10 = bits(x_data_en_q2, 0, 0) @[exu.scala 66:79] node _T_10 = bits(x_data_en_q2, 0, 0) @[exu.scala 65:79]
inst rvclkhdr of rvclkhdr @[lib.scala 404:23] inst rvclkhdr of rvclkhdr @[lib.scala 404:23]
rvclkhdr.clock <= clock rvclkhdr.clock <= clock
rvclkhdr.reset <= reset rvclkhdr.reset <= reset
@ -44638,7 +44638,7 @@ circuit exu :
when _T_10 : @[Reg.scala 28:19] when _T_10 : @[Reg.scala 28:19]
predpipe_x <= predpipe_d @[Reg.scala 28:23] predpipe_x <= predpipe_d @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_11 = bits(r_data_en_q2, 0, 0) @[exu.scala 67:88] node _T_11 = bits(r_data_en_q2, 0, 0) @[exu.scala 66:88]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23]
rvclkhdr_1.clock <= clock rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset rvclkhdr_1.reset <= reset
@ -44649,7 +44649,7 @@ circuit exu :
when _T_11 : @[Reg.scala 28:19] when _T_11 : @[Reg.scala 28:19]
predpipe_r <= predpipe_x @[Reg.scala 28:23] predpipe_r <= predpipe_x @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 68:86] node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 67:86]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23]
rvclkhdr_2.clock <= clock rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset rvclkhdr_2.reset <= reset
@ -44660,7 +44660,7 @@ circuit exu :
when _T_12 : @[Reg.scala 28:19] when _T_12 : @[Reg.scala 28:19]
ghr_x <= ghr_x_ns @[Reg.scala 28:23] ghr_x <= ghr_x_ns @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 69:75] node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 68:75]
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23]
rvclkhdr_3.clock <= clock rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset rvclkhdr_3.reset <= reset
@ -44671,7 +44671,7 @@ circuit exu :
when _T_13 : @[Reg.scala 28:19] when _T_13 : @[Reg.scala 28:19]
i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[Reg.scala 28:23] i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_14 = bits(x_ctl_en, 0, 0) @[exu.scala 70:66] node _T_14 = bits(x_ctl_en, 0, 0) @[exu.scala 69:66]
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23]
rvclkhdr_4.clock <= clock rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset rvclkhdr_4.reset <= reset
@ -44682,7 +44682,7 @@ circuit exu :
when _T_14 : @[Reg.scala 28:19] when _T_14 : @[Reg.scala 28:19]
i0_flush_upper_x <= i0_flush_upper_d @[Reg.scala 28:23] i0_flush_upper_x <= i0_flush_upper_d @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_15 = bits(x_ctl_en, 0, 0) @[exu.scala 71:84] node _T_15 = bits(x_ctl_en, 0, 0) @[exu.scala 70:84]
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23]
rvclkhdr_5.clock <= clock rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset rvclkhdr_5.reset <= reset
@ -44693,7 +44693,7 @@ circuit exu :
when _T_15 : @[Reg.scala 28:19] when _T_15 : @[Reg.scala 28:19]
i0_taken_x <= i0_taken_d @[Reg.scala 28:23] i0_taken_x <= i0_taken_d @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_16 = bits(x_ctl_en, 0, 0) @[exu.scala 72:84] node _T_16 = bits(x_ctl_en, 0, 0) @[exu.scala 71:84]
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23]
rvclkhdr_6.clock <= clock rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset rvclkhdr_6.reset <= reset
@ -44704,7 +44704,7 @@ circuit exu :
when _T_16 : @[Reg.scala 28:19] when _T_16 : @[Reg.scala 28:19]
i0_valid_x <= i0_valid_d @[Reg.scala 28:23] i0_valid_x <= i0_valid_d @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_17 = bits(r_ctl_en, 0, 0) @[exu.scala 73:93] node _T_17 = bits(r_ctl_en, 0, 0) @[exu.scala 72:93]
node _T_18 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44] node _T_18 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44]
wire _T_19 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37] wire _T_19 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37]
_T_19.bits.prett <= UInt<31>("h00") @[lib.scala 598:37] _T_19.bits.prett <= UInt<31>("h00") @[lib.scala 598:37]
@ -44738,44 +44738,44 @@ circuit exu :
_T_20.bits.misp <= i0_predict_p_x.bits.misp @[Reg.scala 28:23] _T_20.bits.misp <= i0_predict_p_x.bits.misp @[Reg.scala 28:23]
_T_20.valid <= i0_predict_p_x.valid @[Reg.scala 28:23] _T_20.valid <= i0_predict_p_x.valid @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
i0_pp_r.bits.prett <= _T_20.bits.prett @[exu.scala 73:31] i0_pp_r.bits.prett <= _T_20.bits.prett @[exu.scala 72:31]
i0_pp_r.bits.pret <= _T_20.bits.pret @[exu.scala 73:31] i0_pp_r.bits.pret <= _T_20.bits.pret @[exu.scala 72:31]
i0_pp_r.bits.way <= _T_20.bits.way @[exu.scala 73:31] i0_pp_r.bits.way <= _T_20.bits.way @[exu.scala 72:31]
i0_pp_r.bits.pja <= _T_20.bits.pja @[exu.scala 73:31] i0_pp_r.bits.pja <= _T_20.bits.pja @[exu.scala 72:31]
i0_pp_r.bits.pcall <= _T_20.bits.pcall @[exu.scala 73:31] i0_pp_r.bits.pcall <= _T_20.bits.pcall @[exu.scala 72:31]
i0_pp_r.bits.br_start_error <= _T_20.bits.br_start_error @[exu.scala 73:31] i0_pp_r.bits.br_start_error <= _T_20.bits.br_start_error @[exu.scala 72:31]
i0_pp_r.bits.br_error <= _T_20.bits.br_error @[exu.scala 73:31] i0_pp_r.bits.br_error <= _T_20.bits.br_error @[exu.scala 72:31]
i0_pp_r.bits.toffset <= _T_20.bits.toffset @[exu.scala 73:31] i0_pp_r.bits.toffset <= _T_20.bits.toffset @[exu.scala 72:31]
i0_pp_r.bits.hist <= _T_20.bits.hist @[exu.scala 73:31] i0_pp_r.bits.hist <= _T_20.bits.hist @[exu.scala 72:31]
i0_pp_r.bits.pc4 <= _T_20.bits.pc4 @[exu.scala 73:31] i0_pp_r.bits.pc4 <= _T_20.bits.pc4 @[exu.scala 72:31]
i0_pp_r.bits.boffset <= _T_20.bits.boffset @[exu.scala 73:31] i0_pp_r.bits.boffset <= _T_20.bits.boffset @[exu.scala 72:31]
i0_pp_r.bits.ataken <= _T_20.bits.ataken @[exu.scala 73:31] i0_pp_r.bits.ataken <= _T_20.bits.ataken @[exu.scala 72:31]
i0_pp_r.bits.misp <= _T_20.bits.misp @[exu.scala 73:31] i0_pp_r.bits.misp <= _T_20.bits.misp @[exu.scala 72:31]
i0_pp_r.valid <= _T_20.valid @[exu.scala 73:31] i0_pp_r.valid <= _T_20.valid @[exu.scala 72:31]
node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 74:94] node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 73:94]
node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 74:111] node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 73:111]
wire _T_23 : UInt<6> @[lib.scala 648:38] wire _T_23 : UInt<6> @[lib.scala 648:38]
_T_23 <= UInt<1>("h00") @[lib.scala 648:38] _T_23 <= UInt<1>("h00") @[lib.scala 648:38]
reg pred_temp1 : UInt, clock with : (reset => (reset, _T_23)) @[Reg.scala 27:20] reg pred_temp1 : UInt, clock with : (reset => (reset, _T_23)) @[Reg.scala 27:20]
when _T_22 : @[Reg.scala 28:19] when _T_22 : @[Reg.scala 28:19]
pred_temp1 <= _T_21 @[Reg.scala 28:23] pred_temp1 <= _T_21 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_24 = bits(r_ctl_en, 0, 0) @[exu.scala 75:109] node _T_24 = bits(r_ctl_en, 0, 0) @[exu.scala 74:109]
wire _T_25 : UInt @[lib.scala 588:35] wire _T_25 : UInt @[lib.scala 588:35]
_T_25 <= UInt<1>("h00") @[lib.scala 588:35] _T_25 <= UInt<1>("h00") @[lib.scala 588:35]
reg i0_pred_correct_upper_r : UInt, clock with : (reset => (reset, _T_25)) @[Reg.scala 27:20] reg i0_pred_correct_upper_r : UInt, clock with : (reset => (reset, _T_25)) @[Reg.scala 27:20]
when _T_24 : @[Reg.scala 28:19] when _T_24 : @[Reg.scala 28:19]
i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[Reg.scala 28:23] i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_26 = bits(r_data_en, 0, 0) @[exu.scala 76:73] node _T_26 = bits(r_data_en, 0, 0) @[exu.scala 75:73]
wire _T_27 : UInt @[lib.scala 648:38] wire _T_27 : UInt @[lib.scala 648:38]
_T_27 <= UInt<1>("h00") @[lib.scala 648:38] _T_27 <= UInt<1>("h00") @[lib.scala 648:38]
reg i0_flush_path_upper_r : UInt, clock with : (reset => (reset, _T_27)) @[Reg.scala 27:20] reg i0_flush_path_upper_r : UInt, clock with : (reset => (reset, _T_27)) @[Reg.scala 27:20]
when _T_26 : @[Reg.scala 28:19] when _T_26 : @[Reg.scala 28:19]
i0_flush_path_upper_r <= i0_flush_path_x @[Reg.scala 28:23] i0_flush_path_upper_r <= i0_flush_path_x @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_28 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 77:106] node _T_28 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 76:106]
node _T_29 = bits(r_data_en, 0, 0) @[exu.scala 77:124] node _T_29 = bits(r_data_en, 0, 0) @[exu.scala 76:124]
wire _T_30 : UInt<25> @[lib.scala 648:38] wire _T_30 : UInt<25> @[lib.scala 648:38]
_T_30 <= UInt<1>("h00") @[lib.scala 648:38] _T_30 <= UInt<1>("h00") @[lib.scala 648:38]
reg pred_temp2 : UInt, clock with : (reset => (reset, _T_30)) @[Reg.scala 27:20] reg pred_temp2 : UInt, clock with : (reset => (reset, _T_30)) @[Reg.scala 27:20]
@ -44783,7 +44783,7 @@ circuit exu :
pred_temp2 <= _T_28 @[Reg.scala 28:23] pred_temp2 <= _T_28 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_31 = cat(pred_temp2, pred_temp1) @[Cat.scala 29:58] node _T_31 = cat(pred_temp2, pred_temp1) @[Cat.scala 29:58]
pred_correct_npc_r <= _T_31 @[exu.scala 78:45] pred_correct_npc_r <= _T_31 @[exu.scala 77:45]
wire _T_32 : UInt wire _T_32 : UInt
_T_32 <= UInt<1>("h00") _T_32 <= UInt<1>("h00")
node _T_33 = xor(ghr_d_ns, _T_32) @[lib.scala 448:21] node _T_33 = xor(ghr_d_ns, _T_32) @[lib.scala 448:21]
@ -44793,7 +44793,7 @@ circuit exu :
_T_35 <= ghr_d_ns @[Reg.scala 28:23] _T_35 <= ghr_d_ns @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
_T_32 <= _T_35 @[lib.scala 451:16] _T_32 <= _T_35 @[lib.scala 451:16]
ghr_d <= _T_32 @[exu.scala 79:43] ghr_d <= _T_32 @[exu.scala 78:43]
wire _T_36 : UInt<1> wire _T_36 : UInt<1>
_T_36 <= UInt<1>("h00") _T_36 <= UInt<1>("h00")
node _T_37 = xor(io.dec_exu.decode_exu.mul_p.valid, _T_36) @[lib.scala 470:21] node _T_37 = xor(io.dec_exu.decode_exu.mul_p.valid, _T_36) @[lib.scala 470:21]
@ -44803,7 +44803,7 @@ circuit exu :
_T_39 <= io.dec_exu.decode_exu.mul_p.valid @[Reg.scala 28:23] _T_39 <= io.dec_exu.decode_exu.mul_p.valid @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
_T_36 <= _T_39 @[lib.scala 473:16] _T_36 <= _T_39 @[lib.scala 473:16]
mul_valid_x <= _T_36 @[exu.scala 80:39] mul_valid_x <= _T_36 @[exu.scala 79:39]
wire _T_40 : UInt wire _T_40 : UInt
_T_40 <= UInt<1>("h00") _T_40 <= UInt<1>("h00")
node _T_41 = xor(io.dec_exu.decode_exu.dec_i0_branch_d, _T_40) @[lib.scala 448:21] node _T_41 = xor(io.dec_exu.decode_exu.dec_i0_branch_d, _T_40) @[lib.scala 448:21]
@ -44813,29 +44813,29 @@ circuit exu :
_T_43 <= io.dec_exu.decode_exu.dec_i0_branch_d @[Reg.scala 28:23] _T_43 <= io.dec_exu.decode_exu.dec_i0_branch_d @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
_T_40 <= _T_43 @[lib.scala 451:16] _T_40 <= _T_43 @[lib.scala 451:16]
i0_branch_x <= _T_40 @[exu.scala 81:39] i0_branch_x <= _T_40 @[exu.scala 80:39]
node _T_44 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 83:80] node _T_44 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 82:80]
node _T_45 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 83:130] node _T_45 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 82:130]
node _T_46 = or(_T_44, _T_45) @[exu.scala 83:84] node _T_46 = or(_T_44, _T_45) @[exu.scala 82:84]
node _T_47 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 83:180] node _T_47 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 82:180]
node _T_48 = or(_T_46, _T_47) @[exu.scala 83:134] node _T_48 = or(_T_46, _T_47) @[exu.scala 82:134]
node _T_49 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 83:230] node _T_49 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 82:230]
node i0_rs1_bypass_en_d = or(_T_48, _T_49) @[exu.scala 83:184] node i0_rs1_bypass_en_d = or(_T_48, _T_49) @[exu.scala 82:184]
node _T_50 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 84:80] node _T_50 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 83:80]
node _T_51 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 84:130] node _T_51 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 83:130]
node _T_52 = or(_T_50, _T_51) @[exu.scala 84:84] node _T_52 = or(_T_50, _T_51) @[exu.scala 83:84]
node _T_53 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 84:180] node _T_53 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 83:180]
node _T_54 = or(_T_52, _T_53) @[exu.scala 84:134] node _T_54 = or(_T_52, _T_53) @[exu.scala 83:134]
node _T_55 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 84:230] node _T_55 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 83:230]
node i0_rs2_bypass_en_d = or(_T_54, _T_55) @[exu.scala 84:184] node i0_rs2_bypass_en_d = or(_T_54, _T_55) @[exu.scala 83:184]
node _T_56 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 87:49] node _T_56 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 86:49]
node _T_57 = bits(_T_56, 0, 0) @[exu.scala 87:53] node _T_57 = bits(_T_56, 0, 0) @[exu.scala 86:53]
node _T_58 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 88:49] node _T_58 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 87:49]
node _T_59 = bits(_T_58, 0, 0) @[exu.scala 88:53] node _T_59 = bits(_T_58, 0, 0) @[exu.scala 87:53]
node _T_60 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 89:49] node _T_60 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 88:49]
node _T_61 = bits(_T_60, 0, 0) @[exu.scala 89:53] node _T_61 = bits(_T_60, 0, 0) @[exu.scala 88:53]
node _T_62 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 90:49] node _T_62 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 89:49]
node _T_63 = bits(_T_62, 0, 0) @[exu.scala 90:53] node _T_63 = bits(_T_62, 0, 0) @[exu.scala 89:53]
node _T_64 = mux(_T_57, io.dec_exu.decode_exu.dec_i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_64 = mux(_T_57, io.dec_exu.decode_exu.dec_i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_65 = mux(_T_59, io.lsu_exu.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_65 = mux(_T_59, io.lsu_exu.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_66 = mux(_T_61, io.dec_exu.decode_exu.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] node _T_66 = mux(_T_61, io.dec_exu.decode_exu.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72]
@ -44845,14 +44845,14 @@ circuit exu :
node _T_70 = or(_T_69, _T_67) @[Mux.scala 27:72] node _T_70 = or(_T_69, _T_67) @[Mux.scala 27:72]
wire i0_rs1_bypass_data_d : UInt<32> @[Mux.scala 27:72] wire i0_rs1_bypass_data_d : UInt<32> @[Mux.scala 27:72]
i0_rs1_bypass_data_d <= _T_70 @[Mux.scala 27:72] i0_rs1_bypass_data_d <= _T_70 @[Mux.scala 27:72]
node _T_71 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 93:49] node _T_71 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 92:49]
node _T_72 = bits(_T_71, 0, 0) @[exu.scala 93:53] node _T_72 = bits(_T_71, 0, 0) @[exu.scala 92:53]
node _T_73 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 94:49] node _T_73 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 93:49]
node _T_74 = bits(_T_73, 0, 0) @[exu.scala 94:53] node _T_74 = bits(_T_73, 0, 0) @[exu.scala 93:53]
node _T_75 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 95:49] node _T_75 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 94:49]
node _T_76 = bits(_T_75, 0, 0) @[exu.scala 95:53] node _T_76 = bits(_T_75, 0, 0) @[exu.scala 94:53]
node _T_77 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 96:49] node _T_77 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 95:49]
node _T_78 = bits(_T_77, 0, 0) @[exu.scala 96:53] node _T_78 = bits(_T_77, 0, 0) @[exu.scala 95:53]
node _T_79 = mux(_T_72, io.dec_exu.decode_exu.dec_i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_79 = mux(_T_72, io.dec_exu.decode_exu.dec_i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_80 = mux(_T_74, io.lsu_exu.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_80 = mux(_T_74, io.lsu_exu.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_81 = mux(_T_76, io.dec_exu.decode_exu.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] node _T_81 = mux(_T_76, io.dec_exu.decode_exu.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72]
@ -44862,19 +44862,19 @@ circuit exu :
node _T_85 = or(_T_84, _T_82) @[Mux.scala 27:72] node _T_85 = or(_T_84, _T_82) @[Mux.scala 27:72]
wire i0_rs2_bypass_data_d : UInt<32> @[Mux.scala 27:72] wire i0_rs2_bypass_data_d : UInt<32> @[Mux.scala 27:72]
i0_rs2_bypass_data_d <= _T_85 @[Mux.scala 27:72] i0_rs2_bypass_data_d <= _T_85 @[Mux.scala 27:72]
node _T_86 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 100:24] node _T_86 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 99:24]
node _T_87 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 101:6] node _T_87 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 100:6]
node _T_88 = and(_T_87, io.dec_exu.decode_exu.dec_i0_select_pc_d) @[exu.scala 101:26] node _T_88 = and(_T_87, io.dec_exu.decode_exu.dec_i0_select_pc_d) @[exu.scala 100:26]
node _T_89 = bits(_T_88, 0, 0) @[exu.scala 101:71] node _T_89 = bits(_T_88, 0, 0) @[exu.scala 100:71]
node _T_90 = cat(io.dec_exu.ib_exu.dec_i0_pc_d, UInt<1>("h00")) @[Cat.scala 29:58] node _T_90 = cat(io.dec_exu.ib_exu.dec_i0_pc_d, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_91 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 102:6] node _T_91 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 101:6]
node _T_92 = and(_T_91, io.dec_exu.ib_exu.dec_debug_wdata_rs1_d) @[exu.scala 102:26] node _T_92 = and(_T_91, io.dec_exu.ib_exu.dec_debug_wdata_rs1_d) @[exu.scala 101:26]
node _T_93 = bits(_T_92, 0, 0) @[exu.scala 102:70] node _T_93 = bits(_T_92, 0, 0) @[exu.scala 101:70]
node _T_94 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 103:6] node _T_94 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 102:6]
node _T_95 = eq(io.dec_exu.ib_exu.dec_debug_wdata_rs1_d, UInt<1>("h00")) @[exu.scala 103:28] node _T_95 = eq(io.dec_exu.ib_exu.dec_debug_wdata_rs1_d, UInt<1>("h00")) @[exu.scala 102:28]
node _T_96 = and(_T_94, _T_95) @[exu.scala 103:26] node _T_96 = and(_T_94, _T_95) @[exu.scala 102:26]
node _T_97 = and(_T_96, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 103:69] node _T_97 = and(_T_96, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 102:69]
node _T_98 = bits(_T_97, 0, 0) @[exu.scala 103:110] node _T_98 = bits(_T_97, 0, 0) @[exu.scala 102:110]
node _T_99 = mux(_T_86, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_99 = mux(_T_86, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_100 = mux(_T_89, _T_90, UInt<1>("h00")) @[Mux.scala 27:72] node _T_100 = mux(_T_89, _T_90, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_101 = mux(_T_93, io.dbg_cmd_wrdata, UInt<1>("h00")) @[Mux.scala 27:72] node _T_101 = mux(_T_93, io.dbg_cmd_wrdata, UInt<1>("h00")) @[Mux.scala 27:72]
@ -44884,7 +44884,7 @@ circuit exu :
node _T_105 = or(_T_104, _T_102) @[Mux.scala 27:72] node _T_105 = or(_T_104, _T_102) @[Mux.scala 27:72]
wire i0_rs1_d : UInt<32> @[Mux.scala 27:72] wire i0_rs1_d : UInt<32> @[Mux.scala 27:72]
i0_rs1_d <= _T_105 @[Mux.scala 27:72] i0_rs1_d <= _T_105 @[Mux.scala 27:72]
node _T_106 = bits(x_data_en_q1, 0, 0) @[exu.scala 105:88] node _T_106 = bits(x_data_en_q1, 0, 0) @[exu.scala 104:88]
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23]
rvclkhdr_7.clock <= clock rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset rvclkhdr_7.reset <= reset
@ -44895,13 +44895,13 @@ circuit exu :
when _T_106 : @[Reg.scala 28:19] when _T_106 : @[Reg.scala 28:19]
_T_107 <= i0_rs1_d @[Reg.scala 28:23] _T_107 <= i0_rs1_d @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
io.dec_exu.decode_exu.exu_csr_rs1_x <= _T_107 @[exu.scala 105:57] io.dec_exu.decode_exu.exu_csr_rs1_x <= _T_107 @[exu.scala 104:57]
node _T_108 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 108:6] node _T_108 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 107:6]
node _T_109 = and(_T_108, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 108:26] node _T_109 = and(_T_108, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 107:26]
node _T_110 = bits(_T_109, 0, 0) @[exu.scala 108:67] node _T_110 = bits(_T_109, 0, 0) @[exu.scala 107:67]
node _T_111 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 109:6] node _T_111 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 108:6]
node _T_112 = bits(_T_111, 0, 0) @[exu.scala 109:27] node _T_112 = bits(_T_111, 0, 0) @[exu.scala 108:27]
node _T_113 = bits(i0_rs2_bypass_en_d, 0, 0) @[exu.scala 110:26] node _T_113 = bits(i0_rs2_bypass_en_d, 0, 0) @[exu.scala 109:26]
node _T_114 = mux(_T_110, io.dec_exu.gpr_exu.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_114 = mux(_T_110, io.dec_exu.gpr_exu.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_115 = mux(_T_112, io.dec_exu.decode_exu.dec_i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_115 = mux(_T_112, io.dec_exu.decode_exu.dec_i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_116 = mux(_T_113, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_116 = mux(_T_113, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
@ -44909,18 +44909,18 @@ circuit exu :
node _T_118 = or(_T_117, _T_116) @[Mux.scala 27:72] node _T_118 = or(_T_117, _T_116) @[Mux.scala 27:72]
wire i0_rs2_d : UInt<32> @[Mux.scala 27:72] wire i0_rs2_d : UInt<32> @[Mux.scala 27:72]
i0_rs2_d <= _T_118 @[Mux.scala 27:72] i0_rs2_d <= _T_118 @[Mux.scala 27:72]
node _T_119 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 115:6] node _T_119 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 114:6]
node _T_120 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 115:28] node _T_120 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 114:28]
node _T_121 = and(_T_119, _T_120) @[exu.scala 115:26] node _T_121 = and(_T_119, _T_120) @[exu.scala 114:26]
node _T_122 = and(_T_121, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 115:68] node _T_122 = and(_T_121, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 114:68]
node _T_123 = and(_T_122, io.dec_qual_lsu_d) @[exu.scala 115:108] node _T_123 = and(_T_122, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 114:108]
node _T_124 = bits(_T_123, 0, 0) @[exu.scala 115:129] node _T_124 = bits(_T_123, 0, 0) @[exu.scala 114:148]
node _T_125 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 116:27] node _T_125 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 115:27]
node _T_126 = and(i0_rs1_bypass_en_d, _T_125) @[exu.scala 116:25] node _T_126 = and(i0_rs1_bypass_en_d, _T_125) @[exu.scala 115:25]
node _T_127 = and(_T_126, io.dec_qual_lsu_d) @[exu.scala 116:67] node _T_127 = and(_T_126, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 115:67]
node _T_128 = bits(_T_127, 0, 0) @[exu.scala 116:88] node _T_128 = bits(_T_127, 0, 0) @[exu.scala 115:107]
node _T_129 = and(io.dec_exu.decode_exu.dec_extint_stall, io.dec_qual_lsu_d) @[exu.scala 117:45] node _T_129 = and(io.dec_exu.decode_exu.dec_extint_stall, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 116:45]
node _T_130 = bits(_T_129, 0, 0) @[exu.scala 117:66] node _T_130 = bits(_T_129, 0, 0) @[exu.scala 116:85]
node _T_131 = cat(io.dec_exu.tlu_exu.dec_tlu_meihap, UInt<2>("h00")) @[Cat.scala 29:58] node _T_131 = cat(io.dec_exu.tlu_exu.dec_tlu_meihap, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_132 = mux(_T_124, io.dec_exu.gpr_exu.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_132 = mux(_T_124, io.dec_exu.gpr_exu.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_133 = mux(_T_128, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_133 = mux(_T_128, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
@ -44929,40 +44929,39 @@ circuit exu :
node _T_136 = or(_T_135, _T_134) @[Mux.scala 27:72] node _T_136 = or(_T_135, _T_134) @[Mux.scala 27:72]
wire _T_137 : UInt<32> @[Mux.scala 27:72] wire _T_137 : UInt<32> @[Mux.scala 27:72]
_T_137 <= _T_136 @[Mux.scala 27:72] _T_137 <= _T_136 @[Mux.scala 27:72]
io.lsu_exu.exu_lsu_rs1_d <= _T_137 @[exu.scala 114:27] io.lsu_exu.exu_lsu_rs1_d <= _T_137 @[exu.scala 113:27]
node _T_138 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 121:6] node _T_138 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 120:6]
node _T_139 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 121:28] node _T_139 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 120:28]
node _T_140 = and(_T_138, _T_139) @[exu.scala 121:26] node _T_140 = and(_T_138, _T_139) @[exu.scala 120:26]
node _T_141 = and(_T_140, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 121:68] node _T_141 = and(_T_140, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 120:68]
node _T_142 = and(_T_141, io.dec_qual_lsu_d) @[exu.scala 121:108] node _T_142 = and(_T_141, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 120:108]
node _T_143 = bits(_T_142, 0, 0) @[exu.scala 121:129] node _T_143 = bits(_T_142, 0, 0) @[exu.scala 120:148]
node _T_144 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 122:27] node _T_144 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 121:27]
node _T_145 = and(i0_rs2_bypass_en_d, _T_144) @[exu.scala 122:25] node _T_145 = and(i0_rs2_bypass_en_d, _T_144) @[exu.scala 121:25]
node _T_146 = and(_T_145, io.dec_qual_lsu_d) @[exu.scala 122:67] node _T_146 = and(_T_145, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 121:67]
node _T_147 = bits(_T_146, 0, 0) @[exu.scala 122:88] node _T_147 = bits(_T_146, 0, 0) @[exu.scala 121:107]
node _T_148 = mux(_T_143, io.dec_exu.gpr_exu.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_148 = mux(_T_143, io.dec_exu.gpr_exu.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_149 = mux(_T_147, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_149 = mux(_T_147, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_150 = or(_T_148, _T_149) @[Mux.scala 27:72] node _T_150 = or(_T_148, _T_149) @[Mux.scala 27:72]
wire _T_151 : UInt<32> @[Mux.scala 27:72] wire _T_151 : UInt<32> @[Mux.scala 27:72]
_T_151 <= _T_150 @[Mux.scala 27:72] _T_151 <= _T_150 @[Mux.scala 27:72]
io.lsu_exu.exu_lsu_rs2_d <= _T_151 @[exu.scala 120:27] io.lsu_exu.exu_lsu_rs2_d <= _T_151 @[exu.scala 119:27]
node _T_152 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 126:6] node _T_152 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 125:6]
node _T_153 = and(_T_152, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 126:26] node _T_153 = and(_T_152, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 125:26]
node _T_154 = bits(_T_153, 0, 0) @[exu.scala 126:67] node _T_154 = bits(_T_153, 0, 0) @[exu.scala 125:67]
node _T_155 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 127:26] node _T_155 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 126:26]
node _T_156 = mux(_T_154, io.dec_exu.gpr_exu.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_156 = mux(_T_154, io.dec_exu.gpr_exu.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_157 = mux(_T_155, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_157 = mux(_T_155, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_158 = or(_T_156, _T_157) @[Mux.scala 27:72] node _T_158 = or(_T_156, _T_157) @[Mux.scala 27:72]
wire muldiv_rs1_d : UInt<32> @[Mux.scala 27:72] wire muldiv_rs1_d : UInt<32> @[Mux.scala 27:72]
muldiv_rs1_d <= _T_158 @[Mux.scala 27:72] muldiv_rs1_d <= _T_158 @[Mux.scala 27:72]
inst i_alu of exu_alu_ctl @[exu.scala 130:19] inst i_alu of exu_alu_ctl @[exu.scala 129:19]
i_alu.clock <= clock i_alu.clock <= clock
i_alu.reset <= reset i_alu.reset <= reset
io.dec_exu.dec_alu.exu_i0_pc_x <= i_alu.io.dec_alu.exu_i0_pc_x @[exu.scala 131:20] io.dec_exu.dec_alu.exu_i0_pc_x <= i_alu.io.dec_alu.exu_i0_pc_x @[exu.scala 130:20]
i_alu.io.dec_alu.dec_i0_br_immed_d <= io.dec_exu.dec_alu.dec_i0_br_immed_d @[exu.scala 131:20] i_alu.io.dec_alu.dec_i0_br_immed_d <= io.dec_exu.dec_alu.dec_i0_br_immed_d @[exu.scala 130:20]
i_alu.io.dec_alu.dec_csr_rddata_d <= io.dec_exu.dec_alu.dec_csr_rddata_d @[exu.scala 131:20] i_alu.io.dec_alu.dec_csr_ren_d <= io.dec_exu.dec_alu.dec_csr_ren_d @[exu.scala 130:20]
i_alu.io.dec_alu.dec_csr_ren_d <= io.dec_exu.dec_alu.dec_csr_ren_d @[exu.scala 131:20] i_alu.io.dec_alu.dec_i0_alu_decode_d <= io.dec_exu.dec_alu.dec_i0_alu_decode_d @[exu.scala 130:20]
i_alu.io.dec_alu.dec_i0_alu_decode_d <= io.dec_exu.dec_alu.dec_i0_alu_decode_d @[exu.scala 131:20]
i_alu.io.scan_mode <= io.scan_mode @[exu.scala 132:35] i_alu.io.scan_mode <= io.scan_mode @[exu.scala 132:35]
i_alu.io.enable <= x_data_en @[exu.scala 133:45] i_alu.io.enable <= x_data_en @[exu.scala 133:45]
i_alu.io.pp_in.bits.prett <= i0_predict_newp_d.bits.prett @[exu.scala 134:45] i_alu.io.pp_in.bits.prett <= i0_predict_newp_d.bits.prett @[exu.scala 134:45]
@ -44980,155 +44979,156 @@ circuit exu :
i_alu.io.pp_in.bits.misp <= i0_predict_newp_d.bits.misp @[exu.scala 134:45] i_alu.io.pp_in.bits.misp <= i0_predict_newp_d.bits.misp @[exu.scala 134:45]
i_alu.io.pp_in.valid <= i0_predict_newp_d.valid @[exu.scala 134:45] i_alu.io.pp_in.valid <= i0_predict_newp_d.valid @[exu.scala 134:45]
i_alu.io.flush_upper_x <= i0_flush_upper_x @[exu.scala 135:33] i_alu.io.flush_upper_x <= i0_flush_upper_x @[exu.scala 135:33]
i_alu.io.dec_tlu_flush_lower_r <= io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[exu.scala 136:41] i_alu.io.csr_rddata_in <= io.dec_csr_rddata_d @[exu.scala 136:33]
node _T_159 = asSInt(i0_rs1_d) @[exu.scala 137:50] i_alu.io.dec_tlu_flush_lower_r <= io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[exu.scala 137:41]
i_alu.io.a_in <= _T_159 @[exu.scala 137:39] node _T_159 = asSInt(i0_rs1_d) @[exu.scala 138:50]
i_alu.io.b_in <= i0_rs2_d @[exu.scala 138:39] i_alu.io.a_in <= _T_159 @[exu.scala 138:39]
i_alu.io.dec_i0_pc_d <= io.dec_exu.ib_exu.dec_i0_pc_d @[exu.scala 139:33] i_alu.io.b_in <= i0_rs2_d @[exu.scala 139:39]
i_alu.io.i0_ap.csr_imm <= io.dec_exu.decode_exu.i0_ap.csr_imm @[exu.scala 140:51] i_alu.io.dec_i0_pc_d <= io.dec_exu.ib_exu.dec_i0_pc_d @[exu.scala 140:33]
i_alu.io.i0_ap.csr_write <= io.dec_exu.decode_exu.i0_ap.csr_write @[exu.scala 140:51] i_alu.io.i0_ap.csr_imm <= io.dec_exu.decode_exu.i0_ap.csr_imm @[exu.scala 141:51]
i_alu.io.i0_ap.predict_nt <= io.dec_exu.decode_exu.i0_ap.predict_nt @[exu.scala 140:51] i_alu.io.i0_ap.csr_write <= io.dec_exu.decode_exu.i0_ap.csr_write @[exu.scala 141:51]
i_alu.io.i0_ap.predict_t <= io.dec_exu.decode_exu.i0_ap.predict_t @[exu.scala 140:51] i_alu.io.i0_ap.predict_nt <= io.dec_exu.decode_exu.i0_ap.predict_nt @[exu.scala 141:51]
i_alu.io.i0_ap.jal <= io.dec_exu.decode_exu.i0_ap.jal @[exu.scala 140:51] i_alu.io.i0_ap.predict_t <= io.dec_exu.decode_exu.i0_ap.predict_t @[exu.scala 141:51]
i_alu.io.i0_ap.unsign <= io.dec_exu.decode_exu.i0_ap.unsign @[exu.scala 140:51] i_alu.io.i0_ap.jal <= io.dec_exu.decode_exu.i0_ap.jal @[exu.scala 141:51]
i_alu.io.i0_ap.slt <= io.dec_exu.decode_exu.i0_ap.slt @[exu.scala 140:51] i_alu.io.i0_ap.unsign <= io.dec_exu.decode_exu.i0_ap.unsign @[exu.scala 141:51]
i_alu.io.i0_ap.sub <= io.dec_exu.decode_exu.i0_ap.sub @[exu.scala 140:51] i_alu.io.i0_ap.slt <= io.dec_exu.decode_exu.i0_ap.slt @[exu.scala 141:51]
i_alu.io.i0_ap.add <= io.dec_exu.decode_exu.i0_ap.add @[exu.scala 140:51] i_alu.io.i0_ap.sub <= io.dec_exu.decode_exu.i0_ap.sub @[exu.scala 141:51]
i_alu.io.i0_ap.bge <= io.dec_exu.decode_exu.i0_ap.bge @[exu.scala 140:51] i_alu.io.i0_ap.add <= io.dec_exu.decode_exu.i0_ap.add @[exu.scala 141:51]
i_alu.io.i0_ap.blt <= io.dec_exu.decode_exu.i0_ap.blt @[exu.scala 140:51] i_alu.io.i0_ap.bge <= io.dec_exu.decode_exu.i0_ap.bge @[exu.scala 141:51]
i_alu.io.i0_ap.bne <= io.dec_exu.decode_exu.i0_ap.bne @[exu.scala 140:51] i_alu.io.i0_ap.blt <= io.dec_exu.decode_exu.i0_ap.blt @[exu.scala 141:51]
i_alu.io.i0_ap.beq <= io.dec_exu.decode_exu.i0_ap.beq @[exu.scala 140:51] i_alu.io.i0_ap.bne <= io.dec_exu.decode_exu.i0_ap.bne @[exu.scala 141:51]
i_alu.io.i0_ap.sra <= io.dec_exu.decode_exu.i0_ap.sra @[exu.scala 140:51] i_alu.io.i0_ap.beq <= io.dec_exu.decode_exu.i0_ap.beq @[exu.scala 141:51]
i_alu.io.i0_ap.srl <= io.dec_exu.decode_exu.i0_ap.srl @[exu.scala 140:51] i_alu.io.i0_ap.sra <= io.dec_exu.decode_exu.i0_ap.sra @[exu.scala 141:51]
i_alu.io.i0_ap.sll <= io.dec_exu.decode_exu.i0_ap.sll @[exu.scala 140:51] i_alu.io.i0_ap.srl <= io.dec_exu.decode_exu.i0_ap.srl @[exu.scala 141:51]
i_alu.io.i0_ap.lxor <= io.dec_exu.decode_exu.i0_ap.lxor @[exu.scala 140:51] i_alu.io.i0_ap.sll <= io.dec_exu.decode_exu.i0_ap.sll @[exu.scala 141:51]
i_alu.io.i0_ap.lor <= io.dec_exu.decode_exu.i0_ap.lor @[exu.scala 140:51] i_alu.io.i0_ap.lxor <= io.dec_exu.decode_exu.i0_ap.lxor @[exu.scala 141:51]
i_alu.io.i0_ap.land <= io.dec_exu.decode_exu.i0_ap.land @[exu.scala 140:51] i_alu.io.i0_ap.lor <= io.dec_exu.decode_exu.i0_ap.lor @[exu.scala 141:51]
i_alu.io.i0_ap.zba <= io.dec_exu.decode_exu.i0_ap.zba @[exu.scala 140:51] i_alu.io.i0_ap.land <= io.dec_exu.decode_exu.i0_ap.land @[exu.scala 141:51]
i_alu.io.i0_ap.sh3add <= io.dec_exu.decode_exu.i0_ap.sh3add @[exu.scala 140:51] i_alu.io.i0_ap.zba <= io.dec_exu.decode_exu.i0_ap.zba @[exu.scala 141:51]
i_alu.io.i0_ap.sh2add <= io.dec_exu.decode_exu.i0_ap.sh2add @[exu.scala 140:51] i_alu.io.i0_ap.sh3add <= io.dec_exu.decode_exu.i0_ap.sh3add @[exu.scala 141:51]
i_alu.io.i0_ap.sh1add <= io.dec_exu.decode_exu.i0_ap.sh1add @[exu.scala 140:51] i_alu.io.i0_ap.sh2add <= io.dec_exu.decode_exu.i0_ap.sh2add @[exu.scala 141:51]
i_alu.io.i0_ap.sbext <= io.dec_exu.decode_exu.i0_ap.sbext @[exu.scala 140:51] i_alu.io.i0_ap.sh1add <= io.dec_exu.decode_exu.i0_ap.sh1add @[exu.scala 141:51]
i_alu.io.i0_ap.sbinv <= io.dec_exu.decode_exu.i0_ap.sbinv @[exu.scala 140:51] i_alu.io.i0_ap.sbext <= io.dec_exu.decode_exu.i0_ap.sbext @[exu.scala 141:51]
i_alu.io.i0_ap.sbclr <= io.dec_exu.decode_exu.i0_ap.sbclr @[exu.scala 140:51] i_alu.io.i0_ap.sbinv <= io.dec_exu.decode_exu.i0_ap.sbinv @[exu.scala 141:51]
i_alu.io.i0_ap.sbset <= io.dec_exu.decode_exu.i0_ap.sbset @[exu.scala 140:51] i_alu.io.i0_ap.sbclr <= io.dec_exu.decode_exu.i0_ap.sbclr @[exu.scala 141:51]
i_alu.io.i0_ap.zbb <= io.dec_exu.decode_exu.i0_ap.zbb @[exu.scala 140:51] i_alu.io.i0_ap.sbset <= io.dec_exu.decode_exu.i0_ap.sbset @[exu.scala 141:51]
i_alu.io.i0_ap.gorc <= io.dec_exu.decode_exu.i0_ap.gorc @[exu.scala 140:51] i_alu.io.i0_ap.zbb <= io.dec_exu.decode_exu.i0_ap.zbb @[exu.scala 141:51]
i_alu.io.i0_ap.grev <= io.dec_exu.decode_exu.i0_ap.grev @[exu.scala 140:51] i_alu.io.i0_ap.gorc <= io.dec_exu.decode_exu.i0_ap.gorc @[exu.scala 141:51]
i_alu.io.i0_ap.ror <= io.dec_exu.decode_exu.i0_ap.ror @[exu.scala 140:51] i_alu.io.i0_ap.grev <= io.dec_exu.decode_exu.i0_ap.grev @[exu.scala 141:51]
i_alu.io.i0_ap.rol <= io.dec_exu.decode_exu.i0_ap.rol @[exu.scala 140:51] i_alu.io.i0_ap.ror <= io.dec_exu.decode_exu.i0_ap.ror @[exu.scala 141:51]
i_alu.io.i0_ap.packh <= io.dec_exu.decode_exu.i0_ap.packh @[exu.scala 140:51] i_alu.io.i0_ap.rol <= io.dec_exu.decode_exu.i0_ap.rol @[exu.scala 141:51]
i_alu.io.i0_ap.packu <= io.dec_exu.decode_exu.i0_ap.packu @[exu.scala 140:51] i_alu.io.i0_ap.packh <= io.dec_exu.decode_exu.i0_ap.packh @[exu.scala 141:51]
i_alu.io.i0_ap.pack <= io.dec_exu.decode_exu.i0_ap.pack @[exu.scala 140:51] i_alu.io.i0_ap.packu <= io.dec_exu.decode_exu.i0_ap.packu @[exu.scala 141:51]
i_alu.io.i0_ap.max <= io.dec_exu.decode_exu.i0_ap.max @[exu.scala 140:51] i_alu.io.i0_ap.pack <= io.dec_exu.decode_exu.i0_ap.pack @[exu.scala 141:51]
i_alu.io.i0_ap.min <= io.dec_exu.decode_exu.i0_ap.min @[exu.scala 140:51] i_alu.io.i0_ap.max <= io.dec_exu.decode_exu.i0_ap.max @[exu.scala 141:51]
i_alu.io.i0_ap.sro <= io.dec_exu.decode_exu.i0_ap.sro @[exu.scala 140:51] i_alu.io.i0_ap.min <= io.dec_exu.decode_exu.i0_ap.min @[exu.scala 141:51]
i_alu.io.i0_ap.slo <= io.dec_exu.decode_exu.i0_ap.slo @[exu.scala 140:51] i_alu.io.i0_ap.sro <= io.dec_exu.decode_exu.i0_ap.sro @[exu.scala 141:51]
i_alu.io.i0_ap.sext_h <= io.dec_exu.decode_exu.i0_ap.sext_h @[exu.scala 140:51] i_alu.io.i0_ap.slo <= io.dec_exu.decode_exu.i0_ap.slo @[exu.scala 141:51]
i_alu.io.i0_ap.sext_b <= io.dec_exu.decode_exu.i0_ap.sext_b @[exu.scala 140:51] i_alu.io.i0_ap.sext_h <= io.dec_exu.decode_exu.i0_ap.sext_h @[exu.scala 141:51]
i_alu.io.i0_ap.pcnt <= io.dec_exu.decode_exu.i0_ap.pcnt @[exu.scala 140:51] i_alu.io.i0_ap.sext_b <= io.dec_exu.decode_exu.i0_ap.sext_b @[exu.scala 141:51]
i_alu.io.i0_ap.ctz <= io.dec_exu.decode_exu.i0_ap.ctz @[exu.scala 140:51] i_alu.io.i0_ap.pcnt <= io.dec_exu.decode_exu.i0_ap.pcnt @[exu.scala 141:51]
i_alu.io.i0_ap.clz <= io.dec_exu.decode_exu.i0_ap.clz @[exu.scala 140:51] i_alu.io.i0_ap.ctz <= io.dec_exu.decode_exu.i0_ap.ctz @[exu.scala 141:51]
i0_flush_upper_d <= i_alu.io.flush_upper_out @[exu.scala 142:35] i_alu.io.i0_ap.clz <= io.dec_exu.decode_exu.i0_ap.clz @[exu.scala 141:51]
i0_flush_path_d <= i_alu.io.flush_path_out @[exu.scala 143:45] i0_flush_upper_d <= i_alu.io.flush_upper_out @[exu.scala 143:35]
io.exu_flush_final <= i_alu.io.flush_final_out @[exu.scala 144:27] i0_flush_path_d <= i_alu.io.flush_path_out @[exu.scala 144:45]
i0_predict_p_d.bits.prett <= i_alu.io.predict_p_out.bits.prett @[exu.scala 145:45] io.exu_flush_final <= i_alu.io.flush_final_out @[exu.scala 145:27]
i0_predict_p_d.bits.pret <= i_alu.io.predict_p_out.bits.pret @[exu.scala 145:45] i0_predict_p_d.bits.prett <= i_alu.io.predict_p_out.bits.prett @[exu.scala 146:45]
i0_predict_p_d.bits.way <= i_alu.io.predict_p_out.bits.way @[exu.scala 145:45] i0_predict_p_d.bits.pret <= i_alu.io.predict_p_out.bits.pret @[exu.scala 146:45]
i0_predict_p_d.bits.pja <= i_alu.io.predict_p_out.bits.pja @[exu.scala 145:45] i0_predict_p_d.bits.way <= i_alu.io.predict_p_out.bits.way @[exu.scala 146:45]
i0_predict_p_d.bits.pcall <= i_alu.io.predict_p_out.bits.pcall @[exu.scala 145:45] i0_predict_p_d.bits.pja <= i_alu.io.predict_p_out.bits.pja @[exu.scala 146:45]
i0_predict_p_d.bits.br_start_error <= i_alu.io.predict_p_out.bits.br_start_error @[exu.scala 145:45] i0_predict_p_d.bits.pcall <= i_alu.io.predict_p_out.bits.pcall @[exu.scala 146:45]
i0_predict_p_d.bits.br_error <= i_alu.io.predict_p_out.bits.br_error @[exu.scala 145:45] i0_predict_p_d.bits.br_start_error <= i_alu.io.predict_p_out.bits.br_start_error @[exu.scala 146:45]
i0_predict_p_d.bits.toffset <= i_alu.io.predict_p_out.bits.toffset @[exu.scala 145:45] i0_predict_p_d.bits.br_error <= i_alu.io.predict_p_out.bits.br_error @[exu.scala 146:45]
i0_predict_p_d.bits.hist <= i_alu.io.predict_p_out.bits.hist @[exu.scala 145:45] i0_predict_p_d.bits.toffset <= i_alu.io.predict_p_out.bits.toffset @[exu.scala 146:45]
i0_predict_p_d.bits.pc4 <= i_alu.io.predict_p_out.bits.pc4 @[exu.scala 145:45] i0_predict_p_d.bits.hist <= i_alu.io.predict_p_out.bits.hist @[exu.scala 146:45]
i0_predict_p_d.bits.boffset <= i_alu.io.predict_p_out.bits.boffset @[exu.scala 145:45] i0_predict_p_d.bits.pc4 <= i_alu.io.predict_p_out.bits.pc4 @[exu.scala 146:45]
i0_predict_p_d.bits.ataken <= i_alu.io.predict_p_out.bits.ataken @[exu.scala 145:45] i0_predict_p_d.bits.boffset <= i_alu.io.predict_p_out.bits.boffset @[exu.scala 146:45]
i0_predict_p_d.bits.misp <= i_alu.io.predict_p_out.bits.misp @[exu.scala 145:45] i0_predict_p_d.bits.ataken <= i_alu.io.predict_p_out.bits.ataken @[exu.scala 146:45]
i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[exu.scala 145:45] i0_predict_p_d.bits.misp <= i_alu.io.predict_p_out.bits.misp @[exu.scala 146:45]
i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[exu.scala 146:27] i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[exu.scala 146:45]
inst i_mul of exu_mul_ctl @[exu.scala 148:21] i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[exu.scala 147:27]
inst i_mul of exu_mul_ctl @[exu.scala 149:21]
i_mul.clock <= clock i_mul.clock <= clock
i_mul.reset <= reset i_mul.reset <= reset
i_mul.io.scan_mode <= io.scan_mode @[exu.scala 149:25] i_mul.io.scan_mode <= io.scan_mode @[exu.scala 150:25]
i_mul.io.mul_p.bits.bfp <= io.dec_exu.decode_exu.mul_p.bits.bfp @[exu.scala 150:23] i_mul.io.mul_p.bits.bfp <= io.dec_exu.decode_exu.mul_p.bits.bfp @[exu.scala 151:23]
i_mul.io.mul_p.bits.crc32c_w <= io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[exu.scala 150:23] i_mul.io.mul_p.bits.crc32c_w <= io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[exu.scala 151:23]
i_mul.io.mul_p.bits.crc32c_h <= io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[exu.scala 150:23] i_mul.io.mul_p.bits.crc32c_h <= io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[exu.scala 151:23]
i_mul.io.mul_p.bits.crc32c_b <= io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[exu.scala 150:23] i_mul.io.mul_p.bits.crc32c_b <= io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[exu.scala 151:23]
i_mul.io.mul_p.bits.crc32_w <= io.dec_exu.decode_exu.mul_p.bits.crc32_w @[exu.scala 150:23] i_mul.io.mul_p.bits.crc32_w <= io.dec_exu.decode_exu.mul_p.bits.crc32_w @[exu.scala 151:23]
i_mul.io.mul_p.bits.crc32_h <= io.dec_exu.decode_exu.mul_p.bits.crc32_h @[exu.scala 150:23] i_mul.io.mul_p.bits.crc32_h <= io.dec_exu.decode_exu.mul_p.bits.crc32_h @[exu.scala 151:23]
i_mul.io.mul_p.bits.crc32_b <= io.dec_exu.decode_exu.mul_p.bits.crc32_b @[exu.scala 150:23] i_mul.io.mul_p.bits.crc32_b <= io.dec_exu.decode_exu.mul_p.bits.crc32_b @[exu.scala 151:23]
i_mul.io.mul_p.bits.unshfl <= io.dec_exu.decode_exu.mul_p.bits.unshfl @[exu.scala 150:23] i_mul.io.mul_p.bits.unshfl <= io.dec_exu.decode_exu.mul_p.bits.unshfl @[exu.scala 151:23]
i_mul.io.mul_p.bits.shfl <= io.dec_exu.decode_exu.mul_p.bits.shfl @[exu.scala 150:23] i_mul.io.mul_p.bits.shfl <= io.dec_exu.decode_exu.mul_p.bits.shfl @[exu.scala 151:23]
i_mul.io.mul_p.bits.gorc <= io.dec_exu.decode_exu.mul_p.bits.gorc @[exu.scala 150:23] i_mul.io.mul_p.bits.gorc <= io.dec_exu.decode_exu.mul_p.bits.gorc @[exu.scala 151:23]
i_mul.io.mul_p.bits.grev <= io.dec_exu.decode_exu.mul_p.bits.grev @[exu.scala 150:23] i_mul.io.mul_p.bits.grev <= io.dec_exu.decode_exu.mul_p.bits.grev @[exu.scala 151:23]
i_mul.io.mul_p.bits.clmulr <= io.dec_exu.decode_exu.mul_p.bits.clmulr @[exu.scala 150:23] i_mul.io.mul_p.bits.clmulr <= io.dec_exu.decode_exu.mul_p.bits.clmulr @[exu.scala 151:23]
i_mul.io.mul_p.bits.clmulh <= io.dec_exu.decode_exu.mul_p.bits.clmulh @[exu.scala 150:23] i_mul.io.mul_p.bits.clmulh <= io.dec_exu.decode_exu.mul_p.bits.clmulh @[exu.scala 151:23]
i_mul.io.mul_p.bits.clmul <= io.dec_exu.decode_exu.mul_p.bits.clmul @[exu.scala 150:23] i_mul.io.mul_p.bits.clmul <= io.dec_exu.decode_exu.mul_p.bits.clmul @[exu.scala 151:23]
i_mul.io.mul_p.bits.bdep <= io.dec_exu.decode_exu.mul_p.bits.bdep @[exu.scala 150:23] i_mul.io.mul_p.bits.bdep <= io.dec_exu.decode_exu.mul_p.bits.bdep @[exu.scala 151:23]
i_mul.io.mul_p.bits.bext <= io.dec_exu.decode_exu.mul_p.bits.bext @[exu.scala 150:23] i_mul.io.mul_p.bits.bext <= io.dec_exu.decode_exu.mul_p.bits.bext @[exu.scala 151:23]
i_mul.io.mul_p.bits.low <= io.dec_exu.decode_exu.mul_p.bits.low @[exu.scala 150:23] i_mul.io.mul_p.bits.low <= io.dec_exu.decode_exu.mul_p.bits.low @[exu.scala 151:23]
i_mul.io.mul_p.bits.rs2_sign <= io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[exu.scala 150:23] i_mul.io.mul_p.bits.rs2_sign <= io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[exu.scala 151:23]
i_mul.io.mul_p.bits.rs1_sign <= io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[exu.scala 150:23] i_mul.io.mul_p.bits.rs1_sign <= io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[exu.scala 151:23]
i_mul.io.mul_p.valid <= io.dec_exu.decode_exu.mul_p.valid @[exu.scala 150:23] i_mul.io.mul_p.valid <= io.dec_exu.decode_exu.mul_p.valid @[exu.scala 151:23]
node _T_160 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] node _T_160 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15]
node _T_161 = mux(_T_160, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] node _T_161 = mux(_T_160, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_162 = and(muldiv_rs1_d, _T_161) @[exu.scala 152:57] node _T_162 = and(muldiv_rs1_d, _T_161) @[exu.scala 153:57]
i_mul.io.rs1_in <= _T_162 @[exu.scala 152:41] i_mul.io.rs1_in <= _T_162 @[exu.scala 153:41]
node _T_163 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] node _T_163 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15]
node _T_164 = mux(_T_163, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] node _T_164 = mux(_T_163, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_165 = and(i0_rs2_d, _T_164) @[exu.scala 153:54] node _T_165 = and(i0_rs2_d, _T_164) @[exu.scala 154:54]
i_mul.io.rs2_in <= _T_165 @[exu.scala 153:41] i_mul.io.rs2_in <= _T_165 @[exu.scala 154:41]
inst i_div of exu_div_ctl @[exu.scala 156:21] inst i_div of exu_div_ctl @[exu.scala 157:21]
i_div.clock <= clock i_div.clock <= clock
i_div.reset <= reset i_div.reset <= reset
i_div.io.dec_div.dec_div_cancel <= io.dec_exu.dec_div.dec_div_cancel @[exu.scala 157:20] i_div.io.dec_div.dec_div_cancel <= io.dec_exu.dec_div.dec_div_cancel @[exu.scala 158:20]
i_div.io.dec_div.div_p.bits.rem <= io.dec_exu.dec_div.div_p.bits.rem @[exu.scala 157:20] i_div.io.dec_div.div_p.bits.rem <= io.dec_exu.dec_div.div_p.bits.rem @[exu.scala 158:20]
i_div.io.dec_div.div_p.bits.unsign <= io.dec_exu.dec_div.div_p.bits.unsign @[exu.scala 157:20] i_div.io.dec_div.div_p.bits.unsign <= io.dec_exu.dec_div.div_p.bits.unsign @[exu.scala 158:20]
i_div.io.dec_div.div_p.valid <= io.dec_exu.dec_div.div_p.valid @[exu.scala 157:20] i_div.io.dec_div.div_p.valid <= io.dec_exu.dec_div.div_p.valid @[exu.scala 158:20]
i_div.io.scan_mode <= io.scan_mode @[exu.scala 158:25] i_div.io.scan_mode <= io.scan_mode @[exu.scala 159:25]
i_div.io.dividend <= muldiv_rs1_d @[exu.scala 159:33] i_div.io.dividend <= muldiv_rs1_d @[exu.scala 160:33]
i_div.io.divisor <= i0_rs2_d @[exu.scala 160:33] i_div.io.divisor <= i0_rs2_d @[exu.scala 161:33]
io.exu_div_wren <= i_div.io.exu_div_wren @[exu.scala 161:41] io.exu_div_wren <= i_div.io.exu_div_wren @[exu.scala 162:41]
io.exu_div_result <= i_div.io.exu_div_result @[exu.scala 162:33] io.exu_div_result <= i_div.io.exu_div_result @[exu.scala 163:33]
node _T_166 = bits(mul_valid_x, 0, 0) @[exu.scala 164:76] node _T_166 = bits(mul_valid_x, 0, 0) @[exu.scala 165:76]
node _T_167 = mux(_T_166, i_mul.io.result_x, i_alu.io.result_ff) @[exu.scala 164:63] node _T_167 = mux(_T_166, i_mul.io.result_x, i_alu.io.result_ff) @[exu.scala 165:63]
io.dec_exu.decode_exu.exu_i0_result_x <= _T_167 @[exu.scala 164:57] io.dec_exu.decode_exu.exu_i0_result_x <= _T_167 @[exu.scala 165:57]
i0_predict_newp_d.bits.prett <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[exu.scala 165:47] i0_predict_newp_d.bits.prett <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[exu.scala 166:47]
i0_predict_newp_d.bits.pret <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[exu.scala 165:47] i0_predict_newp_d.bits.pret <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[exu.scala 166:47]
i0_predict_newp_d.bits.way <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[exu.scala 165:47] i0_predict_newp_d.bits.way <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[exu.scala 166:47]
i0_predict_newp_d.bits.pja <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[exu.scala 165:47] i0_predict_newp_d.bits.pja <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[exu.scala 166:47]
i0_predict_newp_d.bits.pcall <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[exu.scala 165:47] i0_predict_newp_d.bits.pcall <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[exu.scala 166:47]
i0_predict_newp_d.bits.br_start_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[exu.scala 165:47] i0_predict_newp_d.bits.br_start_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[exu.scala 166:47]
i0_predict_newp_d.bits.br_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[exu.scala 165:47] i0_predict_newp_d.bits.br_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[exu.scala 166:47]
i0_predict_newp_d.bits.toffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[exu.scala 165:47] i0_predict_newp_d.bits.toffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[exu.scala 166:47]
i0_predict_newp_d.bits.hist <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[exu.scala 165:47] i0_predict_newp_d.bits.hist <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[exu.scala 166:47]
i0_predict_newp_d.bits.pc4 <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[exu.scala 165:47] i0_predict_newp_d.bits.pc4 <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[exu.scala 166:47]
i0_predict_newp_d.bits.boffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[exu.scala 165:47] i0_predict_newp_d.bits.boffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[exu.scala 166:47]
i0_predict_newp_d.bits.ataken <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[exu.scala 165:47] i0_predict_newp_d.bits.ataken <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[exu.scala 166:47]
i0_predict_newp_d.bits.misp <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[exu.scala 165:47] i0_predict_newp_d.bits.misp <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[exu.scala 166:47]
i0_predict_newp_d.valid <= io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[exu.scala 165:47] i0_predict_newp_d.valid <= io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[exu.scala 166:47]
node _T_168 = bits(io.dec_exu.ib_exu.dec_i0_pc_d, 0, 0) @[exu.scala 166:80] node _T_168 = bits(io.dec_exu.ib_exu.dec_i0_pc_d, 0, 0) @[exu.scala 167:80]
i0_predict_newp_d.bits.boffset <= _T_168 @[exu.scala 166:47] i0_predict_newp_d.bits.boffset <= _T_168 @[exu.scala 167:47]
io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= i0_pp_r.bits.misp @[exu.scala 168:47] io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= i0_pp_r.bits.misp @[exu.scala 169:47]
io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= i0_pp_r.bits.ataken @[exu.scala 169:47] io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= i0_pp_r.bits.ataken @[exu.scala 170:47]
io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= i0_pp_r.bits.pc4 @[exu.scala 170:47] io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= i0_pp_r.bits.pc4 @[exu.scala 171:47]
node _T_169 = and(i0_predict_p_d.valid, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 173:54] node _T_169 = and(i0_predict_p_d.valid, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 174:54]
node _T_170 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 173:97] node _T_170 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 174:97]
node _T_171 = and(_T_169, _T_170) @[exu.scala 173:95] node _T_171 = and(_T_169, _T_170) @[exu.scala 174:95]
i0_valid_d <= _T_171 @[exu.scala 173:28] i0_valid_d <= _T_171 @[exu.scala 174:28]
node _T_172 = and(i0_predict_p_d.bits.ataken, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 174:59] node _T_172 = and(i0_predict_p_d.bits.ataken, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 175:59]
i0_taken_d <= _T_172 @[exu.scala 174:28] i0_taken_d <= _T_172 @[exu.scala 175:28]
node _T_173 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 180:8] node _T_173 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 181:8]
node _T_174 = and(_T_173, i0_valid_d) @[exu.scala 180:50] node _T_174 = and(_T_173, i0_valid_d) @[exu.scala 181:50]
node _T_175 = bits(_T_174, 0, 0) @[exu.scala 180:64] node _T_175 = bits(_T_174, 0, 0) @[exu.scala 181:64]
node _T_176 = bits(ghr_d, 6, 0) @[exu.scala 180:85] node _T_176 = bits(ghr_d, 6, 0) @[exu.scala 181:85]
node _T_177 = cat(_T_176, i0_taken_d) @[Cat.scala 29:58] node _T_177 = cat(_T_176, i0_taken_d) @[Cat.scala 29:58]
node _T_178 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 181:8] node _T_178 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 182:8]
node _T_179 = eq(i0_valid_d, UInt<1>("h00")) @[exu.scala 181:52] node _T_179 = eq(i0_valid_d, UInt<1>("h00")) @[exu.scala 182:52]
node _T_180 = and(_T_178, _T_179) @[exu.scala 181:50] node _T_180 = and(_T_178, _T_179) @[exu.scala 182:50]
node _T_181 = bits(_T_180, 0, 0) @[exu.scala 181:65] node _T_181 = bits(_T_180, 0, 0) @[exu.scala 182:65]
node _T_182 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 182:50] node _T_182 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 183:50]
node _T_183 = mux(_T_175, _T_177, UInt<1>("h00")) @[Mux.scala 27:72] node _T_183 = mux(_T_175, _T_177, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_184 = mux(_T_181, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_184 = mux(_T_181, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_185 = mux(_T_182, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72] node _T_185 = mux(_T_182, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72]
@ -45136,97 +45136,97 @@ circuit exu :
node _T_187 = or(_T_186, _T_185) @[Mux.scala 27:72] node _T_187 = or(_T_186, _T_185) @[Mux.scala 27:72]
wire _T_188 : UInt @[Mux.scala 27:72] wire _T_188 : UInt @[Mux.scala 27:72]
_T_188 <= _T_187 @[Mux.scala 27:72] _T_188 <= _T_187 @[Mux.scala 27:72]
ghr_d_ns <= _T_188 @[exu.scala 179:14] ghr_d_ns <= _T_188 @[exu.scala 180:14]
node _T_189 = eq(i0_valid_x, UInt<1>("h01")) @[exu.scala 186:32] node _T_189 = eq(i0_valid_x, UInt<1>("h01")) @[exu.scala 187:32]
node _T_190 = bits(ghr_x, 6, 0) @[exu.scala 186:50] node _T_190 = bits(ghr_x, 6, 0) @[exu.scala 187:50]
node _T_191 = cat(_T_190, i0_taken_x) @[Cat.scala 29:58] node _T_191 = cat(_T_190, i0_taken_x) @[Cat.scala 29:58]
node _T_192 = mux(_T_189, _T_191, ghr_x) @[exu.scala 186:20] node _T_192 = mux(_T_189, _T_191, ghr_x) @[exu.scala 187:20]
ghr_x_ns <= _T_192 @[exu.scala 186:14] ghr_x_ns <= _T_192 @[exu.scala 187:14]
io.dec_exu.tlu_exu.exu_i0_br_valid_r <= i0_pp_r.valid @[exu.scala 188:43] io.dec_exu.tlu_exu.exu_i0_br_valid_r <= i0_pp_r.valid @[exu.scala 189:43]
io.dec_exu.tlu_exu.exu_i0_br_mp_r <= i0_pp_r.bits.misp @[exu.scala 189:43] io.dec_exu.tlu_exu.exu_i0_br_mp_r <= i0_pp_r.bits.misp @[exu.scala 190:43]
io.exu_bp.exu_i0_br_way_r <= i0_pp_r.bits.way @[exu.scala 190:43] io.exu_bp.exu_i0_br_way_r <= i0_pp_r.bits.way @[exu.scala 191:43]
node _T_193 = bits(i0_pp_r.valid, 0, 0) @[Bitwise.scala 72:15] node _T_193 = bits(i0_pp_r.valid, 0, 0) @[Bitwise.scala 72:15]
node _T_194 = mux(_T_193, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_194 = mux(_T_193, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_195 = and(_T_194, i0_pp_r.bits.hist) @[exu.scala 191:69] node _T_195 = and(_T_194, i0_pp_r.bits.hist) @[exu.scala 192:69]
io.dec_exu.tlu_exu.exu_i0_br_hist_r <= _T_195 @[exu.scala 191:43] io.dec_exu.tlu_exu.exu_i0_br_hist_r <= _T_195 @[exu.scala 192:43]
io.dec_exu.tlu_exu.exu_i0_br_error_r <= i0_pp_r.bits.br_error @[exu.scala 192:43] io.dec_exu.tlu_exu.exu_i0_br_error_r <= i0_pp_r.bits.br_error @[exu.scala 193:43]
node _T_196 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[exu.scala 193:63] node _T_196 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[exu.scala 194:63]
io.dec_exu.tlu_exu.exu_i0_br_middle_r <= _T_196 @[exu.scala 193:43] io.dec_exu.tlu_exu.exu_i0_br_middle_r <= _T_196 @[exu.scala 194:43]
io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= i0_pp_r.bits.br_start_error @[exu.scala 194:48] io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= i0_pp_r.bits.br_start_error @[exu.scala 195:48]
node _T_197 = bits(predpipe_r, 20, 13) @[exu.scala 195:56] node _T_197 = bits(predpipe_r, 20, 13) @[exu.scala 196:56]
io.exu_bp.exu_i0_br_fghr_r <= _T_197 @[exu.scala 195:43] io.exu_bp.exu_i0_br_fghr_r <= _T_197 @[exu.scala 196:43]
node _T_198 = bits(predpipe_r, 12, 5) @[exu.scala 196:56] node _T_198 = bits(predpipe_r, 12, 5) @[exu.scala 197:56]
io.dec_exu.tlu_exu.exu_i0_br_index_r <= _T_198 @[exu.scala 196:43] io.dec_exu.tlu_exu.exu_i0_br_index_r <= _T_198 @[exu.scala 197:43]
io.exu_bp.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[exu.scala 197:43] io.exu_bp.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[exu.scala 198:43]
node _T_199 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 198:67] node _T_199 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 199:67]
wire _T_200 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 198:104] wire _T_200 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 199:104]
_T_200.bits.prett <= UInt<31>("h00") @[exu.scala 198:104] _T_200.bits.prett <= UInt<31>("h00") @[exu.scala 199:104]
_T_200.bits.pret <= UInt<1>("h00") @[exu.scala 198:104] _T_200.bits.pret <= UInt<1>("h00") @[exu.scala 199:104]
_T_200.bits.way <= UInt<1>("h00") @[exu.scala 198:104] _T_200.bits.way <= UInt<1>("h00") @[exu.scala 199:104]
_T_200.bits.pja <= UInt<1>("h00") @[exu.scala 198:104] _T_200.bits.pja <= UInt<1>("h00") @[exu.scala 199:104]
_T_200.bits.pcall <= UInt<1>("h00") @[exu.scala 198:104] _T_200.bits.pcall <= UInt<1>("h00") @[exu.scala 199:104]
_T_200.bits.br_start_error <= UInt<1>("h00") @[exu.scala 198:104] _T_200.bits.br_start_error <= UInt<1>("h00") @[exu.scala 199:104]
_T_200.bits.br_error <= UInt<1>("h00") @[exu.scala 198:104] _T_200.bits.br_error <= UInt<1>("h00") @[exu.scala 199:104]
_T_200.bits.toffset <= UInt<12>("h00") @[exu.scala 198:104] _T_200.bits.toffset <= UInt<12>("h00") @[exu.scala 199:104]
_T_200.bits.hist <= UInt<2>("h00") @[exu.scala 198:104] _T_200.bits.hist <= UInt<2>("h00") @[exu.scala 199:104]
_T_200.bits.pc4 <= UInt<1>("h00") @[exu.scala 198:104] _T_200.bits.pc4 <= UInt<1>("h00") @[exu.scala 199:104]
_T_200.bits.boffset <= UInt<1>("h00") @[exu.scala 198:104] _T_200.bits.boffset <= UInt<1>("h00") @[exu.scala 199:104]
_T_200.bits.ataken <= UInt<1>("h00") @[exu.scala 198:104] _T_200.bits.ataken <= UInt<1>("h00") @[exu.scala 199:104]
_T_200.bits.misp <= UInt<1>("h00") @[exu.scala 198:104] _T_200.bits.misp <= UInt<1>("h00") @[exu.scala 199:104]
_T_200.valid <= UInt<1>("h00") @[exu.scala 198:104] _T_200.valid <= UInt<1>("h00") @[exu.scala 199:104]
node _T_201 = mux(_T_199, i0_predict_p_x, _T_200) @[exu.scala 198:49] node _T_201 = mux(_T_199, i0_predict_p_x, _T_200) @[exu.scala 199:49]
final_predict_mp.bits.prett <= _T_201.bits.prett @[exu.scala 198:43] final_predict_mp.bits.prett <= _T_201.bits.prett @[exu.scala 199:43]
final_predict_mp.bits.pret <= _T_201.bits.pret @[exu.scala 198:43] final_predict_mp.bits.pret <= _T_201.bits.pret @[exu.scala 199:43]
final_predict_mp.bits.way <= _T_201.bits.way @[exu.scala 198:43] final_predict_mp.bits.way <= _T_201.bits.way @[exu.scala 199:43]
final_predict_mp.bits.pja <= _T_201.bits.pja @[exu.scala 198:43] final_predict_mp.bits.pja <= _T_201.bits.pja @[exu.scala 199:43]
final_predict_mp.bits.pcall <= _T_201.bits.pcall @[exu.scala 198:43] final_predict_mp.bits.pcall <= _T_201.bits.pcall @[exu.scala 199:43]
final_predict_mp.bits.br_start_error <= _T_201.bits.br_start_error @[exu.scala 198:43] final_predict_mp.bits.br_start_error <= _T_201.bits.br_start_error @[exu.scala 199:43]
final_predict_mp.bits.br_error <= _T_201.bits.br_error @[exu.scala 198:43] final_predict_mp.bits.br_error <= _T_201.bits.br_error @[exu.scala 199:43]
final_predict_mp.bits.toffset <= _T_201.bits.toffset @[exu.scala 198:43] final_predict_mp.bits.toffset <= _T_201.bits.toffset @[exu.scala 199:43]
final_predict_mp.bits.hist <= _T_201.bits.hist @[exu.scala 198:43] final_predict_mp.bits.hist <= _T_201.bits.hist @[exu.scala 199:43]
final_predict_mp.bits.pc4 <= _T_201.bits.pc4 @[exu.scala 198:43] final_predict_mp.bits.pc4 <= _T_201.bits.pc4 @[exu.scala 199:43]
final_predict_mp.bits.boffset <= _T_201.bits.boffset @[exu.scala 198:43] final_predict_mp.bits.boffset <= _T_201.bits.boffset @[exu.scala 199:43]
final_predict_mp.bits.ataken <= _T_201.bits.ataken @[exu.scala 198:43] final_predict_mp.bits.ataken <= _T_201.bits.ataken @[exu.scala 199:43]
final_predict_mp.bits.misp <= _T_201.bits.misp @[exu.scala 198:43] final_predict_mp.bits.misp <= _T_201.bits.misp @[exu.scala 199:43]
final_predict_mp.valid <= _T_201.valid @[exu.scala 198:43] final_predict_mp.valid <= _T_201.valid @[exu.scala 199:43]
node _T_202 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 199:66] node _T_202 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 200:66]
node final_predpipe_mp = mux(_T_202, predpipe_x, UInt<1>("h00")) @[exu.scala 199:48] node final_predpipe_mp = mux(_T_202, predpipe_x, UInt<1>("h00")) @[exu.scala 200:48]
node _T_203 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 201:67] node _T_203 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 202:67]
node _T_204 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h01")) @[exu.scala 201:120] node _T_204 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h01")) @[exu.scala 202:120]
node _T_205 = eq(_T_204, UInt<1>("h00")) @[exu.scala 201:77] node _T_205 = eq(_T_204, UInt<1>("h00")) @[exu.scala 202:77]
node _T_206 = and(_T_203, _T_205) @[exu.scala 201:75] node _T_206 = and(_T_203, _T_205) @[exu.scala 202:75]
node after_flush_eghr = mux(_T_206, ghr_d, ghr_x) @[exu.scala 201:48] node after_flush_eghr = mux(_T_206, ghr_d, ghr_x) @[exu.scala 202:48]
io.exu_bp.exu_mp_pkt.valid <= final_predict_mp.valid @[exu.scala 203:39] io.exu_bp.exu_mp_pkt.valid <= final_predict_mp.valid @[exu.scala 204:39]
io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 204:39] io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 205:39]
io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 205:39] io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 206:39]
io.exu_bp.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[exu.scala 206:39] io.exu_bp.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[exu.scala 207:39]
io.exu_bp.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[exu.scala 207:39] io.exu_bp.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[exu.scala 208:39]
io.exu_bp.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[exu.scala 208:39] io.exu_bp.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[exu.scala 209:39]
io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 209:39] io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 210:39]
io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 210:39] io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 211:39]
io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 211:39] io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 212:39]
node _T_207 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 212:68] node _T_207 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 213:68]
io.exu_bp.exu_mp_pkt.bits.hist <= _T_207 @[exu.scala 212:39] io.exu_bp.exu_mp_pkt.bits.hist <= _T_207 @[exu.scala 213:39]
node _T_208 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 213:71] node _T_208 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 214:71]
io.exu_bp.exu_mp_pkt.bits.toffset <= _T_208 @[exu.scala 213:39] io.exu_bp.exu_mp_pkt.bits.toffset <= _T_208 @[exu.scala 214:39]
io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 214:39] io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 215:39]
node _T_209 = bits(final_predpipe_mp, 12, 5) @[exu.scala 215:59] node _T_209 = bits(final_predpipe_mp, 12, 5) @[exu.scala 216:59]
io.exu_bp.exu_mp_index <= _T_209 @[exu.scala 215:39] io.exu_bp.exu_mp_index <= _T_209 @[exu.scala 216:39]
node _T_210 = bits(final_predpipe_mp, 4, 0) @[exu.scala 216:59] node _T_210 = bits(final_predpipe_mp, 4, 0) @[exu.scala 217:59]
io.exu_bp.exu_mp_btag <= _T_210 @[exu.scala 216:39] io.exu_bp.exu_mp_btag <= _T_210 @[exu.scala 217:39]
node _T_211 = bits(final_predpipe_mp, 20, 13) @[exu.scala 217:59] node _T_211 = bits(final_predpipe_mp, 20, 13) @[exu.scala 218:59]
io.exu_bp.exu_mp_eghr <= _T_211 @[exu.scala 217:39] io.exu_bp.exu_mp_eghr <= _T_211 @[exu.scala 218:39]
node _T_212 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 239:46] node _T_212 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 240:46]
node _T_213 = not(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[exu.scala 240:6] node _T_213 = not(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[exu.scala 241:6]
node _T_214 = and(_T_213, i0_flush_upper_d) @[exu.scala 240:48] node _T_214 = and(_T_213, i0_flush_upper_d) @[exu.scala 241:48]
node _T_215 = bits(_T_214, 0, 0) @[exu.scala 240:68] node _T_215 = bits(_T_214, 0, 0) @[exu.scala 241:68]
node _T_216 = mux(_T_212, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_216 = mux(_T_212, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_217 = mux(_T_215, i0_flush_path_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_217 = mux(_T_215, i0_flush_path_d, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_218 = or(_T_216, _T_217) @[Mux.scala 27:72] node _T_218 = or(_T_216, _T_217) @[Mux.scala 27:72]
wire _T_219 : UInt<31> @[Mux.scala 27:72] wire _T_219 : UInt<31> @[Mux.scala 27:72]
_T_219 <= _T_218 @[Mux.scala 27:72] _T_219 <= _T_218 @[Mux.scala 27:72]
io.exu_flush_path_final <= _T_219 @[exu.scala 238:33] io.exu_flush_path_final <= _T_219 @[exu.scala 239:33]
node _T_220 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 242:79] node _T_220 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 243:79]
node _T_221 = mux(_T_220, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 242:55] node _T_221 = mux(_T_220, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 243:55]
io.dec_exu.tlu_exu.exu_npc_r <= _T_221 @[exu.scala 242:49] io.dec_exu.tlu_exu.exu_npc_r <= _T_221 @[exu.scala 243:49]

540
exu.v
View File

@ -21,9 +21,9 @@ module exu_alu_ctl(
input reset, input reset,
input io_dec_alu_dec_i0_alu_decode_d, input io_dec_alu_dec_i0_alu_decode_d,
input io_dec_alu_dec_csr_ren_d, input io_dec_alu_dec_csr_ren_d,
input [31:0] io_dec_alu_dec_csr_rddata_d,
input [11:0] io_dec_alu_dec_i0_br_immed_d, input [11:0] io_dec_alu_dec_i0_br_immed_d,
output [30:0] io_dec_alu_exu_i0_pc_x, output [30:0] io_dec_alu_exu_i0_pc_x,
input [31:0] io_csr_rddata_in,
input [30:0] io_dec_i0_pc_d, input [30:0] io_dec_i0_pc_d,
input io_flush_upper_x, input io_flush_upper_x,
input io_dec_tlu_flush_lower_r, input io_dec_tlu_flush_lower_r,
@ -116,7 +116,7 @@ module exu_alu_ctl(
reg [30:0] _T_14; // @[Reg.scala 27:20] reg [30:0] _T_14; // @[Reg.scala 27:20]
wire _T_15 = io_enable & io_dec_alu_dec_i0_alu_decode_d; // @[exu_alu_ctl.scala 135:43] wire _T_15 = io_enable & io_dec_alu_dec_i0_alu_decode_d; // @[exu_alu_ctl.scala 135:43]
reg [31:0] _T_18; // @[Reg.scala 27:20] reg [31:0] _T_18; // @[Reg.scala 27:20]
wire [31:0] _T_153 = io_dec_alu_dec_csr_rddata_d; // @[Mux.scala 27:72] wire [31:0] _T_153 = io_csr_rddata_in; // @[Mux.scala 27:72]
wire [32:0] _T_151 = {{1{_T_153[31]}},_T_153}; // @[Mux.scala 27:72 Mux.scala 27:72] wire [32:0] _T_151 = {{1{_T_153[31]}},_T_153}; // @[Mux.scala 27:72 Mux.scala 27:72]
wire [32:0] _T_172 = io_dec_alu_dec_csr_ren_d ? $signed(_T_151) : $signed(33'sh0); // @[Mux.scala 27:72] wire [32:0] _T_172 = io_dec_alu_dec_csr_ren_d ? $signed(_T_151) : $signed(33'sh0); // @[Mux.scala 27:72]
wire _T_94 = ~io_i0_ap_zbb; // @[exu_alu_ctl.scala 160:22] wire _T_94 = ~io_i0_ap_zbb; // @[exu_alu_ctl.scala 160:22]
@ -1952,7 +1952,6 @@ module exu(
input io_scan_mode, input io_scan_mode,
input io_dec_exu_dec_alu_dec_i0_alu_decode_d, input io_dec_exu_dec_alu_dec_i0_alu_decode_d,
input io_dec_exu_dec_alu_dec_csr_ren_d, input io_dec_exu_dec_alu_dec_csr_ren_d,
input [31:0] io_dec_exu_dec_alu_dec_csr_rddata_d,
input [11:0] io_dec_exu_dec_alu_dec_i0_br_immed_d, input [11:0] io_dec_exu_dec_alu_dec_i0_br_immed_d,
output [30:0] io_dec_exu_dec_alu_exu_i0_pc_x, output [30:0] io_dec_exu_dec_alu_exu_i0_pc_x,
input io_dec_exu_dec_div_div_p_valid, input io_dec_exu_dec_div_div_p_valid,
@ -2027,6 +2026,7 @@ module exu(
input io_dec_exu_decode_exu_dec_i0_rs2_en_d, input io_dec_exu_decode_exu_dec_i0_rs2_en_d,
input [31:0] io_dec_exu_decode_exu_dec_i0_immed_d, input [31:0] io_dec_exu_decode_exu_dec_i0_immed_d,
input [31:0] io_dec_exu_decode_exu_dec_i0_result_r, input [31:0] io_dec_exu_decode_exu_dec_i0_result_r,
input io_dec_exu_decode_exu_dec_qual_lsu_d,
input io_dec_exu_decode_exu_dec_i0_select_pc_d, input io_dec_exu_decode_exu_dec_i0_select_pc_d,
input [3:0] io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d, input [3:0] io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d,
input [3:0] io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d, input [3:0] io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d,
@ -2097,12 +2097,12 @@ module exu(
output [31:0] io_exu_div_result, output [31:0] io_exu_div_result,
output io_exu_div_wren, output io_exu_div_wren,
input [31:0] io_dbg_cmd_wrdata, input [31:0] io_dbg_cmd_wrdata,
input [31:0] io_dec_csr_rddata_d,
output [31:0] io_lsu_exu_exu_lsu_rs1_d, output [31:0] io_lsu_exu_exu_lsu_rs1_d,
output [31:0] io_lsu_exu_exu_lsu_rs2_d, output [31:0] io_lsu_exu_exu_lsu_rs2_d,
input [31:0] io_lsu_exu_lsu_result_m, input [31:0] io_lsu_exu_lsu_result_m,
input [31:0] io_lsu_exu_lsu_nonblock_load_data, input [31:0] io_lsu_exu_lsu_nonblock_load_data,
output [30:0] io_exu_flush_path_final, output [30:0] io_exu_flush_path_final
input io_dec_qual_lsu_d
); );
`ifdef RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0; reg [31:0] _RAND_0;
@ -2160,117 +2160,117 @@ module exu(
wire rvclkhdr_6_io_en; // @[lib.scala 404:23] wire rvclkhdr_6_io_en; // @[lib.scala 404:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] wire rvclkhdr_7_io_clk; // @[lib.scala 404:23]
wire rvclkhdr_7_io_en; // @[lib.scala 404:23] wire rvclkhdr_7_io_en; // @[lib.scala 404:23]
wire i_alu_clock; // @[exu.scala 130:19] wire i_alu_clock; // @[exu.scala 129:19]
wire i_alu_reset; // @[exu.scala 130:19] wire i_alu_reset; // @[exu.scala 129:19]
wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 130:19] wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 129:19]
wire i_alu_io_dec_alu_dec_csr_ren_d; // @[exu.scala 130:19] wire i_alu_io_dec_alu_dec_csr_ren_d; // @[exu.scala 129:19]
wire [31:0] i_alu_io_dec_alu_dec_csr_rddata_d; // @[exu.scala 130:19] wire [11:0] i_alu_io_dec_alu_dec_i0_br_immed_d; // @[exu.scala 129:19]
wire [11:0] i_alu_io_dec_alu_dec_i0_br_immed_d; // @[exu.scala 130:19] wire [30:0] i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 129:19]
wire [30:0] i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 130:19] wire [31:0] i_alu_io_csr_rddata_in; // @[exu.scala 129:19]
wire [30:0] i_alu_io_dec_i0_pc_d; // @[exu.scala 130:19] wire [30:0] i_alu_io_dec_i0_pc_d; // @[exu.scala 129:19]
wire i_alu_io_flush_upper_x; // @[exu.scala 130:19] wire i_alu_io_flush_upper_x; // @[exu.scala 129:19]
wire i_alu_io_dec_tlu_flush_lower_r; // @[exu.scala 130:19] wire i_alu_io_dec_tlu_flush_lower_r; // @[exu.scala 129:19]
wire i_alu_io_enable; // @[exu.scala 130:19] wire i_alu_io_enable; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_clz; // @[exu.scala 130:19] wire i_alu_io_i0_ap_clz; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_ctz; // @[exu.scala 130:19] wire i_alu_io_i0_ap_ctz; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_pcnt; // @[exu.scala 130:19] wire i_alu_io_i0_ap_pcnt; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_sext_b; // @[exu.scala 130:19] wire i_alu_io_i0_ap_sext_b; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_sext_h; // @[exu.scala 130:19] wire i_alu_io_i0_ap_sext_h; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_min; // @[exu.scala 130:19] wire i_alu_io_i0_ap_min; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_max; // @[exu.scala 130:19] wire i_alu_io_i0_ap_max; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_pack; // @[exu.scala 130:19] wire i_alu_io_i0_ap_pack; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_packu; // @[exu.scala 130:19] wire i_alu_io_i0_ap_packu; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_packh; // @[exu.scala 130:19] wire i_alu_io_i0_ap_packh; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_rol; // @[exu.scala 130:19] wire i_alu_io_i0_ap_rol; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_ror; // @[exu.scala 130:19] wire i_alu_io_i0_ap_ror; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_grev; // @[exu.scala 130:19] wire i_alu_io_i0_ap_grev; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_gorc; // @[exu.scala 130:19] wire i_alu_io_i0_ap_gorc; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_zbb; // @[exu.scala 130:19] wire i_alu_io_i0_ap_zbb; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_sbset; // @[exu.scala 130:19] wire i_alu_io_i0_ap_sbset; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_sbclr; // @[exu.scala 130:19] wire i_alu_io_i0_ap_sbclr; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_sbinv; // @[exu.scala 130:19] wire i_alu_io_i0_ap_sbinv; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_sbext; // @[exu.scala 130:19] wire i_alu_io_i0_ap_sbext; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_land; // @[exu.scala 130:19] wire i_alu_io_i0_ap_land; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_lor; // @[exu.scala 130:19] wire i_alu_io_i0_ap_lor; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_lxor; // @[exu.scala 130:19] wire i_alu_io_i0_ap_lxor; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_sll; // @[exu.scala 130:19] wire i_alu_io_i0_ap_sll; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_srl; // @[exu.scala 130:19] wire i_alu_io_i0_ap_srl; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_sra; // @[exu.scala 130:19] wire i_alu_io_i0_ap_sra; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_beq; // @[exu.scala 130:19] wire i_alu_io_i0_ap_beq; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_bne; // @[exu.scala 130:19] wire i_alu_io_i0_ap_bne; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_blt; // @[exu.scala 130:19] wire i_alu_io_i0_ap_blt; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_bge; // @[exu.scala 130:19] wire i_alu_io_i0_ap_bge; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_add; // @[exu.scala 130:19] wire i_alu_io_i0_ap_add; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_sub; // @[exu.scala 130:19] wire i_alu_io_i0_ap_sub; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_slt; // @[exu.scala 130:19] wire i_alu_io_i0_ap_slt; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_unsign; // @[exu.scala 130:19] wire i_alu_io_i0_ap_unsign; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_jal; // @[exu.scala 130:19] wire i_alu_io_i0_ap_jal; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_predict_t; // @[exu.scala 130:19] wire i_alu_io_i0_ap_predict_t; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_predict_nt; // @[exu.scala 130:19] wire i_alu_io_i0_ap_predict_nt; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_csr_write; // @[exu.scala 130:19] wire i_alu_io_i0_ap_csr_write; // @[exu.scala 129:19]
wire i_alu_io_i0_ap_csr_imm; // @[exu.scala 130:19] wire i_alu_io_i0_ap_csr_imm; // @[exu.scala 129:19]
wire [31:0] i_alu_io_a_in; // @[exu.scala 130:19] wire [31:0] i_alu_io_a_in; // @[exu.scala 129:19]
wire [31:0] i_alu_io_b_in; // @[exu.scala 130:19] wire [31:0] i_alu_io_b_in; // @[exu.scala 129:19]
wire i_alu_io_pp_in_valid; // @[exu.scala 130:19] wire i_alu_io_pp_in_valid; // @[exu.scala 129:19]
wire i_alu_io_pp_in_bits_boffset; // @[exu.scala 130:19] wire i_alu_io_pp_in_bits_boffset; // @[exu.scala 129:19]
wire i_alu_io_pp_in_bits_pc4; // @[exu.scala 130:19] wire i_alu_io_pp_in_bits_pc4; // @[exu.scala 129:19]
wire [1:0] i_alu_io_pp_in_bits_hist; // @[exu.scala 130:19] wire [1:0] i_alu_io_pp_in_bits_hist; // @[exu.scala 129:19]
wire [11:0] i_alu_io_pp_in_bits_toffset; // @[exu.scala 130:19] wire [11:0] i_alu_io_pp_in_bits_toffset; // @[exu.scala 129:19]
wire i_alu_io_pp_in_bits_br_error; // @[exu.scala 130:19] wire i_alu_io_pp_in_bits_br_error; // @[exu.scala 129:19]
wire i_alu_io_pp_in_bits_br_start_error; // @[exu.scala 130:19] wire i_alu_io_pp_in_bits_br_start_error; // @[exu.scala 129:19]
wire i_alu_io_pp_in_bits_pcall; // @[exu.scala 130:19] wire i_alu_io_pp_in_bits_pcall; // @[exu.scala 129:19]
wire i_alu_io_pp_in_bits_pja; // @[exu.scala 130:19] wire i_alu_io_pp_in_bits_pja; // @[exu.scala 129:19]
wire i_alu_io_pp_in_bits_way; // @[exu.scala 130:19] wire i_alu_io_pp_in_bits_way; // @[exu.scala 129:19]
wire i_alu_io_pp_in_bits_pret; // @[exu.scala 130:19] wire i_alu_io_pp_in_bits_pret; // @[exu.scala 129:19]
wire [30:0] i_alu_io_pp_in_bits_prett; // @[exu.scala 130:19] wire [30:0] i_alu_io_pp_in_bits_prett; // @[exu.scala 129:19]
wire [31:0] i_alu_io_result_ff; // @[exu.scala 130:19] wire [31:0] i_alu_io_result_ff; // @[exu.scala 129:19]
wire i_alu_io_flush_upper_out; // @[exu.scala 130:19] wire i_alu_io_flush_upper_out; // @[exu.scala 129:19]
wire i_alu_io_flush_final_out; // @[exu.scala 130:19] wire i_alu_io_flush_final_out; // @[exu.scala 129:19]
wire [30:0] i_alu_io_flush_path_out; // @[exu.scala 130:19] wire [30:0] i_alu_io_flush_path_out; // @[exu.scala 129:19]
wire i_alu_io_pred_correct_out; // @[exu.scala 130:19] wire i_alu_io_pred_correct_out; // @[exu.scala 129:19]
wire i_alu_io_predict_p_out_valid; // @[exu.scala 130:19] wire i_alu_io_predict_p_out_valid; // @[exu.scala 129:19]
wire i_alu_io_predict_p_out_bits_misp; // @[exu.scala 130:19] wire i_alu_io_predict_p_out_bits_misp; // @[exu.scala 129:19]
wire i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 130:19] wire i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 129:19]
wire i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 130:19] wire i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 129:19]
wire i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 130:19] wire i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 129:19]
wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[exu.scala 130:19] wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[exu.scala 129:19]
wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 130:19] wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 129:19]
wire i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 130:19] wire i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 129:19]
wire i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 130:19] wire i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 129:19]
wire i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 130:19] wire i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 129:19]
wire i_alu_io_predict_p_out_bits_pja; // @[exu.scala 130:19] wire i_alu_io_predict_p_out_bits_pja; // @[exu.scala 129:19]
wire i_alu_io_predict_p_out_bits_way; // @[exu.scala 130:19] wire i_alu_io_predict_p_out_bits_way; // @[exu.scala 129:19]
wire i_alu_io_predict_p_out_bits_pret; // @[exu.scala 130:19] wire i_alu_io_predict_p_out_bits_pret; // @[exu.scala 129:19]
wire i_mul_clock; // @[exu.scala 148:21] wire i_mul_clock; // @[exu.scala 149:21]
wire i_mul_reset; // @[exu.scala 148:21] wire i_mul_reset; // @[exu.scala 149:21]
wire i_mul_io_mul_p_valid; // @[exu.scala 148:21] wire i_mul_io_mul_p_valid; // @[exu.scala 149:21]
wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 148:21] wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 149:21]
wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 148:21] wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 149:21]
wire i_mul_io_mul_p_bits_low; // @[exu.scala 148:21] wire i_mul_io_mul_p_bits_low; // @[exu.scala 149:21]
wire [31:0] i_mul_io_rs1_in; // @[exu.scala 148:21] wire [31:0] i_mul_io_rs1_in; // @[exu.scala 149:21]
wire [31:0] i_mul_io_rs2_in; // @[exu.scala 148:21] wire [31:0] i_mul_io_rs2_in; // @[exu.scala 149:21]
wire [31:0] i_mul_io_result_x; // @[exu.scala 148:21] wire [31:0] i_mul_io_result_x; // @[exu.scala 149:21]
wire i_div_clock; // @[exu.scala 156:21] wire i_div_clock; // @[exu.scala 157:21]
wire i_div_reset; // @[exu.scala 156:21] wire i_div_reset; // @[exu.scala 157:21]
wire [31:0] i_div_io_dividend; // @[exu.scala 156:21] wire [31:0] i_div_io_dividend; // @[exu.scala 157:21]
wire [31:0] i_div_io_divisor; // @[exu.scala 156:21] wire [31:0] i_div_io_divisor; // @[exu.scala 157:21]
wire [31:0] i_div_io_exu_div_result; // @[exu.scala 156:21] wire [31:0] i_div_io_exu_div_result; // @[exu.scala 157:21]
wire i_div_io_exu_div_wren; // @[exu.scala 156:21] wire i_div_io_exu_div_wren; // @[exu.scala 157:21]
wire i_div_io_dec_div_div_p_valid; // @[exu.scala 156:21] wire i_div_io_dec_div_div_p_valid; // @[exu.scala 157:21]
wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 156:21] wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 157:21]
wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 156:21] wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 157:21]
wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 156:21] wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 157:21]
wire x_data_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 55:69] wire x_data_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 54:69]
wire x_data_en_q1 = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 56:73] wire x_data_en_q1 = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 55:73]
wire x_data_en_q2 = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[exu.scala 57:73] wire x_data_en_q2 = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[exu.scala 56:73]
wire r_data_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[exu.scala 58:69] wire r_data_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[exu.scala 57:69]
reg i0_branch_x; // @[Reg.scala 27:20] reg i0_branch_x; // @[Reg.scala 27:20]
wire r_data_en_q2 = r_data_en & i0_branch_x; // @[exu.scala 59:73] wire r_data_en_q2 = r_data_en & i0_branch_x; // @[exu.scala 58:73]
wire x_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[exu.scala 60:68] wire x_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[exu.scala 59:68]
wire r_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[exu.scala 61:68] wire r_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[exu.scala 60:68]
wire [20:0] predpipe_d = {io_dec_exu_decode_exu_i0_predict_fghr_d,io_dec_exu_decode_exu_i0_predict_index_d,io_dec_exu_decode_exu_i0_predict_btag_d}; // @[Cat.scala 29:58] wire [20:0] predpipe_d = {io_dec_exu_decode_exu_i0_predict_fghr_d,io_dec_exu_decode_exu_i0_predict_index_d,io_dec_exu_decode_exu_i0_predict_btag_d}; // @[Cat.scala 29:58]
reg [30:0] i0_flush_path_x; // @[Reg.scala 27:20] reg [30:0] i0_flush_path_x; // @[Reg.scala 27:20]
wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[exu.scala 41:53 exu.scala 143:45] wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[exu.scala 40:53 exu.scala 144:45]
reg i0_predict_p_x_valid; // @[Reg.scala 27:20] reg i0_predict_p_x_valid; // @[Reg.scala 27:20]
reg i0_predict_p_x_bits_misp; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_misp; // @[Reg.scala 27:20]
reg i0_predict_p_x_bits_ataken; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_ataken; // @[Reg.scala 27:20]
@ -2284,19 +2284,19 @@ module exu(
reg i0_predict_p_x_bits_pja; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_pja; // @[Reg.scala 27:20]
reg i0_predict_p_x_bits_way; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_way; // @[Reg.scala 27:20]
reg i0_predict_p_x_bits_pret; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_pret; // @[Reg.scala 27:20]
wire i0_predict_p_d_bits_pret = i_alu_io_predict_p_out_bits_pret; // @[exu.scala 42:53 exu.scala 145:45] wire i0_predict_p_d_bits_pret = i_alu_io_predict_p_out_bits_pret; // @[exu.scala 41:53 exu.scala 146:45]
wire i0_predict_p_d_bits_way = i_alu_io_predict_p_out_bits_way; // @[exu.scala 42:53 exu.scala 145:45] wire i0_predict_p_d_bits_way = i_alu_io_predict_p_out_bits_way; // @[exu.scala 41:53 exu.scala 146:45]
wire i0_predict_p_d_bits_pja = i_alu_io_predict_p_out_bits_pja; // @[exu.scala 42:53 exu.scala 145:45] wire i0_predict_p_d_bits_pja = i_alu_io_predict_p_out_bits_pja; // @[exu.scala 41:53 exu.scala 146:45]
wire i0_predict_p_d_bits_pcall = i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 42:53 exu.scala 145:45] wire i0_predict_p_d_bits_pcall = i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 41:53 exu.scala 146:45]
wire i0_predict_p_d_bits_br_start_error = i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 42:53 exu.scala 145:45] wire i0_predict_p_d_bits_br_start_error = i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 41:53 exu.scala 146:45]
wire i0_predict_p_d_bits_br_error = i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 42:53 exu.scala 145:45] wire i0_predict_p_d_bits_br_error = i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 41:53 exu.scala 146:45]
wire [11:0] i0_predict_p_d_bits_toffset = i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 42:53 exu.scala 145:45] wire [11:0] i0_predict_p_d_bits_toffset = i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 41:53 exu.scala 146:45]
wire [1:0] i0_predict_p_d_bits_hist = i_alu_io_predict_p_out_bits_hist; // @[exu.scala 42:53 exu.scala 145:45] wire [1:0] i0_predict_p_d_bits_hist = i_alu_io_predict_p_out_bits_hist; // @[exu.scala 41:53 exu.scala 146:45]
wire i0_predict_p_d_bits_pc4 = i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 42:53 exu.scala 145:45] wire i0_predict_p_d_bits_pc4 = i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 41:53 exu.scala 146:45]
wire i0_predict_p_d_bits_boffset = i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 42:53 exu.scala 145:45] wire i0_predict_p_d_bits_boffset = i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 41:53 exu.scala 146:45]
wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 42:53 exu.scala 145:45] wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 41:53 exu.scala 146:45]
wire i0_predict_p_d_bits_misp = i_alu_io_predict_p_out_bits_misp; // @[exu.scala 42:53 exu.scala 145:45] wire i0_predict_p_d_bits_misp = i_alu_io_predict_p_out_bits_misp; // @[exu.scala 41:53 exu.scala 146:45]
wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[exu.scala 42:53 exu.scala 145:45] wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[exu.scala 41:53 exu.scala 146:45]
reg [20:0] predpipe_x; // @[Reg.scala 27:20] reg [20:0] predpipe_x; // @[Reg.scala 27:20]
reg [20:0] predpipe_r; // @[Reg.scala 27:20] reg [20:0] predpipe_r; // @[Reg.scala 27:20]
reg [7:0] ghr_x; // @[Reg.scala 27:20] reg [7:0] ghr_x; // @[Reg.scala 27:20]
@ -2304,13 +2304,13 @@ module exu(
reg i0_taken_x; // @[Reg.scala 27:20] reg i0_taken_x; // @[Reg.scala 27:20]
wire [7:0] _T_191 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58] wire [7:0] _T_191 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58]
reg i0_pred_correct_upper_x; // @[Reg.scala 27:20] reg i0_pred_correct_upper_x; // @[Reg.scala 27:20]
wire i0_pred_correct_upper_d = i_alu_io_pred_correct_out; // @[exu.scala 47:41 exu.scala 146:27] wire i0_pred_correct_upper_d = i_alu_io_pred_correct_out; // @[exu.scala 46:41 exu.scala 147:27]
reg i0_flush_upper_x; // @[Reg.scala 27:20] reg i0_flush_upper_x; // @[Reg.scala 27:20]
wire i0_flush_upper_d = i_alu_io_flush_upper_out; // @[exu.scala 48:45 exu.scala 142:35] wire i0_flush_upper_d = i_alu_io_flush_upper_out; // @[exu.scala 47:45 exu.scala 143:35]
wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 174:59] wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 175:59]
wire _T_169 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 173:54] wire _T_169 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 174:54]
wire _T_170 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 173:97] wire _T_170 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 174:97]
wire i0_valid_d = _T_169 & _T_170; // @[exu.scala 173:95] wire i0_valid_d = _T_169 & _T_170; // @[exu.scala 174:95]
reg i0_pp_r_valid; // @[Reg.scala 27:20] reg i0_pp_r_valid; // @[Reg.scala 27:20]
reg i0_pp_r_bits_misp; // @[Reg.scala 27:20] reg i0_pp_r_bits_misp; // @[Reg.scala 27:20]
reg i0_pp_r_bits_ataken; // @[Reg.scala 27:20] reg i0_pp_r_bits_ataken; // @[Reg.scala 27:20]
@ -2325,12 +2325,12 @@ module exu(
reg [30:0] i0_flush_path_upper_r; // @[Reg.scala 27:20] reg [30:0] i0_flush_path_upper_r; // @[Reg.scala 27:20]
reg [24:0] pred_temp2; // @[Reg.scala 27:20] reg [24:0] pred_temp2; // @[Reg.scala 27:20]
wire [30:0] _T_31 = {pred_temp2,pred_temp1}; // @[Cat.scala 29:58] wire [30:0] _T_31 = {pred_temp2,pred_temp1}; // @[Cat.scala 29:58]
wire _T_174 = _T_170 & i0_valid_d; // @[exu.scala 180:50] wire _T_174 = _T_170 & i0_valid_d; // @[exu.scala 181:50]
reg [7:0] ghr_d; // @[Reg.scala 27:20] reg [7:0] ghr_d; // @[Reg.scala 27:20]
wire [7:0] _T_177 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58] wire [7:0] _T_177 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58]
wire [7:0] _T_183 = _T_174 ? _T_177 : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_183 = _T_174 ? _T_177 : 8'h0; // @[Mux.scala 27:72]
wire _T_179 = ~i0_valid_d; // @[exu.scala 181:52] wire _T_179 = ~i0_valid_d; // @[exu.scala 182:52]
wire _T_180 = _T_170 & _T_179; // @[exu.scala 181:50] wire _T_180 = _T_170 & _T_179; // @[exu.scala 182:50]
wire [7:0] _T_184 = _T_180 ? ghr_d : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_184 = _T_180 ? ghr_d : 8'h0; // @[Mux.scala 27:72]
wire [7:0] _T_186 = _T_183 | _T_184; // @[Mux.scala 27:72] wire [7:0] _T_186 = _T_183 | _T_184; // @[Mux.scala 27:72]
wire [7:0] _T_185 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_185 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72]
@ -2342,12 +2342,12 @@ module exu(
wire _T_38 = |_T_37; // @[lib.scala 470:29] wire _T_38 = |_T_37; // @[lib.scala 470:29]
wire _T_41 = io_dec_exu_decode_exu_dec_i0_branch_d ^ i0_branch_x; // @[lib.scala 448:21] wire _T_41 = io_dec_exu_decode_exu_dec_i0_branch_d ^ i0_branch_x; // @[lib.scala 448:21]
wire _T_42 = |_T_41; // @[lib.scala 448:29] wire _T_42 = |_T_41; // @[lib.scala 448:29]
wire _T_46 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 83:84] wire _T_46 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 82:84]
wire _T_48 = _T_46 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2]; // @[exu.scala 83:134] wire _T_48 = _T_46 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2]; // @[exu.scala 82:134]
wire i0_rs1_bypass_en_d = _T_48 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3]; // @[exu.scala 83:184] wire i0_rs1_bypass_en_d = _T_48 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3]; // @[exu.scala 82:184]
wire _T_52 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1]; // @[exu.scala 84:84] wire _T_52 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1]; // @[exu.scala 83:84]
wire _T_54 = _T_52 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[2]; // @[exu.scala 84:134] wire _T_54 = _T_52 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[2]; // @[exu.scala 83:134]
wire i0_rs2_bypass_en_d = _T_54 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[3]; // @[exu.scala 84:184] wire i0_rs2_bypass_en_d = _T_54 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[3]; // @[exu.scala 83:184]
wire [31:0] _T_64 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] ? io_dec_exu_decode_exu_dec_i0_result_r : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_64 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] ? io_dec_exu_decode_exu_dec_i0_result_r : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_65 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1] ? io_lsu_exu_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_65 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1] ? io_lsu_exu_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_66 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2] ? io_dec_exu_decode_exu_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_66 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2] ? io_dec_exu_decode_exu_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72]
@ -2362,13 +2362,13 @@ module exu(
wire [31:0] _T_83 = _T_79 | _T_80; // @[Mux.scala 27:72] wire [31:0] _T_83 = _T_79 | _T_80; // @[Mux.scala 27:72]
wire [31:0] _T_84 = _T_83 | _T_81; // @[Mux.scala 27:72] wire [31:0] _T_84 = _T_83 | _T_81; // @[Mux.scala 27:72]
wire [31:0] i0_rs2_bypass_data_d = _T_84 | _T_82; // @[Mux.scala 27:72] wire [31:0] i0_rs2_bypass_data_d = _T_84 | _T_82; // @[Mux.scala 27:72]
wire _T_87 = ~i0_rs1_bypass_en_d; // @[exu.scala 101:6] wire _T_87 = ~i0_rs1_bypass_en_d; // @[exu.scala 100:6]
wire _T_88 = _T_87 & io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[exu.scala 101:26] wire _T_88 = _T_87 & io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[exu.scala 100:26]
wire [31:0] _T_90 = {io_dec_exu_ib_exu_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58] wire [31:0] _T_90 = {io_dec_exu_ib_exu_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58]
wire _T_92 = _T_87 & io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 102:26] wire _T_92 = _T_87 & io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 101:26]
wire _T_95 = ~io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 103:28] wire _T_95 = ~io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 102:28]
wire _T_96 = _T_87 & _T_95; // @[exu.scala 103:26] wire _T_96 = _T_87 & _T_95; // @[exu.scala 102:26]
wire _T_97 = _T_96 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 103:69] wire _T_97 = _T_96 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 102:69]
wire [31:0] _T_99 = i0_rs1_bypass_en_d ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_99 = i0_rs1_bypass_en_d ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_100 = _T_88 ? _T_90 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_100 = _T_88 ? _T_90 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_101 = _T_92 ? io_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_101 = _T_92 ? io_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72]
@ -2377,45 +2377,45 @@ module exu(
wire [31:0] _T_104 = _T_103 | _T_101; // @[Mux.scala 27:72] wire [31:0] _T_104 = _T_103 | _T_101; // @[Mux.scala 27:72]
wire [31:0] i0_rs1_d = _T_104 | _T_102; // @[Mux.scala 27:72] wire [31:0] i0_rs1_d = _T_104 | _T_102; // @[Mux.scala 27:72]
reg [31:0] _T_107; // @[Reg.scala 27:20] reg [31:0] _T_107; // @[Reg.scala 27:20]
wire _T_108 = ~i0_rs2_bypass_en_d; // @[exu.scala 108:6] wire _T_108 = ~i0_rs2_bypass_en_d; // @[exu.scala 107:6]
wire _T_109 = _T_108 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 108:26] wire _T_109 = _T_108 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 107:26]
wire [31:0] _T_114 = _T_109 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_114 = _T_109 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_115 = _T_108 ? io_dec_exu_decode_exu_dec_i0_immed_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_115 = _T_108 ? io_dec_exu_decode_exu_dec_i0_immed_d : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_116 = i0_rs2_bypass_en_d ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_116 = i0_rs2_bypass_en_d ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_117 = _T_114 | _T_115; // @[Mux.scala 27:72] wire [31:0] _T_117 = _T_114 | _T_115; // @[Mux.scala 27:72]
wire [31:0] _T_118 = _T_117 | _T_116; // @[Mux.scala 27:72] wire [31:0] _T_118 = _T_117 | _T_116; // @[Mux.scala 27:72]
wire _T_120 = ~io_dec_exu_decode_exu_dec_extint_stall; // @[exu.scala 115:28] wire _T_120 = ~io_dec_exu_decode_exu_dec_extint_stall; // @[exu.scala 114:28]
wire _T_121 = _T_87 & _T_120; // @[exu.scala 115:26] wire _T_121 = _T_87 & _T_120; // @[exu.scala 114:26]
wire _T_122 = _T_121 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 115:68] wire _T_122 = _T_121 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 114:68]
wire _T_123 = _T_122 & io_dec_qual_lsu_d; // @[exu.scala 115:108] wire _T_123 = _T_122 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 114:108]
wire _T_126 = i0_rs1_bypass_en_d & _T_120; // @[exu.scala 116:25] wire _T_126 = i0_rs1_bypass_en_d & _T_120; // @[exu.scala 115:25]
wire _T_127 = _T_126 & io_dec_qual_lsu_d; // @[exu.scala 116:67] wire _T_127 = _T_126 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 115:67]
wire _T_129 = io_dec_exu_decode_exu_dec_extint_stall & io_dec_qual_lsu_d; // @[exu.scala 117:45] wire _T_129 = io_dec_exu_decode_exu_dec_extint_stall & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 116:45]
wire [31:0] _T_131 = {io_dec_exu_tlu_exu_dec_tlu_meihap,2'h0}; // @[Cat.scala 29:58] wire [31:0] _T_131 = {io_dec_exu_tlu_exu_dec_tlu_meihap,2'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_132 = _T_123 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_132 = _T_123 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_133 = _T_127 ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_133 = _T_127 ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_134 = _T_129 ? _T_131 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_134 = _T_129 ? _T_131 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_135 = _T_132 | _T_133; // @[Mux.scala 27:72] wire [31:0] _T_135 = _T_132 | _T_133; // @[Mux.scala 27:72]
wire _T_140 = _T_108 & _T_120; // @[exu.scala 121:26] wire _T_140 = _T_108 & _T_120; // @[exu.scala 120:26]
wire _T_141 = _T_140 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 121:68] wire _T_141 = _T_140 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 120:68]
wire _T_142 = _T_141 & io_dec_qual_lsu_d; // @[exu.scala 121:108] wire _T_142 = _T_141 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 120:108]
wire _T_145 = i0_rs2_bypass_en_d & _T_120; // @[exu.scala 122:25] wire _T_145 = i0_rs2_bypass_en_d & _T_120; // @[exu.scala 121:25]
wire _T_146 = _T_145 & io_dec_qual_lsu_d; // @[exu.scala 122:67] wire _T_146 = _T_145 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 121:67]
wire [31:0] _T_148 = _T_142 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_148 = _T_142 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_149 = _T_146 ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_149 = _T_146 ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
wire _T_153 = _T_87 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 126:26] wire _T_153 = _T_87 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 125:26]
wire [31:0] _T_156 = _T_153 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_156 = _T_153 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72]
wire [31:0] muldiv_rs1_d = _T_156 | _T_99; // @[Mux.scala 27:72] wire [31:0] muldiv_rs1_d = _T_156 | _T_99; // @[Mux.scala 27:72]
wire [31:0] _T_161 = io_dec_exu_decode_exu_mul_p_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_161 = io_dec_exu_decode_exu_mul_p_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] i0_rs2_d = _T_118; // @[Mux.scala 27:72 Mux.scala 27:72] wire [31:0] i0_rs2_d = _T_118; // @[Mux.scala 27:72 Mux.scala 27:72]
wire [1:0] _T_194 = i0_pp_r_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_194 = i0_pp_r_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[exu.scala 199:48] wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[exu.scala 200:48]
wire _T_206 = i0_flush_upper_x & _T_170; // @[exu.scala 201:75] wire _T_206 = i0_flush_upper_x & _T_170; // @[exu.scala 202:75]
wire _T_214 = _T_170 & i0_flush_upper_d; // @[exu.scala 240:48] wire _T_214 = _T_170 & i0_flush_upper_d; // @[exu.scala 241:48]
wire [30:0] _T_216 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_216 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_217 = _T_214 ? i0_flush_path_d : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_217 = _T_214 ? i0_flush_path_d : 31'h0; // @[Mux.scala 27:72]
wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 46:51 exu.scala 78:45] wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 45:51 exu.scala 77:45]
wire [31:0] _T_221 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 242:55] wire [31:0] _T_221 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 243:55]
rvclkhdr rvclkhdr ( // @[lib.scala 404:23] rvclkhdr rvclkhdr ( // @[lib.scala 404:23]
.io_clk(rvclkhdr_io_clk), .io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en) .io_en(rvclkhdr_io_en)
@ -2448,14 +2448,14 @@ module exu(
.io_clk(rvclkhdr_7_io_clk), .io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en) .io_en(rvclkhdr_7_io_en)
); );
exu_alu_ctl i_alu ( // @[exu.scala 130:19] exu_alu_ctl i_alu ( // @[exu.scala 129:19]
.clock(i_alu_clock), .clock(i_alu_clock),
.reset(i_alu_reset), .reset(i_alu_reset),
.io_dec_alu_dec_i0_alu_decode_d(i_alu_io_dec_alu_dec_i0_alu_decode_d), .io_dec_alu_dec_i0_alu_decode_d(i_alu_io_dec_alu_dec_i0_alu_decode_d),
.io_dec_alu_dec_csr_ren_d(i_alu_io_dec_alu_dec_csr_ren_d), .io_dec_alu_dec_csr_ren_d(i_alu_io_dec_alu_dec_csr_ren_d),
.io_dec_alu_dec_csr_rddata_d(i_alu_io_dec_alu_dec_csr_rddata_d),
.io_dec_alu_dec_i0_br_immed_d(i_alu_io_dec_alu_dec_i0_br_immed_d), .io_dec_alu_dec_i0_br_immed_d(i_alu_io_dec_alu_dec_i0_br_immed_d),
.io_dec_alu_exu_i0_pc_x(i_alu_io_dec_alu_exu_i0_pc_x), .io_dec_alu_exu_i0_pc_x(i_alu_io_dec_alu_exu_i0_pc_x),
.io_csr_rddata_in(i_alu_io_csr_rddata_in),
.io_dec_i0_pc_d(i_alu_io_dec_i0_pc_d), .io_dec_i0_pc_d(i_alu_io_dec_i0_pc_d),
.io_flush_upper_x(i_alu_io_flush_upper_x), .io_flush_upper_x(i_alu_io_flush_upper_x),
.io_dec_tlu_flush_lower_r(i_alu_io_dec_tlu_flush_lower_r), .io_dec_tlu_flush_lower_r(i_alu_io_dec_tlu_flush_lower_r),
@ -2531,7 +2531,7 @@ module exu(
.io_predict_p_out_bits_way(i_alu_io_predict_p_out_bits_way), .io_predict_p_out_bits_way(i_alu_io_predict_p_out_bits_way),
.io_predict_p_out_bits_pret(i_alu_io_predict_p_out_bits_pret) .io_predict_p_out_bits_pret(i_alu_io_predict_p_out_bits_pret)
); );
exu_mul_ctl i_mul ( // @[exu.scala 148:21] exu_mul_ctl i_mul ( // @[exu.scala 149:21]
.clock(i_mul_clock), .clock(i_mul_clock),
.reset(i_mul_reset), .reset(i_mul_reset),
.io_mul_p_valid(i_mul_io_mul_p_valid), .io_mul_p_valid(i_mul_io_mul_p_valid),
@ -2542,7 +2542,7 @@ module exu(
.io_rs2_in(i_mul_io_rs2_in), .io_rs2_in(i_mul_io_rs2_in),
.io_result_x(i_mul_io_result_x) .io_result_x(i_mul_io_result_x)
); );
exu_div_ctl i_div ( // @[exu.scala 156:21] exu_div_ctl i_div ( // @[exu.scala 157:21]
.clock(i_div_clock), .clock(i_div_clock),
.reset(i_div_reset), .reset(i_div_reset),
.io_dividend(i_div_io_dividend), .io_dividend(i_div_io_dividend),
@ -2554,47 +2554,47 @@ module exu(
.io_dec_div_div_p_bits_rem(i_div_io_dec_div_div_p_bits_rem), .io_dec_div_div_p_bits_rem(i_div_io_dec_div_div_p_bits_rem),
.io_dec_div_dec_div_cancel(i_div_io_dec_div_dec_div_cancel) .io_dec_div_dec_div_cancel(i_div_io_dec_div_dec_div_cancel)
); );
assign io_dec_exu_dec_alu_exu_i0_pc_x = i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 131:20] assign io_dec_exu_dec_alu_exu_i0_pc_x = i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 130:20]
assign io_dec_exu_decode_exu_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[exu.scala 164:57] assign io_dec_exu_decode_exu_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[exu.scala 165:57]
assign io_dec_exu_decode_exu_exu_csr_rs1_x = _T_107; // @[exu.scala 105:57] assign io_dec_exu_decode_exu_exu_csr_rs1_x = _T_107; // @[exu.scala 104:57]
assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_194 & i0_pp_r_bits_hist; // @[exu.scala 191:43] assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_194 & i0_pp_r_bits_hist; // @[exu.scala 192:43]
assign io_dec_exu_tlu_exu_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[exu.scala 192:43] assign io_dec_exu_tlu_exu_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[exu.scala 193:43]
assign io_dec_exu_tlu_exu_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[exu.scala 194:48] assign io_dec_exu_tlu_exu_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[exu.scala 195:48]
assign io_dec_exu_tlu_exu_exu_i0_br_index_r = predpipe_r[12:5]; // @[exu.scala 196:43] assign io_dec_exu_tlu_exu_exu_i0_br_index_r = predpipe_r[12:5]; // @[exu.scala 197:43]
assign io_dec_exu_tlu_exu_exu_i0_br_valid_r = i0_pp_r_valid; // @[exu.scala 188:43] assign io_dec_exu_tlu_exu_exu_i0_br_valid_r = i0_pp_r_valid; // @[exu.scala 189:43]
assign io_dec_exu_tlu_exu_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[exu.scala 189:43] assign io_dec_exu_tlu_exu_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[exu.scala 190:43]
assign io_dec_exu_tlu_exu_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[exu.scala 193:43] assign io_dec_exu_tlu_exu_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[exu.scala 194:43]
assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 168:47] assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 169:47]
assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 169:47] assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 170:47]
assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 170:47] assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 171:47]
assign io_dec_exu_tlu_exu_exu_npc_r = _T_221[30:0]; // @[exu.scala 242:49] assign io_dec_exu_tlu_exu_exu_npc_r = _T_221[30:0]; // @[exu.scala 243:49]
assign io_exu_bp_exu_i0_br_index_r = io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[exu.scala 197:43] assign io_exu_bp_exu_i0_br_index_r = io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[exu.scala 198:43]
assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 195:43] assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 196:43]
assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 190:43] assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 191:43]
assign io_exu_bp_exu_mp_pkt_valid = i0_flush_upper_x & i0_predict_p_x_valid; // @[exu.scala 52:53 exu.scala 203:39] assign io_exu_bp_exu_mp_pkt_valid = i0_flush_upper_x & i0_predict_p_x_valid; // @[exu.scala 51:53 exu.scala 204:39]
assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 205:39] assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 206:39]
assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 209:39] assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 210:39]
assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 210:39] assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 211:39]
assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 211:39] assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 212:39]
assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 212:39] assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 213:39]
assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 213:39] assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 214:39]
assign io_exu_bp_exu_mp_pkt_bits_br_error = 1'h0; // @[exu.scala 51:39] assign io_exu_bp_exu_mp_pkt_bits_br_error = 1'h0; // @[exu.scala 50:39]
assign io_exu_bp_exu_mp_pkt_bits_br_start_error = 1'h0; // @[exu.scala 50:44] assign io_exu_bp_exu_mp_pkt_bits_br_start_error = 1'h0; // @[exu.scala 49:44]
assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 206:39] assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 207:39]
assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 207:39] assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 208:39]
assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 204:39] assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 205:39]
assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 208:39] assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 209:39]
assign io_exu_bp_exu_mp_pkt_bits_prett = 31'h0; // @[exu.scala 49:57] assign io_exu_bp_exu_mp_pkt_bits_prett = 31'h0; // @[exu.scala 48:57]
assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 217:39] assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 218:39]
assign io_exu_bp_exu_mp_fghr = _T_206 ? ghr_d : ghr_x; // @[exu.scala 214:39] assign io_exu_bp_exu_mp_fghr = _T_206 ? ghr_d : ghr_x; // @[exu.scala 215:39]
assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 215:39] assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 216:39]
assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 216:39] assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 217:39]
assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 144:27] assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 145:27]
assign io_exu_div_result = i_div_io_exu_div_result; // @[exu.scala 162:33] assign io_exu_div_result = i_div_io_exu_div_result; // @[exu.scala 163:33]
assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 161:41] assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 162:41]
assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 114:27] assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 113:27]
assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 120:27] assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 119:27]
assign io_exu_flush_path_final = _T_216 | _T_217; // @[exu.scala 238:33] assign io_exu_flush_path_final = _T_216 | _T_217; // @[exu.scala 239:33]
assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18]
assign rvclkhdr_io_en = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[lib.scala 407:17] assign rvclkhdr_io_en = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[lib.scala 407:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18]
@ -2613,54 +2613,54 @@ module exu(
assign rvclkhdr_7_io_en = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[lib.scala 407:17] assign rvclkhdr_7_io_en = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[lib.scala 407:17]
assign i_alu_clock = clock; assign i_alu_clock = clock;
assign i_alu_reset = reset; assign i_alu_reset = reset;
assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 131:20] assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 130:20]
assign i_alu_io_dec_alu_dec_csr_ren_d = io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 131:20] assign i_alu_io_dec_alu_dec_csr_ren_d = io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 130:20]
assign i_alu_io_dec_alu_dec_csr_rddata_d = io_dec_exu_dec_alu_dec_csr_rddata_d; // @[exu.scala 131:20] assign i_alu_io_dec_alu_dec_i0_br_immed_d = io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[exu.scala 130:20]
assign i_alu_io_dec_alu_dec_i0_br_immed_d = io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[exu.scala 131:20] assign i_alu_io_csr_rddata_in = io_dec_csr_rddata_d; // @[exu.scala 136:33]
assign i_alu_io_dec_i0_pc_d = io_dec_exu_ib_exu_dec_i0_pc_d; // @[exu.scala 139:33] assign i_alu_io_dec_i0_pc_d = io_dec_exu_ib_exu_dec_i0_pc_d; // @[exu.scala 140:33]
assign i_alu_io_flush_upper_x = i0_flush_upper_x; // @[exu.scala 135:33] assign i_alu_io_flush_upper_x = i0_flush_upper_x; // @[exu.scala 135:33]
assign i_alu_io_dec_tlu_flush_lower_r = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 136:41] assign i_alu_io_dec_tlu_flush_lower_r = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 137:41]
assign i_alu_io_enable = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 133:45] assign i_alu_io_enable = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 133:45]
assign i_alu_io_i0_ap_clz = io_dec_exu_decode_exu_i0_ap_clz; // @[exu.scala 140:51] assign i_alu_io_i0_ap_clz = io_dec_exu_decode_exu_i0_ap_clz; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_ctz = io_dec_exu_decode_exu_i0_ap_ctz; // @[exu.scala 140:51] assign i_alu_io_i0_ap_ctz = io_dec_exu_decode_exu_i0_ap_ctz; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_pcnt = io_dec_exu_decode_exu_i0_ap_pcnt; // @[exu.scala 140:51] assign i_alu_io_i0_ap_pcnt = io_dec_exu_decode_exu_i0_ap_pcnt; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_sext_b = io_dec_exu_decode_exu_i0_ap_sext_b; // @[exu.scala 140:51] assign i_alu_io_i0_ap_sext_b = io_dec_exu_decode_exu_i0_ap_sext_b; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_sext_h = io_dec_exu_decode_exu_i0_ap_sext_h; // @[exu.scala 140:51] assign i_alu_io_i0_ap_sext_h = io_dec_exu_decode_exu_i0_ap_sext_h; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_min = io_dec_exu_decode_exu_i0_ap_min; // @[exu.scala 140:51] assign i_alu_io_i0_ap_min = io_dec_exu_decode_exu_i0_ap_min; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_max = io_dec_exu_decode_exu_i0_ap_max; // @[exu.scala 140:51] assign i_alu_io_i0_ap_max = io_dec_exu_decode_exu_i0_ap_max; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_pack = io_dec_exu_decode_exu_i0_ap_pack; // @[exu.scala 140:51] assign i_alu_io_i0_ap_pack = io_dec_exu_decode_exu_i0_ap_pack; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_packu = io_dec_exu_decode_exu_i0_ap_packu; // @[exu.scala 140:51] assign i_alu_io_i0_ap_packu = io_dec_exu_decode_exu_i0_ap_packu; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_packh = io_dec_exu_decode_exu_i0_ap_packh; // @[exu.scala 140:51] assign i_alu_io_i0_ap_packh = io_dec_exu_decode_exu_i0_ap_packh; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_rol = io_dec_exu_decode_exu_i0_ap_rol; // @[exu.scala 140:51] assign i_alu_io_i0_ap_rol = io_dec_exu_decode_exu_i0_ap_rol; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_ror = io_dec_exu_decode_exu_i0_ap_ror; // @[exu.scala 140:51] assign i_alu_io_i0_ap_ror = io_dec_exu_decode_exu_i0_ap_ror; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_grev = io_dec_exu_decode_exu_i0_ap_grev; // @[exu.scala 140:51] assign i_alu_io_i0_ap_grev = io_dec_exu_decode_exu_i0_ap_grev; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_gorc = io_dec_exu_decode_exu_i0_ap_gorc; // @[exu.scala 140:51] assign i_alu_io_i0_ap_gorc = io_dec_exu_decode_exu_i0_ap_gorc; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_zbb = io_dec_exu_decode_exu_i0_ap_zbb; // @[exu.scala 140:51] assign i_alu_io_i0_ap_zbb = io_dec_exu_decode_exu_i0_ap_zbb; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_sbset = io_dec_exu_decode_exu_i0_ap_sbset; // @[exu.scala 140:51] assign i_alu_io_i0_ap_sbset = io_dec_exu_decode_exu_i0_ap_sbset; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_sbclr = io_dec_exu_decode_exu_i0_ap_sbclr; // @[exu.scala 140:51] assign i_alu_io_i0_ap_sbclr = io_dec_exu_decode_exu_i0_ap_sbclr; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_sbinv = io_dec_exu_decode_exu_i0_ap_sbinv; // @[exu.scala 140:51] assign i_alu_io_i0_ap_sbinv = io_dec_exu_decode_exu_i0_ap_sbinv; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_sbext = io_dec_exu_decode_exu_i0_ap_sbext; // @[exu.scala 140:51] assign i_alu_io_i0_ap_sbext = io_dec_exu_decode_exu_i0_ap_sbext; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_land = io_dec_exu_decode_exu_i0_ap_land; // @[exu.scala 140:51] assign i_alu_io_i0_ap_land = io_dec_exu_decode_exu_i0_ap_land; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_lor = io_dec_exu_decode_exu_i0_ap_lor; // @[exu.scala 140:51] assign i_alu_io_i0_ap_lor = io_dec_exu_decode_exu_i0_ap_lor; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_lxor = io_dec_exu_decode_exu_i0_ap_lxor; // @[exu.scala 140:51] assign i_alu_io_i0_ap_lxor = io_dec_exu_decode_exu_i0_ap_lxor; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_sll = io_dec_exu_decode_exu_i0_ap_sll; // @[exu.scala 140:51] assign i_alu_io_i0_ap_sll = io_dec_exu_decode_exu_i0_ap_sll; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_srl = io_dec_exu_decode_exu_i0_ap_srl; // @[exu.scala 140:51] assign i_alu_io_i0_ap_srl = io_dec_exu_decode_exu_i0_ap_srl; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_sra = io_dec_exu_decode_exu_i0_ap_sra; // @[exu.scala 140:51] assign i_alu_io_i0_ap_sra = io_dec_exu_decode_exu_i0_ap_sra; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_beq = io_dec_exu_decode_exu_i0_ap_beq; // @[exu.scala 140:51] assign i_alu_io_i0_ap_beq = io_dec_exu_decode_exu_i0_ap_beq; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_bne = io_dec_exu_decode_exu_i0_ap_bne; // @[exu.scala 140:51] assign i_alu_io_i0_ap_bne = io_dec_exu_decode_exu_i0_ap_bne; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_blt = io_dec_exu_decode_exu_i0_ap_blt; // @[exu.scala 140:51] assign i_alu_io_i0_ap_blt = io_dec_exu_decode_exu_i0_ap_blt; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_bge = io_dec_exu_decode_exu_i0_ap_bge; // @[exu.scala 140:51] assign i_alu_io_i0_ap_bge = io_dec_exu_decode_exu_i0_ap_bge; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_add = io_dec_exu_decode_exu_i0_ap_add; // @[exu.scala 140:51] assign i_alu_io_i0_ap_add = io_dec_exu_decode_exu_i0_ap_add; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_sub = io_dec_exu_decode_exu_i0_ap_sub; // @[exu.scala 140:51] assign i_alu_io_i0_ap_sub = io_dec_exu_decode_exu_i0_ap_sub; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_slt = io_dec_exu_decode_exu_i0_ap_slt; // @[exu.scala 140:51] assign i_alu_io_i0_ap_slt = io_dec_exu_decode_exu_i0_ap_slt; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_unsign = io_dec_exu_decode_exu_i0_ap_unsign; // @[exu.scala 140:51] assign i_alu_io_i0_ap_unsign = io_dec_exu_decode_exu_i0_ap_unsign; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_jal = io_dec_exu_decode_exu_i0_ap_jal; // @[exu.scala 140:51] assign i_alu_io_i0_ap_jal = io_dec_exu_decode_exu_i0_ap_jal; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_predict_t = io_dec_exu_decode_exu_i0_ap_predict_t; // @[exu.scala 140:51] assign i_alu_io_i0_ap_predict_t = io_dec_exu_decode_exu_i0_ap_predict_t; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_predict_nt = io_dec_exu_decode_exu_i0_ap_predict_nt; // @[exu.scala 140:51] assign i_alu_io_i0_ap_predict_nt = io_dec_exu_decode_exu_i0_ap_predict_nt; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_csr_write = io_dec_exu_decode_exu_i0_ap_csr_write; // @[exu.scala 140:51] assign i_alu_io_i0_ap_csr_write = io_dec_exu_decode_exu_i0_ap_csr_write; // @[exu.scala 141:51]
assign i_alu_io_i0_ap_csr_imm = io_dec_exu_decode_exu_i0_ap_csr_imm; // @[exu.scala 140:51] assign i_alu_io_i0_ap_csr_imm = io_dec_exu_decode_exu_i0_ap_csr_imm; // @[exu.scala 141:51]
assign i_alu_io_a_in = _T_104 | _T_102; // @[exu.scala 137:39] assign i_alu_io_a_in = _T_104 | _T_102; // @[exu.scala 138:39]
assign i_alu_io_b_in = i0_rs2_d; // @[exu.scala 138:39] assign i_alu_io_b_in = i0_rs2_d; // @[exu.scala 139:39]
assign i_alu_io_pp_in_valid = io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[exu.scala 134:45] assign i_alu_io_pp_in_valid = io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[exu.scala 134:45]
assign i_alu_io_pp_in_bits_boffset = io_dec_exu_ib_exu_dec_i0_pc_d[0]; // @[exu.scala 134:45] assign i_alu_io_pp_in_bits_boffset = io_dec_exu_ib_exu_dec_i0_pc_d[0]; // @[exu.scala 134:45]
assign i_alu_io_pp_in_bits_pc4 = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[exu.scala 134:45] assign i_alu_io_pp_in_bits_pc4 = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[exu.scala 134:45]
@ -2675,20 +2675,20 @@ module exu(
assign i_alu_io_pp_in_bits_prett = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[exu.scala 134:45] assign i_alu_io_pp_in_bits_prett = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[exu.scala 134:45]
assign i_mul_clock = clock; assign i_mul_clock = clock;
assign i_mul_reset = reset; assign i_mul_reset = reset;
assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 150:23] assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 151:23]
assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 150:23] assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 151:23]
assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 150:23] assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 151:23]
assign i_mul_io_mul_p_bits_low = io_dec_exu_decode_exu_mul_p_bits_low; // @[exu.scala 150:23] assign i_mul_io_mul_p_bits_low = io_dec_exu_decode_exu_mul_p_bits_low; // @[exu.scala 151:23]
assign i_mul_io_rs1_in = muldiv_rs1_d & _T_161; // @[exu.scala 152:41] assign i_mul_io_rs1_in = muldiv_rs1_d & _T_161; // @[exu.scala 153:41]
assign i_mul_io_rs2_in = i0_rs2_d & _T_161; // @[exu.scala 153:41] assign i_mul_io_rs2_in = i0_rs2_d & _T_161; // @[exu.scala 154:41]
assign i_div_clock = clock; assign i_div_clock = clock;
assign i_div_reset = reset; assign i_div_reset = reset;
assign i_div_io_dividend = _T_156 | _T_99; // @[exu.scala 159:33] assign i_div_io_dividend = _T_156 | _T_99; // @[exu.scala 160:33]
assign i_div_io_divisor = i0_rs2_d; // @[exu.scala 160:33] assign i_div_io_divisor = i0_rs2_d; // @[exu.scala 161:33]
assign i_div_io_dec_div_div_p_valid = io_dec_exu_dec_div_div_p_valid; // @[exu.scala 157:20] assign i_div_io_dec_div_div_p_valid = io_dec_exu_dec_div_div_p_valid; // @[exu.scala 158:20]
assign i_div_io_dec_div_div_p_bits_unsign = io_dec_exu_dec_div_div_p_bits_unsign; // @[exu.scala 157:20] assign i_div_io_dec_div_div_p_bits_unsign = io_dec_exu_dec_div_div_p_bits_unsign; // @[exu.scala 158:20]
assign i_div_io_dec_div_div_p_bits_rem = io_dec_exu_dec_div_div_p_bits_rem; // @[exu.scala 157:20] assign i_div_io_dec_div_div_p_bits_rem = io_dec_exu_dec_div_div_p_bits_rem; // @[exu.scala 158:20]
assign i_div_io_dec_div_dec_div_cancel = io_dec_exu_dec_div_dec_div_cancel; // @[exu.scala 157:20] assign i_div_io_dec_div_dec_div_cancel = io_dec_exu_dec_div_dec_div_cancel; // @[exu.scala 158:20]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE `define RANDOMIZE
`endif `endif

547
lsu.anno.json Normal file
View File

@ -0,0 +1,547 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn",
"sources":[
"~lsu|lsu>io_axi_ar_ready",
"~lsu|lsu>io_axi_aw_ready",
"~lsu|lsu>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_mken",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_single_ecc_error_incr",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dccm_ready",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_trigger_match_m",
"sources":[
"~lsu|lsu>io_trigger_pkt_any_0_store",
"~lsu|lsu>io_trigger_pkt_any_1_store",
"~lsu|lsu>io_trigger_pkt_any_3_m",
"~lsu|lsu>io_trigger_pkt_any_0_load",
"~lsu|lsu>io_trigger_pkt_any_0_select",
"~lsu|lsu>io_trigger_pkt_any_3_store",
"~lsu|lsu>io_trigger_pkt_any_2_store",
"~lsu|lsu>io_trigger_pkt_any_1_load",
"~lsu|lsu>io_trigger_pkt_any_1_select",
"~lsu|lsu>io_trigger_pkt_any_2_m",
"~lsu|lsu>io_trigger_pkt_any_3_load",
"~lsu|lsu>io_trigger_pkt_any_3_select",
"~lsu|lsu>io_trigger_pkt_any_2_load",
"~lsu|lsu>io_trigger_pkt_any_2_select",
"~lsu|lsu>io_trigger_pkt_any_0_m",
"~lsu|lsu>io_trigger_pkt_any_1_m",
"~lsu|lsu>io_trigger_pkt_any_0_tdata2",
"~lsu|lsu>io_trigger_pkt_any_0_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_1_tdata2",
"~lsu|lsu>io_trigger_pkt_any_1_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_3_tdata2",
"~lsu|lsu>io_trigger_pkt_any_3_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_2_tdata2",
"~lsu|lsu>io_trigger_pkt_any_2_match_pkt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wren",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy",
"sources":[
"~lsu|lsu>io_axi_ar_ready",
"~lsu|lsu>io_axi_aw_ready",
"~lsu|lsu>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_data_hi",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_addr_lo",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_store_stall_any",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata",
"sources":[
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_addr_hi",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_fastint_stall_any",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_exu_lsu_result_m",
"sources":[
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rd_addr_hi",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_data_lo",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wren",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_rden",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_load_stall_any",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rden",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rd_addr_lo",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wr_data",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wraddr",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m",
"sources":[
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_force_halt"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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11116
lsu.v Normal file
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113
lsu_bus_intf.anno.json Normal file
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_misaligned",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_lsu_commit_r",
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_bus_read_data_m",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m",
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_m",
"~lsu_bus_intf|lsu_bus_intf>io_dec_tlu_force_halt",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_bits_store",
"~lsu_bus_intf|lsu_bus_intf>io_store_data_r",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_by",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_valid",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_r",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_word",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_half",
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_valid_m",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_load",
"~lsu_bus_intf|lsu_bus_intf>io_flush_m_up",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_valid",
"~lsu_bus_intf|lsu_bus_intf>io_is_sideeffects_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_m",
"~lsu_bus_intf|lsu_bus_intf>io_dec_tlu_force_halt",
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_by",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_bits_store",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_word",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_half",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_valid",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_r",
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_busy",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_axi_ar_ready",
"~lsu_bus_intf|lsu_bus_intf>io_axi_aw_ready",
"~lsu_bus_intf|lsu_bus_intf>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_tag_m",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_lsu_bus_buffer_full_any",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_d",
"~lsu_bus_intf|lsu_bus_intf>io_dec_lsu_valid_raw_d",
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m",
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_inv_r",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_lsu_commit_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_trxn",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_axi_ar_ready",
"~lsu_bus_intf|lsu_bus_intf>io_axi_aw_ready",
"~lsu_bus_intf|lsu_bus_intf>io_axi_w_ready"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_bus_intf.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_bus_intf"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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5244
lsu_bus_intf.v Normal file
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331
lsu_lsc_ctl.anno.json Normal file
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_fast_int",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_fir_addr",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_store_data_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_picm_mask_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_store_data_bypass_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dma",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_stack",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_stack",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_valid",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_dccm_req",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_m_up",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_unsign",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_incr",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_by",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_dccm_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_corr_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_lsc_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_lsc_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

987
lsu_lsc_ctl.fir Normal file
View File

@ -0,0 +1,987 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit lsu_lsc_ctl :
module lsu_addrcheck :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 370:27]
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 370:49]
wire start_addr_in_dccm_d : UInt<1> @[lib.scala 371:26]
node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 375:24]
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 375:39]
start_addr_in_dccm_d <= _T_2 @[lib.scala 375:16]
node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 370:27]
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 370:49]
wire end_addr_in_dccm_d : UInt<1> @[lib.scala 371:26]
node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 375:24]
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 375:39]
end_addr_in_dccm_d <= _T_5 @[lib.scala 375:16]
wire addr_in_iccm : UInt<1>
addr_in_iccm <= UInt<1>("h00")
node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37]
node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45]
addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18]
node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89]
node _T_9 = bits(_T_8, 31, 28) @[lib.scala 370:27]
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 370:49]
wire start_addr_in_pic_d : UInt<1> @[lib.scala 371:26]
node _T_10 = bits(_T_8, 31, 15) @[lib.scala 375:24]
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 375:39]
start_addr_in_pic_d <= _T_11 @[lib.scala 375:16]
node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83]
node _T_13 = bits(_T_12, 31, 28) @[lib.scala 370:27]
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 370:49]
wire end_addr_in_pic_d : UInt<1> @[lib.scala 371:26]
node _T_14 = bits(_T_12, 31, 15) @[lib.scala 375:24]
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 375:39]
end_addr_in_pic_d <= _T_15 @[lib.scala 375:16]
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60]
node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49]
node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55]
node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74]
node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109]
node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115]
node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91]
node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57]
io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32]
node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56]
io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32]
node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63]
node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33]
io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30]
node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51]
node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50]
node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50]
node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92]
node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62]
node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60]
node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137]
node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185]
node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158]
node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80]
node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56]
node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138]
node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116]
node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90]
node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148]
node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58]
node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58]
node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58]
node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99]
node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33]
node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49]
node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56]
node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121]
node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88]
node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30]
node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49]
node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56]
node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121]
node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88]
node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30]
node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153]
node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49]
node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56]
node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121]
node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88]
node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30]
node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153]
node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49]
node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56]
node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121]
node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88]
node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30]
node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153]
node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49]
node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56]
node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121]
node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88]
node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30]
node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153]
node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49]
node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56]
node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121]
node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88]
node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30]
node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153]
node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49]
node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56]
node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121]
node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88]
node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30]
node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153]
node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49]
node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56]
node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121]
node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88]
node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30]
node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153]
node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48]
node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57]
node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122]
node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89]
node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31]
node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49]
node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58]
node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123]
node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90]
node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32]
node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154]
node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49]
node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58]
node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123]
node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90]
node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32]
node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155]
node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49]
node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58]
node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123]
node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90]
node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32]
node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155]
node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49]
node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58]
node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123]
node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90]
node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32]
node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155]
node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49]
node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58]
node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123]
node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90]
node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32]
node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155]
node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49]
node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58]
node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123]
node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90]
node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32]
node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155]
node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49]
node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58]
node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123]
node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90]
node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32]
node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155]
node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7]
node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104]
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57]
node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70]
node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76]
node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92]
node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90]
node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51]
wire unmapped_access_fault_d : UInt<1>
unmapped_access_fault_d <= UInt<1>("h01")
wire mpu_access_fault_d : UInt<1>
mpu_access_fault_d <= UInt<1>("h01")
node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87]
node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64]
node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62]
node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57]
node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36]
node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34]
node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112]
node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29]
node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85]
node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29]
node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85]
unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29]
node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33]
node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64]
node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62]
mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29]
node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49]
node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70]
node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92]
node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118]
node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141]
node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139]
io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21]
node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60]
node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100]
node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144]
node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185]
node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164]
node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120]
node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80]
node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35]
node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53]
node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78]
node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61]
node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59]
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57]
node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90]
node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57]
node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113]
node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136]
node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134]
io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25]
node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111]
node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80]
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39]
node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50]
node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84]
node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113]
node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27]
io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21]
node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66]
node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64]
node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120]
node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118]
node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88]
node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142]
node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163]
io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31]
node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66]
node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36]
node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95]
node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116]
io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33]
reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60]
_T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60]
io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50]
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_3 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
module lsu_lsc_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
wire end_addr_pre_m : UInt<29>
end_addr_pre_m <= UInt<29>("h00")
wire end_addr_pre_r : UInt<29>
end_addr_pre_r <= UInt<29>("h00")
wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 93:29]
wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 94:29]
wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29]
wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 96:29]
wire _T : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 97:35]
_T.bits.addr <= UInt<32>("h00") @[lsu_lsc_ctl.scala 97:35]
_T.bits.mscause <= UInt<4>("h00") @[lsu_lsc_ctl.scala 97:35]
_T.bits.exc_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35]
_T.bits.inst_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35]
_T.bits.single_ecc_error <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35]
_T.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35]
lsu_error_pkt_m.bits.addr <= _T.bits.addr @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.bits.mscause <= _T.bits.mscause @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.bits.exc_type <= _T.bits.exc_type @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.bits.inst_type <= _T.bits.inst_type @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.bits.single_ecc_error <= _T.bits.single_ecc_error @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.valid <= _T.valid @[lsu_lsc_ctl.scala 97:20]
node _T_1 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 99:52]
node lsu_rs1_d = mux(_T_1, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 99:28]
node _T_2 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 100:44]
node _T_3 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15]
node _T_4 = mux(_T_3, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node lsu_offset_d = and(_T_2, _T_4) @[lsu_lsc_ctl.scala 100:51]
node _T_5 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 103:66]
node rs1_d = mux(_T_5, io.lsu_exu.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 103:28]
node _T_6 = bits(rs1_d, 11, 0) @[lib.scala 92:31]
node _T_7 = cat(UInt<1>("h00"), _T_6) @[Cat.scala 29:58]
node _T_8 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60]
node _T_9 = cat(UInt<1>("h00"), _T_8) @[Cat.scala 29:58]
node _T_10 = add(_T_7, _T_9) @[lib.scala 92:39]
node _T_11 = tail(_T_10, 1) @[lib.scala 92:39]
node _T_12 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41]
node _T_13 = bits(_T_11, 12, 12) @[lib.scala 93:50]
node _T_14 = xor(_T_12, _T_13) @[lib.scala 93:46]
node _T_15 = not(_T_14) @[lib.scala 93:33]
node _T_16 = bits(_T_15, 0, 0) @[Bitwise.scala 72:15]
node _T_17 = mux(_T_16, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_18 = bits(rs1_d, 31, 12) @[lib.scala 93:63]
node _T_19 = and(_T_17, _T_18) @[lib.scala 93:58]
node _T_20 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25]
node _T_21 = not(_T_20) @[lib.scala 94:18]
node _T_22 = bits(_T_11, 12, 12) @[lib.scala 94:34]
node _T_23 = and(_T_21, _T_22) @[lib.scala 94:30]
node _T_24 = bits(_T_23, 0, 0) @[Bitwise.scala 72:15]
node _T_25 = mux(_T_24, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_26 = bits(rs1_d, 31, 12) @[lib.scala 94:47]
node _T_27 = add(_T_26, UInt<1>("h01")) @[lib.scala 94:54]
node _T_28 = tail(_T_27, 1) @[lib.scala 94:54]
node _T_29 = and(_T_25, _T_28) @[lib.scala 94:41]
node _T_30 = or(_T_19, _T_29) @[lib.scala 93:72]
node _T_31 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24]
node _T_32 = bits(_T_11, 12, 12) @[lib.scala 95:34]
node _T_33 = not(_T_32) @[lib.scala 95:31]
node _T_34 = and(_T_31, _T_33) @[lib.scala 95:29]
node _T_35 = bits(_T_34, 0, 0) @[Bitwise.scala 72:15]
node _T_36 = mux(_T_35, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_37 = bits(rs1_d, 31, 12) @[lib.scala 95:47]
node _T_38 = sub(_T_37, UInt<1>("h01")) @[lib.scala 95:54]
node _T_39 = tail(_T_38, 1) @[lib.scala 95:54]
node _T_40 = and(_T_36, _T_39) @[lib.scala 95:41]
node _T_41 = or(_T_30, _T_40) @[lib.scala 94:61]
node _T_42 = bits(_T_11, 11, 0) @[lib.scala 96:22]
node full_addr_d = cat(_T_41, _T_42) @[Cat.scala 29:58]
node _T_43 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15]
node _T_44 = mux(_T_43, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_45 = and(_T_44, UInt<3>("h01")) @[lsu_lsc_ctl.scala 108:58]
node _T_46 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_47 = mux(_T_46, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_48 = and(_T_47, UInt<3>("h03")) @[lsu_lsc_ctl.scala 109:40]
node _T_49 = or(_T_45, _T_48) @[lsu_lsc_ctl.scala 108:70]
node _T_50 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15]
node _T_51 = mux(_T_50, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_52 = and(_T_51, UInt<3>("h07")) @[lsu_lsc_ctl.scala 110:40]
node addr_offset_d = or(_T_49, _T_52) @[lsu_lsc_ctl.scala 109:52]
node _T_53 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 112:39]
node _T_54 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 112:52]
node _T_55 = cat(_T_53, _T_54) @[Cat.scala 29:58]
node _T_56 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_57 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 112:91]
node _T_58 = cat(_T_56, _T_57) @[Cat.scala 29:58]
node _T_59 = add(_T_55, _T_58) @[lsu_lsc_ctl.scala 112:60]
node end_addr_offset_d = tail(_T_59, 1) @[lsu_lsc_ctl.scala 112:60]
node _T_60 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 113:32]
node _T_61 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 113:70]
node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15]
node _T_63 = mux(_T_62, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
node _T_64 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 113:93]
node _T_65 = cat(_T_63, _T_64) @[Cat.scala 29:58]
node _T_66 = add(_T_60, _T_65) @[lsu_lsc_ctl.scala 113:39]
node full_end_addr_d = tail(_T_66, 1) @[lsu_lsc_ctl.scala 113:39]
io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 114:24]
inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 117:25]
addrcheck.clock <= clock
addrcheck.reset <= reset
addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 119:42]
addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 121:42]
addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 122:42]
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 124:42]
node _T_67 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 125:50]
addrcheck.io.rs1_region_d <= _T_67 @[lsu_lsc_ctl.scala 125:42]
addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 126:42]
io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 127:42]
io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 128:42]
io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 129:42]
addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 136:42]
wire exc_mscause_r : UInt<4>
exc_mscause_r <= UInt<4>("h00")
wire fir_dccm_access_error_r : UInt<1>
fir_dccm_access_error_r <= UInt<1>("h00")
wire fir_nondccm_access_error_r : UInt<1>
fir_nondccm_access_error_r <= UInt<1>("h00")
wire access_fault_r : UInt<1>
access_fault_r <= UInt<1>("h00")
wire misaligned_fault_r : UInt<1>
misaligned_fault_r <= UInt<1>("h00")
wire lsu_fir_error_m : UInt<2>
lsu_fir_error_m <= UInt<2>("h00")
wire fir_dccm_access_error_m : UInt<1>
fir_dccm_access_error_m <= UInt<1>("h00")
wire fir_nondccm_access_error_m : UInt<1>
fir_nondccm_access_error_m <= UInt<1>("h00")
reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 148:75]
access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 148:75]
reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75]
misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 149:75]
reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75]
exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 150:75]
reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75]
_T_68 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 151:75]
fir_dccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 151:38]
reg _T_69 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75]
_T_69 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 152:75]
fir_nondccm_access_error_m <= _T_69 @[lsu_lsc_ctl.scala 152:38]
node _T_70 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 154:34]
io.lsu_exc_m <= _T_70 @[lsu_lsc_ctl.scala 154:16]
node _T_71 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 155:64]
node _T_72 = and(io.lsu_single_ecc_error_r, _T_71) @[lsu_lsc_ctl.scala 155:62]
node _T_73 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 155:111]
node _T_74 = and(_T_72, _T_73) @[lsu_lsc_ctl.scala 155:92]
node _T_75 = and(_T_74, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 155:136]
io.lsu_single_ecc_error_incr <= _T_75 @[lsu_lsc_ctl.scala 155:32]
node _T_76 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 177:46]
node _T_77 = or(_T_76, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 177:67]
node _T_78 = and(_T_77, io.lsu_pkt_m.valid) @[lsu_lsc_ctl.scala 177:96]
node _T_79 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:119]
node _T_80 = and(_T_78, _T_79) @[lsu_lsc_ctl.scala 177:117]
node _T_81 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:144]
node _T_82 = and(_T_80, _T_81) @[lsu_lsc_ctl.scala 177:142]
node _T_83 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:174]
node _T_84 = and(_T_82, _T_83) @[lsu_lsc_ctl.scala 177:172]
lsu_error_pkt_m.valid <= _T_84 @[lsu_lsc_ctl.scala 177:27]
node _T_85 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:75]
node _T_86 = and(io.lsu_single_ecc_error_m, _T_85) @[lsu_lsc_ctl.scala 178:73]
node _T_87 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:101]
node _T_88 = and(_T_86, _T_87) @[lsu_lsc_ctl.scala 178:99]
lsu_error_pkt_m.bits.single_ecc_error <= _T_88 @[lsu_lsc_ctl.scala 178:43]
lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 179:43]
node _T_89 = not(misaligned_fault_m) @[lsu_lsc_ctl.scala 180:46]
lsu_error_pkt_m.bits.exc_type <= _T_89 @[lsu_lsc_ctl.scala 180:43]
node _T_90 = eq(misaligned_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 181:80]
node _T_91 = and(io.lsu_double_ecc_error_m, _T_90) @[lsu_lsc_ctl.scala 181:78]
node _T_92 = eq(access_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 181:102]
node _T_93 = and(_T_91, _T_92) @[lsu_lsc_ctl.scala 181:100]
node _T_94 = eq(_T_93, UInt<1>("h01")) @[lsu_lsc_ctl.scala 181:118]
node _T_95 = bits(exc_mscause_m, 3, 0) @[lsu_lsc_ctl.scala 181:149]
node _T_96 = mux(_T_94, UInt<4>("h01"), _T_95) @[lsu_lsc_ctl.scala 181:49]
lsu_error_pkt_m.bits.mscause <= _T_96 @[lsu_lsc_ctl.scala 181:43]
node _T_97 = bits(io.lsu_addr_m, 31, 0) @[lsu_lsc_ctl.scala 182:59]
lsu_error_pkt_m.bits.addr <= _T_97 @[lsu_lsc_ctl.scala 182:43]
node _T_98 = bits(fir_nondccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 183:72]
node _T_99 = bits(fir_dccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 183:117]
node _T_100 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 183:166]
node _T_101 = bits(_T_100, 0, 0) @[lsu_lsc_ctl.scala 183:195]
node _T_102 = mux(_T_101, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 183:137]
node _T_103 = mux(_T_99, UInt<2>("h02"), _T_102) @[lsu_lsc_ctl.scala 183:92]
node _T_104 = mux(_T_98, UInt<2>("h03"), _T_103) @[lsu_lsc_ctl.scala 183:44]
lsu_fir_error_m <= _T_104 @[lsu_lsc_ctl.scala 183:38]
node _T_105 = or(lsu_error_pkt_m.valid, lsu_error_pkt_m.bits.single_ecc_error) @[lsu_lsc_ctl.scala 184:73]
node _T_106 = or(_T_105, io.clk_override) @[lsu_lsc_ctl.scala 184:113]
node _T_107 = bits(_T_106, 0, 0) @[lib.scala 8:44]
node _T_108 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr of rvclkhdr @[lib.scala 417:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 419:18]
rvclkhdr.io.en <= _T_107 @[lib.scala 420:17]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 421:24]
wire _T_109 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lib.scala 423:50]
_T_109.bits.addr <= UInt<32>("h00") @[lib.scala 423:50]
_T_109.bits.mscause <= UInt<4>("h00") @[lib.scala 423:50]
_T_109.bits.exc_type <= UInt<1>("h00") @[lib.scala 423:50]
_T_109.bits.inst_type <= UInt<1>("h00") @[lib.scala 423:50]
_T_109.bits.single_ecc_error <= UInt<1>("h00") @[lib.scala 423:50]
_T_109.valid <= UInt<1>("h00") @[lib.scala 423:50]
reg _T_110 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, clock with : (reset => (reset, _T_109)) @[Reg.scala 27:20]
when _T_107 : @[Reg.scala 28:19]
_T_110.bits.addr <= lsu_error_pkt_m.bits.addr @[Reg.scala 28:23]
_T_110.bits.mscause <= lsu_error_pkt_m.bits.mscause @[Reg.scala 28:23]
_T_110.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[Reg.scala 28:23]
_T_110.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[Reg.scala 28:23]
_T_110.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[Reg.scala 28:23]
_T_110.valid <= lsu_error_pkt_m.valid @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
io.lsu_error_pkt_r.bits.addr <= _T_110.bits.addr @[lsu_lsc_ctl.scala 184:24]
io.lsu_error_pkt_r.bits.mscause <= _T_110.bits.mscause @[lsu_lsc_ctl.scala 184:24]
io.lsu_error_pkt_r.bits.exc_type <= _T_110.bits.exc_type @[lsu_lsc_ctl.scala 184:24]
io.lsu_error_pkt_r.bits.inst_type <= _T_110.bits.inst_type @[lsu_lsc_ctl.scala 184:24]
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_110.bits.single_ecc_error @[lsu_lsc_ctl.scala 184:24]
io.lsu_error_pkt_r.valid <= _T_110.valid @[lsu_lsc_ctl.scala 184:24]
reg _T_111 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 185:83]
_T_111 <= lsu_error_pkt_m.bits.single_ecc_error @[lsu_lsc_ctl.scala 185:83]
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_111 @[lsu_lsc_ctl.scala 185:46]
reg _T_112 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 186:67]
_T_112 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 186:67]
io.lsu_error_pkt_r.valid <= _T_112 @[lsu_lsc_ctl.scala 186:30]
reg _T_113 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:75]
_T_113 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 187:75]
io.lsu_fir_error <= _T_113 @[lsu_lsc_ctl.scala 187:38]
dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 189:27]
dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:26]
dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:27]
dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 192:22]
dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 193:27]
dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 194:27]
node _T_114 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 195:30]
dma_pkt_d.bits.load <= _T_114 @[lsu_lsc_ctl.scala 195:27]
node _T_115 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 196:56]
node _T_116 = eq(_T_115, UInt<3>("h00")) @[lsu_lsc_ctl.scala 196:62]
dma_pkt_d.bits.by <= _T_116 @[lsu_lsc_ctl.scala 196:27]
node _T_117 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56]
node _T_118 = eq(_T_117, UInt<3>("h01")) @[lsu_lsc_ctl.scala 197:62]
dma_pkt_d.bits.half <= _T_118 @[lsu_lsc_ctl.scala 197:27]
node _T_119 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56]
node _T_120 = eq(_T_119, UInt<3>("h02")) @[lsu_lsc_ctl.scala 198:62]
dma_pkt_d.bits.word <= _T_120 @[lsu_lsc_ctl.scala 198:27]
node _T_121 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56]
node _T_122 = eq(_T_121, UInt<3>("h03")) @[lsu_lsc_ctl.scala 199:62]
dma_pkt_d.bits.dword <= _T_122 @[lsu_lsc_ctl.scala 199:27]
dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 200:39]
dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39]
dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39]
wire lsu_ld_datafn_r : UInt<32>
lsu_ld_datafn_r <= UInt<32>("h00")
wire lsu_ld_datafn_corr_r : UInt<32>
lsu_ld_datafn_corr_r <= UInt<32>("h00")
wire lsu_ld_datafn_m : UInt<32>
lsu_ld_datafn_m <= UInt<32>("h00")
node _T_123 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 208:50]
node _T_124 = mux(_T_123, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 208:26]
io.lsu_pkt_d.bits.store_data_bypass_m <= _T_124.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_124.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.bits.store_data_bypass_d <= _T_124.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.bits.dma <= _T_124.bits.dma @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.bits.unsign <= _T_124.bits.unsign @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.bits.store <= _T_124.bits.store @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.bits.load <= _T_124.bits.load @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.bits.dword <= _T_124.bits.dword @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.bits.word <= _T_124.bits.word @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.bits.half <= _T_124.bits.half @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.bits.by <= _T_124.bits.by @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.bits.stack <= _T_124.bits.stack @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.bits.fast_int <= _T_124.bits.fast_int @[lsu_lsc_ctl.scala 208:20]
io.lsu_pkt_d.valid <= _T_124.valid @[lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 210:20]
node _T_125 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:64]
node _T_126 = and(io.flush_m_up, _T_125) @[lsu_lsc_ctl.scala 212:61]
node _T_127 = eq(_T_126, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:45]
node _T_128 = and(io.lsu_p.valid, _T_127) @[lsu_lsc_ctl.scala 212:43]
node _T_129 = or(_T_128, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 212:90]
io.lsu_pkt_d.valid <= _T_129 @[lsu_lsc_ctl.scala 212:24]
node _T_130 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:68]
node _T_131 = and(io.flush_m_up, _T_130) @[lsu_lsc_ctl.scala 213:65]
node _T_132 = eq(_T_131, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:49]
node _T_133 = and(io.lsu_pkt_d.valid, _T_132) @[lsu_lsc_ctl.scala 213:47]
lsu_pkt_m_in.valid <= _T_133 @[lsu_lsc_ctl.scala 213:24]
node _T_134 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68]
node _T_135 = and(io.flush_m_up, _T_134) @[lsu_lsc_ctl.scala 214:65]
node _T_136 = eq(_T_135, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49]
node _T_137 = and(io.lsu_pkt_m.valid, _T_136) @[lsu_lsc_ctl.scala 214:47]
lsu_pkt_r_in.valid <= _T_137 @[lsu_lsc_ctl.scala 214:24]
wire _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
_T_138.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
reg _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_138)) @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 216:65]
_T_139.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 216:65]
_T_139.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 216:65]
io.lsu_pkt_m.bits.store_data_bypass_m <= _T_139.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_139.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.bits.store_data_bypass_d <= _T_139.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.bits.dma <= _T_139.bits.dma @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.bits.unsign <= _T_139.bits.unsign @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.bits.store <= _T_139.bits.store @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.bits.load <= _T_139.bits.load @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.bits.dword <= _T_139.bits.dword @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.bits.word <= _T_139.bits.word @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.bits.half <= _T_139.bits.half @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.bits.by <= _T_139.bits.by @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.bits.stack <= _T_139.bits.stack @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.bits.fast_int <= _T_139.bits.fast_int @[lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_m.valid <= _T_139.valid @[lsu_lsc_ctl.scala 216:28]
wire _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_140.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
reg _T_141 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_140)) @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 217:65]
_T_141.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65]
_T_141.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 217:65]
io.lsu_pkt_r.bits.store_data_bypass_m <= _T_141.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_141.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.bits.store_data_bypass_d <= _T_141.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.bits.dma <= _T_141.bits.dma @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.bits.unsign <= _T_141.bits.unsign @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.bits.store <= _T_141.bits.store @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.bits.load <= _T_141.bits.load @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.bits.dword <= _T_141.bits.dword @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.bits.word <= _T_141.bits.word @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.bits.half <= _T_141.bits.half @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.bits.by <= _T_141.bits.by @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.bits.stack <= _T_141.bits.stack @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.bits.fast_int <= _T_141.bits.fast_int @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_r.valid <= _T_141.valid @[lsu_lsc_ctl.scala 217:28]
reg _T_142 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 218:65]
_T_142 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 218:65]
io.lsu_pkt_m.valid <= _T_142 @[lsu_lsc_ctl.scala 218:28]
reg _T_143 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65]
_T_143 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 219:65]
io.lsu_pkt_r.valid <= _T_143 @[lsu_lsc_ctl.scala 219:28]
node _T_144 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 221:59]
node _T_145 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 221:100]
node _T_146 = cat(_T_145, UInt<3>("h00")) @[Cat.scala 29:58]
node dma_mem_wdata_shifted = dshr(_T_144, _T_146) @[lsu_lsc_ctl.scala 221:66]
node _T_147 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 222:63]
node _T_148 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 222:91]
node _T_149 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 222:122]
node store_data_d = mux(_T_147, _T_148, _T_149) @[lsu_lsc_ctl.scala 222:34]
node _T_150 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 223:73]
node _T_151 = bits(io.lsu_exu.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:103]
node _T_152 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:122]
node store_data_m_in = mux(_T_150, _T_151, _T_152) @[lsu_lsc_ctl.scala 223:34]
node _T_153 = bits(io.lsu_addr_d, 2, 2) @[lsu_lsc_ctl.scala 225:61]
reg _T_154 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:47]
_T_154 <= _T_153 @[lsu_lsc_ctl.scala 225:47]
node _T_155 = bits(io.end_addr_d, 2, 2) @[lsu_lsc_ctl.scala 225:123]
reg _T_156 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:109]
_T_156 <= _T_155 @[lsu_lsc_ctl.scala 225:109]
node int = neq(_T_154, _T_156) @[lsu_lsc_ctl.scala 225:71]
node _T_157 = bits(io.lsu_addr_m, 2, 2) @[lsu_lsc_ctl.scala 226:62]
reg _T_158 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:48]
_T_158 <= _T_157 @[lsu_lsc_ctl.scala 226:48]
node _T_159 = bits(io.end_addr_m, 2, 2) @[lsu_lsc_ctl.scala 226:124]
reg _T_160 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:110]
_T_160 <= _T_159 @[lsu_lsc_ctl.scala 226:110]
node int1 = neq(_T_158, _T_160) @[lsu_lsc_ctl.scala 226:72]
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:72]
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 229:72]
reg _T_161 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:62]
_T_161 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 230:62]
io.lsu_addr_m <= _T_161 @[lsu_lsc_ctl.scala 230:24]
reg _T_162 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 231:62]
_T_162 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 231:62]
io.lsu_addr_r <= _T_162 @[lsu_lsc_ctl.scala 231:24]
node _T_163 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:60]
node _T_164 = mux(int, end_addr_pre_m, _T_163) @[lsu_lsc_ctl.scala 232:27]
node _T_165 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 232:117]
reg _T_166 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:103]
_T_166 <= _T_165 @[lsu_lsc_ctl.scala 232:103]
node _T_167 = cat(_T_164, _T_166) @[Cat.scala 29:58]
io.end_addr_m <= _T_167 @[lsu_lsc_ctl.scala 232:17]
node _T_168 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 233:61]
node _T_169 = mux(int1, end_addr_pre_r, _T_168) @[lsu_lsc_ctl.scala 233:27]
node _T_170 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 233:118]
reg _T_171 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:104]
_T_171 <= _T_170 @[lsu_lsc_ctl.scala 233:104]
node _T_172 = cat(_T_169, _T_171) @[Cat.scala 29:58]
io.end_addr_r <= _T_172 @[lsu_lsc_ctl.scala 233:17]
node _T_173 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 234:41]
node _T_174 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 234:69]
node _T_175 = or(_T_174, io.clk_override) @[lsu_lsc_ctl.scala 234:87]
node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 406:18]
rvclkhdr_1.io.en <= _T_175 @[lib.scala 407:17]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
reg _T_177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_175 : @[Reg.scala 28:19]
_T_177 <= _T_173 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
end_addr_pre_m <= _T_177 @[lsu_lsc_ctl.scala 234:18]
node _T_178 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 235:41]
node _T_179 = and(io.lsu_pkt_m.valid, int) @[lsu_lsc_ctl.scala 235:69]
node _T_180 = or(_T_179, io.clk_override) @[lsu_lsc_ctl.scala 235:76]
node _T_181 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 406:18]
rvclkhdr_2.io.en <= _T_180 @[lib.scala 407:17]
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
reg _T_182 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_180 : @[Reg.scala 28:19]
_T_182 <= _T_178 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
end_addr_pre_r <= _T_182 @[lsu_lsc_ctl.scala 235:18]
reg _T_183 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
_T_183 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 236:62]
io.addr_in_dccm_m <= _T_183 @[lsu_lsc_ctl.scala 236:24]
reg _T_184 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62]
_T_184 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 237:62]
io.addr_in_dccm_r <= _T_184 @[lsu_lsc_ctl.scala 237:24]
reg _T_185 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:62]
_T_185 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 238:62]
io.addr_in_pic_m <= _T_185 @[lsu_lsc_ctl.scala 238:24]
reg _T_186 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 239:62]
_T_186 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 239:62]
io.addr_in_pic_r <= _T_186 @[lsu_lsc_ctl.scala 239:24]
reg _T_187 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 240:62]
_T_187 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 240:62]
io.addr_external_m <= _T_187 @[lsu_lsc_ctl.scala 240:24]
reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 241:66]
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 241:66]
node _T_188 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 242:77]
node _T_189 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[lib.scala 406:18]
rvclkhdr_3.io.en <= _T_188 @[lib.scala 407:17]
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
reg bus_read_data_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_188 : @[Reg.scala 28:19]
bus_read_data_r <= io.bus_read_data_m @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
node _T_190 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 245:52]
io.lsu_fir_addr <= _T_190 @[lsu_lsc_ctl.scala 245:28]
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 247:28]
node _T_191 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 249:68]
node _T_192 = and(io.lsu_pkt_r.valid, _T_191) @[lsu_lsc_ctl.scala 249:41]
node _T_193 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 249:96]
node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 249:94]
node _T_195 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 249:110]
node _T_196 = and(_T_194, _T_195) @[lsu_lsc_ctl.scala 249:108]
io.lsu_commit_r <= _T_196 @[lsu_lsc_ctl.scala 249:19]
node _T_197 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 250:52]
node _T_198 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 250:69]
node _T_199 = bits(_T_198, 0, 0) @[Bitwise.scala 72:15]
node _T_200 = mux(_T_199, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_201 = or(_T_197, _T_200) @[lsu_lsc_ctl.scala 250:59]
node _T_202 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 250:133]
node _T_203 = mux(_T_202, io.lsu_exu.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 250:94]
node _T_204 = and(_T_201, _T_203) @[lsu_lsc_ctl.scala 250:89]
io.store_data_m <= _T_204 @[lsu_lsc_ctl.scala 250:29]
node _T_205 = mux(io.addr_external_m, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 271:33]
lsu_ld_datafn_m <= _T_205 @[lsu_lsc_ctl.scala 271:27]
node _T_206 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 272:49]
node _T_207 = mux(_T_206, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 272:33]
lsu_ld_datafn_corr_r <= _T_207 @[lsu_lsc_ctl.scala 272:27]
node _T_208 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 273:74]
node _T_209 = bits(_T_208, 0, 0) @[Bitwise.scala 72:15]
node _T_210 = mux(_T_209, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_211 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 273:133]
node _T_212 = cat(UInt<24>("h00"), _T_211) @[Cat.scala 29:58]
node _T_213 = and(_T_210, _T_212) @[lsu_lsc_ctl.scala 273:102]
node _T_214 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 274:43]
node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 72:15]
node _T_216 = mux(_T_215, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_217 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 274:102]
node _T_218 = cat(UInt<16>("h00"), _T_217) @[Cat.scala 29:58]
node _T_219 = and(_T_216, _T_218) @[lsu_lsc_ctl.scala 274:71]
node _T_220 = or(_T_213, _T_219) @[lsu_lsc_ctl.scala 273:141]
node _T_221 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 275:17]
node _T_222 = and(_T_221, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 275:43]
node _T_223 = bits(_T_222, 0, 0) @[Bitwise.scala 72:15]
node _T_224 = mux(_T_223, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_225 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 275:102]
node _T_226 = bits(_T_225, 0, 0) @[Bitwise.scala 72:15]
node _T_227 = mux(_T_226, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_228 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 275:125]
node _T_229 = cat(_T_227, _T_228) @[Cat.scala 29:58]
node _T_230 = and(_T_224, _T_229) @[lsu_lsc_ctl.scala 275:71]
node _T_231 = or(_T_220, _T_230) @[lsu_lsc_ctl.scala 274:114]
node _T_232 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 276:17]
node _T_233 = and(_T_232, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 276:43]
node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 72:15]
node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_236 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 276:101]
node _T_237 = bits(_T_236, 0, 0) @[Bitwise.scala 72:15]
node _T_238 = mux(_T_237, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_239 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 276:125]
node _T_240 = cat(_T_238, _T_239) @[Cat.scala 29:58]
node _T_241 = and(_T_235, _T_240) @[lsu_lsc_ctl.scala 276:71]
node _T_242 = or(_T_231, _T_241) @[lsu_lsc_ctl.scala 275:134]
node _T_243 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_244 = mux(_T_243, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_245 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 277:60]
node _T_246 = and(_T_244, _T_245) @[lsu_lsc_ctl.scala 277:43]
node _T_247 = or(_T_242, _T_246) @[lsu_lsc_ctl.scala 276:134]
io.lsu_exu.lsu_result_m <= _T_247 @[lsu_lsc_ctl.scala 273:35]
node _T_248 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 278:66]
node _T_249 = bits(_T_248, 0, 0) @[Bitwise.scala 72:15]
node _T_250 = mux(_T_249, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_251 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 278:130]
node _T_252 = cat(UInt<24>("h00"), _T_251) @[Cat.scala 29:58]
node _T_253 = and(_T_250, _T_252) @[lsu_lsc_ctl.scala 278:94]
node _T_254 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 279:43]
node _T_255 = bits(_T_254, 0, 0) @[Bitwise.scala 72:15]
node _T_256 = mux(_T_255, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_257 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 279:107]
node _T_258 = cat(UInt<16>("h00"), _T_257) @[Cat.scala 29:58]
node _T_259 = and(_T_256, _T_258) @[lsu_lsc_ctl.scala 279:71]
node _T_260 = or(_T_253, _T_259) @[lsu_lsc_ctl.scala 278:138]
node _T_261 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 280:17]
node _T_262 = and(_T_261, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 280:43]
node _T_263 = bits(_T_262, 0, 0) @[Bitwise.scala 72:15]
node _T_264 = mux(_T_263, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 280:107]
node _T_266 = bits(_T_265, 0, 0) @[Bitwise.scala 72:15]
node _T_267 = mux(_T_266, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_268 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 280:135]
node _T_269 = cat(_T_267, _T_268) @[Cat.scala 29:58]
node _T_270 = and(_T_264, _T_269) @[lsu_lsc_ctl.scala 280:71]
node _T_271 = or(_T_260, _T_270) @[lsu_lsc_ctl.scala 279:119]
node _T_272 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 281:17]
node _T_273 = and(_T_272, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 281:43]
node _T_274 = bits(_T_273, 0, 0) @[Bitwise.scala 72:15]
node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 281:106]
node _T_277 = bits(_T_276, 0, 0) @[Bitwise.scala 72:15]
node _T_278 = mux(_T_277, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_279 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 281:135]
node _T_280 = cat(_T_278, _T_279) @[Cat.scala 29:58]
node _T_281 = and(_T_275, _T_280) @[lsu_lsc_ctl.scala 281:71]
node _T_282 = or(_T_271, _T_281) @[lsu_lsc_ctl.scala 280:144]
node _T_283 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_284 = mux(_T_283, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_285 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 282:65]
node _T_286 = and(_T_284, _T_285) @[lsu_lsc_ctl.scala 282:43]
node _T_287 = or(_T_282, _T_286) @[lsu_lsc_ctl.scala 281:144]
io.lsu_result_corr_r <= _T_287 @[lsu_lsc_ctl.scala 278:27]

1500
lsu_lsc_ctl.v Normal file
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File diff suppressed because it is too large Load Diff

5
src/main/scala/exu/exu.scala
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@ -22,6 +22,7 @@ class exu extends Module with lib with RequireAsyncReset{
//debug //debug
val dbg_cmd_wrdata = Input(UInt(32.W)) // Debug data to primary I0 RS1 val dbg_cmd_wrdata = Input(UInt(32.W)) // Debug data to primary I0 RS1
val dec_csr_rddata_d = Input(UInt(32.W)) val dec_csr_rddata_d = Input(UInt(32.W))
val lsu_nonblock_load_data = Input(UInt(32.W))
//lsu //lsu
val lsu_exu = Flipped(new lsu_exu()) val lsu_exu = Flipped(new lsu_exu())
//ifu_ifc //ifu_ifc
@ -86,13 +87,13 @@ class exu extends Module with lib with RequireAsyncReset{
io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_result_r, io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_result_r,
io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(1).asBool -> io.lsu_exu.lsu_result_m, io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(1).asBool -> io.lsu_exu.lsu_result_m,
io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(2).asBool -> io.dec_exu.decode_exu.exu_i0_result_x, io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(2).asBool -> io.dec_exu.decode_exu.exu_i0_result_x,
io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(3).asBool -> io.lsu_exu.lsu_nonblock_load_data io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(3).asBool -> io.lsu_nonblock_load_data
)) ))
val i0_rs2_bypass_data_d = Mux1H(Seq( val i0_rs2_bypass_data_d = Mux1H(Seq(
io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_result_r, io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_result_r,
io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(1).asBool -> io.lsu_exu.lsu_result_m, io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(1).asBool -> io.lsu_exu.lsu_result_m,
io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(2).asBool -> io.dec_exu.decode_exu.exu_i0_result_x, io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(2).asBool -> io.dec_exu.decode_exu.exu_i0_result_x,
io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(3).asBool -> io.lsu_exu.lsu_nonblock_load_data io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(3).asBool -> io.lsu_nonblock_load_data
)) ))
val i0_rs1_d = Mux1H(Seq( val i0_rs1_d = Mux1H(Seq(

3
src/main/scala/include/bundle.scala
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@ -176,8 +176,7 @@ class lsu_exu extends Bundle{
val exu_lsu_rs1_d = Input(UInt(32.W)) val exu_lsu_rs1_d = Input(UInt(32.W))
val exu_lsu_rs2_d = Input(UInt(32.W)) val exu_lsu_rs2_d = Input(UInt(32.W))
val lsu_result_m = Output(UInt(32.W)) val lsu_result_m = Output(UInt(32.W))
val lsu_nonblock_load_data = Output(UInt(32.W)) //val lsu_nonblock_load_data = Output(UInt(32.W))
} }
class lsu_dec extends Bundle { class lsu_dec extends Bundle {
val tlu_busbuff = new tlu_busbuff val tlu_busbuff = new tlu_busbuff

703
src/main/scala/lsu/lsu.scala
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@ -1,358 +1,359 @@
//package lsu package lsu
//
//import lib._ import lib._
//import chisel3._ import chisel3._
//import chisel3.util._ import chisel3.util._
//import include._ import include._
//import mem._ import mem._
//
//class lsu extends Module with RequireAsyncReset with param with lib { class lsu extends Module with RequireAsyncReset with param with lib {
// val io = IO (new Bundle { val io = IO (new Bundle {
// val clk_override = Input(Bool()) val clk_override = Input(Bool())
// val lsu_dma = new lsu_dma val lsu_dma = new lsu_dma
// val lsu_pic = new lsu_pic val lsu_pic = new lsu_pic
// val lsu_exu = new lsu_exu val lsu_exu = new lsu_exu
// val lsu_dec = new lsu_dec val lsu_dec = new lsu_dec
// val dccm = Flipped(new mem_lsu) val dccm = Flipped(new mem_lsu)
// val lsu_tlu = new lsu_tlu val lsu_tlu = new lsu_tlu
// val axi = new axi_channels(LSU_BUS_TAG) val axi = new axi_channels(LSU_BUS_TAG)
//
// val dec_tlu_flush_lower_r = Input(Bool()) val dec_tlu_flush_lower_r = Input(Bool())
// val dec_tlu_i0_kill_writeb_r = Input(Bool()) val dec_tlu_i0_kill_writeb_r = Input(Bool())
// val dec_tlu_force_halt = Input(Bool()) val dec_tlu_force_halt = Input(Bool())
//
// val dec_tlu_core_ecc_disable = Input(Bool()) val dec_tlu_core_ecc_disable = Input(Bool())
//
// val dec_lsu_offset_d = Input(UInt(12.W)) val dec_lsu_offset_d = Input(UInt(12.W))
// val lsu_p = Flipped(Valid(new lsu_pkt_t())) val lsu_p = Flipped(Valid(new lsu_pkt_t()))
// val trigger_pkt_any = Input(Vec(4, new trigger_pkt_t())) val trigger_pkt_any = Input(Vec(4, new trigger_pkt_t()))
//
// val dec_lsu_valid_raw_d = Input(Bool()) val dec_lsu_valid_raw_d = Input(Bool())
// val dec_tlu_mrac_ff = Input(UInt(32.W)) val dec_tlu_mrac_ff = Input(UInt(32.W))
//
// //Outputs //Outputs
// val lsu_result_m = Output(UInt(32.W)) // val lsu_result_m = Output(UInt(32.W))
// val lsu_result_corr_r = Output(UInt(32.W)) val lsu_result_corr_r = Output(UInt(32.W))
// val lsu_load_stall_any = Output(Bool()) val lsu_load_stall_any = Output(Bool())
// val lsu_store_stall_any = Output(Bool()) val lsu_store_stall_any = Output(Bool())
// val lsu_fastint_stall_any = Output(Bool()) val lsu_fastint_stall_any = Output(Bool())
// val lsu_idle_any = Output(Bool()) val lsu_idle_any = Output(Bool())
// val lsu_active = Output(Bool()) val lsu_active = Output(Bool())
// val lsu_fir_addr = Output(UInt(31.W)) val lsu_fir_addr = Output(UInt(31.W))
// val lsu_fir_error = Output(UInt(2.W)) val lsu_fir_error = Output(UInt(2.W))
// val lsu_single_ecc_error_incr = Output(Bool()) val lsu_single_ecc_error_incr = Output(Bool())
// val lsu_error_pkt_r = Valid(new lsu_error_pkt_t()) val lsu_error_pkt_r = Valid(new lsu_error_pkt_t())
// val lsu_pmu_misaligned_m = Output(Bool()) val lsu_pmu_misaligned_m = Output(Bool())
// val lsu_trigger_match_m = Output(UInt(4.W)) val lsu_trigger_match_m = Output(UInt(4.W))
//
// val lsu_bus_clk_en = Input(Bool()) val lsu_bus_clk_en = Input(Bool())
// val scan_mode = Input(Bool())
// val scan_mode = Input(Bool()) val active_clk = Input(Clock())
// val active_clk = Input(Clock()) val lsu_nonblock_load_data = Output(UInt(32.W))
// })
// }) val dma_dccm_wdata = WireInit(0.U(64.W))
// val dma_dccm_wdata = WireInit(0.U(64.W)) val dma_dccm_wdata_lo = WireInit(0.U(32.W))
// val dma_dccm_wdata_lo = WireInit(0.U(32.W)) val dma_dccm_wdata_hi = WireInit(0.U(32.W))
// val dma_dccm_wdata_hi = WireInit(0.U(32.W)) val dma_mem_tag_m = WireInit(0.U(3.W))
// val dma_mem_tag_m = WireInit(0.U(3.W)) val lsu_raw_fwd_lo_r = WireInit(0.U(1.W))
// val lsu_raw_fwd_lo_r = WireInit(0.U(1.W)) val lsu_raw_fwd_hi_r = WireInit(0.U(1.W))
// val lsu_raw_fwd_hi_r = WireInit(0.U(1.W)) val lsu_busm_clken = WireInit(0.U(1.W))
// val lsu_busm_clken = WireInit(0.U(1.W)) val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W))
// val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W))
// val lsu_addr_d = WireInit(0.U(32.W)) // val lsu_addr_d = WireInit(0.U(32.W))
// val lsu_addr_m = WireInit(0.U(32.W)) // val lsu_addr_m = WireInit(0.U(32.W))
// val lsu_addr_r = WireInit(0.U(32.W)) // val lsu_addr_r = WireInit(0.U(32.W))
// val end_addr_d = WireInit(0.U(32.W)) // val end_addr_d = WireInit(0.U(32.W))
// val end_addr_m = WireInit(0.U(32.W)) // val end_addr_m = WireInit(0.U(32.W))
// val end_addr_r = WireInit(0.U(32.W)) // val end_addr_r = WireInit(0.U(32.W))
// val lsu_busreq_r = WireInit(Bool(),false.B) val lsu_busreq_r = WireInit(Bool(),false.B)
// // val ldst_dual_d = WireInit(Bool(),false.B)
// val lsu_lsc_ctl = Module(new lsu_lsc_ctl()) // val ldst_dual_m = WireInit(Bool(),false.B)
// io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m // val ldst_dual_r = WireInit(Bool(),false.B)
// io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r
// val dccm_ctl = Module(new lsu_dccm_ctl()) val lsu_lsc_ctl = Module(new lsu_lsc_ctl())
// val stbuf = Module(new lsu_stbuf()) // io.lsu_exu.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m
// val ecc = Module(new lsu_ecc()) // io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data
// val trigger = Module(new lsu_trigger()) io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r
// val clkdomain = Module(new lsu_clkdomain()) val dccm_ctl = Module(new lsu_dccm_ctl())
// val bus_intf = Module(new lsu_bus_intf()) val stbuf = Module(new lsu_stbuf())
// val ecc = Module(new lsu_ecc())
// val lsu_raw_fwd_lo_m = stbuf.io.stbuf_fwdbyteen_lo_m.orR val trigger = Module(new lsu_trigger())
// val lsu_raw_fwd_hi_m = stbuf.io.stbuf_fwdbyteen_hi_m.orR val clkdomain = Module(new lsu_clkdomain())
// val bus_intf = Module(new lsu_bus_intf())
// // block stores in decode - for either bus or stbuf reasons
// io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff val lsu_raw_fwd_lo_m = stbuf.io.stbuf_fwdbyteen_lo_m.orR
// io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff val lsu_raw_fwd_hi_m = stbuf.io.stbuf_fwdbyteen_hi_m.orR
// io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage
// // block stores in decode - for either bus or stbuf reasons
// // Ready to accept dma trxns io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff
// // There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff
// val dma_mem_tag_d = io.lsu_dma.dma_mem_tag io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage
// val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store
// io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff) // Ready to accept dma trxns
// val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1) // There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m
// val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d val dma_mem_tag_d = io.lsu_dma.dma_mem_tag
// dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store
// dma_dccm_wdata_hi := dma_dccm_wdata(63,32) io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff)
// dma_dccm_wdata_lo := dma_dccm_wdata(31,0) val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1)
// val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d
// val flush_m_up = io.dec_tlu_flush_lower_r dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
// val flush_r = io.dec_tlu_i0_kill_writeb_r dma_dccm_wdata_hi := dma_dccm_wdata(63,32)
// dma_dccm_wdata_lo := dma_dccm_wdata(31,0)
// // lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence.
// // Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error val flush_m_up = io.dec_tlu_flush_lower_r
// // Store buffer now have only non-dma dccm stores val flush_r = io.dec_tlu_i0_kill_writeb_r
// // stbuf_empty not needed since it has only dccm stores
// // lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence.
// io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any // Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error
// io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock // Store buffer now have only non-dma dccm stores
// // Instantiate the store buffer // stbuf_empty not needed since it has only dccm stores
// val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & (!lsu_lsc_ctl.io.lsu_pkt_r.bits.dma | ((lsu_lsc_ctl.io.lsu_pkt_r.bits.by | lsu_lsc_ctl.io.lsu_pkt_r.bits.half) & !ecc.io.lsu_double_ecc_error_r)) io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any
// // Disable Forwarding for now io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock
// val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) // Instantiate the store buffer
// // Bus signals val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & (!lsu_lsc_ctl.io.lsu_pkt_r.bits.dma | ((lsu_lsc_ctl.io.lsu_pkt_r.bits.by | lsu_lsc_ctl.io.lsu_pkt_r.bits.half) & !ecc.io.lsu_double_ecc_error_r))
// val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int // Disable Forwarding for now
// // Dual signals val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m)
// val ldst_dual_d = lsu_addr_d(2) =/= end_addr_d(2) // Bus signals
// val ldst_dual_m = lsu_addr_m(2) =/= end_addr_m(2) val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int
// val ldst_dual_r = lsu_addr_r(2) =/= end_addr_r(2) // Dual signals
// // PMU signals
// io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR)) // PMU signals
// io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR))
// io.lsu_tlu.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m
// io.lsu_tlu.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m
// //LSU_LSC_Control
// //Inputs //LSU_LSC_Control
// lsu_lsc_ctl.io.clk_override := io.clk_override //Inputs
// lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk lsu_lsc_ctl.io.clk_override := io.clk_override
// lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk
// lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
// lsu_lsc_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk
// lsu_lsc_ctl.io.lsu_store_c1_m_clk := clkdomain.io.lsu_store_c1_m_clk lsu_lsc_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
// lsu_lsc_ctl.io.lsu_ld_data_r := dccm_ctl.io.lsu_ld_data_r lsu_lsc_ctl.io.lsu_store_c1_m_clk := clkdomain.io.lsu_store_c1_m_clk
// lsu_lsc_ctl.io.lsu_ld_data_corr_r := dccm_ctl.io.lsu_ld_data_corr_r lsu_lsc_ctl.io.lsu_ld_data_r := dccm_ctl.io.lsu_ld_data_r
// lsu_lsc_ctl.io.lsu_single_ecc_error_r := ecc.io.lsu_single_ecc_error_r lsu_lsc_ctl.io.lsu_ld_data_corr_r := dccm_ctl.io.lsu_ld_data_corr_r
// lsu_lsc_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r lsu_lsc_ctl.io.lsu_single_ecc_error_r := ecc.io.lsu_single_ecc_error_r
// lsu_lsc_ctl.io.lsu_ld_data_m := dccm_ctl.io.lsu_ld_data_m lsu_lsc_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r
// lsu_lsc_ctl.io.lsu_single_ecc_error_m := ecc.io.lsu_single_ecc_error_m lsu_lsc_ctl.io.lsu_ld_data_m := dccm_ctl.io.lsu_ld_data_m
// lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m lsu_lsc_ctl.io.lsu_single_ecc_error_m := ecc.io.lsu_single_ecc_error_m
// lsu_lsc_ctl.io.flush_m_up := flush_m_up lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m
// lsu_lsc_ctl.io.flush_r := flush_r lsu_lsc_ctl.io.flush_m_up := flush_m_up
// lsu_lsc_ctl.io.ldst_dual_d := ldst_dual_d lsu_lsc_ctl.io.flush_r := flush_r
// lsu_lsc_ctl.io.ldst_dual_m := ldst_dual_m lsu_lsc_ctl.io.ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2)
// lsu_lsc_ctl.io.ldst_dual_r := ldst_dual_r lsu_lsc_ctl.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2)
// lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu lsu_lsc_ctl.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
// lsu_lsc_ctl.io.lsu_p <> io.lsu_p lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu
// lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d lsu_lsc_ctl.io.lsu_p <> io.lsu_p
// lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
// lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d
// lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m
// lsu_lsc_ctl.io.dma_lsc_ctl <> io.lsu_dma.dma_lsc_ctl lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m
// lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff lsu_lsc_ctl.io.dma_lsc_ctl <> io.lsu_dma.dma_lsc_ctl
// lsu_lsc_ctl.io.scan_mode := io.scan_mode lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff
// //Outputs lsu_lsc_ctl.io.scan_mode := io.scan_mode
// lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d //Outputs
// lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
// lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
// end_addr_d := lsu_lsc_ctl.io.lsu_addr_d // ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2)
// end_addr_m := lsu_lsc_ctl.io.lsu_addr_m // ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2)
// end_addr_r := lsu_lsc_ctl.io.lsu_addr_r // ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
// io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr
// io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr
// io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r
// io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr
// // DCCM Control io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error
// //Inputs // DCCM Control
// dccm_ctl.io.clk_override := io.clk_override //Inputs
// dccm_ctl.io.ldst_dual_m := ldst_dual_m dccm_ctl.io.clk_override := io.clk_override
// dccm_ctl.io.ldst_dual_r := ldst_dual_r dccm_ctl.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2)
// dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk dccm_ctl.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
// dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk
// dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
// dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
// dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_store_c1_r_clk dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
// dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_store_c1_r_clk
// dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d
// dccm_ctl.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
// dccm_ctl.io.addr_in_dccm_d := lsu_lsc_ctl.io.addr_in_dccm_d dccm_ctl.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
// dccm_ctl.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m dccm_ctl.io.addr_in_dccm_d := lsu_lsc_ctl.io.addr_in_dccm_d
// dccm_ctl.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r dccm_ctl.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
// dccm_ctl.io.addr_in_pic_d := lsu_lsc_ctl.io.addr_in_pic_d dccm_ctl.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
// dccm_ctl.io.addr_in_pic_m := lsu_lsc_ctl.io.addr_in_pic_m dccm_ctl.io.addr_in_pic_d := lsu_lsc_ctl.io.addr_in_pic_d
// dccm_ctl.io.addr_in_pic_r := lsu_lsc_ctl.io.addr_in_pic_r dccm_ctl.io.addr_in_pic_m := lsu_lsc_ctl.io.addr_in_pic_m
// dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r dccm_ctl.io.addr_in_pic_r := lsu_lsc_ctl.io.addr_in_pic_r
// dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r
// dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r
// dccm_ctl.io.lsu_addr_d := lsu_addr_d dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
// dccm_ctl.io.lsu_addr_m := lsu_addr_m(DCCM_BITS-1,0) dccm_ctl.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d
// dccm_ctl.io.lsu_addr_r := lsu_addr_r dccm_ctl.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m(DCCM_BITS-1,0)
// dccm_ctl.io.end_addr_d := end_addr_d(DCCM_BITS-1,0) dccm_ctl.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
// dccm_ctl.io.end_addr_m := end_addr_m(DCCM_BITS-1,0) dccm_ctl.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d(DCCM_BITS-1,0)
// dccm_ctl.io.end_addr_r := end_addr_r(DCCM_BITS-1,0) dccm_ctl.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m(DCCM_BITS-1,0)
// dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any dccm_ctl.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r(DCCM_BITS-1,0)
// dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any
// dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any
// dccm_ctl.io.stbuf_ecc_any := ecc.io.stbuf_ecc_any dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any
// dccm_ctl.io.stbuf_fwddata_hi_m := stbuf.io.stbuf_fwddata_hi_m dccm_ctl.io.stbuf_ecc_any := ecc.io.stbuf_ecc_any
// dccm_ctl.io.stbuf_fwddata_lo_m := stbuf.io.stbuf_fwddata_lo_m dccm_ctl.io.stbuf_fwddata_hi_m := stbuf.io.stbuf_fwddata_hi_m
// dccm_ctl.io.stbuf_fwdbyteen_lo_m := stbuf.io.stbuf_fwdbyteen_lo_m dccm_ctl.io.stbuf_fwddata_lo_m := stbuf.io.stbuf_fwddata_lo_m
// dccm_ctl.io.stbuf_fwdbyteen_hi_m := stbuf.io.stbuf_fwdbyteen_hi_m dccm_ctl.io.stbuf_fwdbyteen_lo_m := stbuf.io.stbuf_fwdbyteen_lo_m
// dccm_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r dccm_ctl.io.stbuf_fwdbyteen_hi_m := stbuf.io.stbuf_fwdbyteen_hi_m
// dccm_ctl.io.single_ecc_error_hi_r := ecc.io.single_ecc_error_hi_r dccm_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r
// dccm_ctl.io.single_ecc_error_lo_r := ecc.io.single_ecc_error_lo_r dccm_ctl.io.single_ecc_error_hi_r := ecc.io.single_ecc_error_hi_r
// dccm_ctl.io.sec_data_hi_r := ecc.io.sec_data_hi_r dccm_ctl.io.single_ecc_error_lo_r := ecc.io.single_ecc_error_lo_r
// dccm_ctl.io.sec_data_lo_r := ecc.io.sec_data_lo_r dccm_ctl.io.sec_data_hi_r := ecc.io.sec_data_hi_r
// dccm_ctl.io.sec_data_hi_r_ff := ecc.io.sec_data_hi_r_ff dccm_ctl.io.sec_data_lo_r := ecc.io.sec_data_lo_r
// dccm_ctl.io.sec_data_lo_r_ff := ecc.io.sec_data_lo_r_ff dccm_ctl.io.sec_data_hi_r_ff := ecc.io.sec_data_hi_r_ff
// dccm_ctl.io.sec_data_ecc_hi_r_ff := ecc.io.sec_data_ecc_hi_r_ff dccm_ctl.io.sec_data_lo_r_ff := ecc.io.sec_data_lo_r_ff
// dccm_ctl.io.sec_data_ecc_lo_r_ff := ecc.io.sec_data_ecc_lo_r_ff dccm_ctl.io.sec_data_ecc_hi_r_ff := ecc.io.sec_data_ecc_hi_r_ff
// dccm_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m dccm_ctl.io.sec_data_ecc_lo_r_ff := ecc.io.sec_data_ecc_lo_r_ff
// dccm_ctl.io.sec_data_hi_m := ecc.io.sec_data_hi_m dccm_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m
// dccm_ctl.io.sec_data_lo_m := ecc.io.sec_data_lo_m dccm_ctl.io.sec_data_hi_m := ecc.io.sec_data_hi_m
// dccm_ctl.io.store_data_m := lsu_lsc_ctl.io.store_data_m dccm_ctl.io.sec_data_lo_m := ecc.io.sec_data_lo_m
// dccm_ctl.io.dma_dccm_wen := dma_dccm_wen dccm_ctl.io.store_data_m := lsu_lsc_ctl.io.store_data_m
// dccm_ctl.io.dma_pic_wen := dma_pic_wen dccm_ctl.io.dma_dccm_wen := dma_dccm_wen
// dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m dccm_ctl.io.dma_pic_wen := dma_pic_wen
// dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m
// dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo
// dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi
// dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi
// dccm_ctl.io.scan_mode := io.scan_mode dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo
// //Outputs dccm_ctl.io.scan_mode := io.scan_mode
// io.lsu_dma.dma_dccm_ctl <> dccm_ctl.io.dma_dccm_ctl //Outputs
// io.dccm <> dccm_ctl.io.dccm io.lsu_dma.dma_dccm_ctl <> dccm_ctl.io.dma_dccm_ctl
// io.lsu_pic <> dccm_ctl.io.lsu_pic io.dccm <> dccm_ctl.io.dccm
// //Store Buffer io.lsu_pic <> dccm_ctl.io.lsu_pic
// //Inputs //Store Buffer
// stbuf.io.ldst_dual_d := ldst_dual_d //Inputs
// stbuf.io.ldst_dual_m := ldst_dual_m stbuf.io.ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2)
// stbuf.io.ldst_dual_r := ldst_dual_r stbuf.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2)
// stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk stbuf.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
// stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk
// stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
// stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
// stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
// stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r
// stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
// stbuf.io.store_data_hi_r := dccm_ctl.io.store_data_hi_r stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
// stbuf.io.store_data_lo_r := dccm_ctl.io.store_data_lo_r stbuf.io.store_data_hi_r := dccm_ctl.io.store_data_hi_r
// stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r stbuf.io.store_data_lo_r := dccm_ctl.io.store_data_lo_r
// stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r
// stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r
// stbuf.io.lsu_addr_d := lsu_addr_d stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any
// stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m stbuf.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d
// stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
// stbuf.io.end_addr_d := end_addr_d stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
// stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m stbuf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d
// stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
// stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
// stbuf.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
// stbuf.io.lsu_cmpen_m := lsu_cmpen_m stbuf.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
// stbuf.io.scan_mode := io.scan_mode stbuf.io.lsu_cmpen_m := lsu_cmpen_m
// stbuf.io.scan_mode := io.scan_mode
// // ECC
// //Inputs // ECC
// ecc.io.clk_override := io.clk_override //Inputs
// ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk ecc.io.clk_override := io.clk_override
// ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
// ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
// ecc.io.stbuf_data_any := stbuf.io.stbuf_data_any ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
// ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable ecc.io.stbuf_data_any := stbuf.io.stbuf_data_any
// ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable
// ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r
// ecc.io.lsu_addr_r := lsu_addr_r ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
// ecc.io.end_addr_r := end_addr_r ecc.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
// ecc.io.lsu_addr_m := lsu_addr_m ecc.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
// ecc.io.end_addr_m := end_addr_m ecc.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
// ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r ecc.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
// ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r
// ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r
// ecc.io.dccm_rdata_lo_m := dccm_ctl.io.dccm_rdata_lo_m ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m
// ecc.io.dccm_data_ecc_hi_r := dccm_ctl.io.dccm_data_ecc_hi_r ecc.io.dccm_rdata_lo_m := dccm_ctl.io.dccm_rdata_lo_m
// ecc.io.dccm_data_ecc_lo_r := dccm_ctl.io.dccm_data_ecc_lo_r ecc.io.dccm_data_ecc_hi_r := dccm_ctl.io.dccm_data_ecc_hi_r
// ecc.io.dccm_data_ecc_hi_m := dccm_ctl.io.dccm_data_ecc_hi_m ecc.io.dccm_data_ecc_lo_r := dccm_ctl.io.dccm_data_ecc_lo_r
// ecc.io.dccm_data_ecc_lo_m := dccm_ctl.io.dccm_data_ecc_lo_m ecc.io.dccm_data_ecc_hi_m := dccm_ctl.io.dccm_data_ecc_hi_m
// ecc.io.ld_single_ecc_error_r := dccm_ctl.io.ld_single_ecc_error_r ecc.io.dccm_data_ecc_lo_m := dccm_ctl.io.dccm_data_ecc_lo_m
// ecc.io.ld_single_ecc_error_r_ff := dccm_ctl.io.ld_single_ecc_error_r_ff ecc.io.ld_single_ecc_error_r := dccm_ctl.io.ld_single_ecc_error_r
// ecc.io.lsu_dccm_rden_m := dccm_ctl.io.lsu_dccm_rden_m ecc.io.ld_single_ecc_error_r_ff := dccm_ctl.io.ld_single_ecc_error_r_ff
// ecc.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m ecc.io.lsu_dccm_rden_m := dccm_ctl.io.lsu_dccm_rden_m
// ecc.io.dma_dccm_wen := dma_dccm_wen ecc.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
// ecc.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo ecc.io.dma_dccm_wen := dma_dccm_wen
// ecc.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi ecc.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo
// ecc.io.scan_mode := io.scan_mode ecc.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi
// ecc.io.scan_mode := io.scan_mode
// //Trigger
// //Inputs //Trigger
// trigger.io.trigger_pkt_any <> io.trigger_pkt_any //Inputs
// trigger.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m trigger.io.trigger_pkt_any <> io.trigger_pkt_any
// trigger.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m trigger.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
// trigger.io.store_data_m := lsu_lsc_ctl.io.store_data_m trigger.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
// //Outputs trigger.io.store_data_m := lsu_lsc_ctl.io.store_data_m
// io.lsu_trigger_match_m :=trigger.io.lsu_trigger_match_m //Outputs
// io.lsu_trigger_match_m :=trigger.io.lsu_trigger_match_m
// //Clock Domain
// //Inputs //Clock Domain
// clkdomain.io.active_clk := io.active_clk //Inputs
// clkdomain.io.clk_override := io.clk_override clkdomain.io.active_clk := io.active_clk
// clkdomain.io.dec_tlu_force_halt := io.dec_tlu_force_halt clkdomain.io.clk_override := io.clk_override
// clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req clkdomain.io.dec_tlu_force_halt := io.dec_tlu_force_halt
// clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req
// clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r
// clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any
// clkdomain.io.lsu_busreq_r := bus_intf.io.lsu_busreq_r clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any
// clkdomain.io.lsu_bus_buffer_pend_any := bus_intf.io.lsu_bus_buffer_pend_any clkdomain.io.lsu_busreq_r := bus_intf.io.lsu_busreq_r
// clkdomain.io.lsu_bus_buffer_empty_any := bus_intf.io.lsu_bus_buffer_empty_any clkdomain.io.lsu_bus_buffer_pend_any := bus_intf.io.lsu_bus_buffer_pend_any
// clkdomain.io.lsu_stbuf_empty_any := stbuf.io.lsu_stbuf_empty_any clkdomain.io.lsu_bus_buffer_empty_any := bus_intf.io.lsu_bus_buffer_empty_any
// clkdomain.io.lsu_bus_clk_en := io.lsu_bus_clk_en clkdomain.io.lsu_stbuf_empty_any := stbuf.io.lsu_stbuf_empty_any
// clkdomain.io.lsu_p := io.lsu_p clkdomain.io.lsu_bus_clk_en := io.lsu_bus_clk_en
// clkdomain.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d clkdomain.io.lsu_p := io.lsu_p
// clkdomain.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m clkdomain.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d
// clkdomain.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r clkdomain.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
// clkdomain.io.scan_mode := io.scan_mode clkdomain.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
// clkdomain.io.scan_mode := io.scan_mode
// //Bus Interface
// //Inputs //Bus Interface
// bus_intf.io.scan_mode := io.scan_mode //Inputs
// io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff bus_intf.io.scan_mode := io.scan_mode
// bus_intf.io.clk_override := io.clk_override io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff
// bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk bus_intf.io.clk_override := io.clk_override
// bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
// bus_intf.io.lsu_busm_clken := lsu_busm_clken bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
// bus_intf.io.lsu_bus_obuf_c1_clken := lsu_bus_obuf_c1_clken bus_intf.io.lsu_busm_clken := lsu_busm_clken
// bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk bus_intf.io.lsu_bus_obuf_c1_clken := lsu_bus_obuf_c1_clken
// bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk
// bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk
// bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk
// bus_intf.io.active_clk := io.active_clk bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
// bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk bus_intf.io.active_clk := io.active_clk
// bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk
// bus_intf.io.lsu_busreq_m := lsu_busreq_m bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
// bus_intf.io.ldst_dual_d := ldst_dual_d bus_intf.io.lsu_busreq_m := lsu_busreq_m
// bus_intf.io.ldst_dual_m := ldst_dual_m bus_intf.io.ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2)
// bus_intf.io.ldst_dual_r := ldst_dual_r bus_intf.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2)
// bus_intf.io.lsu_addr_m := lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) bus_intf.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
// bus_intf.io.lsu_addr_r := lsu_addr_r & Fill(32,lsu_busreq_r) bus_intf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid)
// bus_intf.io.end_addr_m := end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) bus_intf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r & Fill(32,lsu_busreq_r)
// bus_intf.io.end_addr_r := end_addr_r & Fill(32,lsu_busreq_r) bus_intf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid)
// bus_intf.io.store_data_r := dccm_ctl.io.store_data_r & Fill(32,lsu_busreq_r) bus_intf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r & Fill(32,lsu_busreq_r)
// bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m bus_intf.io.store_data_r := dccm_ctl.io.store_data_r & Fill(32,lsu_busreq_r)
// bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
// bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
// bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt
// bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
// bus_intf.io.flush_m_up := flush_m_up bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m
// bus_intf.io.flush_r := flush_r bus_intf.io.flush_m_up := flush_m_up
// //Outputs bus_intf.io.flush_r := flush_r
// io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff //Outputs
// lsu_busreq_r := bus_intf.io.lsu_busreq_r io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff
// io.axi <> bus_intf.io.axi io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data
// bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en lsu_busreq_r := bus_intf.io.lsu_busreq_r
// io.axi <> bus_intf.io.axi
// withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)} bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en
// withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)}
// withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)} withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)}
// withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)}
//} withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)}
//object lsu_main extends App {
// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu())) }
//} object lsu_main extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu()))
}

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src/main/scala/lsu/lsu_bus_buffer.scala
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406
src/main/scala/lsu/lsu_bus_intf.scala
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@ -1,205 +1,205 @@
//package lsu package lsu
//import chisel3._ import chisel3._
//import chisel3.util._ import chisel3.util._
//import lib._ import lib._
//import include._ import include._
class lsu_bus_intf extends Module with RequireAsyncReset with lib {
val io = IO (new Bundle {
val scan_mode = Input(Bool())
val clk_override = Input(Bool())
val tlu_busbuff = new tlu_busbuff()
val lsu_bus_obuf_c1_clken = Input(Bool())// obuf clock enable
val lsu_busm_clken = Input(Bool())
val lsu_c1_r_clk = Input(Clock())
val lsu_c2_r_clk = Input(Clock())
val lsu_bus_ibuf_c1_clk = Input(Clock())
val lsu_bus_obuf_c1_clk = Input(Clock())
val lsu_bus_buf_c1_clk = Input(Clock())
val lsu_free_c2_clk = Input(Clock())
val active_clk = Input(Clock())
val lsu_busm_clk = Input(Clock())
val axi = new axi_channels(LSU_BUS_TAG)
val dec_lsu_valid_raw_d = Input(Bool())
val lsu_busreq_m = Input(Bool())
val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t()))
val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t()))
val lsu_addr_m = Input(UInt(32.W))
val lsu_addr_r = Input(UInt(32.W))
val end_addr_m = Input(UInt(32.W))
val end_addr_r = Input(UInt(32.W))
val ldst_dual_d = Input(Bool())
val ldst_dual_m = Input(Bool())
val ldst_dual_r = Input(Bool())
val store_data_r = Input(UInt(32.W))
val dec_tlu_force_halt = Input(Bool())
val lsu_commit_r = Input(Bool())
val is_sideeffects_m = Input(Bool())
val flush_m_up = Input(Bool())
val flush_r = Input(Bool())
val lsu_busreq_r = Output(Bool())
val lsu_bus_buffer_pend_any = Output(Bool())
val lsu_bus_buffer_full_any = Output(Bool())
val lsu_bus_buffer_empty_any = Output(Bool())
//val lsu_bus_idle_any = Output(Bool())
val bus_read_data_m = Output(UInt(32.W))
val lsu_nonblock_load_data = Output((UInt(32.W)))
val dctl_busbuff = new dctl_busbuff()
val lsu_bus_clk_en = Input(Bool())
})
val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B)
val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U)
val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U)
val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U)
val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U)
val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U)
val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U)
val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U)
val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U)
val is_sideeffects_r = WireInit(Bool(), init = false.B)
val store_data_ext_r = WireInit(UInt(64.W), init = 0.U)
val store_data_hi_r = WireInit(UInt(32.W), init = 0.U)
val store_data_lo_r = WireInit(UInt(32.W), init = 0.U)
val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B)
val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B)
val no_word_merge_r = WireInit(Bool(), init = false.B)
val no_dword_merge_r = WireInit(Bool(), init = false.B)
val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B)
val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B)
val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B)
val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B)
val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U)
val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U)
val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U)
val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U)
val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U)
val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U)
val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U)
val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U)
val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U)
val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U)
val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U)
val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U)
val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U)
val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U)
val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U)
val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U)
val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U)
val ld_full_hit_hi_m = WireInit(Bool(), init = true.B)
val ld_full_hit_lo_m = WireInit(Bool(), init = true.B)
val ld_full_hit_m = WireInit(Bool(), init = false.B)
val bus_buffer = Module(new lsu_bus_buffer)
bus_buffer.io.scan_mode := io.scan_mode
io.tlu_busbuff <> bus_buffer.io.tlu_busbuff
bus_buffer.io.clk_override := io.clk_override
bus_buffer.io.lsu_bus_obuf_c1_clken := io.lsu_bus_obuf_c1_clken
bus_buffer.io.lsu_busm_clken := io.lsu_busm_clken
bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt
bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk
bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk
bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk
bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk
bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk
bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk
bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
// //
//class lsu_bus_intf extends Module with RequireAsyncReset with lib { bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m
// val io = IO (new Bundle { bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r
// val scan_mode = Input(Bool())
// val clk_override = Input(Bool())
// val tlu_busbuff = new tlu_busbuff()
// val lsu_bus_obuf_c1_clken = Input(Bool())// obuf clock enable
// val lsu_busm_clken = Input(Bool())
// val lsu_c1_r_clk = Input(Clock())
// val lsu_c2_r_clk = Input(Clock())
// val lsu_bus_ibuf_c1_clk = Input(Clock())
// val lsu_bus_obuf_c1_clk = Input(Clock())
// val lsu_bus_buf_c1_clk = Input(Clock())
// val lsu_free_c2_clk = Input(Clock())
// val active_clk = Input(Clock())
// val lsu_busm_clk = Input(Clock())
// val axi = new axi_channels(LSU_BUS_TAG)
// val dec_lsu_valid_raw_d = Input(Bool())
// val lsu_busreq_m = Input(Bool())
// //
// val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t()))
// val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) bus_buffer.io.lsu_addr_m := io.lsu_addr_m
// bus_buffer.io.end_addr_m := io.end_addr_m
// val lsu_addr_m = Input(UInt(32.W)) bus_buffer.io.lsu_addr_r := io.lsu_addr_r
// val lsu_addr_r = Input(UInt(32.W)) bus_buffer.io.end_addr_r := io.end_addr_r
// bus_buffer.io.store_data_r := io.store_data_r
// val end_addr_m = Input(UInt(32.W))
// val end_addr_r = Input(UInt(32.W)) bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m
// val ldst_dual_d = Input(Bool()) bus_buffer.io.flush_m_up := io.flush_m_up
// val ldst_dual_m = Input(Bool()) bus_buffer.io.flush_r := io.flush_r
// val ldst_dual_r = Input(Bool()) bus_buffer.io.lsu_commit_r := io.lsu_commit_r
// bus_buffer.io.lsu_axi <> io.axi
// val store_data_r = Input(UInt(32.W)) bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en
// val dec_tlu_force_halt = Input(Bool()) io.lsu_nonblock_load_data := bus_buffer.io.lsu_nonblock_load_data
// io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r
// val lsu_commit_r = Input(Bool()) io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any
// val is_sideeffects_m = Input(Bool()) io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any
// val flush_m_up = Input(Bool()) io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any
// val flush_r = Input(Bool()) //io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any
// ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo
// val lsu_busreq_r = Output(Bool()) ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi
// val lsu_bus_buffer_pend_any = Output(Bool()) ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo
// val lsu_bus_buffer_full_any = Output(Bool()) ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi
// val lsu_bus_buffer_empty_any = Output(Bool()) io.dctl_busbuff <> bus_buffer.io.dctl_busbuff
// //val lsu_bus_idle_any = Output(Bool()) bus_buffer.io.no_word_merge_r := no_word_merge_r
// val bus_read_data_m = Output(UInt(32.W)) bus_buffer.io.no_dword_merge_r := no_dword_merge_r
// bus_buffer.io.is_sideeffects_r := is_sideeffects_r
// val dctl_busbuff = new dctl_busbuff() bus_buffer.io.ldst_dual_d := io.ldst_dual_d
// bus_buffer.io.ldst_dual_m := io.ldst_dual_m
// val lsu_bus_clk_en = Input(Bool()) bus_buffer.io.ldst_dual_r := io.ldst_dual_r
// }) bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m
// bus_buffer.io.ld_full_hit_m := ld_full_hit_m
// val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B) bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q
// val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U)
// val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U) ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W)))
// val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U) addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3))
// val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U) addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2))
// val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U) no_word_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m)
// val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U) no_dword_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m)
// val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U)
// val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U) ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0)
// val is_sideeffects_r = WireInit(Bool(), init = false.B) ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0)
// val store_data_ext_r = WireInit(UInt(64.W), init = 0.U) store_data_ext_r := io.store_data_r(31,0) << Cat(io.lsu_addr_r(1,0),0.U(3.W))
// val store_data_hi_r = WireInit(UInt(32.W), init = 0.U) ldst_byteen_hi_m := ldst_byteen_ext_m(7,4)
// val store_data_lo_r = WireInit(UInt(32.W), init = 0.U) ldst_byteen_lo_m := ldst_byteen_ext_m(3,0)
// val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B) ldst_byteen_hi_r := ldst_byteen_ext_r(7,4)
// val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B) ldst_byteen_lo_r := ldst_byteen_ext_r(3,0)
// val no_word_merge_r = WireInit(Bool(), init = false.B)
// val no_dword_merge_r = WireInit(Bool(), init = false.B) store_data_hi_r := store_data_ext_r(63,32)
// val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B) store_data_lo_r := store_data_ext_r(31,0)
// val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B) ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
// val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B) ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
// val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B) ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
// val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U) ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
// val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U)
// val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U) ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_))
// val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U) ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_))
// val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U) ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_))
// val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U) ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_))
// val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U)
// val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U) ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_))
// val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U) ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_))
// val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U) ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_))
// val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U) ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_))
// val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U) ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_))
// val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U) ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_))
// val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U) ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
// val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U) ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
// val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U) ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_)
// val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U) ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_)
// val ld_full_hit_hi_m = WireInit(Bool(), init = true.B) ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.bits.load & !io.is_sideeffects_m
// val ld_full_hit_lo_m = WireInit(Bool(), init = true.B) ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0))
// val ld_full_hit_m = WireInit(Bool(), init = false.B) io.bus_read_data_m := ld_fwddata_m(31,0)
//
// val bus_buffer = Module(new lsu_bus_buffer) withClock(io.active_clk) {
// lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U)
// bus_buffer.io.scan_mode := io.scan_mode }
// io.tlu_busbuff <> bus_buffer.io.tlu_busbuff
// bus_buffer.io.clk_override := io.clk_override withClock(io.lsu_c1_r_clk) {
// bus_buffer.io.lsu_bus_obuf_c1_clken := io.lsu_bus_obuf_c1_clken is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U)
// bus_buffer.io.lsu_busm_clken := io.lsu_busm_clken ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W))
// bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt }
// bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk }
// bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk object bus_intf extends App {
// bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf()))
// bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk }
// bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk
// bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk
// bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
//
// //
// bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m
// bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r
// //
//
// bus_buffer.io.lsu_addr_m := io.lsu_addr_m
// bus_buffer.io.end_addr_m := io.end_addr_m
// bus_buffer.io.lsu_addr_r := io.lsu_addr_r
// bus_buffer.io.end_addr_r := io.end_addr_r
// bus_buffer.io.store_data_r := io.store_data_r
//
// bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m
// bus_buffer.io.flush_m_up := io.flush_m_up
// bus_buffer.io.flush_r := io.flush_r
// bus_buffer.io.lsu_commit_r := io.lsu_commit_r
// bus_buffer.io.lsu_axi <> io.axi
// bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en
//
// io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r
// io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any
// io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any
// io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any
// //io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any
// ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo
// ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi
// ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo
// ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi
// io.dctl_busbuff <> bus_buffer.io.dctl_busbuff
// bus_buffer.io.no_word_merge_r := no_word_merge_r
// bus_buffer.io.no_dword_merge_r := no_dword_merge_r
// bus_buffer.io.is_sideeffects_r := is_sideeffects_r
// bus_buffer.io.ldst_dual_d := io.ldst_dual_d
// bus_buffer.io.ldst_dual_m := io.ldst_dual_m
// bus_buffer.io.ldst_dual_r := io.ldst_dual_r
// bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m
// bus_buffer.io.ld_full_hit_m := ld_full_hit_m
// bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q
//
// ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W)))
// addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3))
// addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2))
// no_word_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m)
// no_dword_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m)
//
// ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0)
// ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0)
// store_data_ext_r := io.store_data_r(31,0) << Cat(io.lsu_addr_r(1,0),0.U(3.W))
// ldst_byteen_hi_m := ldst_byteen_ext_m(7,4)
// ldst_byteen_lo_m := ldst_byteen_ext_m(3,0)
// ldst_byteen_hi_r := ldst_byteen_ext_r(7,4)
// ldst_byteen_lo_r := ldst_byteen_ext_r(3,0)
//
// store_data_hi_r := store_data_ext_r(63,32)
// store_data_lo_r := store_data_ext_r(31,0)
// ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
// ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
// ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
// ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
//
// ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_))
// ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_))
// ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_))
// ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_))
//
// ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_))
// ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_))
// ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_))
// ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_))
// ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_))
// ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_))
// ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
// ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
// ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_)
// ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_)
// ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.bits.load & !io.is_sideeffects_m
// ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0))
// io.bus_read_data_m := ld_fwddata_m(31,0)
//
// withClock(io.active_clk) {
// lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U)
// }
//
// withClock(io.lsu_c1_r_clk) {
// is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U)
// ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W))
// }
//}
//object bus_intf extends App {
// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf()))
//}

27
src/main/scala/lsu/lsu_lsc_ctl.scala
View File

@ -26,9 +26,9 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
val flush_m_up = Input(UInt(1.W)) val flush_m_up = Input(UInt(1.W))
val flush_r = Input(UInt(1.W)) val flush_r = Input(UInt(1.W))
val ldst_dual_d = Input(UInt(1.W)) val ldst_dual_d = Input(Bool())
val ldst_dual_m = Input(UInt(1.W)) val ldst_dual_m = Input(Bool())
val ldst_dual_r = Input(UInt(1.W)) val ldst_dual_r = Input(Bool())
val lsu_exu = new lsu_exu() val lsu_exu = new lsu_exu()
@ -39,7 +39,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
val picm_mask_data_m = Input(UInt(32.W)) val picm_mask_data_m = Input(UInt(32.W))
val bus_read_data_m = Input(UInt(32.W)) //coming from bus interface val bus_read_data_m = Input(UInt(32.W)) //coming from bus interface
val lsu_result_m = Output(UInt(32.W)) // val lsu_result_m = Output(UInt(32.W))
val lsu_result_corr_r = Output(UInt(32.W)) // This is the ECC corrected data going to RF val lsu_result_corr_r = Output(UInt(32.W)) // This is the ECC corrected data going to RF
// lsu address down the pipe // lsu address down the pipe
@ -100,7 +100,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
val lsu_offset_d = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d) val lsu_offset_d = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d)
val rs1_d_raw = lsu_rs1_d val rs1_d_raw = lsu_rs1_d
val offset_d = lsu_offset_d val offset_d = lsu_offset_d
val rs1_d = Mux(io.lsu_pkt_d.bits.load_ldst_bypass_d.asBool,io.lsu_result_m,rs1_d_raw) val rs1_d = Mux(io.lsu_pkt_d.bits.load_ldst_bypass_d.asBool,io.lsu_exu.lsu_result_m,rs1_d_raw)
// generate the ls address // generate the ls address
val full_addr_d = rvlsadder(rs1_d,offset_d) val full_addr_d = rvlsadder(rs1_d,offset_d)
@ -220,15 +220,16 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
val dma_mem_wdata_shifted = io.dma_lsc_ctl.dma_mem_wdata(63,0) >> Cat(io.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores val dma_mem_wdata_shifted = io.dma_lsc_ctl.dma_mem_wdata(63,0) >> Cat(io.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
val store_data_d = Mux(io.dma_lsc_ctl.dma_dccm_req.asBool,dma_mem_wdata_shifted(31,0),io.lsu_exu.exu_lsu_rs2_d(31,0)) // Write to PIC still happens in r stage val store_data_d = Mux(io.dma_lsc_ctl.dma_dccm_req.asBool,dma_mem_wdata_shifted(31,0),io.lsu_exu.exu_lsu_rs2_d(31,0)) // Write to PIC still happens in r stage
val store_data_m_in = Mux(io.lsu_pkt_d.bits.store_data_bypass_d.asBool,io.lsu_result_m(31,0),store_data_d(31,0)) val store_data_m_in = Mux(io.lsu_pkt_d.bits.store_data_bypass_d.asBool,io.lsu_exu.lsu_result_m(31,0),store_data_d(31,0))
val int = withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d(2),0.U)} =/= withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2),0.U)}
val int1 = withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m(2),0.U)} =/= withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2),0.U)}
val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)} val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)}
io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)} io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)}
io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)} io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)}
io.end_addr_m := Cat(Mux(io.ldst_dual_m,end_addr_pre_m,io.lsu_addr_m(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2,0),0.U)}) io.end_addr_m := Cat(Mux(int,end_addr_pre_m,io.lsu_addr_m(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2,0),0.U)})
io.end_addr_r := Cat(Mux(io.ldst_dual_r,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2,0),0.U)}) io.end_addr_r := Cat(Mux(int1,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2,0),0.U)})
end_addr_pre_m := rvdffe(io.end_addr_d(31,3),((io.lsu_pkt_d.valid & io.ldst_dual_d) | io.clk_override),clock,io.scan_mode) end_addr_pre_m := rvdffe(io.end_addr_d(31,3),((io.lsu_pkt_d.valid & io.ldst_dual_d) | io.clk_override),clock,io.scan_mode)
end_addr_pre_r := rvdffe(io.end_addr_m(31,3),((io.lsu_pkt_m.valid & io.ldst_dual_m) | io.clk_override),clock,io.scan_mode) end_addr_pre_r := rvdffe(io.end_addr_m(31,3),((io.lsu_pkt_m.valid & int) | io.clk_override),clock,io.scan_mode)
io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)} io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)}
io.addr_in_dccm_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_dccm_m,0.U)} io.addr_in_dccm_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_dccm_m,0.U)}
io.addr_in_pic_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_pic_d,0.U)} io.addr_in_pic_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_pic_d,0.U)}
@ -243,14 +244,14 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
io.lsu_addr_d := full_addr_d io.lsu_addr_d := full_addr_d
// Interrupt as a flush source allows the WB to occur // Interrupt as a flush source allows the WB to occur
io.lsu_commit_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.bits.store | io.lsu_pkt_r.bits.load) & !io.flush_r & !io.lsu_pkt_r.bits.dma io.lsu_commit_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.bits.store | io.lsu_pkt_r.bits.load) & !io.flush_r & !io.lsu_pkt_r.bits.dma
io.store_data_m := (io.picm_mask_data_m(31,0) | Fill(32,!io.addr_in_pic_m)) & Mux(io.lsu_pkt_m.bits.store_data_bypass_m.asBool,io.lsu_result_m,store_data_pre_m) io.store_data_m := (io.picm_mask_data_m(31,0) | Fill(32,!io.addr_in_pic_m)) & Mux(io.lsu_pkt_m.bits.store_data_bypass_m.asBool,io.lsu_exu.lsu_result_m,store_data_pre_m)
if (LOAD_TO_USE_PLUS1 == 1){ if (LOAD_TO_USE_PLUS1 == 1){
//bus_read_data_r coming from bus interface, lsu_ld_data_r -> coming from dccm_ctl //bus_read_data_r coming from bus interface, lsu_ld_data_r -> coming from dccm_ctl
lsu_ld_datafn_r := Mux(addr_external_r, bus_read_data_r,io.lsu_ld_data_r) lsu_ld_datafn_r := Mux(addr_external_r, bus_read_data_r,io.lsu_ld_data_r)
lsu_ld_datafn_corr_r := Mux(addr_external_r, bus_read_data_r,io.lsu_ld_data_corr_r) lsu_ld_datafn_corr_r := Mux(addr_external_r, bus_read_data_r,io.lsu_ld_data_corr_r)
// this is really R stage but don't want to make all the changes to support M,R buses // this is really R stage but don't want to make all the changes to support M,R buses
io.lsu_result_m := ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) | io.lsu_exu.lsu_result_m := ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) |
((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_r(15,0))) | ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_r(15,0))) |
((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat((Fill(24, lsu_ld_datafn_r(7))) ,lsu_ld_datafn_r(7,0))) | ((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat((Fill(24, lsu_ld_datafn_r(7))) ,lsu_ld_datafn_r(7,0))) |
((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat((Fill(16,lsu_ld_datafn_r(15))) ,lsu_ld_datafn_r(15,0))) | ((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat((Fill(16,lsu_ld_datafn_r(15))) ,lsu_ld_datafn_r(15,0))) |
@ -266,7 +267,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
else { else {
lsu_ld_datafn_m := Mux(io.addr_external_m, io.bus_read_data_m,io.lsu_ld_data_m) lsu_ld_datafn_m := Mux(io.addr_external_m, io.bus_read_data_m,io.lsu_ld_data_m)
lsu_ld_datafn_corr_r := Mux(addr_external_r===1.U, bus_read_data_r,io.lsu_ld_data_corr_r) lsu_ld_datafn_corr_r := Mux(addr_external_r===1.U, bus_read_data_r,io.lsu_ld_data_corr_r)
io.lsu_result_m := ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) | io.lsu_exu.lsu_result_m := ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) |
((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_m(15,0))) | ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_m(15,0))) |
((Fill(32,!io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat((Fill(24, lsu_ld_datafn_m(7))) ,lsu_ld_datafn_m(7,0))) | ((Fill(32,!io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat((Fill(24, lsu_ld_datafn_m(7))) ,lsu_ld_datafn_m(7,0))) |
((Fill(32,!io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.half)) & Cat((Fill(16,lsu_ld_datafn_m(15))) ,lsu_ld_datafn_m(15,0))) | ((Fill(32,!io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.half)) & Cat((Fill(16,lsu_ld_datafn_m(15))) ,lsu_ld_datafn_m(15,0))) |

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