adding I$

EL2_IC_DATA.fir

@@ -3041,9 +3041,582 @@ circuit EL2_IC_DATA :
     node _T_1602 = and(_T_1601, _T_1458) @[el2_lib.scala 189:94]
     node _T_1603 = or(_T_1530, _T_1602) @[el2_lib.scala 189:110]
     io.ic_debug_rd_data <= _T_1603 @[el2_ifu_ic_mem.scala 284:23]
-    io.test_port2 <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 286:17]
+    node _T_1604 = bits(ic_rd_hit_q, 0, 0) @[el2_ifu_ic_mem.scala 286:76]
-    io.test_port[0][0] <= wb_dout[0][0] @[el2_ifu_ic_mem.scala 287:16]
+    node _T_1605 = bits(ic_rd_hit_q, 1, 1) @[el2_ifu_ic_mem.scala 286:76]
-    io.test_port[0][1] <= wb_dout[0][1] @[el2_ifu_ic_mem.scala 287:16]
+    wire _T_1606 : UInt<1>[142] @[el2_lib.scala 187:48]
-    io.test_port[1][0] <= wb_dout[1][0] @[el2_ifu_ic_mem.scala 287:16]
+    _T_1606[0] <= _T_1604 @[el2_lib.scala 187:48]
-    io.test_port[1][1] <= wb_dout[1][1] @[el2_ifu_ic_mem.scala 287:16]
+    _T_1606[1] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[2] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[3] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[4] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[5] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[6] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[7] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[8] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[9] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[10] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[11] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[12] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[13] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[14] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[15] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[16] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[17] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[18] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[19] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[20] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[21] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[22] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[23] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[24] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[25] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[26] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[27] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[28] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[29] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[30] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[31] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[32] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[33] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[34] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[35] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[36] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[37] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[38] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[39] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[40] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[41] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[42] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[43] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[44] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[45] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[46] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[47] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[48] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[49] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[50] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[51] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[52] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[53] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[54] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[55] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[56] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[57] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[58] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[59] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[60] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[61] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[62] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[63] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[64] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[65] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[66] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[67] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[68] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[69] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[70] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[71] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[72] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[73] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[74] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[75] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[76] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[77] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[78] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[79] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[80] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[81] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[82] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[83] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[84] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[85] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[86] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[87] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[88] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[89] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[90] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[91] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[92] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[93] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[94] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[95] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[96] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[97] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[98] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[99] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[100] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[101] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[102] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[103] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[104] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[105] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[106] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[107] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[108] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[109] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[110] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[111] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[112] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[113] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[114] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[115] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[116] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[117] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[118] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[119] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[120] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[121] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[122] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[123] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[124] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[125] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[126] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[127] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[128] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[129] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[130] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[131] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[132] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[133] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[134] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[135] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[136] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[137] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[138] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[139] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[140] <= _T_1604 @[el2_lib.scala 187:48]
+    _T_1606[141] <= _T_1604 @[el2_lib.scala 187:48]
+    node _T_1607 = cat(_T_1606[0], _T_1606[1]) @[Cat.scala 29:58]
+    node _T_1608 = cat(_T_1607, _T_1606[2]) @[Cat.scala 29:58]
+    node _T_1609 = cat(_T_1608, _T_1606[3]) @[Cat.scala 29:58]
+    node _T_1610 = cat(_T_1609, _T_1606[4]) @[Cat.scala 29:58]
+    node _T_1611 = cat(_T_1610, _T_1606[5]) @[Cat.scala 29:58]
+    node _T_1612 = cat(_T_1611, _T_1606[6]) @[Cat.scala 29:58]
+    node _T_1613 = cat(_T_1612, _T_1606[7]) @[Cat.scala 29:58]
+    node _T_1614 = cat(_T_1613, _T_1606[8]) @[Cat.scala 29:58]
+    node _T_1615 = cat(_T_1614, _T_1606[9]) @[Cat.scala 29:58]
+    node _T_1616 = cat(_T_1615, _T_1606[10]) @[Cat.scala 29:58]
+    node _T_1617 = cat(_T_1616, _T_1606[11]) @[Cat.scala 29:58]
+    node _T_1618 = cat(_T_1617, _T_1606[12]) @[Cat.scala 29:58]
+    node _T_1619 = cat(_T_1618, _T_1606[13]) @[Cat.scala 29:58]
+    node _T_1620 = cat(_T_1619, _T_1606[14]) @[Cat.scala 29:58]
+    node _T_1621 = cat(_T_1620, _T_1606[15]) @[Cat.scala 29:58]
+    node _T_1622 = cat(_T_1621, _T_1606[16]) @[Cat.scala 29:58]
+    node _T_1623 = cat(_T_1622, _T_1606[17]) @[Cat.scala 29:58]
+    node _T_1624 = cat(_T_1623, _T_1606[18]) @[Cat.scala 29:58]
+    node _T_1625 = cat(_T_1624, _T_1606[19]) @[Cat.scala 29:58]
+    node _T_1626 = cat(_T_1625, _T_1606[20]) @[Cat.scala 29:58]
+    node _T_1627 = cat(_T_1626, _T_1606[21]) @[Cat.scala 29:58]
+    node _T_1628 = cat(_T_1627, _T_1606[22]) @[Cat.scala 29:58]
+    node _T_1629 = cat(_T_1628, _T_1606[23]) @[Cat.scala 29:58]
+    node _T_1630 = cat(_T_1629, _T_1606[24]) @[Cat.scala 29:58]
+    node _T_1631 = cat(_T_1630, _T_1606[25]) @[Cat.scala 29:58]
+    node _T_1632 = cat(_T_1631, _T_1606[26]) @[Cat.scala 29:58]
+    node _T_1633 = cat(_T_1632, _T_1606[27]) @[Cat.scala 29:58]
+    node _T_1634 = cat(_T_1633, _T_1606[28]) @[Cat.scala 29:58]
+    node _T_1635 = cat(_T_1634, _T_1606[29]) @[Cat.scala 29:58]
+    node _T_1636 = cat(_T_1635, _T_1606[30]) @[Cat.scala 29:58]
+    node _T_1637 = cat(_T_1636, _T_1606[31]) @[Cat.scala 29:58]
+    node _T_1638 = cat(_T_1637, _T_1606[32]) @[Cat.scala 29:58]
+    node _T_1639 = cat(_T_1638, _T_1606[33]) @[Cat.scala 29:58]
+    node _T_1640 = cat(_T_1639, _T_1606[34]) @[Cat.scala 29:58]
+    node _T_1641 = cat(_T_1640, _T_1606[35]) @[Cat.scala 29:58]
+    node _T_1642 = cat(_T_1641, _T_1606[36]) @[Cat.scala 29:58]
+    node _T_1643 = cat(_T_1642, _T_1606[37]) @[Cat.scala 29:58]
+    node _T_1644 = cat(_T_1643, _T_1606[38]) @[Cat.scala 29:58]
+    node _T_1645 = cat(_T_1644, _T_1606[39]) @[Cat.scala 29:58]
+    node _T_1646 = cat(_T_1645, _T_1606[40]) @[Cat.scala 29:58]
+    node _T_1647 = cat(_T_1646, _T_1606[41]) @[Cat.scala 29:58]
+    node _T_1648 = cat(_T_1647, _T_1606[42]) @[Cat.scala 29:58]
+    node _T_1649 = cat(_T_1648, _T_1606[43]) @[Cat.scala 29:58]
+    node _T_1650 = cat(_T_1649, _T_1606[44]) @[Cat.scala 29:58]
+    node _T_1651 = cat(_T_1650, _T_1606[45]) @[Cat.scala 29:58]
+    node _T_1652 = cat(_T_1651, _T_1606[46]) @[Cat.scala 29:58]
+    node _T_1653 = cat(_T_1652, _T_1606[47]) @[Cat.scala 29:58]
+    node _T_1654 = cat(_T_1653, _T_1606[48]) @[Cat.scala 29:58]
+    node _T_1655 = cat(_T_1654, _T_1606[49]) @[Cat.scala 29:58]
+    node _T_1656 = cat(_T_1655, _T_1606[50]) @[Cat.scala 29:58]
+    node _T_1657 = cat(_T_1656, _T_1606[51]) @[Cat.scala 29:58]
+    node _T_1658 = cat(_T_1657, _T_1606[52]) @[Cat.scala 29:58]
+    node _T_1659 = cat(_T_1658, _T_1606[53]) @[Cat.scala 29:58]
+    node _T_1660 = cat(_T_1659, _T_1606[54]) @[Cat.scala 29:58]
+    node _T_1661 = cat(_T_1660, _T_1606[55]) @[Cat.scala 29:58]
+    node _T_1662 = cat(_T_1661, _T_1606[56]) @[Cat.scala 29:58]
+    node _T_1663 = cat(_T_1662, _T_1606[57]) @[Cat.scala 29:58]
+    node _T_1664 = cat(_T_1663, _T_1606[58]) @[Cat.scala 29:58]
+    node _T_1665 = cat(_T_1664, _T_1606[59]) @[Cat.scala 29:58]
+    node _T_1666 = cat(_T_1665, _T_1606[60]) @[Cat.scala 29:58]
+    node _T_1667 = cat(_T_1666, _T_1606[61]) @[Cat.scala 29:58]
+    node _T_1668 = cat(_T_1667, _T_1606[62]) @[Cat.scala 29:58]
+    node _T_1669 = cat(_T_1668, _T_1606[63]) @[Cat.scala 29:58]
+    node _T_1670 = cat(_T_1669, _T_1606[64]) @[Cat.scala 29:58]
+    node _T_1671 = cat(_T_1670, _T_1606[65]) @[Cat.scala 29:58]
+    node _T_1672 = cat(_T_1671, _T_1606[66]) @[Cat.scala 29:58]
+    node _T_1673 = cat(_T_1672, _T_1606[67]) @[Cat.scala 29:58]
+    node _T_1674 = cat(_T_1673, _T_1606[68]) @[Cat.scala 29:58]
+    node _T_1675 = cat(_T_1674, _T_1606[69]) @[Cat.scala 29:58]
+    node _T_1676 = cat(_T_1675, _T_1606[70]) @[Cat.scala 29:58]
+    node _T_1677 = cat(_T_1676, _T_1606[71]) @[Cat.scala 29:58]
+    node _T_1678 = cat(_T_1677, _T_1606[72]) @[Cat.scala 29:58]
+    node _T_1679 = cat(_T_1678, _T_1606[73]) @[Cat.scala 29:58]
+    node _T_1680 = cat(_T_1679, _T_1606[74]) @[Cat.scala 29:58]
+    node _T_1681 = cat(_T_1680, _T_1606[75]) @[Cat.scala 29:58]
+    node _T_1682 = cat(_T_1681, _T_1606[76]) @[Cat.scala 29:58]
+    node _T_1683 = cat(_T_1682, _T_1606[77]) @[Cat.scala 29:58]
+    node _T_1684 = cat(_T_1683, _T_1606[78]) @[Cat.scala 29:58]
+    node _T_1685 = cat(_T_1684, _T_1606[79]) @[Cat.scala 29:58]
+    node _T_1686 = cat(_T_1685, _T_1606[80]) @[Cat.scala 29:58]
+    node _T_1687 = cat(_T_1686, _T_1606[81]) @[Cat.scala 29:58]
+    node _T_1688 = cat(_T_1687, _T_1606[82]) @[Cat.scala 29:58]
+    node _T_1689 = cat(_T_1688, _T_1606[83]) @[Cat.scala 29:58]
+    node _T_1690 = cat(_T_1689, _T_1606[84]) @[Cat.scala 29:58]
+    node _T_1691 = cat(_T_1690, _T_1606[85]) @[Cat.scala 29:58]
+    node _T_1692 = cat(_T_1691, _T_1606[86]) @[Cat.scala 29:58]
+    node _T_1693 = cat(_T_1692, _T_1606[87]) @[Cat.scala 29:58]
+    node _T_1694 = cat(_T_1693, _T_1606[88]) @[Cat.scala 29:58]
+    node _T_1695 = cat(_T_1694, _T_1606[89]) @[Cat.scala 29:58]
+    node _T_1696 = cat(_T_1695, _T_1606[90]) @[Cat.scala 29:58]
+    node _T_1697 = cat(_T_1696, _T_1606[91]) @[Cat.scala 29:58]
+    node _T_1698 = cat(_T_1697, _T_1606[92]) @[Cat.scala 29:58]
+    node _T_1699 = cat(_T_1698, _T_1606[93]) @[Cat.scala 29:58]
+    node _T_1700 = cat(_T_1699, _T_1606[94]) @[Cat.scala 29:58]
+    node _T_1701 = cat(_T_1700, _T_1606[95]) @[Cat.scala 29:58]
+    node _T_1702 = cat(_T_1701, _T_1606[96]) @[Cat.scala 29:58]
+    node _T_1703 = cat(_T_1702, _T_1606[97]) @[Cat.scala 29:58]
+    node _T_1704 = cat(_T_1703, _T_1606[98]) @[Cat.scala 29:58]
+    node _T_1705 = cat(_T_1704, _T_1606[99]) @[Cat.scala 29:58]
+    node _T_1706 = cat(_T_1705, _T_1606[100]) @[Cat.scala 29:58]
+    node _T_1707 = cat(_T_1706, _T_1606[101]) @[Cat.scala 29:58]
+    node _T_1708 = cat(_T_1707, _T_1606[102]) @[Cat.scala 29:58]
+    node _T_1709 = cat(_T_1708, _T_1606[103]) @[Cat.scala 29:58]
+    node _T_1710 = cat(_T_1709, _T_1606[104]) @[Cat.scala 29:58]
+    node _T_1711 = cat(_T_1710, _T_1606[105]) @[Cat.scala 29:58]
+    node _T_1712 = cat(_T_1711, _T_1606[106]) @[Cat.scala 29:58]
+    node _T_1713 = cat(_T_1712, _T_1606[107]) @[Cat.scala 29:58]
+    node _T_1714 = cat(_T_1713, _T_1606[108]) @[Cat.scala 29:58]
+    node _T_1715 = cat(_T_1714, _T_1606[109]) @[Cat.scala 29:58]
+    node _T_1716 = cat(_T_1715, _T_1606[110]) @[Cat.scala 29:58]
+    node _T_1717 = cat(_T_1716, _T_1606[111]) @[Cat.scala 29:58]
+    node _T_1718 = cat(_T_1717, _T_1606[112]) @[Cat.scala 29:58]
+    node _T_1719 = cat(_T_1718, _T_1606[113]) @[Cat.scala 29:58]
+    node _T_1720 = cat(_T_1719, _T_1606[114]) @[Cat.scala 29:58]
+    node _T_1721 = cat(_T_1720, _T_1606[115]) @[Cat.scala 29:58]
+    node _T_1722 = cat(_T_1721, _T_1606[116]) @[Cat.scala 29:58]
+    node _T_1723 = cat(_T_1722, _T_1606[117]) @[Cat.scala 29:58]
+    node _T_1724 = cat(_T_1723, _T_1606[118]) @[Cat.scala 29:58]
+    node _T_1725 = cat(_T_1724, _T_1606[119]) @[Cat.scala 29:58]
+    node _T_1726 = cat(_T_1725, _T_1606[120]) @[Cat.scala 29:58]
+    node _T_1727 = cat(_T_1726, _T_1606[121]) @[Cat.scala 29:58]
+    node _T_1728 = cat(_T_1727, _T_1606[122]) @[Cat.scala 29:58]
+    node _T_1729 = cat(_T_1728, _T_1606[123]) @[Cat.scala 29:58]
+    node _T_1730 = cat(_T_1729, _T_1606[124]) @[Cat.scala 29:58]
+    node _T_1731 = cat(_T_1730, _T_1606[125]) @[Cat.scala 29:58]
+    node _T_1732 = cat(_T_1731, _T_1606[126]) @[Cat.scala 29:58]
+    node _T_1733 = cat(_T_1732, _T_1606[127]) @[Cat.scala 29:58]
+    node _T_1734 = cat(_T_1733, _T_1606[128]) @[Cat.scala 29:58]
+    node _T_1735 = cat(_T_1734, _T_1606[129]) @[Cat.scala 29:58]
+    node _T_1736 = cat(_T_1735, _T_1606[130]) @[Cat.scala 29:58]
+    node _T_1737 = cat(_T_1736, _T_1606[131]) @[Cat.scala 29:58]
+    node _T_1738 = cat(_T_1737, _T_1606[132]) @[Cat.scala 29:58]
+    node _T_1739 = cat(_T_1738, _T_1606[133]) @[Cat.scala 29:58]
+    node _T_1740 = cat(_T_1739, _T_1606[134]) @[Cat.scala 29:58]
+    node _T_1741 = cat(_T_1740, _T_1606[135]) @[Cat.scala 29:58]
+    node _T_1742 = cat(_T_1741, _T_1606[136]) @[Cat.scala 29:58]
+    node _T_1743 = cat(_T_1742, _T_1606[137]) @[Cat.scala 29:58]
+    node _T_1744 = cat(_T_1743, _T_1606[138]) @[Cat.scala 29:58]
+    node _T_1745 = cat(_T_1744, _T_1606[139]) @[Cat.scala 29:58]
+    node _T_1746 = cat(_T_1745, _T_1606[140]) @[Cat.scala 29:58]
+    node _T_1747 = cat(_T_1746, _T_1606[141]) @[Cat.scala 29:58]
+    node _T_1748 = and(_T_1747, wb_dout_way_pre_0) @[el2_lib.scala 189:94]
+    wire _T_1749 : UInt<1>[142] @[el2_lib.scala 187:48]
+    _T_1749[0] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[1] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[2] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[3] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[4] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[5] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[6] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[7] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[8] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[9] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[10] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[11] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[12] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[13] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[14] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[15] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[16] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[17] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[18] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[19] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[20] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[21] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[22] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[23] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[24] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[25] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[26] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[27] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[28] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[29] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[30] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[31] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[32] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[33] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[34] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[35] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[36] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[37] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[38] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[39] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[40] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[41] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[42] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[43] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[44] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[45] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[46] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[47] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[48] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[49] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[50] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[51] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[52] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[53] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[54] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[55] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[56] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[57] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[58] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[59] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[60] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[61] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[62] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[63] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[64] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[65] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[66] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[67] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[68] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[69] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[70] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[71] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[72] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[73] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[74] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[75] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[76] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[77] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[78] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[79] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[80] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[81] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[82] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[83] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[84] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[85] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[86] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[87] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[88] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[89] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[90] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[91] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[92] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[93] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[94] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[95] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[96] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[97] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[98] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[99] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[100] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[101] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[102] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[103] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[104] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[105] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[106] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[107] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[108] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[109] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[110] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[111] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[112] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[113] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[114] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[115] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[116] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[117] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[118] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[119] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[120] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[121] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[122] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[123] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[124] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[125] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[126] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[127] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[128] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[129] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[130] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[131] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[132] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[133] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[134] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[135] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[136] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[137] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[138] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[139] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[140] <= _T_1605 @[el2_lib.scala 187:48]
+    _T_1749[141] <= _T_1605 @[el2_lib.scala 187:48]
+    node _T_1750 = cat(_T_1749[0], _T_1749[1]) @[Cat.scala 29:58]
+    node _T_1751 = cat(_T_1750, _T_1749[2]) @[Cat.scala 29:58]
+    node _T_1752 = cat(_T_1751, _T_1749[3]) @[Cat.scala 29:58]
+    node _T_1753 = cat(_T_1752, _T_1749[4]) @[Cat.scala 29:58]
+    node _T_1754 = cat(_T_1753, _T_1749[5]) @[Cat.scala 29:58]
+    node _T_1755 = cat(_T_1754, _T_1749[6]) @[Cat.scala 29:58]
+    node _T_1756 = cat(_T_1755, _T_1749[7]) @[Cat.scala 29:58]
+    node _T_1757 = cat(_T_1756, _T_1749[8]) @[Cat.scala 29:58]
+    node _T_1758 = cat(_T_1757, _T_1749[9]) @[Cat.scala 29:58]
+    node _T_1759 = cat(_T_1758, _T_1749[10]) @[Cat.scala 29:58]
+    node _T_1760 = cat(_T_1759, _T_1749[11]) @[Cat.scala 29:58]
+    node _T_1761 = cat(_T_1760, _T_1749[12]) @[Cat.scala 29:58]
+    node _T_1762 = cat(_T_1761, _T_1749[13]) @[Cat.scala 29:58]
+    node _T_1763 = cat(_T_1762, _T_1749[14]) @[Cat.scala 29:58]
+    node _T_1764 = cat(_T_1763, _T_1749[15]) @[Cat.scala 29:58]
+    node _T_1765 = cat(_T_1764, _T_1749[16]) @[Cat.scala 29:58]
+    node _T_1766 = cat(_T_1765, _T_1749[17]) @[Cat.scala 29:58]
+    node _T_1767 = cat(_T_1766, _T_1749[18]) @[Cat.scala 29:58]
+    node _T_1768 = cat(_T_1767, _T_1749[19]) @[Cat.scala 29:58]
+    node _T_1769 = cat(_T_1768, _T_1749[20]) @[Cat.scala 29:58]
+    node _T_1770 = cat(_T_1769, _T_1749[21]) @[Cat.scala 29:58]
+    node _T_1771 = cat(_T_1770, _T_1749[22]) @[Cat.scala 29:58]
+    node _T_1772 = cat(_T_1771, _T_1749[23]) @[Cat.scala 29:58]
+    node _T_1773 = cat(_T_1772, _T_1749[24]) @[Cat.scala 29:58]
+    node _T_1774 = cat(_T_1773, _T_1749[25]) @[Cat.scala 29:58]
+    node _T_1775 = cat(_T_1774, _T_1749[26]) @[Cat.scala 29:58]
+    node _T_1776 = cat(_T_1775, _T_1749[27]) @[Cat.scala 29:58]
+    node _T_1777 = cat(_T_1776, _T_1749[28]) @[Cat.scala 29:58]
+    node _T_1778 = cat(_T_1777, _T_1749[29]) @[Cat.scala 29:58]
+    node _T_1779 = cat(_T_1778, _T_1749[30]) @[Cat.scala 29:58]
+    node _T_1780 = cat(_T_1779, _T_1749[31]) @[Cat.scala 29:58]
+    node _T_1781 = cat(_T_1780, _T_1749[32]) @[Cat.scala 29:58]
+    node _T_1782 = cat(_T_1781, _T_1749[33]) @[Cat.scala 29:58]
+    node _T_1783 = cat(_T_1782, _T_1749[34]) @[Cat.scala 29:58]
+    node _T_1784 = cat(_T_1783, _T_1749[35]) @[Cat.scala 29:58]
+    node _T_1785 = cat(_T_1784, _T_1749[36]) @[Cat.scala 29:58]
+    node _T_1786 = cat(_T_1785, _T_1749[37]) @[Cat.scala 29:58]
+    node _T_1787 = cat(_T_1786, _T_1749[38]) @[Cat.scala 29:58]
+    node _T_1788 = cat(_T_1787, _T_1749[39]) @[Cat.scala 29:58]
+    node _T_1789 = cat(_T_1788, _T_1749[40]) @[Cat.scala 29:58]
+    node _T_1790 = cat(_T_1789, _T_1749[41]) @[Cat.scala 29:58]
+    node _T_1791 = cat(_T_1790, _T_1749[42]) @[Cat.scala 29:58]
+    node _T_1792 = cat(_T_1791, _T_1749[43]) @[Cat.scala 29:58]
+    node _T_1793 = cat(_T_1792, _T_1749[44]) @[Cat.scala 29:58]
+    node _T_1794 = cat(_T_1793, _T_1749[45]) @[Cat.scala 29:58]
+    node _T_1795 = cat(_T_1794, _T_1749[46]) @[Cat.scala 29:58]
+    node _T_1796 = cat(_T_1795, _T_1749[47]) @[Cat.scala 29:58]
+    node _T_1797 = cat(_T_1796, _T_1749[48]) @[Cat.scala 29:58]
+    node _T_1798 = cat(_T_1797, _T_1749[49]) @[Cat.scala 29:58]
+    node _T_1799 = cat(_T_1798, _T_1749[50]) @[Cat.scala 29:58]
+    node _T_1800 = cat(_T_1799, _T_1749[51]) @[Cat.scala 29:58]
+    node _T_1801 = cat(_T_1800, _T_1749[52]) @[Cat.scala 29:58]
+    node _T_1802 = cat(_T_1801, _T_1749[53]) @[Cat.scala 29:58]
+    node _T_1803 = cat(_T_1802, _T_1749[54]) @[Cat.scala 29:58]
+    node _T_1804 = cat(_T_1803, _T_1749[55]) @[Cat.scala 29:58]
+    node _T_1805 = cat(_T_1804, _T_1749[56]) @[Cat.scala 29:58]
+    node _T_1806 = cat(_T_1805, _T_1749[57]) @[Cat.scala 29:58]
+    node _T_1807 = cat(_T_1806, _T_1749[58]) @[Cat.scala 29:58]
+    node _T_1808 = cat(_T_1807, _T_1749[59]) @[Cat.scala 29:58]
+    node _T_1809 = cat(_T_1808, _T_1749[60]) @[Cat.scala 29:58]
+    node _T_1810 = cat(_T_1809, _T_1749[61]) @[Cat.scala 29:58]
+    node _T_1811 = cat(_T_1810, _T_1749[62]) @[Cat.scala 29:58]
+    node _T_1812 = cat(_T_1811, _T_1749[63]) @[Cat.scala 29:58]
+    node _T_1813 = cat(_T_1812, _T_1749[64]) @[Cat.scala 29:58]
+    node _T_1814 = cat(_T_1813, _T_1749[65]) @[Cat.scala 29:58]
+    node _T_1815 = cat(_T_1814, _T_1749[66]) @[Cat.scala 29:58]
+    node _T_1816 = cat(_T_1815, _T_1749[67]) @[Cat.scala 29:58]
+    node _T_1817 = cat(_T_1816, _T_1749[68]) @[Cat.scala 29:58]
+    node _T_1818 = cat(_T_1817, _T_1749[69]) @[Cat.scala 29:58]
+    node _T_1819 = cat(_T_1818, _T_1749[70]) @[Cat.scala 29:58]
+    node _T_1820 = cat(_T_1819, _T_1749[71]) @[Cat.scala 29:58]
+    node _T_1821 = cat(_T_1820, _T_1749[72]) @[Cat.scala 29:58]
+    node _T_1822 = cat(_T_1821, _T_1749[73]) @[Cat.scala 29:58]
+    node _T_1823 = cat(_T_1822, _T_1749[74]) @[Cat.scala 29:58]
+    node _T_1824 = cat(_T_1823, _T_1749[75]) @[Cat.scala 29:58]
+    node _T_1825 = cat(_T_1824, _T_1749[76]) @[Cat.scala 29:58]
+    node _T_1826 = cat(_T_1825, _T_1749[77]) @[Cat.scala 29:58]
+    node _T_1827 = cat(_T_1826, _T_1749[78]) @[Cat.scala 29:58]
+    node _T_1828 = cat(_T_1827, _T_1749[79]) @[Cat.scala 29:58]
+    node _T_1829 = cat(_T_1828, _T_1749[80]) @[Cat.scala 29:58]
+    node _T_1830 = cat(_T_1829, _T_1749[81]) @[Cat.scala 29:58]
+    node _T_1831 = cat(_T_1830, _T_1749[82]) @[Cat.scala 29:58]
+    node _T_1832 = cat(_T_1831, _T_1749[83]) @[Cat.scala 29:58]
+    node _T_1833 = cat(_T_1832, _T_1749[84]) @[Cat.scala 29:58]
+    node _T_1834 = cat(_T_1833, _T_1749[85]) @[Cat.scala 29:58]
+    node _T_1835 = cat(_T_1834, _T_1749[86]) @[Cat.scala 29:58]
+    node _T_1836 = cat(_T_1835, _T_1749[87]) @[Cat.scala 29:58]
+    node _T_1837 = cat(_T_1836, _T_1749[88]) @[Cat.scala 29:58]
+    node _T_1838 = cat(_T_1837, _T_1749[89]) @[Cat.scala 29:58]
+    node _T_1839 = cat(_T_1838, _T_1749[90]) @[Cat.scala 29:58]
+    node _T_1840 = cat(_T_1839, _T_1749[91]) @[Cat.scala 29:58]
+    node _T_1841 = cat(_T_1840, _T_1749[92]) @[Cat.scala 29:58]
+    node _T_1842 = cat(_T_1841, _T_1749[93]) @[Cat.scala 29:58]
+    node _T_1843 = cat(_T_1842, _T_1749[94]) @[Cat.scala 29:58]
+    node _T_1844 = cat(_T_1843, _T_1749[95]) @[Cat.scala 29:58]
+    node _T_1845 = cat(_T_1844, _T_1749[96]) @[Cat.scala 29:58]
+    node _T_1846 = cat(_T_1845, _T_1749[97]) @[Cat.scala 29:58]
+    node _T_1847 = cat(_T_1846, _T_1749[98]) @[Cat.scala 29:58]
+    node _T_1848 = cat(_T_1847, _T_1749[99]) @[Cat.scala 29:58]
+    node _T_1849 = cat(_T_1848, _T_1749[100]) @[Cat.scala 29:58]
+    node _T_1850 = cat(_T_1849, _T_1749[101]) @[Cat.scala 29:58]
+    node _T_1851 = cat(_T_1850, _T_1749[102]) @[Cat.scala 29:58]
+    node _T_1852 = cat(_T_1851, _T_1749[103]) @[Cat.scala 29:58]
+    node _T_1853 = cat(_T_1852, _T_1749[104]) @[Cat.scala 29:58]
+    node _T_1854 = cat(_T_1853, _T_1749[105]) @[Cat.scala 29:58]
+    node _T_1855 = cat(_T_1854, _T_1749[106]) @[Cat.scala 29:58]
+    node _T_1856 = cat(_T_1855, _T_1749[107]) @[Cat.scala 29:58]
+    node _T_1857 = cat(_T_1856, _T_1749[108]) @[Cat.scala 29:58]
+    node _T_1858 = cat(_T_1857, _T_1749[109]) @[Cat.scala 29:58]
+    node _T_1859 = cat(_T_1858, _T_1749[110]) @[Cat.scala 29:58]
+    node _T_1860 = cat(_T_1859, _T_1749[111]) @[Cat.scala 29:58]
+    node _T_1861 = cat(_T_1860, _T_1749[112]) @[Cat.scala 29:58]
+    node _T_1862 = cat(_T_1861, _T_1749[113]) @[Cat.scala 29:58]
+    node _T_1863 = cat(_T_1862, _T_1749[114]) @[Cat.scala 29:58]
+    node _T_1864 = cat(_T_1863, _T_1749[115]) @[Cat.scala 29:58]
+    node _T_1865 = cat(_T_1864, _T_1749[116]) @[Cat.scala 29:58]
+    node _T_1866 = cat(_T_1865, _T_1749[117]) @[Cat.scala 29:58]
+    node _T_1867 = cat(_T_1866, _T_1749[118]) @[Cat.scala 29:58]
+    node _T_1868 = cat(_T_1867, _T_1749[119]) @[Cat.scala 29:58]
+    node _T_1869 = cat(_T_1868, _T_1749[120]) @[Cat.scala 29:58]
+    node _T_1870 = cat(_T_1869, _T_1749[121]) @[Cat.scala 29:58]
+    node _T_1871 = cat(_T_1870, _T_1749[122]) @[Cat.scala 29:58]
+    node _T_1872 = cat(_T_1871, _T_1749[123]) @[Cat.scala 29:58]
+    node _T_1873 = cat(_T_1872, _T_1749[124]) @[Cat.scala 29:58]
+    node _T_1874 = cat(_T_1873, _T_1749[125]) @[Cat.scala 29:58]
+    node _T_1875 = cat(_T_1874, _T_1749[126]) @[Cat.scala 29:58]
+    node _T_1876 = cat(_T_1875, _T_1749[127]) @[Cat.scala 29:58]
+    node _T_1877 = cat(_T_1876, _T_1749[128]) @[Cat.scala 29:58]
+    node _T_1878 = cat(_T_1877, _T_1749[129]) @[Cat.scala 29:58]
+    node _T_1879 = cat(_T_1878, _T_1749[130]) @[Cat.scala 29:58]
+    node _T_1880 = cat(_T_1879, _T_1749[131]) @[Cat.scala 29:58]
+    node _T_1881 = cat(_T_1880, _T_1749[132]) @[Cat.scala 29:58]
+    node _T_1882 = cat(_T_1881, _T_1749[133]) @[Cat.scala 29:58]
+    node _T_1883 = cat(_T_1882, _T_1749[134]) @[Cat.scala 29:58]
+    node _T_1884 = cat(_T_1883, _T_1749[135]) @[Cat.scala 29:58]
+    node _T_1885 = cat(_T_1884, _T_1749[136]) @[Cat.scala 29:58]
+    node _T_1886 = cat(_T_1885, _T_1749[137]) @[Cat.scala 29:58]
+    node _T_1887 = cat(_T_1886, _T_1749[138]) @[Cat.scala 29:58]
+    node _T_1888 = cat(_T_1887, _T_1749[139]) @[Cat.scala 29:58]
+    node _T_1889 = cat(_T_1888, _T_1749[140]) @[Cat.scala 29:58]
+    node _T_1890 = cat(_T_1889, _T_1749[141]) @[Cat.scala 29:58]
+    node _T_1891 = and(_T_1890, wb_dout_way_pre_1) @[el2_lib.scala 189:94]
+    node wb_dout_ecc = or(_T_1748, _T_1891) @[el2_lib.scala 189:110]
+    io.test_port2 <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 288:17]
+    io.test_port[0][0] <= wb_dout[0][0] @[el2_ifu_ic_mem.scala 289:16]
+    io.test_port[0][1] <= wb_dout[0][1] @[el2_ifu_ic_mem.scala 289:16]
+    io.test_port[1][0] <= wb_dout[1][0] @[el2_ifu_ic_mem.scala 289:16]
+    io.test_port[1][1] <= wb_dout[1][1] @[el2_ifu_ic_mem.scala 289:16]
     

EL2_IC_DATA.v

@@ -488,11 +488,11 @@ module EL2_IC_DATA(
   assign io_ic_debug_rd_data = _T_1530 | _T_1602; // @[el2_ifu_ic_mem.scala 278:23 el2_ifu_ic_mem.scala 284:23]
   assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 279:16]
   assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 280:16]
-  assign io_test_port2 = 1'h0; // @[el2_ifu_ic_mem.scala 286:17]
+  assign io_test_port2 = 1'h0; // @[el2_ifu_ic_mem.scala 288:17]
-  assign io_test_port_0_0 = data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 287:16]
+  assign io_test_port_0_0 = data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 289:16]
-  assign io_test_port_0_1 = data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 287:16]
+  assign io_test_port_0_1 = data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 289:16]
-  assign io_test_port_1_0 = data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 287:16]
+  assign io_test_port_1_0 = data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 289:16]
-  assign io_test_port_1_1 = data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 287:16]
+  assign io_test_port_1_1 = data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 289:16]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif

el2_ifu_ifc_ctrl.anno.json

@@ -0,0 +1,25 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_test1",
+    "sources":[
+      "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"el2_ifu_ifc_ctrl"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

el2_ifu_ifc_ctrl.fir

@@ -0,0 +1,139 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit el2_ifu_ifc_ctrl : 
+  module el2_ifu_ifc_ctrl : 
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<32>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<32>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<32>, ifc_fetch_addr_bf : UInt<32>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, flip testin : UInt<1>, test1 : UInt}
+    
+    io.ifc_fetch_addr_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 39:23]
+    io.ifc_fetch_addr_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 40:24]
+    io.ifc_fetch_req_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 41:22]
+    io.ifu_pmu_fetch_stall <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 42:26]
+    io.ifc_fetch_uncacheable_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 43:31]
+    io.ifc_fetch_req_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 44:23]
+    io.ifc_fetch_req_bf_raw <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 45:27]
+    io.ifc_iccm_access_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 46:25]
+    io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 47:30]
+    io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 48:24]
+    wire fetch_addr_bf : UInt<32>
+    fetch_addr_bf <= UInt<1>("h00")
+    wire fetch_addr_next : UInt<32>
+    fetch_addr_next <= UInt<1>("h00")
+    wire fb_write_f : UInt<4>
+    fb_write_f <= UInt<1>("h00")
+    wire fb_write_ns : UInt<4>
+    fb_write_ns <= UInt<1>("h00")
+    wire fb_full_f_ns : UInt<1>
+    fb_full_f_ns <= UInt<1>("h00")
+    wire fb_full_f : UInt<1>
+    fb_full_f <= UInt<1>("h00")
+    wire fb_right : UInt<1>
+    fb_right <= UInt<1>("h00")
+    wire fb_right2 : UInt<1>
+    fb_right2 <= UInt<1>("h00")
+    wire fb_left : UInt<1>
+    fb_left <= UInt<1>("h00")
+    wire wfm : UInt<1>
+    wfm <= UInt<1>("h00")
+    wire idle : UInt<1>
+    idle <= UInt<1>("h00")
+    wire sel_last_addr_bf : UInt<1>
+    sel_last_addr_bf <= UInt<1>("h00")
+    wire sel_btb_addr_bf : UInt<1>
+    sel_btb_addr_bf <= UInt<1>("h00")
+    wire sel_next_addr_bf : UInt<1>
+    sel_next_addr_bf <= UInt<1>("h00")
+    wire miss_f : UInt<1>
+    miss_f <= UInt<1>("h00")
+    wire miss_a : UInt<1>
+    miss_a <= UInt<1>("h00")
+    wire flush_fb : UInt<1>
+    flush_fb <= UInt<1>("h00")
+    wire dma_iccm_stall_any_f : UInt<1>
+    dma_iccm_stall_any_f <= UInt<1>("h00")
+    wire mb_empty_mod : UInt<1>
+    mb_empty_mod <= UInt<1>("h00")
+    wire goto_idle : UInt<1>
+    goto_idle <= UInt<1>("h00")
+    wire leave_idle : UInt<1>
+    leave_idle <= UInt<1>("h00")
+    wire fetch_bf_en : UInt<1>
+    fetch_bf_en <= UInt<1>("h00")
+    wire line_wrap : UInt<1>
+    line_wrap <= UInt<1>("h00")
+    wire fetch_addr_next_1 : UInt<1>
+    fetch_addr_next_1 <= UInt<1>("h00")
+    reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 76:34]
+    _T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 76:34]
+    dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctrl.scala 76:24]
+    node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 77:36]
+    reg _T_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 79:34]
+    _T_1 <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 79:34]
+    dma_iccm_stall_any_f <= _T_1 @[el2_ifu_ifc_ctrl.scala 79:24]
+    reg _T_2 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 80:20]
+    _T_2 <= miss_f @[el2_ifu_ifc_ctrl.scala 80:20]
+    miss_a <= _T_2 @[el2_ifu_ifc_ctrl.scala 80:10]
+    node _T_3 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 81:23]
+    node _T_4 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 81:46]
+    node _T_5 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 81:68]
+    node _T_6 = or(_T_4, _T_5) @[el2_ifu_ifc_ctrl.scala 81:66]
+    node _T_7 = and(_T_3, _T_6) @[el2_ifu_ifc_ctrl.scala 81:43]
+    sel_last_addr_bf <= _T_7 @[el2_ifu_ifc_ctrl.scala 81:20]
+    node _T_8 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 82:23]
+    node _T_9 = and(_T_8, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 82:43]
+    node _T_10 = and(_T_9, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 82:64]
+    node _T_11 = and(_T_10, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 82:88]
+    sel_btb_addr_bf <= _T_11 @[el2_ifu_ifc_ctrl.scala 82:20]
+    node _T_12 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 83:23]
+    node _T_13 = and(_T_12, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 83:43]
+    node _T_14 = not(io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 83:66]
+    node _T_15 = and(_T_13, _T_14) @[el2_ifu_ifc_ctrl.scala 83:64]
+    node _T_16 = and(_T_15, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 83:89]
+    sel_next_addr_bf <= _T_16 @[el2_ifu_ifc_ctrl.scala 83:20]
+    node _T_17 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 84:55]
+    node _T_18 = cat(io.exu_flush_path_final, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_19 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 85:52]
+    node _T_20 = cat(io.ifc_fetch_addr_f, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_21 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 86:51]
+    node _T_22 = cat(io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_23 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 87:52]
+    node _T_24 = cat(fetch_addr_next, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_25 = mux(_T_17, _T_18, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_26 = mux(_T_19, _T_20, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_27 = mux(_T_21, _T_22, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_28 = mux(_T_23, _T_24, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_29 = or(_T_25, _T_26) @[Mux.scala 27:72]
+    node _T_30 = or(_T_29, _T_27) @[Mux.scala 27:72]
+    node _T_31 = or(_T_30, _T_28) @[Mux.scala 27:72]
+    wire _T_32 : UInt<33> @[Mux.scala 27:72]
+    _T_32 <= _T_31 @[Mux.scala 27:72]
+    fetch_addr_bf <= _T_32 @[el2_ifu_ifc_ctrl.scala 84:17]
+    node _T_33 = bits(io.ifc_fetch_addr_f, 31, 2) @[el2_ifu_ifc_ctrl.scala 88:46]
+    node _T_34 = add(_T_33, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 88:53]
+    node _T_35 = tail(_T_34, 1) @[el2_ifu_ifc_ctrl.scala 88:53]
+    node _T_36 = cat(_T_35, fetch_addr_next_1) @[Cat.scala 29:58]
+    fetch_addr_next <= _T_36 @[el2_ifu_ifc_ctrl.scala 88:19]
+    node _T_37 = bits(fetch_addr_next, 6, 6) @[el2_ifu_ifc_ctrl.scala 89:32]
+    node _T_38 = bits(io.ifc_fetch_addr_f, 6, 6) @[el2_ifu_ifc_ctrl.scala 89:75]
+    node _T_39 = xor(_T_37, _T_38) @[el2_ifu_ifc_ctrl.scala 89:54]
+    line_wrap <= _T_39 @[el2_ifu_ifc_ctrl.scala 89:13]
+    node _T_40 = not(line_wrap) @[el2_ifu_ifc_ctrl.scala 90:24]
+    node _T_41 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_ifc_ctrl.scala 90:56]
+    node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctrl.scala 90:35]
+    fetch_addr_next_1 <= _T_42 @[el2_ifu_ifc_ctrl.scala 90:21]
+    node _T_43 = not(idle) @[el2_ifu_ifc_ctrl.scala 91:30]
+    io.ifc_fetch_req_bf_raw <= _T_43 @[el2_ifu_ifc_ctrl.scala 91:27]
+    node _T_44 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 92:91]
+    node _T_45 = not(_T_44) @[el2_ifu_ifc_ctrl.scala 92:70]
+    node _T_46 = and(fb_full_f_ns, _T_45) @[el2_ifu_ifc_ctrl.scala 92:68]
+    node _T_47 = not(_T_46) @[el2_ifu_ifc_ctrl.scala 92:53]
+    node _T_48 = and(io.ifc_fetch_req_bf_raw, _T_47) @[el2_ifu_ifc_ctrl.scala 92:51]
+    node _T_49 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 93:5]
+    node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctrl.scala 92:114]
+    node _T_51 = not(io.ic_write_stall) @[el2_ifu_ifc_ctrl.scala 93:18]
+    node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctrl.scala 93:16]
+    node _T_53 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 93:39]
+    node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctrl.scala 93:37]
+    io.ifc_fetch_req_bf <= _T_54 @[el2_ifu_ifc_ctrl.scala 92:23]
+    io.test1 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 96:12]
+    

el2_ifu_ifc_ctrl.v

@@ -0,0 +1,47 @@
+module el2_ifu_ifc_ctrl(
+  input         clock,
+  input         reset,
+  input         io_free_clk,
+  input         io_active_clk,
+  input         io_rst_l,
+  input         io_scan_mode,
+  input         io_ic_hit_f,
+  input         io_ifu_ic_mb_empty,
+  input         io_ifu_fb_consume1,
+  input         io_ifu_fb_consume2,
+  input         io_dec_tlu_flush_noredir_wb,
+  input         io_exu_flush_final,
+  input  [31:0] io_exu_flush_path_final,
+  input         io_ifu_bp_hit_taken_f,
+  input  [31:0] io_ifu_bp_btb_target_f,
+  input         io_ic_dma_active,
+  input         io_ic_write_stall,
+  input         io_dma_iccm_stall_any,
+  input  [31:0] io_dec_tlu_mrac_ff,
+  output [31:0] io_ifc_fetch_addr_f,
+  output [31:0] io_ifc_fetch_addr_bf,
+  output        io_ifc_fetch_req_f,
+  output        io_ifu_pmu_fetch_stall,
+  output        io_ifc_fetch_uncacheable_bf,
+  output        io_ifc_fetch_req_bf,
+  output        io_ifc_fetch_req_bf_raw,
+  output        io_ifc_iccm_access_bf,
+  output        io_ifc_region_acc_fault_bf,
+  output        io_ifc_dma_access_ok,
+  input         io_testin,
+  output [31:0] io_test1
+);
+  wire [29:0] _T_35 = io_ifc_fetch_addr_f[31:2] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 88:53]
+  wire [30:0] _T_36 = {_T_35,1'h0}; // @[Cat.scala 29:58]
+  assign io_ifc_fetch_addr_f = 32'h0; // @[el2_ifu_ifc_ctrl.scala 39:23]
+  assign io_ifc_fetch_addr_bf = 32'h0; // @[el2_ifu_ifc_ctrl.scala 40:24]
+  assign io_ifc_fetch_req_f = 1'h0; // @[el2_ifu_ifc_ctrl.scala 41:22]
+  assign io_ifu_pmu_fetch_stall = 1'h0; // @[el2_ifu_ifc_ctrl.scala 42:26]
+  assign io_ifc_fetch_uncacheable_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 43:31]
+  assign io_ifc_fetch_req_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 44:23]
+  assign io_ifc_fetch_req_bf_raw = 1'h0; // @[el2_ifu_ifc_ctrl.scala 45:27]
+  assign io_ifc_iccm_access_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 46:25]
+  assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 47:30]
+  assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 48:24]
+  assign io_test1 = {{1'd0}, _T_36}; // @[el2_ifu_ifc_ctrl.scala 89:12]
+endmodule

src/main/scala/ifu/el2_ifu_ic_mem.scala

@@ -298,6 +298,6 @@ class EL2_IC_DATA extends Module with el2_lib {
 //println(s"${DATA_MEM_LINE._2}")
 }
 
-object ifu_ic extends App {
+//object ifu_ic extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_DATA()))
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_DATA()))
-}
+//}

src/main/scala/ifu/el2_ifu_ifc_ctrl.scala

@@ -0,0 +1,177 @@
+package ifu
+import lib._
+import chisel3._
+import chisel3.util._
+class el2_ifu_ifc_ctrl extends Module with el2_lib {
+val io = IO(new Bundle{
+  val free_clk = Input(Bool())
+  val active_clk = Input(Bool())
+  val rst_l = Input(Bool())
+  val scan_mode = Input(Bool())
+  val ic_hit_f = Input(Bool())
+  val ifu_ic_mb_empty = Input(Bool())
+  val ifu_fb_consume1 = Input(Bool())
+  val ifu_fb_consume2 = Input(Bool())
+  val dec_tlu_flush_noredir_wb = Input(Bool())
+  val exu_flush_final = Input(Bool())
+  val exu_flush_path_final = Input(UInt(32.W))
+  val ifu_bp_hit_taken_f = Input(Bool())
+  val ifu_bp_btb_target_f = Input(UInt(32.W))
+  val ic_dma_active = Input(Bool())
+  val ic_write_stall = Input(Bool())
+  val dma_iccm_stall_any = Input(Bool())
+  val dec_tlu_mrac_ff = Input(UInt(32.W))
+
+  val ifc_fetch_addr_f = Output(UInt(32.W))
+  val ifc_fetch_addr_bf = Output(UInt(32.W))
+  val ifc_fetch_req_f = Output(Bool())
+  val ifu_pmu_fetch_stall = Output(Bool())
+  val ifc_fetch_uncacheable_bf = Output(Bool())
+  val ifc_fetch_req_bf = Output(Bool())
+  val ifc_fetch_req_bf_raw = Output(Bool())
+  val ifc_iccm_access_bf = Output(Bool())
+  val ifc_region_acc_fault_bf = Output(Bool())
+  val ifc_dma_access_ok = Output(Bool())
+  val testin = Input(Bool())
+  val test1 = Output(UInt())
+  //val test2 = Output(Bool())
+})
+  io.ifc_fetch_addr_f := 0.U
+  io.ifc_fetch_addr_bf := 0.U
+  io.ifc_fetch_req_f := 0.U
+  io.ifu_pmu_fetch_stall := 0.U
+  io.ifc_fetch_uncacheable_bf := 0.U
+  io.ifc_fetch_req_bf := 0.U
+  io.ifc_fetch_req_bf_raw := 0.U
+  io.ifc_iccm_access_bf := 0.U
+  io.ifc_region_acc_fault_bf := 0.U
+  io.ifc_dma_access_ok := 0.U
+
+  val fetch_addr_bf = WireInit(UInt(32.W), init = 0.U)
+  val fetch_addr_next = WireInit(UInt(32.W), init = 0.U)
+  val fb_write_f = WireInit(UInt(4.W), init = 0.U)
+  val fb_write_ns = WireInit(UInt(4.W), init = 0.U)
+  val fb_full_f_ns = WireInit(Bool(), init = 0.U)
+  val fb_full_f = WireInit(Bool(), init = 0.U)
+  val fb_right = WireInit(Bool(), init = 0.U)
+  val fb_right2 = WireInit(Bool(), init = 0.U)
+  val fb_left = WireInit(Bool(), init = 0.U)
+  val wfm = WireInit(Bool(), init = 0.U)
+  val idle = WireInit(Bool(), init = 0.U)
+  val sel_last_addr_bf = WireInit(Bool(), init = 0.U)
+  val sel_btb_addr_bf = WireInit(Bool(), init = 0.U)
+  val sel_next_addr_bf = WireInit(Bool(), init = 0.U)
+  val miss_f = WireInit(Bool(), init = 0.U)
+  val miss_a = WireInit(Bool(), init = 0.U)
+  val flush_fb = WireInit(Bool(), init = 0.U)
+  val dma_iccm_stall_any_f = WireInit(Bool(), init = 0.U)
+  val mb_empty_mod = WireInit(Bool(), init = 0.U)
+  val goto_idle = WireInit(Bool(), init = 0.U)
+  val leave_idle = WireInit(Bool(), init = 0.U)
+  val fetch_bf_en = WireInit(Bool(), init = 0.U)
+  val line_wrap = WireInit(Bool(), init = 0.U)
+  val fetch_addr_next_1 = WireInit(Bool(), init = 0.U)
+
+  val idle_E :: fetch_E :: stall_E :: wfm_E :: Nil = Enum(4)
+  dma_iccm_stall_any_f := RegNext(io.dma_iccm_stall_any, init = 0.U)
+  val dma_stall = io.ic_dma_active | dma_iccm_stall_any_f
+
+  dma_iccm_stall_any_f := RegNext(io.dma_iccm_stall_any, init = 0.U)
+  miss_a := RegNext(miss_f, init = 0.U)
+  sel_last_addr_bf := ~io.exu_flush_final & (~io.ifc_fetch_req_f | ~io.ic_hit_f)
+  sel_btb_addr_bf  := ~io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f
+  sel_next_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & ~io.ifu_bp_hit_taken_f & io.ic_hit_f
+  fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool()-> Cat(io.exu_flush_path_final,0.U),
+                            sel_last_addr_bf.asBool()   -> Cat(io.ifc_fetch_addr_f,0.U),
+                            sel_btb_addr_bf.asBool()    -> Cat(io.ifu_bp_btb_target_f,0.U),
+                            sel_next_addr_bf.asBool()   -> Cat(fetch_addr_next, 0.U)))
+  fetch_addr_next := Cat((io.ifc_fetch_addr_f(31,2) + 1.U), fetch_addr_next_1)
+  line_wrap := (fetch_addr_next(ICACHE_TAG_INDEX_LO) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO))
+  fetch_addr_next_1 := ~line_wrap & io.ifc_fetch_addr_f(1)
+  io.ifc_fetch_req_bf_raw := ~idle
+  io.ifc_fetch_req_bf :=  io.ifc_fetch_req_bf_raw & ~(fb_full_f_ns & ~(io.ifu_fb_consume2 | io.ifu_fb_consume1)) &
+    ~dma_stall & ~io.ic_write_stall & ~io.dec_tlu_flush_noredir_wb
+
+
+  io.test1 := io.ifc_fetch_req_bf // RegNext(miss_f, init = 0.U)//waleed// RegNext(miss_f, init = 0.U)
+
+  /*
+
+
+
+
+
+
+  io.ifc_fetch_req_bf_raw := ~idle
+  io.ifc_fetch_req_bf := io.ifc_fetch_req_bf_raw & ~(fb_full_f_ns & ~(io.ifu_fb_consume2 | io.ifu_fb_consume1)) &
+    ~dma_stall & ~io.ic_write_stall & ~io.dec_tlu_flush_noredir_wb
+
+
+
+
+  val goto_idle = io.exu_flush_final & io.dec_tlu_flush_noredir_wb
+  val mb_empty_mod = (io.ifu_ic_mb_empty | io.exu_flush_final) & ~dma_stall & ~miss_f & ~miss_a
+  val leave_idle = io.exu_flush_final & ~io.dec_tlu_flush_noredir_wb & idle
+  val state = RegNext(next_state, init = 0.U)
+  val next_state = Wire(UInt(2.W))
+  next_state := Cat((~state(1) & state(0) & miss_f & ~goto_idle) | (state(1) & ~mb_empty_mod & ~goto_idle),
+    (~goto_idle & leave_idle) | (state(0) & ~goto_idle))
+  val fb_right = Wire(UInt(1.W))
+  fb_right := ( io.ifu_fb_consume1 & ~io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)) | // Consumed and no new fetch
+    (io.ifu_fb_consume2 &  io.ifc_fetch_req_f) // Consumed 2 and new fetch
+
+  val fb_right2 = io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)
+  val fb_left = io.ifc_fetch_req_f & ~(io.ifu_fb_consume1 | io.ifu_fb_consume2) & ~miss_f
+  val fb_write_ns = Wire(UInt(4.W))
+
+  fb_write_ns := Mux1H(Seq(flush_fb->1.U(4.W),
+    (~flush_fb & fb_right).asBool                           ->fb_write_f(3,1),
+    (~flush_fb & fb_right2).asBool                          ->0.U,
+    (~flush_fb & fb_left).asBool           -> Cat(fb_write_f,0.U),
+    (~flush_fb & ~fb_right & ~fb_right2 & ~fb_left).asBool  ->fb_write_f))
+
+  val fb_full_f_ns = fb_write_ns(3)
+  val idle     = state === idle_E
+  val wfm      = state === wfm_E
+  val fb_full_f = RegNext(fb_full_f_ns, init = 0.U)
+  val fb_write_f = RegNext(fb_write_ns, init = 0.U)
+  val flush_fb = io.exu_flush_final
+  val ifu_pmu_fetch_stall = wfm | (io.ifc_fetch_req_bf_raw & ( (fb_full_f &
+    ~(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
+
+  io.test1 := dma_iccm_stall_any_f
+  io.test2 := dma_stall
+
+
+
+
+
+  io.ifc_fetch_req_f := RegNext(io.ifc_fetch_req_bf, init = 0.U)
+  val ifc_fetch_addr_bf = Cat(fetch_addr_bf(31,1), 0.U)
+
+
+
+  val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE)
+    rvrangecheck(ICCM_SADR, ICCM_SIZE, ifc_fetch_addr_bf) else (0.U, 0.U)
+
+  io.ifc_iccm_access_bf := iccm_acc_in_range_bf
+  io.ifc_region_acc_fault_bf := ~iccm_acc_in_range_bf & iccm_acc_in_region_bf
+  io.ifc_dma_access_ok := ( (~io.ifc_iccm_access_bf |
+    (fb_full_f & ~(io.ifu_fb_consume2 | io.ifu_fb_consume1)) |
+    (wfm  & ~io.ifc_fetch_req_bf) | idle ) & ~io.exu_flush_final) | dma_iccm_stall_any_f*/
+
+}
+
+class test extends Module with el2_lib {
+  val io= IO(new Bundle() {
+    val addr = Input(UInt(32.W))
+    val in_range = Output(Bool())
+    val in_region = Output(Bool())
+  })
+  val (range, region) = rvrangecheck(ICCM_SADR, ICCM_SIZE, io.addr)
+  io.in_region := region
+  io.in_range := range
+}
+object ifu_ifc extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctrl()))
+}

src/main/scala/lib/el2_lib.scala

@@ -97,13 +97,13 @@ trait param {
   val ICCM_BANK_HI           = 0x03  //.U(5.W)
   val ICCM_BANK_INDEX_LO     = 0x04  //.U(5.W)
   val ICCM_BITS              = 0x10  //.U(5.W)
-  val ICCM_ENABLE            = 0x1   //.U(1.W)
+  val ICCM_ENABLE            = true   //.U(1.W)
   val ICCM_ICACHE            = 0x1   //.U(1.W)
   val ICCM_INDEX_BITS        = 0xC   //.U(4.W)
   val ICCM_NUM_BANKS         = 0x04  //.U(5.W)
   val ICCM_ONLY              = 0x0   //.U(1.W)
   val ICCM_REGION            = 0xE   //.U(4.W)
-  val ICCM_SADR              = 0xEE000000 //.U(32.W)
+  val ICCM_SADR              = 0xEE000000L //.U(32.W)
   val ICCM_SIZE              = 0x040 //.U(10.W)
   val IFU_BUS_ID             = 0x1   //.U(1.W)
   val IFU_BUS_PRTY           = 0x2   //.U(2.W)
@@ -194,6 +194,19 @@ trait el2_lib extends param{
   def rveven_paritygen(data_in : UInt) =
     data_in.xorR.asUInt
 
+  // RV range
+  def rvrangecheck(CCM_SADR:Long, CCM_SIZE:Int, addr:UInt) = {
+    val REGION_BITS = 4;
+    val MASK_BITS = 10 + log2Ceil(CCM_SIZE)
+    val start_addr = CCM_SADR.U(32.W)
+    val region = start_addr(31,32-REGION_BITS)
+    val in_region = addr(31,(32-REGION_BITS)) === region
+    val in_range = if(CCM_SIZE==48)
+      (addr(31, MASK_BITS) === start_addr(31,MASK_BITS)) & ~addr(MASK_BITS-1 , MASK_BITS-2).andR
+    else addr(31,MASK_BITS) === start_addr(31,MASK_BITS)
+    (in_region, in_range)
+  }
+
   // Move rvecc_encode to a proper trait
   def rvecc_encode(din:UInt) = {   //Done for verification and testing
     val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1)

test.anno.json

@@ -0,0 +1,32 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~test|test>io_in_region",
+    "sources":[
+      "~test|test>io_addr"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~test|test>io_in_range",
+    "sources":[
+      "~test|test>io_addr"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"test"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

test.fir

@@ -0,0 +1,14 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit test : 
+  module test : 
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
+    
+    node _T = bits(io.addr, 31, 28) @[el2_lib.scala 203:25]
+    node range = eq(_T, UInt<4>("h0e")) @[el2_lib.scala 203:47]
+    node _T_1 = bits(io.addr, 31, 16) @[el2_lib.scala 206:14]
+    node region = eq(_T_1, UInt<16>("h0ee00")) @[el2_lib.scala 206:29]
+    io.in_region <= region @[el2_ifu_ifc_ctrl.scala 142:16]
+    io.in_range <= range @[el2_ifu_ifc_ctrl.scala 143:15]
+    

test.v

@@ -0,0 +1,10 @@
+module test(
+  input         clock,
+  input         reset,
+  input  [31:0] io_addr,
+  output        io_in_range,
+  output        io_in_region
+);
+  assign io_in_range = io_addr[31:28] == 4'he; // @[el2_ifu_ifc_ctrl.scala 143:15]
+  assign io_in_region = io_addr[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 142:16]
+endmodule