Bus-buffer testing start
This commit is contained in:
waleed-lm
parent
23a61528a4
commit
b4a84e2c47
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@ -0,0 +1,175 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_lo",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_hi",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_buffer_full_any",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_d",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_dec_lsu_valid_raw_d"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_valid_m",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_full_hit_m",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_m_load",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_flush_m_up",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_m_valid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_trxn",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arvalid",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arready",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awvalid",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awready",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wvalid",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_hi",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_valid",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_addr_any",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_tag",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_inv_r",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_commit_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_load_any",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_lo",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_misaligned",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_commit_r",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_busy",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arvalid",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awvalid",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wvalid",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arready",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awready",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_error",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_load_any",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_tag"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_tag_m",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"el2_lsu_bus_buffer.TEC_RV_ICG",
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"resourceId":"/vsrc/TEC_RV_ICG.v"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"el2_lsu_bus_buffer"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -169,19 +169,19 @@ class el2_alu_pkt_t extends Bundle {
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}
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}
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class el2_lsu_pkt_t extends Bundle {
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class el2_lsu_pkt_t extends Bundle {
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val fast_int = UInt(1.W)
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val fast_int = Bool()
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val by = UInt(1.W)
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val by = Bool()
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val half = UInt(1.W)
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val half = Bool()
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val word = UInt(1.W)
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val word = Bool()
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val dword = UInt(1.W) // for dma
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val dword = Bool() // for dma
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val load = UInt(1.W)
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val load = Bool()
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val store = UInt(1.W)
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val store = Bool()
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val unsign = UInt(1.W)
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val unsign = Bool()
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val dma = UInt(1.W) // dma pkt
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val dma = Bool() // dma pkt
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val store_data_bypass_d = UInt(1.W)
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val store_data_bypass_d = Bool()
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val load_ldst_bypass_d = UInt(1.W)
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val load_ldst_bypass_d = Bool()
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val store_data_bypass_m = UInt(1.W)
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val store_data_bypass_m = Bool()
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val valid = UInt(1.W)
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val valid = Bool()
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}
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}
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class el2_lsu_error_pkt_t extends Bundle {
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class el2_lsu_error_pkt_t extends Bundle {
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@ -1,9 +1,8 @@
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/* package lsu
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package lsu
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import chisel3._
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import chisel3._
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import chisel3.util._
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import chisel3.util._
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import lib._
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import lib._
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import include._
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import include._
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import snapshot._
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import chisel3.experimental.{ChiselEnum, chiselName}
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import chisel3.experimental.{ChiselEnum, chiselName}
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import chisel3.util.ImplicitConversions.intToUInt
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import chisel3.util.ImplicitConversions.intToUInt
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@ -108,6 +107,8 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
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val lsu_axi_rready = Output(Bool())
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val lsu_axi_rready = Output(Bool())
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})
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})
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def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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val DEPTH = LSU_NUM_NBLOAD
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val DEPTH = LSU_NUM_NBLOAD
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val DEPTH_LOG2 = LSU_NUM_NBLOAD_WIDTH
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val DEPTH_LOG2 = LSU_NUM_NBLOAD_WIDTH
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@ -127,20 +128,73 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
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val ld_addr_hitvec_lo = (0 until DEPTH).map(i => (io.lsu_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m)
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val ld_addr_hitvec_lo = (0 until DEPTH).map(i => (io.lsu_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m)
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val ld_addr_hitvec_hi = (0 until DEPTH).map(i => (io.end_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m)
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val ld_addr_hitvec_hi = (0 until DEPTH).map(i => (io.end_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m)
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val ld_byte_hitvecfn_lo = Wire(Vec(4, UInt(DEPTH.W)))
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val ld_byte_hitvecfn_lo = Wire(Vec(4, UInt(DEPTH.W)))
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val ld_byte_ibuf_hit_lo = WireInit(UInt(4.W))
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val ld_byte_ibuf_hit_lo = WireInit(UInt(4.W), 0.U)
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val ld_byte_hitvecfn_hi = Wire(Vec(4, UInt(DEPTH.W)))
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val ld_byte_hitvecfn_hi = Wire(Vec(4, UInt(DEPTH.W)))
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val ld_byte_ibuf_hit_hi = WireInit(UInt(4.W))
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val ld_byte_ibuf_hit_hi = WireInit(UInt(4.W), 0.U)
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val buf_byteen = Wire(Vec(DEPTH, UInt(4.W)))
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val buf_byteen = Wire(Vec(DEPTH, UInt(4.W)))
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buf_byteen := buf_byteen.map(i=>0.U)
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val buf_nxtstate = Wire(Vec(DEPTH, UInt(3.W)))
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buf_nxtstate := buf_nxtstate.map(i=>0.U)
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val buf_wr_en = Wire(Vec(DEPTH, Bool()))
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buf_wr_en := buf_wr_en.map(i=> false.B)
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val buf_data_en = Wire(Vec(DEPTH, Bool()))
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buf_data_en := buf_data_en.map(i=> false.B)
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val buf_state_bus_en = Wire(Vec(DEPTH, Bool()))
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buf_state_bus_en := buf_state_bus_en.map(i=> false.B)
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val buf_ldfwd_in = Wire(Vec(DEPTH, Bool()))
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buf_ldfwd_in := buf_ldfwd_in.map(i=> false.B)
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val buf_ldfwd_en = Wire(Vec(DEPTH, Bool()))
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buf_ldfwd_en := buf_ldfwd_en.map(i=> false.B)
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val buf_data_in = Wire(Vec(DEPTH, UInt(DEPTH.W)))
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buf_data_in := buf_data_in.map(i=> 0.U)
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val buf_ldfwdtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W)))
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buf_ldfwdtag_in := buf_ldfwdtag_in.map(i=> 0.U)
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val buf_error_en = Wire(Vec(DEPTH, Bool()))
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buf_error_en := buf_error_en.map(i=> false.B)
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val bus_rsp_read_error = WireInit(Bool(), false.B)
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val bus_rsp_rdata = WireInit(UInt(64.W), 0.U)
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val bus_rsp_write_error = WireInit(Bool(), false.B)
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val buf_dualtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W)))
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buf_dualtag := buf_dualtag.map(i=> 0.U)
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val buf_ldfwd = WireInit(UInt(DEPTH.W), 0.U)
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val buf_resp_state_bus_en = Wire(Vec(DEPTH, Bool()))
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buf_resp_state_bus_en := buf_resp_state_bus_en.map(i=> false.B)
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val any_done_wait_state = WireInit(Bool(), false.B)
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val bus_rsp_write = WireInit(Bool(), false.B)
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||||||
|
val bus_rsp_write_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U)
|
||||||
|
val buf_ldfwdtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W)))
|
||||||
|
buf_ldfwdtag := buf_ldfwdtag.map(i=> 0.U)
|
||||||
|
val buf_rst = Wire(Vec(DEPTH, Bool()))
|
||||||
|
buf_rst := buf_rst.map(i=> false.B)
|
||||||
|
val ibuf_drainvec_vld = WireInit(UInt(DEPTH.W), 0.U)
|
||||||
|
val buf_byteen_in = Wire(Vec(DEPTH, UInt(3.W)))
|
||||||
|
buf_byteen_in := buf_byteen_in.map(i=> 0.U)
|
||||||
|
val buf_addr_in = Wire(Vec(DEPTH, UInt(32.W)))
|
||||||
|
buf_addr_in := buf_addr_in.map(i=> 0.U)
|
||||||
|
val buf_dual_in = WireInit(UInt(DEPTH.W), 0.U)
|
||||||
|
val buf_samedw_in = WireInit(UInt(DEPTH.W), 0.U)
|
||||||
|
val buf_nomerge_in = WireInit(UInt(DEPTH.W), 0.U)
|
||||||
|
val buf_dualhi_in = WireInit(UInt(DEPTH.W), 0.U)
|
||||||
|
val buf_dualtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W)))
|
||||||
|
buf_dualtag_in := buf_dualtag_in.map(i=> 0.U)
|
||||||
|
val buf_sideeffect_in = WireInit(UInt(DEPTH.W), 0.U)
|
||||||
|
val buf_unsign_in = WireInit(UInt(DEPTH.W), 0.U)
|
||||||
|
val buf_sz_in = Wire(Vec(DEPTH, UInt(2.W)))
|
||||||
|
buf_sz_in := buf_sz_in.map(i=> 0.U)
|
||||||
|
val buf_write_in = WireInit(UInt(DEPTH.W), 0.U)
|
||||||
|
val buf_unsign = WireInit(UInt(DEPTH.W), 0.U)
|
||||||
|
val buf_error = WireInit(UInt(DEPTH.W), 0.U)
|
||||||
|
|
||||||
io.ld_byte_hit_buf_lo := (0 until 4).map(i => ld_byte_hitvecfn_lo(i).orR | ld_byte_ibuf_hit_lo(i)).reverse.reduce(Cat(_, _))
|
io.ld_byte_hit_buf_lo := (0 until 4).map(i => (ld_byte_hitvecfn_lo(i).orR | ld_byte_ibuf_hit_lo(i)).asUInt).reverse.reduce(Cat(_, _))
|
||||||
io.ld_byte_hit_buf_hi := (0 until 4).map(i => ld_byte_hitvecfn_hi(i).orR | ld_byte_ibuf_hit_hi(i)).reverse.reduce(Cat(_, _))
|
io.ld_byte_hit_buf_hi := (0 until 4).map(i => (ld_byte_hitvecfn_hi(i).orR | ld_byte_ibuf_hit_hi(i)).asUInt).reverse.reduce(Cat(_, _))
|
||||||
|
|
||||||
val ld_byte_hitvec_lo = (0 until 4).map(j => (0 until DEPTH).map(i => ld_addr_hitvec_lo(i) & buf_byteen(i)(j) & ldst_byteen_lo_m(j)).reverse.reduce(Cat(_, _)))
|
val ld_byte_hitvec_lo = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_lo(i) & buf_byteen(i)(j) & ldst_byteen_lo_m(j)).asUInt).reverse.reduce(Cat(_, _)))
|
||||||
val ld_byte_hitvec_hi = (0 until 4).map(j => (0 until DEPTH).map(i => ld_addr_hitvec_hi(i) & buf_byteen(i)(j) & ldst_byteen_hi_m(j)).reverse.reduce(Cat(_, _)))
|
val ld_byte_hitvec_hi = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_hi(i) & buf_byteen(i)(j) & ldst_byteen_hi_m(j)).asUInt).reverse.reduce(Cat(_, _)))
|
||||||
|
|
||||||
val buf_age_younger = Wire(Vec(DEPTH, UInt(DEPTH.W)))
|
val buf_age_younger = Wire(Vec(DEPTH, UInt(DEPTH.W)))
|
||||||
ld_byte_hitvecfn_lo := (0 until 4).map(j => (0 until DEPTH).map(i => ld_byte_hitvec_lo(j)(i) & !(ld_byte_hitvec_lo(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_lo(j)).reverse.reduce(Cat(_, _)))
|
buf_age_younger := buf_age_younger.map(i=> 0.U)
|
||||||
ld_byte_hitvecfn_hi := (0 until 4).map(j => (0 until DEPTH).map(i => ld_byte_hitvec_hi(j)(i) & !(ld_byte_hitvec_hi(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_hi(j)).reverse.reduce(Cat(_, _)))
|
ld_byte_hitvecfn_lo := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_lo(j)(i) & !(ld_byte_hitvec_lo(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_lo(j)).asUInt).reverse.reduce(Cat(_, _)))
|
||||||
|
ld_byte_hitvecfn_hi := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_hi(j)(i) & !(ld_byte_hitvec_hi(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_hi(j)).asUInt).reverse.reduce(Cat(_, _)))
|
||||||
|
|
||||||
val ibuf_addr = WireInit(UInt(32.W), 0.U)
|
val ibuf_addr = WireInit(UInt(32.W), 0.U)
|
||||||
val ibuf_write = WireInit(Bool(), false.B)
|
val ibuf_write = WireInit(Bool(), false.B)
|
||||||
|
|
@ -154,8 +208,8 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
||||||
ld_byte_ibuf_hit_hi := ld_addr_ibuf_hit_hi & ibuf_byteen(i) & ldst_byteen_hi_m(i)
|
ld_byte_ibuf_hit_hi := ld_addr_ibuf_hit_hi & ibuf_byteen(i) & ldst_byteen_hi_m(i)
|
||||||
}
|
}
|
||||||
val buf_data = Wire(Vec(DEPTH, UInt(32.W)))
|
val buf_data = Wire(Vec(DEPTH, UInt(32.W)))
|
||||||
|
buf_data := buf_data.map(i=> 0.U)
|
||||||
val fwd_data = WireInit(UInt(32.W))
|
val fwd_data = WireInit(UInt(32.W), 0.U)
|
||||||
|
|
||||||
io.ld_fwddata_buf_lo := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(3)(i)) & buf_data(i)(31, 23)).reduce(_ | _),
|
io.ld_fwddata_buf_lo := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(3)(i)) & buf_data(i)(31, 23)).reduce(_ | _),
|
||||||
(0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _),
|
(0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _),
|
||||||
|
|
@ -190,7 +244,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
||||||
val ibuf_timer = WireInit(UInt(TIMER_LOG2.W), 0.U)
|
val ibuf_timer = WireInit(UInt(TIMER_LOG2.W), 0.U)
|
||||||
val ibuf_merge_en = WireInit(Bool(), false.B)
|
val ibuf_merge_en = WireInit(Bool(), false.B)
|
||||||
val ibuf_merge_in = WireInit(Bool(), false.B)
|
val ibuf_merge_in = WireInit(Bool(), false.B)
|
||||||
val ibuf_drain_vld = ibuf_valid & (((ibuf_wr_en | (ibuf_timer === TIMER_MAX.U)) & !(ibuf_merge_en & ibuf_merge_in))
|
ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === TIMER_MAX.U)) & !(ibuf_merge_en & ibuf_merge_in))
|
||||||
| ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable)
|
| ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable)
|
||||||
val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
||||||
val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
||||||
|
|
@ -206,430 +260,378 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
||||||
|
|
||||||
val ibuf_data_in = (0 until 4).map(i => Mux(ibuf_merge_en & ibuf_merge_in,
|
val ibuf_data_in = (0 until 4).map(i => Mux(ibuf_merge_en & ibuf_merge_in,
|
||||||
Mux(ldst_byteen_lo_r(i), store_data_lo_r((8 * i) + 7, 8 * i), ibuf_data((8 * i) + 7, 8 * i)), ibuf_data((8 * i) + 7, 8 * i))).reverse.reduce(Cat(_, _))
|
Mux(ldst_byteen_lo_r(i), store_data_lo_r((8 * i) + 7, 8 * i), ibuf_data((8 * i) + 7, 8 * i)), ibuf_data((8 * i) + 7, 8 * i))).reverse.reduce(Cat(_, _))
|
||||||
|
val ibuf_timer_in = Mux(ibuf_wr_en, 0.U, Mux((ibuf_timer<TIMER_MAX.U).asBool(), ibuf_timer+1.U, ibuf_timer))
|
||||||
|
|
||||||
//ibuf_valid := RegEnable(true.B, false.B, )
|
ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.store & ibuf_valid & ibuf_write & (io.lsu_addr_r(31,2) === ibuf_addr(31,2)) & !io.is_sideeffects_r & !bus_coalescing_disable
|
||||||
ibuf_tag := RegEnable(ibuf_tag_in, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())
|
ibuf_merge_in := !io.ldst_dual_r
|
||||||
val ibuf_dualtag = RegEnable(ibuf_dualtag_in, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())
|
val ibuf_byteen_out = (0 until 4).map(i=>(Mux(ibuf_merge_en & !ibuf_merge_in, ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_))
|
||||||
val ibuf_dual = RegEnable(io.ldst_dual_r, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())
|
val ibuf_data_out = (0 until 4).map(i=>Mux(ibuf_merge_en & !ibuf_merge_in, Mux(ldst_byteen_lo_r(i), store_data_lo_r((8*i)+7, 8*i), ibuf_data((8*i)+7, 8*i)), ibuf_data((8*i)+7, 8*i))).reverse.reduce(Cat(_,_))
|
||||||
val ibuf_samedw = RegEnable(ldst_samedw_r, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())
|
|
||||||
val ibuf_nomerge = RegEnable(io.no_dword_merge_r, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())
|
ibuf_valid := RegNext(Mux(ibuf_wr_en, true.B, ibuf_valid) & ibuf_rst, false.B)
|
||||||
ibuf_sideeffect := RegEnable(io.is_sideeffects_r, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())
|
ibuf_tag := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_tag_in, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())}
|
||||||
val ibuf_unsign = RegEnable(io.lsu_pkt_r.unsign, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())
|
val ibuf_dualtag = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_dualtag_in, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())}
|
||||||
ibuf_write := rvdffe(btb_lru_b0_ns, 0.U, io.ifc_fetch_req_f | io.exu_mp_valid)
|
val ibuf_dual = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.ldst_dual_r, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())}
|
||||||
}*/
|
val ibuf_samedw = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ldst_samedw_r, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())}
|
||||||
////
|
val ibuf_nomerge = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.no_dword_merge_r, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())}
|
||||||
////
|
ibuf_sideeffect := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.is_sideeffects_r, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())}
|
||||||
////
|
val ibuf_unsign = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.unsign, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())}
|
||||||
////
|
ibuf_write := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.store, 0.U, ibuf_wr_en)}
|
||||||
////
|
val ibuf_sz = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_sz_in, 0.U, ibuf_wr_en)}
|
||||||
////
|
ibuf_addr := rvdffe(ibuf_addr_in, ibuf_wr_en, clock, io.scan_mode)
|
||||||
////
|
ibuf_byteen := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_byteen_in, 0.U, ibuf_wr_en)}
|
||||||
////
|
ibuf_data := rvdffe(ibuf_data_in, ibuf_wr_en, clock, io.scan_mode)
|
||||||
//// //Forwarding MUX
|
ibuf_timer := withClock(io.lsu_bus_ibuf_c1_clk) {RegNext(ibuf_timer_in, 0.U)}
|
||||||
//// io.ld_fwddata_buf_lo := (0 until 4).map(i =>(Mux(ld_byte_ibuf_hit_lo(i),ibuf_data(i*8+7,i*8),Mux1H((0 until DEPTH).map(j =>(ld_byte_hitvecfn_lo(i)(j)) -> buf_data(j)(i*8+7,i*8)))))).reverse.reduce(Cat(_,_))
|
val buf_numvld_wrcmd_any = WireInit(UInt(4.W), 0.U)
|
||||||
//// io.ld_fwddata_buf_hi := (0 until 4).map(i =>(Mux(ld_byte_ibuf_hit_hi(i),ibuf_data(i*8+7,i*8),Mux1H((0 until DEPTH).map(j =>(ld_byte_hitvecfn_hi(i)(j)) -> buf_data(j)(i*8+7,i*8)))))).reverse.reduce(Cat(_,_))
|
val buf_numvld_cmd_any = WireInit(UInt(4.W), 0.U)
|
||||||
////
|
val obuf_wr_timer = WireInit(UInt(TIMER_LOG2.W), 0.U)
|
||||||
//// /////////////////////////////////////////////////////////////////////////////
|
val buf_nomerge = Wire(Vec(DEPTH, Bool()))
|
||||||
//// bus_coalescing_disable := io.dec_tlu_wb_coalescing_disable | pt.BUILD_AHB_LITE
|
buf_nomerge := buf_nomerge.map(i=> false.B)
|
||||||
//// ldst_byteen_r := Mux1H(Seq(
|
val Cmdptr0 = WireInit(UInt(LSU_NUM_NBLOAD_WIDTH.W), 0.U)
|
||||||
//// io.lsu_pkt_r.word.asBool -> 15.U(4.W),
|
val buf_sideeffect = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
|
||||||
//// io.lsu_pkt_r.half.asBool -> 3.U(4.W),
|
val obuf_force_wr_en = WireInit(Bool(), false.B)
|
||||||
//// io.lsu_pkt_r.by.asBool -> 1.U(4.W)
|
val obuf_wr_en = WireInit(Bool(), false.B)
|
||||||
//// ))
|
val obuf_wr_wait = (buf_numvld_wrcmd_any===1.U) & (buf_numvld_cmd_any===1.U) & (obuf_wr_timer =/= TIMER_MAX.U) &
|
||||||
//// val ldst_byteen_extended_r = Cat(Fill(4,0.U),ldst_byteen_r(3,0)) << io.lsu_addr_r(1,0)
|
!bus_coalescing_disable & !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(Cmdptr0===i.U)->buf_nomerge(i))) &
|
||||||
//// val store_data_extended_r = Cat(Fill(32,0.U),io.store_data_r(31,0)) << (8.U*io.lsu_addr_r(1,0))
|
!Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(Cmdptr0===i.U)->buf_sideeffect(i))) & !obuf_force_wr_en
|
||||||
//// ldst_byteen_hi_r := ldst_byteen_extended_r(7,4)
|
val obuf_wr_timer_in = Mux(obuf_wr_en, 0.U(3.W), Mux(buf_numvld_cmd_any.orR & (obuf_wr_timer<TIMER_MAX), obuf_wr_timer+1.U, obuf_wr_timer))
|
||||||
//// ldst_byteen_lo_r := ldst_byteen_extended_r(3,0)
|
obuf_force_wr_en := io.lsu_busreq_m & !io.lsu_busreq_r & !ibuf_valid & (buf_numvld_cmd_any===1.U) & (io.lsu_addr_m(31,2)=/=Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(Cmdptr0===i.U)->buf_addr(i)(31,2))))
|
||||||
//// store_data_hi_r := store_data_extended_r(63,32)
|
val buf_numvld_pend_any = WireInit(UInt(4.W), 0.U)
|
||||||
//// store_data_lo_r := store_data_extended_r(31, 0)
|
val ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any===0.U) & (!io.lsu_pkt_r.store | io.no_dword_merge_r)
|
||||||
//// ldst_samedw_r := io.lsu_addr_r(3) === io.end_addr_r(3)
|
val bus_sideeffect_pend = WireInit(Bool(), false.B)
|
||||||
//// is_aligned_r := Mux1H(Seq(
|
val found_cmdptr0 = WireInit(Bool(), false.B)
|
||||||
//// io.lsu_pkt_r.by.asBool -> true.B,
|
val buf_cmd_state_bus_en = Wire(Vec(DEPTH, Bool()))
|
||||||
//// io.lsu_pkt_r.half.asBool -> (io.lsu_addr_r(0).asUInt === 0.U),
|
buf_cmd_state_bus_en := buf_cmd_state_bus_en.map(i=> false.B)
|
||||||
//// io.lsu_pkt_r.word.asBool -> (io.lsu_addr_r(1,0).asUInt === 0.U)
|
val buf_dual = Wire(Vec(DEPTH, Bool()))
|
||||||
//// ))
|
buf_dual := buf_dual.map(i=> false.B)
|
||||||
//// ////////////////////////////////////////////////////////////////////////////
|
val buf_samedw = Wire(Vec(DEPTH, Bool()))
|
||||||
//// ibuf_byp := (io.lsu_busreq_r & (io.lsu_pkt_r.load | io.no_word_merge_r) & !ibuf_valid).asBool
|
buf_samedw := buf_samedw.map(i=> false.B)
|
||||||
//// ibuf_wr_en := (io.lsu_busreq_r & io.lsu_commit_r & !ibuf_byp).asBool
|
val found_cmdptr1 = WireInit(Bool(), false.B)
|
||||||
//// ibuf_rst := ((ibuf_drain_vld & !ibuf_wr_en) | io.dec_tlu_force_halt).asBool
|
val bus_cmd_ready = WireInit(Bool(), false.B)
|
||||||
//// ibuf_force_drain := (io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.load | (ibuf_addr(31,2) =/= io.lsu_addr_m(31,2)))).asBool
|
val obuf_valid = WireInit(Bool(), false.B)
|
||||||
//// ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === (TIMER_MAX.asUInt(TIMER_LOG2.W)))) & !(ibuf_merge_en & ibuf_merge_in)) |
|
val obuf_nosend = WireInit(Bool(), false.B)
|
||||||
//// ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable)
|
val lsu_bus_cntr_overflow = WireInit(Bool(), false.B)
|
||||||
//// ibuf_tag_in := Mux((ibuf_merge_en & ibuf_merge_in), ibuf_tag(DEPTH_LOG2-1,0),Mux(io.ldst_dual_r,WrPtr1_r,WrPtr0_r))
|
val bus_addr_match_pending = WireInit(Bool(), false.B)
|
||||||
//// ibuf_dualtag_in := WrPtr0_r(DEPTH_LOG2-1,0)
|
obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & !(io.is_sideeffects_r & bus_sideeffect_pend)) |
|
||||||
//// ibuf_sz_in := Cat(io.lsu_pkt_r.word,io.lsu_pkt_r.half)
|
((Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(Cmdptr0===1.U)->buf_state(i))) === cmd_C) &
|
||||||
//// ibuf_addr_in := Mux(io.ldst_dual_r,io.end_addr_r,io.lsu_addr_r)
|
found_cmdptr0 & !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) & !(indexing(buf_sideeffect, Cmdptr0) & bus_sideeffect_pend) &
|
||||||
//// ibuf_byteen_in := Mux(ibuf_merge_en & ibuf_merge_in, ibuf_byteen(3,0) | ldst_byteen_lo_r(3,0), Mux(io.ldst_dual_r, ldst_byteen_hi_r(3,0), ldst_byteen_lo_r(3,0)))
|
(!(indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) & !indexing(buf_write, Cmdptr0)) | found_cmdptr1 | indexing(buf_nomerge.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) |
|
||||||
//// ibuf_data_in := (0 until 4).map(i =>(Mux((ibuf_merge_en & ibuf_merge_in),Mux(ldst_byteen_lo_r(i),store_data_lo_r((8*i)+7,(8*i)) , ibuf_data((8*i)+7,(8*i))),Mux(io.ldst_dual_r, store_data_hi_r((8*i)+7,(8*i)), store_data_lo_r((8*i)+7,(8*i)))))).reverse.reduce(Cat(_,_))
|
obuf_force_wr_en))) & (bus_cmd_ready | !obuf_valid | obuf_nosend) & !obuf_wr_wait & !lsu_bus_cntr_overflow & !bus_addr_match_pending & io.lsu_bus_clk_en
|
||||||
//// ibuf_timer_in := Mux(ibuf_wr_en, 0.U, Mux(ibuf_timer < (TIMER_MAX.asUInt(TIMER_LOG2.W)), ibuf_timer+1.U, ibuf_timer))
|
val bus_cmd_sent = WireInit(Bool(), false.B)
|
||||||
//// ibuf_byteen_out := (0 until 4).map(i =>(Mux((ibuf_merge_en & ~ibuf_merge_in),ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_))
|
val obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & !obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
|
||||||
//// ibuf_data_out := (0 until 4).map(i =>(Mux((ibuf_merge_en & ~ibuf_merge_in),Mux(ldst_byteen_lo_r(i),store_data_lo_r((8*i)+7,(8*i)) , ibuf_data((8*i)+7,(8*i))),ibuf_data(i*8+7,i*8)))).reverse.reduce(Cat(_,_))
|
val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.store, indexing(buf_write, Cmdptr0))
|
||||||
//// ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.store & ibuf_valid & ibuf_write & io.lsu_addr_r(31,2)===ibuf_addr(31,2) & ~io.is_sideeffects_r & ~bus_coalescing_disable
|
val obuf_sideeffect_in = Mux(ibuf_buf_byp, io.is_sideeffects_r, indexing(buf_sideeffect, Cmdptr0))
|
||||||
//// ibuf_merge_in := ~io.ldst_dual_r.asUInt()
|
val obuf_addr_in = Mux(ibuf_buf_byp, io.lsu_addr_r, indexing(buf_addr, Cmdptr0))
|
||||||
////
|
val buf_sz = Wire(Vec(DEPTH, UInt(2.W)))
|
||||||
//// withClock(io.lsu_free_c2_clk){
|
buf_sz := buf_sz.map(i=> 0.U)
|
||||||
//// ibuf_valid := RegNext(Mux(ibuf_wr_en.asBool(),1.U ,ibuf_valid) & !ibuf_rst, false.B)
|
val obuf_sz_in = Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half), indexing(buf_sz, Cmdptr0))
|
||||||
//// ibuf_timer := RegNext(ibuf_timer_in ,init = 0.U)
|
val obuf_merge_en = WireInit(Bool(), false.B)
|
||||||
//// }
|
val obuf_merge_in = obuf_merge_en
|
||||||
//// withClock(io.lsu_bus_ibuf_c1_clk) {
|
val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, Cmdptr0)
|
||||||
//// ibuf_dual := RegEnable(io.ldst_dual_r ,init = 0.U, ibuf_wr_en)
|
val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
||||||
//// ibuf_samedw := RegEnable(ldst_samedw_r ,init = 0.U, ibuf_wr_en)
|
val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, Cmdptr1)
|
||||||
//// ibuf_nomerge := RegEnable(io.no_dword_merge_r ,init = 0.U, ibuf_wr_en)
|
val obuf_cmd_done = WireInit(Bool(), false.B)
|
||||||
//// ibuf_sideeffect := RegEnable(io.is_sideeffects_r ,init = 0.U, ibuf_wr_en)
|
val bus_wcmd_sent = WireInit(Bool(), false.B)
|
||||||
//// ibuf_unsign := RegEnable(io.lsu_pkt_r.unsign ,init = 0.U, ibuf_wr_en)
|
val obuf_cmd_done_in = !(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent)
|
||||||
//// ibuf_write := RegEnable(io.lsu_pkt_r.store ,init = 0.U, ibuf_wr_en)
|
val obuf_data_done = WireInit(Bool(), false.B)
|
||||||
//// ibuf_sz := RegEnable(ibuf_sz_in(1, 0) ,init = 0.U, ibuf_wr_en)
|
val bus_wdata_sent = WireInit(Bool(), false.B)
|
||||||
//// ibuf_byteen := RegEnable(ibuf_byteen_in ,init = 0.U, ibuf_wr_en)
|
val obuf_data_done_in = !(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent)
|
||||||
//// ibuf_addr := RegEnable(ibuf_addr_in(31, 0) ,init = 0.U, ibuf_wr_en)
|
val obuf_aligned_in = Mux(ibuf_buf_byp, is_aligned_r, obuf_sz_in(1,0)===0.U | (obuf_sz_in(0) & !obuf_addr_in(0)) | (obuf_sz_in(1)&(!obuf_addr_in(1,0).orR)))
|
||||||
//// ibuf_data := RegEnable(ibuf_data_in(31, 0) ,init = 0.U, ibuf_wr_en)
|
|
||||||
//// ibuf_tag := RegEnable(ibuf_tag_in ,init = 0.U, ibuf_wr_en)
|
val obuf_nosend_in = WireInit(Bool(), false.B)
|
||||||
//// ibuf_dualtag := RegEnable(ibuf_dualtag_in ,init = 0.U, ibuf_wr_en)
|
val obuf_rdrsp_pend = WireInit(Bool(), false.B)
|
||||||
//// }
|
val bus_rsp_read = WireInit(Bool(), false.B)
|
||||||
//// ///////////////////////////////////////////////////////////////////////////////////////
|
val bus_rsp_read_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U)
|
||||||
////
|
val obuf_rdrsp_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U)
|
||||||
//// ibuf_buf_byp := (ibuf_byp & (buf_numvld_pend_any(3,0) === 0.U) & (~io.lsu_pkt_r.store | io.no_dword_merge_r))
|
val obuf_write = WireInit(Bool(), false.B)
|
||||||
//// obuf_force_wr_en := io.lsu_busreq_m & ~io.lsu_busreq_r & ~ibuf_valid & (buf_numvld_cmd_any(3,0) === 1.U(4.W)) & (io.lsu_addr_m(31,2) =/= buf_addr(CmdPtr0)(31,2))
|
val obuf_rdrsp_pend_in = (!(obuf_wr_en & !obuf_nosend_in) & obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) |
|
||||||
//// obuf_wr_wait := (buf_numvld_wrcmd_any(3,0) === 1.U(4.W)) & (buf_numvld_cmd_any(3,0) === 1.U(4.W)) & (obuf_wr_timer =/= (TIMER_MAX.asUInt(TIMER_LOG2.W))) &
|
((bus_cmd_sent & !obuf_write) & !io.dec_tlu_force_halt)
|
||||||
//// ~bus_coalescing_disable & ~buf_nomerge(CmdPtr0) & ~buf_sideeffect(CmdPtr0) & ~obuf_force_wr_en
|
val obuf_tag0 = WireInit(UInt(LSU_BUS_TAG.W), 0.U)
|
||||||
//// obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & ~(io.is_sideeffects_r & bus_sideeffect_pend)) |
|
val obuf_rdrsp_tag_in = Mux(bus_cmd_sent | !obuf_write, obuf_tag0, obuf_rdrsp_tag)
|
||||||
//// ((buf_state(CmdPtr0) === cmd_C) & found_cmdptr0 & ~buf_cmd_state_bus_en(CmdPtr0) & ~(buf_sideeffect(CmdPtr0) & bus_sideeffect_pend) &
|
val obuf_addr = WireInit(UInt(32.W), 0.U)
|
||||||
//// (~(buf_dual(CmdPtr0) & buf_samedw(CmdPtr0) & ~buf_write(CmdPtr0)) | found_cmdptr1 | buf_nomerge(CmdPtr0) | obuf_force_wr_en))) &
|
val obuf_sideeffect = WireInit(Bool(), false.B)
|
||||||
//// (bus_cmd_ready | ~obuf_valid | obuf_nosend) & ~obuf_wr_wait & ~lsu_bus_cntr_overflow & ~bus_addr_match_pending & io.lsu_bus_clk_en
|
obuf_nosend_in := (obuf_addr_in(31,3)===obuf_addr(31,3)) & obuf_aligned_in & !obuf_sideeffect & !obuf_write & !obuf_write_in & !io.dec_tlu_external_ldfwd_disable &
|
||||||
//// obuf_rst := ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & ~obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
|
((obuf_valid & !obuf_nosend) | (obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))))
|
||||||
//// obuf_write_in := Mux(ibuf_buf_byp, io.lsu_pkt_r.store, buf_write(CmdPtr0))
|
val obuf_byteen0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_lo_r)),
|
||||||
//// obuf_nosend_in := (obuf_addr_in(31,3) === obuf_addr(31,3)) & obuf_aligned_in & ~obuf_sideeffect & ~obuf_write & ~obuf_write_in & ~io.dec_tlu_external_ldfwd_disable &
|
Mux(indexing(buf_addr, Cmdptr0)(2).asBool(), Cat(indexing(buf_byteen, Cmdptr0), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, Cmdptr0))))
|
||||||
//// ((obuf_valid & ~obuf_nosend) | (obuf_rdrsp_pend & ~(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))))
|
val obuf_byteen1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_hi_r)),
|
||||||
//// obuf_rdrsp_pend_in := (~(obuf_wr_en & ~obuf_nosend_in) & obuf_rdrsp_pend & ~(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) | ((bus_cmd_sent & ~obuf_write) & ~io.dec_tlu_force_halt)
|
Mux(indexing(buf_addr, Cmdptr1)(2).asBool(), Cat(indexing(buf_byteen, Cmdptr1), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, Cmdptr1))))
|
||||||
//// obuf_sideeffect_in := Mux(ibuf_buf_byp, io.is_sideeffects_r, buf_sideeffect(CmdPtr0))
|
|
||||||
//// obuf_aligned_in := Mux(ibuf_buf_byp, is_aligned_r, (obuf_sz_in(1,0) === 0.U(2.W) | (obuf_sz_in(0) & ~obuf_addr_in(0)) | (obuf_sz_in(1) & ~(obuf_addr_in(1,0).orR))))
|
val obuf_data0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r, 0.U(32.W)), Cat(0.U(32.W), store_data_lo_r)),
|
||||||
//// obuf_addr_in := Mux(ibuf_buf_byp, io.lsu_addr_r, buf_addr(CmdPtr0))
|
Mux(indexing(buf_addr, Cmdptr0)(2).asBool(), Cat(indexing(buf_data, Cmdptr0), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, Cmdptr0))))
|
||||||
//// obuf_data_in := (0 until 8).map(i =>(Mux((obuf_merge_en & obuf_byteen1_in(i)),obuf_data1_in((8*i)+7,(8*i)), obuf_data0_in((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
|
val obuf_data1_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_hi_r, 0.U(32.W)), Cat(0.U(32.W), store_data_hi_r)),
|
||||||
//// obuf_sz_in := Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.word,io.lsu_pkt_r.half), buf_sz(CmdPtr0))
|
Mux(indexing(buf_addr, Cmdptr1)(2).asBool(), Cat(indexing(buf_data, Cmdptr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, Cmdptr1))))
|
||||||
//// obuf_byteen_in := (0 until 8).map(i =>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_))
|
val obuf_byteen_in = (0 until 8).map(i=>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_))
|
||||||
//// obuf_merge_in := obuf_merge_en
|
val obuf_data_in = (0 until 8).map(i=>Mux(obuf_merge_en & obuf_byteen1_in(i), obuf_data1_in((8*i)+7, 8*i), obuf_data1_in((8*i)+7, 8*i))).reverse.reduce(Cat(_,_))
|
||||||
//// obuf_cmd_done_in := ~(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent )
|
val buf_dualhi = Wire(Vec(DEPTH, Bool()))
|
||||||
//// obuf_data_done_in := ~(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent)
|
buf_dualhi := buf_dualhi.map(i=> false.B)
|
||||||
//// obuf_tag0_in := Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0)
|
obuf_merge_en := ((Cmdptr0 =/= Cmdptr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, Cmdptr0) === cmd_C) & (indexing(buf_state, Cmdptr1) === cmd_C) &
|
||||||
//// obuf_tag1_in := Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr0)
|
!indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) & !indexing(buf_sideeffect, Cmdptr0) &
|
||||||
//// obuf_rdrsp_tag_in := Mux((bus_cmd_sent & ~obuf_write), obuf_tag0(pt1.LSU_BUS_TAG-1,0), obuf_rdrsp_tag(pt1.LSU_BUS_TAG-1,0))
|
((indexing(buf_write, Cmdptr0) & indexing(buf_write, Cmdptr1) &
|
||||||
////
|
(indexing(buf_addr, Cmdptr0)(31,3)===indexing(buf_addr, Cmdptr1)(31,3)) & !bus_coalescing_disable & !BUILD_AXI_NATIVE.B) |
|
||||||
//// obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (buf_state(CmdPtr0) === cmd_C) & (buf_state(CmdPtr1) === cmd_C) &
|
(!indexing(buf_write, Cmdptr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0)))) |
|
||||||
//// ~buf_cmd_state_bus_en(CmdPtr0) & ~buf_sideeffect(CmdPtr0) &
|
(ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r)
|
||||||
//// ((buf_write(CmdPtr0) & buf_write(CmdPtr1) & (buf_addr(CmdPtr0)(31,3) === buf_addr(CmdPtr1)(31,3)) & ~bus_coalescing_disable & ~pt.BUILD_AXI_NATIVE) |
|
|
||||||
//// (~buf_write(CmdPtr0) & buf_dual(CmdPtr0) & ~buf_dualhi(CmdPtr0) & buf_samedw(CmdPtr0)))) |
|
val obuf_wr_enQ = withClock(io.lsu_busm_clk){RegNext(obuf_wr_en, false.B)}
|
||||||
//// (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r)
|
obuf_valid := withClock(io.lsu_busm_clk){RegNext(Mux(obuf_wr_en, true.B, obuf_valid) & obuf_rst, false.B)}
|
||||||
//// obuf_wr_timer_in := Mux(obuf_wr_en, 0.U, Mux(((buf_numvld_cmd_any > 0.U(4.W)) & (obuf_wr_timer < TIMER_MAX.asUInt(TIMER_LOG2.W))), (obuf_wr_timer + 1.U), obuf_wr_timer))
|
obuf_nosend := withClock(io.lsu_busm_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)}
|
||||||
//// obuf_byteen0_in := Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r(3,0),0.U(4.W)), Cat(0.U(4.W),ldst_byteen_lo_r(3,0))), Mux(buf_addr(CmdPtr0)(2), Cat(buf_byteen(CmdPtr0),0.U(4.W)), Cat(0.U(4.W),buf_byteen(CmdPtr0))))
|
obuf_cmd_done := withClock(io.lsu_busm_clk){RegNext(obuf_cmd_done_in, false.B)}
|
||||||
//// obuf_byteen1_in := Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r(3,0),0.U(4.W)), Cat(0.U(4.W),ldst_byteen_hi_r(3,0))), Mux(buf_addr(CmdPtr1)(2), Cat(buf_byteen(CmdPtr1),0.U(4.W)), Cat(0.U(4.W),buf_byteen(CmdPtr1))))
|
obuf_data_done := withClock(io.lsu_busm_clk){RegNext(obuf_data_done_in, false.B)}
|
||||||
//// obuf_data0_in := Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r(31,0),0.U(32.W)), Cat(0.U(32.W),store_data_lo_r(31,0))), Mux(buf_addr(CmdPtr0)(2), Cat(buf_data(CmdPtr0), 0.U(32.W)), Cat(0.U(32.W), buf_data(CmdPtr0))))
|
obuf_rdrsp_pend := withClock(io.lsu_busm_clk){RegNext(obuf_rdrsp_pend_in, false.B)}
|
||||||
//// obuf_data1_in := Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_hi_r(31,0),0.U(32.W)), Cat(0.U(32.W),store_data_hi_r(31,0))), Mux(buf_addr(CmdPtr1)(2), Cat(buf_data(CmdPtr1), 0.U(32.W)), Cat(0.U(32.W), buf_data(CmdPtr1))))
|
obuf_rdrsp_tag := withClock(io.lsu_busm_clk){RegNext(obuf_rdrsp_tag_in, 0.U)}
|
||||||
////
|
obuf_tag0 := withClock(io.lsu_busm_clk){RegEnable(obuf_tag0_in, 0.U, obuf_wr_en)}
|
||||||
//// obuf_addr := RegEnable(obuf_addr_in , init = 0.U, obuf_wr_en)
|
val obuf_tag1 = withClock(io.lsu_busm_clk){RegEnable(obuf_tag1_in, 0.U, obuf_wr_en)}
|
||||||
//// obuf_data := RegEnable(obuf_data_in , init = 0.U, obuf_wr_en)
|
val obuf_merge = withClock(io.lsu_busm_clk){RegEnable(obuf_merge_in, false.B, obuf_wr_en)}
|
||||||
//// withClock(io.lsu_busm_clk){
|
obuf_write := withClock(io.lsu_busm_clk){RegEnable(obuf_write_in, false.B, obuf_wr_en)}
|
||||||
//// obuf_rdrsp_pend := RegNext(obuf_rdrsp_pend_in , init = 0.U)
|
obuf_sideeffect := withClock(io.lsu_busm_clk){RegEnable(obuf_sideeffect_in, false.B, obuf_wr_en)}
|
||||||
//// obuf_rdrsp_tag := RegNext(obuf_rdrsp_tag_in , init = 0.U)
|
val obuf_sz = withClock(io.lsu_busm_clk){RegEnable(obuf_sz_in, 0.U, obuf_wr_en)}
|
||||||
//// obuf_cmd_done := RegNext(obuf_cmd_done_in , init = 0.U)
|
obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, io.lsu_busm_clk, io.scan_mode)
|
||||||
//// obuf_data_done := RegNext(obuf_data_done_in , init = 0.U)
|
val obuf_byteen = withClock(io.lsu_busm_clk){RegEnable(obuf_byteen_in, 0.U, obuf_wr_en)}
|
||||||
//// obuf_wr_timer := RegNext(obuf_wr_timer_in , init = 0.U)
|
val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, io.lsu_busm_clk, io.scan_mode)
|
||||||
//// obuf_wr_enQ := RegNext(obuf_wr_en , init = 0.U)
|
obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)}
|
||||||
//// }
|
val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
||||||
//// withClock(io.lsu_free_c2_clk){
|
val found_array1 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
|
||||||
//// obuf_valid := RegNext(Mux(obuf_wr_en.asBool(),1.U ,obuf_valid) & !obuf_rst, false.B)
|
(io.lsu_busreq_m & (WrPtr0_r===i.U)) | (io.ldst_dual_r & (WrPtr1_r === i.U))))->i.U)
|
||||||
//// obuf_nosend := RegEnable(obuf_nosend_in , init = 0.U, obuf_wr_en)
|
WrPtr0_m := MuxCase(0.U, found_array1)
|
||||||
//// }
|
val found_array2 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
|
||||||
//// withClock(io.lsu_bus_obuf_c1_clk){
|
(io.lsu_busreq_m & (WrPtr0_m===i.U)) | (io.lsu_busreq_r & (WrPtr0_r === i.U)) | (io.ldst_dual_r & (WrPtr1_r===i.U))))->i.U)
|
||||||
//// obuf_write := RegEnable(obuf_write_in , init = 0.U, obuf_wr_en)
|
val WrPtr1_m = MuxCase(0.U, found_array2)
|
||||||
//// obuf_sideeffect := RegEnable(obuf_sideeffect_in , init = 0.U, obuf_wr_en)
|
val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W)))
|
||||||
//// obuf_sz := RegEnable(obuf_sz_in , init = 0.U, obuf_wr_en)
|
buf_age := buf_age.map(i=> 0.U)
|
||||||
//// obuf_byteen := RegEnable(obuf_byteen_in , init = 0.U, obuf_wr_en)
|
val CmdPtr0Dec = (0 until DEPTH).map(i=> (!(buf_age(i).orR) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
//// obuf_merge := RegEnable(obuf_merge_in , init = 0.U, obuf_wr_en)
|
val CmdPtr1Dec = (0 until DEPTH).map(i=> (!((buf_age(i) & (~CmdPtr0Dec)).orR) & !CmdPtr0Dec(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
//// obuf_tag0 := RegEnable(obuf_tag0_in , init = 0.U, obuf_wr_en)
|
val buf_rsp_pickage = Wire(Vec(DEPTH, UInt(DEPTH.W)))
|
||||||
//// obuf_tag1 := RegEnable(obuf_tag1_in , init = 0.U, obuf_wr_en)
|
buf_rsp_pickage := buf_rsp_pickage.map(i=> 0.U)
|
||||||
//// }
|
val RspPtrDec = (0 until DEPTH).map(i=> (!(buf_rsp_pickage(i).orR) & (buf_state(i)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
//// ////////////////////////////////////////////////////////////////////////////////////
|
found_cmdptr0 := CmdPtr0Dec.orR
|
||||||
////
|
found_cmdptr1 := CmdPtr1Dec.orR
|
||||||
//// // WrPtr0_m := PriorityMux((0 until DEPTH).map(i =>(((buf_state(i)===IDLE.U) & !((ibuf_valid & (ibuf_tag====i.U)) | (io.lsu_busreq_r & ((WrPtr0_r === i) | (io.ldst_dual_r & (WrPtr1_r === i)))))).asBool -> i.asUInt(DEPTH_LOG2.W))))
|
|
||||||
//// val test_seq = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & ibuf_tag===i.U) |
|
val CmdPtr0 = PriorityEncoder(CmdPtr0Dec)
|
||||||
//// (io.lsu_busreq_r & ((WrPtr0_r===i.U) | (io.ldst_dual_r & (WrPtr1_r===i.U)))))).asBool() -> i.U)
|
val CmdPtr1 = PriorityEncoder(CmdPtr1Dec)
|
||||||
//// WrPtr0_m := MuxCase(0.U, test_seq)
|
val RspPtr = PriorityEncoder(RspPtrDec)
|
||||||
//// val test_seq2 = (0 until DEPTH).map(i=>((buf_state(i) === idle_C) & !((ibuf_valid & (ibuf_tag === i.U)) |
|
val buf_state_en = Wire(Vec(DEPTH, Bool()))
|
||||||
//// (io.lsu_busreq_m & (WrPtr0_m === i.U)) | (io.lsu_busreq_r & (WrPtr0_r === i.U) |
|
buf_state_en := buf_state_en.map(i=> false.B)
|
||||||
//// (io.ldst_dual_r & (WrPtr1_r === i.U))))).asBool -> i.U)
|
val buf_rspageQ = Wire(Vec(DEPTH, UInt(DEPTH.W)))
|
||||||
//// WrPtr1_m := MuxCase(0.U, test_seq2)
|
buf_rspageQ := buf_rspageQ.map(i=> 0.U)
|
||||||
////
|
val buf_rspage_set = Wire(Vec(DEPTH, UInt(DEPTH.W)))
|
||||||
//// for {
|
buf_rspage_set := buf_rspage_set.map(i=> 0.U)
|
||||||
//// i <- 0 until DEPTH
|
val buf_rspage_in = Wire(Vec(DEPTH, UInt(DEPTH.W)))
|
||||||
//// j <- 0 until DEPTH
|
buf_rspage_in := buf_rspage_in.map(i=> 0.U)
|
||||||
//// }{
|
val buf_rspage = Wire(Vec(DEPTH, UInt(DEPTH.W)))
|
||||||
//// CmdPtr0Dec(i) := ~(buf_age(i).asUInt.orR()) & (buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i)
|
buf_rspage := buf_rspage.map(i=> 0.U)
|
||||||
//// CmdPtr1Dec(i) := ~((buf_age(i).asUInt & ~CmdPtr0Dec.asUInt).orR()) & ~CmdPtr0Dec(i) & (buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i)
|
|
||||||
//// RspPtrDec(i) := ~(buf_rsp_pickage(i).asUInt.orR()) & (buf_state(i) === done_wait_C)
|
val buf_age_in = (0 until DEPTH).map(i=>(0 until DEPTH).map(j=> ((((buf_state(i)===idle_C) & buf_state_en(i)) &
|
||||||
////
|
(((buf_state(j)===wait_C) | ((buf_state(j)===cmd_C) & !buf_cmd_state_bus_en(j))) |
|
||||||
//// buf_age_in(i)(j) := (((buf_state(i) === idle_C) & buf_state_en(i)) &
|
(ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r === i.U) & (ibuf_tag === j.U)) |
|
||||||
//// (((buf_state(j) === wait_C) | ((buf_state(j) === cmd_C) & ~buf_cmd_state_bus_en(j))) |
|
(ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r === i.U) & (WrPtr0_r === j.U)))) | buf_age(i)(j)).asUInt).reverse.reduce(Cat(_,_)))
|
||||||
//// (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (i === WrPtr0_r) & (j === ibuf_tag)) |
|
val buf_ageQ = Wire(Vec(DEPTH, UInt(DEPTH.W)))
|
||||||
//// (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (i === WrPtr1_r) & (j === WrPtr0_r)))) | buf_age(i)(j)
|
buf_ageQ := buf_ageQ.map(i=> 0.U)
|
||||||
////
|
buf_age := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_ageQ(i)(j) & ((buf_state(j)===cmd_C) & buf_cmd_state_bus_en(j))).asUInt).reverse.reduce(Cat(_,_)))
|
||||||
//// buf_age(i)(j) := buf_ageQ(i)(j) & ~((buf_state(j) === cmd_C) & buf_cmd_state_bus_en(j))
|
buf_age_younger := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(Mux(i.U===j.U, 0.U, !buf_age(i)(j) & (buf_state(j)=/=idle_C))).asUInt).reverse.reduce(Cat(_,_)))
|
||||||
//// buf_age_younger(i)(j) := Mux(i.asUInt(DEPTH_LOG2.W) === j.asUInt(DEPTH_LOG2.W), 0.U, (~buf_age(i)(j) & (buf_state(j) =/= idle_C)))
|
buf_rsp_pickage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & (buf_state(j)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_)))
|
||||||
////
|
|
||||||
//// buf_rspage_set(i)(j) := ((buf_state(i) === idle_C) & buf_state_en(i)) & (~((buf_state(j) === idle_C) | (buf_state(j) === done_C)) |
|
buf_rspage_set := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(((buf_state(i)===idle_C) & buf_state_en(i)) &
|
||||||
//// (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (i === WrPtr0_r) & (j === ibuf_tag)) |
|
(!((buf_state(j)===idle_C) | (buf_state(j)===done_C)) |
|
||||||
//// (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (i === WrPtr1_r) & (j === WrPtr0_r)))
|
(ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r===i.U) & (ibuf_tag===j.U)) |
|
||||||
//// buf_rspage_in(i)(j) := buf_rspage_set(i)(j) | buf_rspage(i)(j)
|
(ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r===i.U) & (WrPtr0_r===j.U)))).asUInt).reverse.reduce(Cat(_,_)))
|
||||||
//// buf_rspage(i)(j) := buf_rspageQ(i)(j) & ~((buf_state(j) === done_C) | (buf_state(j) === idle_C))
|
buf_rspage_in := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspage_set(i)(j) | buf_rspage(i)(j)).asUInt).reverse.reduce(Cat(_,_)))
|
||||||
//// buf_rsp_pickage(i)(j) := buf_rspageQ(i)(j) & (buf_state(j) === done_wait_C)
|
buf_rspage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & !((buf_state(j)===done_C) | (buf_state(j)===idle_C))).asUInt).reverse.reduce(Cat(_,_)))
|
||||||
//// }
|
|
||||||
////
|
|
||||||
//// CmdPtr0 := PriorityEncoderOH(CmdPtr0Dec.asUInt)
|
|
||||||
//// CmdPtr1 := PriorityEncoderOH(CmdPtr1Dec.asUInt)
|
|
||||||
//// RspPtr := PriorityEncoderOH(RspPtrDec.asUInt)
|
ibuf_drainvec_vld := (0 until DEPTH).map(i=>(ibuf_drain_vld & (ibuf_tag === i.U)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
//// found_cmdptr0 := CmdPtr0Dec.reduce(_|_)
|
buf_byteen_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_byteen_out(3,0), Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), ldst_byteen_hi_r(3,0), ldst_byteen_lo_r(3,0))))
|
||||||
//// found_cmdptr1 := CmdPtr1Dec.reduce(_|_)
|
buf_addr_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_addr, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), io.end_addr_r, io.lsu_addr_r)))
|
||||||
////
|
buf_dual_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual, io.ldst_dual_r)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
//// ////////////////////////// FSM ///////////////////////////////////////
|
buf_samedw_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_samedw, ldst_samedw_r)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
//// for (i <- 0 until DEPTH){
|
buf_nomerge_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_nomerge | ibuf_force_drain, io.no_dword_merge_r)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
//// buf_nxtstate(i) := idle_C
|
buf_dualhi_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual ,ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U))).asUInt).reverse.reduce(Cat(_,_))
|
||||||
//// buf_state_en(i) := 0.U
|
buf_dualtag_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), WrPtr0_r, WrPtr1_r)))
|
||||||
//// buf_cmd_state_bus_en(i) := 0.U
|
buf_sideeffect_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
//// buf_resp_state_bus_en(i) := 0.U
|
buf_unsign_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.unsign)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
//// buf_state_bus_en(i) := 0.U
|
buf_sz_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half)))
|
||||||
//// buf_wr_en(i) := 0.U
|
buf_write_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.store)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
//// buf_data_in(i) := 0.U
|
|
||||||
//// buf_data_en(i) := 0.U
|
for(i<- 0 until DEPTH) {
|
||||||
//// buf_error_en(i) := 0.U
|
switch(buf_state(i)) {
|
||||||
//// buf_rst(i) := 0.U
|
is(idle_C) {
|
||||||
//// buf_ldfwd_en(i) := 0.U
|
buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C)
|
||||||
//// buf_ldfwd_in(i) := 0.U
|
buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag))
|
||||||
//// buf_ldfwdtag_in(i) := 0.U
|
buf_wr_en(i) := buf_state_en(i)
|
||||||
////
|
buf_data_en(i) := buf_state_en(i)
|
||||||
//// ibuf_drainvec_vld(i) := (ibuf_drain_vld & (i === ibuf_tag))
|
buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0))
|
||||||
//// buf_byteen_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_byteen_out(3,0), Mux((ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)).asBool(), ldst_byteen_hi_r(3, 0), ldst_byteen_lo_r(3, 0)))
|
}
|
||||||
//// buf_addr_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_addr(31,0), Mux((ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)).asBool(), io.end_addr_r(31, 0), io.lsu_addr_r(31, 0)))
|
is(wait_C) {
|
||||||
//// buf_dual_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_dual, io.ldst_dual_r)
|
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C)
|
||||||
//// buf_samedw_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_samedw, ldst_samedw_r)
|
buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt
|
||||||
//// buf_nomerge_in(i) := Mux(ibuf_drainvec_vld(i), (ibuf_nomerge | ibuf_force_drain), io.no_dword_merge_r)
|
}
|
||||||
//// buf_dualhi_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_dual, (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))
|
is(cmd_C) {
|
||||||
//// buf_dualtag_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux((ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)).asBool(), WrPtr0_r, WrPtr1_r))
|
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C))
|
||||||
//// buf_sideeffect_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r)
|
buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ
|
||||||
//// buf_unsign_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.unsign)
|
buf_state_bus_en(i) := buf_cmd_state_bus_en(i)
|
||||||
//// buf_sz_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half))
|
buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
|
||||||
//// buf_write_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.store)
|
buf_ldfwd_in(i) := true.B
|
||||||
////
|
buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt
|
||||||
//// // Buffer entry state machine
|
buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(LSU_BUS_TAG - 2, 0)).asUInt
|
||||||
//// switch (buf_state(i)){
|
buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read
|
||||||
//// is (idle_C) {
|
buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error
|
||||||
//// buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C)
|
buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)))
|
||||||
//// buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag))
|
}
|
||||||
//// buf_wr_en(i) := buf_state_en(i)
|
is(resp_C) {
|
||||||
//// buf_data_en(i) := buf_state_en(i)
|
buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & !(BUILD_AXI_NATIVE.B & bus_rsp_write_error))).asBool(), idle_C,
|
||||||
//// buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0))
|
Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C,
|
||||||
//// }
|
Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & !buf_samedw(i) & !buf_write(i) & indexing(buf_ldfwd,buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C)))
|
||||||
//// is (wait_C) {
|
buf_resp_state_bus_en(i) := (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(LSU_BUS_TAG.W)))) |
|
||||||
//// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C)
|
(bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W))) |
|
||||||
//// buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt
|
(buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) |
|
||||||
//// }
|
(buf_dual(i) & buf_dualhi(i) & ~buf_write(i) & buf_samedw(i) & (bus_rsp_read_tag === (buf_dualtag(i))))))
|
||||||
//// is (cmd_C) {
|
buf_state_bus_en(i) := buf_resp_state_bus_en(i)
|
||||||
//// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C))
|
buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
|
||||||
//// buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(pt1.LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(pt1.LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ
|
buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en
|
||||||
//// buf_state_bus_en(i) := buf_cmd_state_bus_en(i)
|
buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) |
|
||||||
//// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
|
(bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) |
|
||||||
//// buf_ldfwd_in(i) := 1.U(1.W)
|
(bus_rsp_write_error & BUILD_AXI_NATIVE.B & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W))))
|
||||||
//// buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt
|
buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0))
|
||||||
//// buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(pt1.LSU_BUS_TAG - 2,0)).asUInt
|
}
|
||||||
//// buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read
|
is(done_partial_C) { // Other part of dual load hasn't returned
|
||||||
//// buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error
|
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C))
|
||||||
//// buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31,0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)))
|
buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) |
|
||||||
//// }
|
(buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt())))
|
||||||
//// is (resp_C){
|
buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
|
||||||
//// buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & ~(pt.BUILD_AXI_NATIVE & bus_rsp_write_error))).asBool(), idle_C,
|
}
|
||||||
//// Mux((buf_dual(i) & ~ buf_samedw(i) & ~ buf_write(i) &(buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C,
|
is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns
|
||||||
//// Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & ~ buf_samedw(i) & ~ buf_write(i) & buf_ldfwd(buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C)))
|
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C)
|
||||||
//// buf_resp_state_bus_en(i):= (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(pt1.LSU_BUS_TAG.W)))) |
|
buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt
|
||||||
//// (bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(pt1.LSU_BUS_TAG.W))) |
|
}
|
||||||
//// (buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) |
|
is(done_C) {
|
||||||
//// (buf_dual(i) & buf_dualhi(i) & ~buf_write(i) & buf_samedw(i) & (bus_rsp_read_tag === (buf_dualtag(i))))))
|
buf_nxtstate(i) := idle_C
|
||||||
//// buf_state_bus_en(i) := buf_resp_state_bus_en(i)
|
buf_rst(i) := 1.U
|
||||||
//// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
|
buf_state_en(i) := 1.U
|
||||||
//// buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en
|
buf_ldfwd_in(i) := false.B
|
||||||
//// buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(pt1.LSU_BUS_TAG.W))) ) |
|
buf_ldfwd_en(i) := buf_state_en(i)
|
||||||
//// (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) |
|
}
|
||||||
//// (bus_rsp_write_error & pt.BUILD_AXI_NATIVE & (bus_rsp_write_tag === i.asUInt(pt1.LSU_BUS_TAG.W))))
|
}
|
||||||
//// buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0))
|
buf_state(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nxtstate(i), 0.U, buf_state_en(i).asBool())}
|
||||||
//// }
|
buf_ageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_age_in(i), 0.U)}
|
||||||
//// is (done_partial_C){ // Other part of dual load hasn't returned
|
buf_rspageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_rspage_in(i), 0.U)}
|
||||||
//// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C))
|
buf_dualtag(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualtag_in(i), 0.U, buf_wr_en(i).asBool())}
|
||||||
//// buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) |
|
buf_dual(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dual_in(i), false.B, buf_wr_en(i).asBool())}
|
||||||
//// (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt())))
|
buf_samedw(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_samedw_in(i), false.B, buf_wr_en(i).asBool())}
|
||||||
//// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
|
buf_nomerge(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nomerge_in(i), false.B, buf_wr_en(i).asBool())}
|
||||||
//// }
|
buf_dualhi(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualhi_in(i), false.B, buf_wr_en(i).asBool())}
|
||||||
//// is (done_wait_C) { // WAIT state if there are multiple outstanding nb returns
|
}
|
||||||
//// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C)
|
|
||||||
//// buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) |(buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt
|
buf_ldfwd := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwd_in(i), false.B, buf_ldfwd_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_))
|
||||||
//// }
|
buf_ldfwdtag := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwdtag_in(i), 0.U, buf_ldfwd_en(i).asBool())})
|
||||||
//// is (done_C) {
|
buf_sideeffect := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sideeffect_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_))
|
||||||
//// buf_nxtstate(i) := idle_C
|
buf_unsign := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_unsign_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_))
|
||||||
//// buf_rst(i) := 1.U
|
buf_write := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_write_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_))
|
||||||
//// buf_state_en(i) := 1.U
|
buf_sz := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sz_in(i), 0.U, buf_wr_en(i).asBool())})
|
||||||
//// buf_ldfwd_in(i) := 0.U
|
buf_addr := (0 until DEPTH).map(i=>rvdffe(buf_addr_in(i), buf_wr_en(i).asBool(), clock, io.scan_mode))
|
||||||
//// buf_ldfwd_en(i) := buf_state_en(i)
|
buf_byteen := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_byteen_in(i), 0.U, buf_wr_en(i).asBool())})
|
||||||
//// }
|
buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode))
|
||||||
//// }
|
buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(Mux(buf_error_en(i), true.B, buf_error(i)) & buf_rst(i), false.B)}).asUInt()).reverse.reduce(Cat(_,_))
|
||||||
////
|
|
||||||
//// buf_byteen(i) := RegEnable(buf_byteen_in(i) , init = 0.U ,buf_wr_en(i))
|
val buf_numvld_any = (0 until DEPTH).map(i=>(buf_state(i)=/=idle_C).asUInt).reverse.reduce(_ +& _)
|
||||||
//// buf_data(i) := RegEnable(buf_data_in(i) , init = 0.U ,buf_data_en(i))
|
buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_write(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _)
|
||||||
//// withClock(io.lsu_bus_buf_c1_clk){
|
buf_numvld_cmd_any := (0 until DEPTH).map(i=>((buf_write(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _)
|
||||||
//// buf_state(i) := RegEnable(buf_nxtstate(i) , init = idle_C ,buf_state_en(i))
|
buf_numvld_pend_any := (0 until DEPTH).map(i=>(((buf_write(i)===wait_C)|(buf_write(i)===cmd_C)) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _)
|
||||||
//// buf_dualtag(i) := RegEnable(buf_dualtag_in(i) , init = 0.U ,buf_wr_en(i))
|
any_done_wait_state := (0 until DEPTH).map(i=>buf_state(i)===done_wait_C).reverse.reduce(_|_)
|
||||||
//// buf_dual(i) := RegEnable(buf_dual_in(i) , init = 0.U ,buf_wr_en(i))
|
io.lsu_bus_buffer_pend_any := buf_numvld_pend_any.orR
|
||||||
//// buf_samedw(i) := RegEnable(buf_samedw_in(i) , init = 0.U ,buf_wr_en(i))
|
io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1), buf_numvld_any===(DEPTH-1))
|
||||||
//// buf_nomerge(i) := RegEnable(buf_nomerge_in(i) , init = 0.U ,buf_wr_en(i))
|
io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid
|
||||||
//// buf_dualhi(i) := RegEnable(buf_dualhi_in(i) , init = 0.U ,buf_wr_en(i))
|
|
||||||
//// buf_sideeffect(i) := RegEnable(buf_sideeffect_in(i) , init = 0.U ,buf_wr_en(i))
|
io.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.load & !io.flush_m_up & !io.ld_full_hit_m
|
||||||
//// buf_unsign(i) := RegEnable(buf_unsign_in(i) , init = 0.U ,buf_wr_en(i))
|
io.lsu_nonblock_load_tag_m := WrPtr0_m
|
||||||
//// buf_write(i) := RegEnable(buf_write_in(i) , init = 0.U ,buf_wr_en(i))
|
val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B)
|
||||||
//// buf_sz(i) := RegEnable(buf_sz_in(i) , init = 0.U ,buf_wr_en(i))
|
io.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r
|
||||||
//// buf_addr(i) := RegEnable(buf_addr_in(i) , init = 0.U ,buf_wr_en(i))
|
io.lsu_nonblock_load_inv_tag_r := WrPtr0_r
|
||||||
//// buf_ldfwd(i) := RegEnable(buf_ldfwd_in(i) , init = 0.U ,buf_ldfwd_en(i))
|
val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(BUILD_AXI_NATIVE.B & buf_write(i)))))
|
||||||
//// buf_ldfwdtag(i) := RegEnable(buf_ldfwdtag_in(i) , init = 0.U ,buf_ldfwd_en(i))
|
io.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i))))
|
||||||
//// buf_error(i) := RegEnable(~buf_rst(i) , init = 0.U ,(buf_error_en(i)|buf_rst(i)).asBool)
|
io.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U))
|
||||||
//// buf_ageQ(i) := RegNext(buf_age_in(i) , init = VecInit((0 until 4).map(i=>false.B)))
|
val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i)))
|
||||||
//// buf_rspageQ(i) := RegNext(buf_rspage_in(i) , init = VecInit((0 until 4).map(i=>false.B)))
|
val lsu_nonblock_load_data_hi = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (buf_dual(i) | buf_dualhi(i))) -> buf_data(i)))
|
||||||
//// }
|
val lsu_nonblock_addr_offset = indexing(buf_addr, io.lsu_nonblock_load_data_tag)
|
||||||
//// }
|
val lsu_nonblock_sz = indexing(buf_sz, io.lsu_nonblock_load_data_tag)
|
||||||
////
|
val lsu_nonblock_unsign = indexing(buf_unsign, io.lsu_nonblock_load_data_tag)
|
||||||
//// //////////////////////////////////////////////////////////////////////////////////
|
val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.lsu_nonblock_load_data_tag)
|
||||||
//// buf_numvld_any := (io.lsu_busreq_m << io.ldst_dual_m) + (io.lsu_busreq_r << io.ldst_dual_r) + ibuf_valid +
|
val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U)
|
||||||
//// {for(i <- 0 until DEPTH) yield ( buf_state(i) =/= idle_C).asUInt }.reduce(_+_)
|
io.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.lsu_nonblock_load_data_error
|
||||||
//// buf_numvld_wrcmd_any := {for(i <- 0 until DEPTH) yield (( buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i) & buf_write(i)).asUInt }.reduce(_+_)
|
io.lsu_nonblock_load_data := Mux1H(Seq((lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(0.U(24.W),lsu_nonblock_data_unalgn(7,0)),
|
||||||
//// buf_numvld_cmd_any := {for(i <- 0 until DEPTH) yield (( buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i)).asUInt }.reduce(_+_)
|
(lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(0.U(16.W),lsu_nonblock_data_unalgn(15,0)),
|
||||||
//// buf_numvld_pend_any := {for(i <- 0 until DEPTH) yield (((buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i)) | (buf_state(i) === wait_C)).asUInt }.reduce(_+_)
|
(!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)),
|
||||||
//// any_done_wait_state := {for(i <- 0 until DEPTH) yield buf_state(i) === done_wait_C }.reduce(_|_)
|
(!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)),
|
||||||
////
|
(lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn))
|
||||||
//// io.lsu_bus_buffer_pend_any := buf_numvld_pend_any =/= 0.U
|
bus_sideeffect_pend := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)->(buf_sideeffect(i) & io.dec_tlu_sideeffect_posted_disable)))
|
||||||
//// io.lsu_bus_buffer_full_any := Mux((io.ldst_dual_d & io.dec_lsu_valid_raw_d),buf_numvld_any(3,0) >= (DEPTH-1).asUInt(4.W), buf_numvld_any(3,0) === DEPTH.asUInt(4.W))
|
bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)->
|
||||||
//// io.lsu_bus_buffer_empty_any := ~((0 until DEPTH).map(i =>(buf_state(i)).asUInt).reduce(_|_)) & ~ibuf_valid & ~obuf_valid
|
(BUILD_AXI_NATIVE.B & obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U))))))
|
||||||
////
|
|
||||||
//// io.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.load & ~io.flush_m_up & ~ io.ld_full_hit_m
|
bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready), io.lsu_axi_awready & io.lsu_axi_awready), io.lsu_axi_arready)
|
||||||
//// io.lsu_nonblock_load_tag_m := WrPtr0_m(DEPTH_LOG2-1,0)
|
bus_wcmd_sent := io.lsu_axi_awvalid & io.lsu_axi_awready
|
||||||
//// io.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & ~io.lsu_commit_r
|
bus_wdata_sent := io.lsu_axi_wvalid & io.lsu_axi_wready
|
||||||
//// io.lsu_nonblock_load_inv_tag_r := WrPtr0_r(DEPTH_LOG2-1,0)
|
bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi_arvalid & io.lsu_axi_arready)
|
||||||
////
|
bus_rsp_read := io.lsu_axi_rvalid & io.lsu_axi_rready
|
||||||
//// lsu_nonblock_load_data_ready := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C) -> ~(pt.BUILD_AXI_NATIVE & buf_write(i))))
|
bus_rsp_write := io.lsu_axi_bvalid & io.lsu_axi_bready
|
||||||
//// io.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & ~buf_write(i)) -> (buf_error(i))))
|
bus_rsp_read_tag := io.lsu_axi_rid
|
||||||
//// io.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & (~buf_dual(i) | ~buf_dualhi(i)) & ~buf_write(i)) -> intToUInt(i)))
|
bus_rsp_write_tag := io.lsu_axi_bid
|
||||||
//// lsu_nonblock_load_data_lo := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & ~buf_write(i) & (~buf_dual(i) | ~buf_dualhi(i))) -> buf_data(i)))
|
bus_rsp_write_error := bus_rsp_write & (io.lsu_axi_bresp =/= 0.U)
|
||||||
//// lsu_nonblock_load_data_hi := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & ~buf_write(i) & ( buf_dual(i) & buf_dualhi(i))) -> buf_data(i)))
|
bus_rsp_read_error := bus_rsp_read & (io.lsu_axi_bresp =/= 0.U)
|
||||||
////
|
bus_rsp_rdata := io.lsu_axi_rdata
|
||||||
//// lsu_nonblock_addr_offset := buf_addr(io.lsu_nonblock_load_data_tag)(1,0)
|
|
||||||
//// lsu_nonblock_sz := buf_sz(io.lsu_nonblock_load_data_tag)(1,0)
|
// AXI Command signals
|
||||||
//// lsu_nonblock_unsign := buf_unsign(io.lsu_nonblock_load_data_tag)
|
io.lsu_axi_awvalid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending
|
||||||
//// lsu_nonblock_dual := buf_dual(io.lsu_nonblock_load_data_tag)
|
io.lsu_axi_awid := obuf_tag0
|
||||||
//// lsu_nonblock_data_unalgn := (Cat(lsu_nonblock_load_data_hi(31,0), lsu_nonblock_load_data_lo(31,0)) >> 8*lsu_nonblock_addr_offset(1,0))(31,0)
|
io.lsu_axi_awaddr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W)))
|
||||||
//// io.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & ~io.lsu_nonblock_load_data_error
|
io.lsu_axi_awsize := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 2.U(3.W))
|
||||||
//// io.lsu_nonblock_load_data := Mux1H(Seq(
|
io.lsu_axi_awprot := 0.U
|
||||||
//// (lsu_nonblock_unsign & lsu_nonblock_sz === 0.U) -> Cat(Fill(24,0.U(1.W)),lsu_nonblock_data_unalgn(7,0)),
|
io.lsu_axi_awcache := Mux(obuf_sideeffect, 0.U, 15.U)
|
||||||
//// (lsu_nonblock_unsign & lsu_nonblock_sz === 1.U) -> Cat(Fill(16,0.U(1.W)),lsu_nonblock_data_unalgn(15,0)),
|
io.lsu_axi_awregion := obuf_addr(31,28)
|
||||||
//// (~lsu_nonblock_unsign & lsu_nonblock_sz === 0.U) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)),lsu_nonblock_data_unalgn(7,0)),
|
io.lsu_axi_awlen := 0.U
|
||||||
//// (~lsu_nonblock_unsign & lsu_nonblock_sz === 1.U) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)),lsu_nonblock_data_unalgn(15,0)),
|
io.lsu_axi_awburst := 1.U(2.W)
|
||||||
//// (lsu_nonblock_unsign & lsu_nonblock_sz === 2.U) -> lsu_nonblock_data_unalgn(31,0)
|
io.lsu_axi_awqos := 0.U
|
||||||
//// ))
|
io.lsu_axi_awlock := 0.U
|
||||||
//// bus_sideeffect_pend := Mux(obuf_valid,obuf_sideeffect & io.dec_tlu_sideeffect_posted_disable,Mux1H((0 until DEPTH).map(i =>(buf_state(i) === resp_C) -> (buf_sideeffect(i) & io.dec_tlu_sideeffect_posted_disable))))
|
|
||||||
//// bus_addr_match_pending := Mux1H((0 until DEPTH).map(i =>(pt.BUILD_AXI_NATIVE & obuf_valid & (obuf_addr(31,3) === buf_addr(i)(31,3))).asBool -> ((buf_state(i) === resp_C) & ~((obuf_tag0 === intToUInt(i)) | (obuf_merge & (obuf_tag1 === intToUInt(i)))))))
|
io.lsu_axi_wvalid := obuf_valid & obuf_write & !obuf_data_done & !bus_addr_match_pending
|
||||||
////
|
io.lsu_axi_wstrb := obuf_byteen & Fill(8, obuf_write)
|
||||||
//// bus_cmd_ready := Mux(obuf_write, Mux((obuf_cmd_done | obuf_data_done), Mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready), (io.lsu_axi_awready & io.lsu_axi_wready)), io.lsu_axi_arready)
|
io.lsu_axi_wdata := obuf_data
|
||||||
//// bus_wcmd_sent := io.lsu_axi_awvalid & io.lsu_axi_awready
|
io.lsu_axi_wlast := 1.U
|
||||||
//// bus_wdata_sent := io.lsu_axi_wvalid & io.lsu_axi_wready
|
|
||||||
//// bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi_arvalid & io.lsu_axi_arready)
|
io.lsu_axi_arvalid := obuf_valid & !obuf_write & !obuf_nosend & !bus_addr_match_pending
|
||||||
////
|
io.lsu_axi_arid := obuf_tag0
|
||||||
//// bus_rsp_read := io.lsu_axi_rvalid & io.lsu_axi_rready
|
io.lsu_axi_araddr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W)))
|
||||||
//// bus_rsp_write := io.lsu_axi_bvalid & io.lsu_axi_bready
|
io.lsu_axi_arsize := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W))
|
||||||
//// bus_rsp_read_tag := io.lsu_axi_rid(pt1.LSU_BUS_TAG-1,0)
|
io.lsu_axi_arprot := 0.U
|
||||||
//// bus_rsp_write_tag := io.lsu_axi_bid(pt1.LSU_BUS_TAG-1,0)
|
io.lsu_axi_arcache := Mux(obuf_sideeffect, 0.U(4.W), 15.U)
|
||||||
//// bus_rsp_write_error := bus_rsp_write & (io.lsu_axi_bresp(1,0) =/= 0.U(2.W))
|
io.lsu_axi_arregion := obuf_addr(31,28)
|
||||||
//// bus_rsp_read_error := bus_rsp_read & (io.lsu_axi_rresp(1,0) =/= 0.U(2.W))
|
io.lsu_axi_arlen := 0.U
|
||||||
//// bus_rsp_rdata := io.lsu_axi_rdata(63,0)
|
io.lsu_axi_arburst := 1.U(2.W)
|
||||||
//// //////////////////////////////////////////////////////////////////////////////////
|
io.lsu_axi_arqos := 0.U
|
||||||
//// lsu_axi_rdata_q := RegEnable(io.lsu_axi_rdata, init = 0.U, io.lsu_axi_rvalid&io.lsu_bus_clk_en)
|
io.lsu_axi_arlock := 0.U
|
||||||
//// withClock(io.lsu_c2_r_clk){
|
io.lsu_axi_bready := 1.U
|
||||||
//// io.lsu_busreq_r := RegNext((io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m), 0.U)
|
io.lsu_axi_rready := 1.U
|
||||||
//// WrPtr0_r := RegNext(WrPtr0_m, init = 0.U)
|
io.lsu_imprecise_error_store_any := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C)->(io.lsu_bus_clk_en_q & buf_error(i) & buf_write(i))))
|
||||||
//// WrPtr1_r := RegNext(WrPtr1_m, init = 0.U)
|
val lsu_imprecise_error_store_tag = Mux1H((0 until DEPTH_LOG2).map(i=>((buf_state(i)===done_C) & buf_error(i) & buf_write(i))->i.U))
|
||||||
//// lsu_nonblock_load_valid_r := RegNext(io.lsu_nonblock_load_valid_m, init = 0.U)
|
|
||||||
//// }
|
io.lsu_imprecise_error_load_any := io.lsu_nonblock_load_data_error & !io.lsu_imprecise_error_store_any
|
||||||
//// withClock(io.lsu_busm_clk){
|
io.lsu_imprecise_error_addr_any := Mux(io.lsu_imprecise_error_store_any, indexing(buf_addr, lsu_imprecise_error_store_tag), indexing(buf_addr, io.lsu_nonblock_load_data_tag))
|
||||||
//// lsu_axi_awvalid_q := RegNext(io.lsu_axi_awvalid, init = 0.U)
|
lsu_bus_cntr_overflow := 0.U
|
||||||
//// lsu_axi_awready_q := RegNext(io.lsu_axi_awready, init = 0.U)
|
|
||||||
//// lsu_axi_wvalid_q := RegNext(io.lsu_axi_wvalid, init = 0.U)
|
io.lsu_bus_idle_any := 1.U
|
||||||
//// lsu_axi_wready_q := RegNext(io.lsu_axi_wready, init = 0.U)
|
|
||||||
//// lsu_axi_arvalid_q := RegNext(io.lsu_axi_arvalid, init = 0.U)
|
// PMU signals
|
||||||
//// lsu_axi_arready_q := RegNext(io.lsu_axi_arready, init = 0.U)
|
io.lsu_pmu_bus_trxn := (io.lsu_axi_awvalid & io.lsu_axi_awready) | (io.lsu_axi_wvalid & io.lsu_axi_wready) | (io.lsu_axi_arvalid & io.lsu_axi_arready)
|
||||||
//// lsu_axi_bvalid_q := RegNext(io.lsu_axi_bvalid, init = 0.U)
|
io.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r
|
||||||
//// lsu_axi_bready_q := RegNext(io.lsu_axi_bready, init = 0.U)
|
io.lsu_pmu_bus_error := io.lsu_imprecise_error_load_any | io.lsu_imprecise_error_store_any
|
||||||
//// lsu_axi_rvalid_q := RegNext(io.lsu_axi_rvalid, init = 0.U)
|
|
||||||
//// lsu_axi_rready_q := RegNext(io.lsu_axi_rready, init = 0.U)
|
io.lsu_pmu_bus_busy := (io.lsu_axi_awvalid & !io.lsu_axi_awready) | (io.lsu_axi_wvalid & !io.lsu_axi_wready) | (io.lsu_axi_arvalid & !io.lsu_axi_arready)
|
||||||
//// lsu_axi_bid_q := RegNext(io.lsu_axi_bid, init = 0.U)
|
|
||||||
//// lsu_axi_rid_q := RegNext(io.lsu_axi_rid, init = 0.U)
|
WrPtr0_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr0_m, 0.U)}
|
||||||
//// lsu_axi_bresp_q := RegNext(io.lsu_axi_bresp, init = 0.U)
|
WrPtr1_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr1_m, 0.U)}
|
||||||
//// lsu_axi_rresp_q := RegNext(io.lsu_axi_rresp, init = 0.U)
|
io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)}
|
||||||
//// }
|
lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_nonblock_load_valid_m, false.B)}
|
||||||
//// ///////////////////////////////////////////////////////////////////////////////////
|
}
|
||||||
////
|
|
||||||
//// io.ld_fwddata_buf_lo := 0.U
|
object BusBufmain extends App{
|
||||||
//// io.ld_fwddata_buf_hi := 0.U
|
println("Generate Verilog")
|
||||||
////
|
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_lsu_bus_buffer())))
|
||||||
//// lsu_imprecise_error_store_tag := Mux1H((0 until DEPTH).map(i =>(((buf_state(i) === done_C) & buf_error(i) & buf_write(i)) -> intToUInt(i))))
|
}
|
||||||
//// io.lsu_imprecise_error_load_any := io.lsu_nonblock_load_data_error & ~io.lsu_imprecise_error_store_any
|
|
||||||
//// io.lsu_imprecise_error_store_any := {for(i <- 0 until DEPTH) yield io.lsu_bus_clk_en_q & (buf_state(i) === done_C) & buf_error(i) & buf_write(i)}.reduce(_|_)
|
|
||||||
//// io.lsu_imprecise_error_addr_any := Mux(io.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.lsu_nonblock_load_data_tag))
|
|
||||||
////
|
|
||||||
//// bus_pend_trxnQ := 0.U(8.W)
|
|
||||||
//// bus_pend_trxn := 0.U(8.W)
|
|
||||||
//// bus_pend_trxn_ns := 0.U(8.W)
|
|
||||||
//// lsu_bus_cntr_overflow := 0.U(1.W)
|
|
||||||
//// io.lsu_bus_idle_any := true.B
|
|
||||||
////
|
|
||||||
//// io.lsu_pmu_bus_trxn := (io.lsu_axi_awvalid & io.lsu_axi_awready) | (io.lsu_axi_wvalid & io.lsu_axi_wready) | (io.lsu_axi_arvalid & io.lsu_axi_arready)
|
|
||||||
//// io.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r
|
|
||||||
//// io.lsu_pmu_bus_error := io.lsu_imprecise_error_load_any | io.lsu_imprecise_error_store_any
|
|
||||||
//// io.lsu_pmu_bus_busy := (io.lsu_axi_awvalid & ~io.lsu_axi_awready | (io.lsu_axi_wvalid & ~io.lsu_axi_wready) | (io.lsu_axi_arvalid & ~io.lsu_axi_arready))
|
|
||||||
////
|
|
||||||
//// io.lsu_axi_awvalid := obuf_valid & obuf_write & ~obuf_cmd_done & ~bus_addr_match_pending
|
|
||||||
//// io.lsu_axi_awid := obuf_tag0.asUInt
|
|
||||||
//// io.lsu_axi_awaddr := Mux(obuf_sideeffect, obuf_addr,Cat(obuf_addr(31,3),0.U(3.W)))
|
|
||||||
//// io.lsu_axi_awregion := obuf_addr(31,28)
|
|
||||||
//// io.lsu_axi_awlen := 0.U(8.W)
|
|
||||||
//// io.lsu_axi_awsize := Mux(obuf_sideeffect, Cat(false.B,obuf_sz),3.U(3.W))
|
|
||||||
//// io.lsu_axi_awburst := 1.U(2.W)
|
|
||||||
//// io.lsu_axi_awlock := 0.U
|
|
||||||
//// io.lsu_axi_awcache := Mux(obuf_sideeffect, 0.U(4.W),15.U(4.W))
|
|
||||||
//// io.lsu_axi_awprot := 0.U(3.W)
|
|
||||||
//// io.lsu_axi_awqos := 0.U(4.W)
|
|
||||||
////
|
|
||||||
//// io.lsu_axi_wvalid := obuf_valid & obuf_write & ~obuf_data_done & ~bus_addr_match_pending
|
|
||||||
//// io.lsu_axi_wdata := obuf_data
|
|
||||||
//// io.lsu_axi_wstrb := obuf_byteen & Fill(8,obuf_write)
|
|
||||||
//// io.lsu_axi_wlast := 1.U
|
|
||||||
////
|
|
||||||
//// io.lsu_axi_arvalid := obuf_valid & ~obuf_write & ~obuf_nosend & ~bus_addr_match_pending
|
|
||||||
//// io.lsu_axi_arid := obuf_tag0.asUInt
|
|
||||||
//// io.lsu_axi_araddr := io.lsu_axi_awaddr
|
|
||||||
//// io.lsu_axi_arregion := obuf_addr(31,28)
|
|
||||||
//// io.lsu_axi_arlen := 0.U(8.W)
|
|
||||||
//// io.lsu_axi_arsize := io.lsu_axi_awsize
|
|
||||||
//// io.lsu_axi_arburst := 1.U(2.W)
|
|
||||||
//// io.lsu_axi_arlock := 0.U
|
|
||||||
//// io.lsu_axi_arcache := io.lsu_axi_awcache
|
|
||||||
//// io.lsu_axi_arprot := 0.U
|
|
||||||
//// io.lsu_axi_arqos := 0.U
|
|
||||||
////
|
|
||||||
//// io.lsu_axi_bready := 1.U
|
|
||||||
//// io.lsu_axi_rready := 1.U
|
|
||||||
////
|
|
||||||
////
|
|
||||||
////}
|
|
||||||
////object BusBufmain extends App{
|
|
||||||
//// println("Generate Verilog")
|
|
||||||
//// println((new chisel3.stage.ChiselStage).emitVerilog((new el2_lsu_bus_buffer())))
|
|
||||||
////}
|
|
||||||
|
|
|
||||||
|
|
@ -1,163 +0,0 @@
|
||||||
package lsu
|
|
||||||
|
|
||||||
import include._
|
|
||||||
import lib._
|
|
||||||
import snapshot._
|
|
||||||
|
|
||||||
import chisel3._
|
|
||||||
import chisel3.util._
|
|
||||||
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
|
|
||||||
import chisel3.experimental.ChiselEnum
|
|
||||||
import chisel3.experimental.{withClock, withReset, withClockAndReset}
|
|
||||||
import chisel3.experimental.BundleLiterals._
|
|
||||||
import chisel3.tester._
|
|
||||||
import chisel3.tester.RawTester.test
|
|
||||||
import chisel3.util.HasBlackBoxResource
|
|
||||||
import chisel3.experimental.chiselName
|
|
||||||
@chiselName
|
|
||||||
class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib {
|
|
||||||
val io = IO(new Bundle{
|
|
||||||
val lsu_c2_m_clk = Input(Clock())
|
|
||||||
|
|
||||||
val start_addr_d = Input(UInt(32.W))
|
|
||||||
val end_addr_d = Input(UInt(32.W))
|
|
||||||
val lsu_pkt_d = Input(new el2_lsu_pkt_t)
|
|
||||||
val dec_tlu_mrac_ff = Input(UInt(32.W))
|
|
||||||
val rs1_region_d = Input(UInt(4.W))
|
|
||||||
val rs1_d = Input(UInt(32.W))
|
|
||||||
|
|
||||||
|
|
||||||
val is_sideeffects_m = Output(UInt(1.W))
|
|
||||||
val addr_in_dccm_d = Output(UInt(1.W))
|
|
||||||
val addr_in_pic_d = Output(UInt(1.W))
|
|
||||||
val addr_external_d = Output(UInt(1.W))
|
|
||||||
val access_fault_d = Output(UInt(1.W))
|
|
||||||
val misaligned_fault_d = Output(UInt(1.W))
|
|
||||||
val exc_mscause_d = Output(UInt(4.W))
|
|
||||||
val fir_dccm_access_error_d = Output(UInt(1.W))
|
|
||||||
val fir_nondccm_access_error_d = Output(UInt(1.W))
|
|
||||||
val scan_mode = Input(UInt(1.W))})
|
|
||||||
|
|
||||||
val start_addr_in_dccm_d = WireInit(0.U(1.W))
|
|
||||||
val start_addr_in_dccm_region_d = WireInit(0.U(1.W))
|
|
||||||
val end_addr_in_dccm_d = WireInit(0.U(1.W))
|
|
||||||
val end_addr_in_dccm_region_d = WireInit(0.U(1.W))
|
|
||||||
|
|
||||||
//DCCM check
|
|
||||||
// Start address check
|
|
||||||
if(DCCM_ENABLE==1){ // Gen_dccm_enable
|
|
||||||
val start_addr_dccm_rangecheck = Module(new rvrangecheck(DCCM_SADR,DCCM_SIZE))
|
|
||||||
start_addr_dccm_rangecheck.io.addr := io.start_addr_d
|
|
||||||
start_addr_in_dccm_d := start_addr_dccm_rangecheck.io.in_range
|
|
||||||
start_addr_in_dccm_region_d := start_addr_dccm_rangecheck.io.in_region
|
|
||||||
|
|
||||||
// End address check
|
|
||||||
val end_addr_dccm_rangecheck = Module(new rvrangecheck(DCCM_SADR,DCCM_SIZE))
|
|
||||||
end_addr_dccm_rangecheck.io.addr := io.end_addr_d
|
|
||||||
end_addr_in_dccm_d := end_addr_dccm_rangecheck.io.in_range
|
|
||||||
end_addr_in_dccm_region_d := end_addr_dccm_rangecheck.io.in_region
|
|
||||||
}
|
|
||||||
else{ //Gen_dccm_disable
|
|
||||||
start_addr_in_dccm_d := 0.U
|
|
||||||
start_addr_in_dccm_region_d := 0.U
|
|
||||||
end_addr_in_dccm_d := 0.U
|
|
||||||
end_addr_in_dccm_region_d := 0.U
|
|
||||||
}
|
|
||||||
|
|
||||||
val addr_in_iccm = WireInit(0.U(1.W))
|
|
||||||
if(ICCM_ENABLE == 1){ //check_iccm
|
|
||||||
addr_in_iccm := (io.start_addr_d(31,28) === pt.ICCM_REGION)
|
|
||||||
}
|
|
||||||
else{
|
|
||||||
addr_in_iccm := 1.U
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
//PIC memory check
|
|
||||||
//start address check
|
|
||||||
val start_addr_pic_rangecheck = Module(new rvrangecheck(PIC_BASE_ADDR,PIC_SIZE))
|
|
||||||
start_addr_pic_rangecheck.io.addr := io.start_addr_d(31,0)
|
|
||||||
val start_addr_in_pic_d = start_addr_pic_rangecheck.io.in_range
|
|
||||||
val start_addr_in_pic_region_d = start_addr_pic_rangecheck.io.in_region
|
|
||||||
|
|
||||||
//End address check
|
|
||||||
val end_addr_pic_rangecheck = Module(new rvrangecheck(PIC_BASE_ADDR,PIC_SIZE))
|
|
||||||
end_addr_pic_rangecheck.io.addr := io.end_addr_d(31,0)
|
|
||||||
val end_addr_in_pic_d = end_addr_pic_rangecheck.io.in_range
|
|
||||||
val end_addr_in_pic_region_d = end_addr_pic_rangecheck.io.in_region
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val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d
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val base_reg_dccm_or_pic = (io.rs1_region_d(3,0) === DCCM_REGION.U) | (io.rs1_region_d(3,0) === PIC_REGION.U) //base region
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io.addr_in_dccm_d := (start_addr_in_dccm_d & end_addr_in_dccm_d)
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io.addr_in_pic_d := (start_addr_in_pic_d & end_addr_in_pic_d)
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io.addr_external_d := ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d); //if start address does not belong to dccm/pic
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val csr_idx = Cat(io.start_addr_d(31,28),1.U)
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val is_sideeffects_d = io.dec_tlu_mrac_ff(csr_idx) & ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & io.lsu_pkt_d.valid & (io.lsu_pkt_d.store | io.lsu_pkt_d.load) //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
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val is_aligned_d = (io.lsu_pkt_d.word & (io.start_addr_d(1,0) === 0.U)) | (io.lsu_pkt_d.half & (io.start_addr_d(0) === 0.U)) | io.lsu_pkt_d.by
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val non_dccm_access_ok = (~(Cat(DATA_ACCESS_ENABLE0.B, DATA_ACCESS_ENABLE1.B, DATA_ACCESS_ENABLE2.B, DATA_ACCESS_ENABLE3.B,
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DATA_ACCESS_ENABLE4.B, DATA_ACCESS_ENABLE5.B, DATA_ACCESS_ENABLE6.B, DATA_ACCESS_ENABLE7.B)).orR) |
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(((DATA_ACCESS_ENABLE0.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK0.U)) === (DATA_ACCESS_ADDR0.U | DATA_ACCESS_MASK0.U)) | //0111
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(DATA_ACCESS_ENABLE1.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK1.U)) === (DATA_ACCESS_ADDR1.U | DATA_ACCESS_MASK1.U)) | //1111
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(DATA_ACCESS_ENABLE2.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK2.U)) === (DATA_ACCESS_ADDR2.U | DATA_ACCESS_MASK2.U)) | //1011
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(DATA_ACCESS_ENABLE3.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK3.U)) === (DATA_ACCESS_ADDR3.U | DATA_ACCESS_MASK3.U)) | //1000
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(DATA_ACCESS_ENABLE4.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK4.U)) === (DATA_ACCESS_ADDR4.U | DATA_ACCESS_MASK4.U)) |
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(DATA_ACCESS_ENABLE5.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK5.U)) === (DATA_ACCESS_ADDR5.U | DATA_ACCESS_MASK5.U)) |
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(DATA_ACCESS_ENABLE6.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK6.U)) === (DATA_ACCESS_ADDR6.U | DATA_ACCESS_MASK6.U)) |
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||||||
(DATA_ACCESS_ENABLE7.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK7.U)) === (DATA_ACCESS_ADDR7.U | DATA_ACCESS_MASK7.U)))
|
|
||||||
&
|
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||||||
((DATA_ACCESS_ENABLE0.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK0.U)) === (DATA_ACCESS_ADDR0.U | DATA_ACCESS_MASK0.U)) |
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||||||
(DATA_ACCESS_ENABLE1.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK1.U)) === (DATA_ACCESS_ADDR1.U | DATA_ACCESS_MASK1.U)) |
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||||||
(DATA_ACCESS_ENABLE2.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK2.U)) === (DATA_ACCESS_ADDR2.U | DATA_ACCESS_MASK2.U)) |
|
|
||||||
(DATA_ACCESS_ENABLE3.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK3.U)) === (DATA_ACCESS_ADDR3.U | DATA_ACCESS_MASK3.U)) |
|
|
||||||
(DATA_ACCESS_ENABLE4.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK4.U)) === (DATA_ACCESS_ADDR4.U | DATA_ACCESS_MASK4.U)) |
|
|
||||||
(DATA_ACCESS_ENABLE5.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK5.U)) === (DATA_ACCESS_ADDR5.U | DATA_ACCESS_MASK5.U)) |
|
|
||||||
(DATA_ACCESS_ENABLE6.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK6.U)) === (DATA_ACCESS_ADDR6.U | DATA_ACCESS_MASK6.U)) |
|
|
||||||
(DATA_ACCESS_ENABLE7.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK7.U)) === (DATA_ACCESS_ADDR7.U | DATA_ACCESS_MASK7.U))))
|
|
||||||
|
|
||||||
val regpred_access_fault_d = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic)
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|
||||||
val picm_access_fault_d = (io.addr_in_pic_d & ((io.start_addr_d(1,0) =/= 0.U(2.W)) | ~io.lsu_pkt_d.word))
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|
||||||
|
|
||||||
val unmapped_access_fault_d = WireInit(1.U(1.W))
|
|
||||||
val mpu_access_fault_d = WireInit(1.U(1.W))
|
|
||||||
if(DCCM_REGION == PIC_REGION){
|
|
||||||
unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~(start_addr_in_dccm_d | start_addr_in_pic_d)) |
|
|
||||||
// 0. Addr in dccm/pic region but not in dccm/pic offset
|
|
||||||
(end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d)) |
|
|
||||||
// 0. Addr in dccm/pic region but not in dccm/pic offset
|
|
||||||
(start_addr_in_dccm_d & end_addr_in_pic_d) |
|
|
||||||
// 0. DCCM -> PIC cross when DCCM/PIC in same region
|
|
||||||
(start_addr_in_pic_d & end_addr_in_dccm_d))
|
|
||||||
// 0. DCCM -> PIC cross when DCCM/PIC in same region
|
|
||||||
mpu_access_fault_d := (~start_addr_in_dccm_region_d & ~non_dccm_access_ok)
|
|
||||||
// 3. Address is not in a populated non-dccm region
|
|
||||||
}
|
|
||||||
|
|
||||||
else{
|
|
||||||
unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d) |
|
|
||||||
(start_addr_in_pic_region_d & ~start_addr_in_pic_d) | (end_addr_in_pic_region_d & ~end_addr_in_pic_d))
|
|
||||||
mpu_access_fault_d := (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);
|
|
||||||
// 3. Address is not in a populated non-dccm region
|
|
||||||
}
|
|
||||||
|
|
||||||
//check width of access_fault_mscause_d
|
|
||||||
io.access_fault_d := (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma
|
|
||||||
val access_fault_mscause_d = Mux(unmapped_access_fault_d.asBool,2.U(4.W), Mux(mpu_access_fault_d.asBool,3.U(4.W), Mux(regpred_access_fault_d.asBool,5.U(4.W), Mux(picm_access_fault_d.asBool,6.U(4.W),0.U(4.W)))))
|
|
||||||
val regcross_misaligned_fault_d = (io.start_addr_d(31,28) =/= io.end_addr_d(31,28))
|
|
||||||
val sideeffect_misaligned_fault_d = (is_sideeffects_d & ~ is_aligned_d)
|
|
||||||
io.misaligned_fault_d := (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & io.addr_external_d)) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma
|
|
||||||
val misaligned_fault_mscause_d = Mux(regcross_misaligned_fault_d,2.U(4.W),Mux(sideeffect_misaligned_fault_d.asBool,1.U(4.W),0.U(4.W)))
|
|
||||||
io.exc_mscause_d := Mux(io.misaligned_fault_d.asBool, misaligned_fault_mscause_d(3,0), access_fault_mscause_d(3,0))
|
|
||||||
io.fir_dccm_access_error_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d)|(end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
|
||||||
io.fir_nondccm_access_error_d := ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
|
||||||
|
|
||||||
withClock(io.lsu_c2_m_clk){io.is_sideeffects_m := RegNext(is_sideeffects_d,0.U)} //TBD for clock and reset
|
|
||||||
}
|
|
||||||
//println(chisel3.Driver.emitVerilog(new el2_lsu_addrcheck))
|
|
||||||
|
|
||||||
object address_checker extends App{
|
|
||||||
println("Generate Verilog")
|
|
||||||
chisel3.Driver.execute(args, ()=> new el2_lsu_addrcheck)
|
|
||||||
}
|
|
||||||
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Reference in New Issue