colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

LSU Top added

This commit is contained in:
​Laraib Khan 2021-01-08 16:13:00 +05:00
parent 7881351a25
commit be9a487ba1
23 changed files with 20154 additions and 13576 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

623
lsu.anno.json
View File

@ -10,29 +10,11 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_mken", "sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata",
"sources":[ "sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", "~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi", "~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo", "~lsu|lsu>io_dccm_rd_data_lo"
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
] ]
}, },
{ {
@ -45,6 +27,17 @@
"~lsu|lsu>io_dccm_rd_data_lo" "~lsu|lsu>io_dccm_rd_data_lo"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rd_addr_hi",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dccm_ready", "sink":"~lsu|lsu>io_lsu_dma_dccm_ready",
@ -52,6 +45,166 @@
"~lsu|lsu>io_dec_lsu_valid_raw_d" "~lsu|lsu>io_dec_lsu_valid_raw_d"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_data_hi",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wren",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_addr_hi",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy",
"sources":[
"~lsu|lsu>io_axi_ar_ready",
"~lsu|lsu>io_axi_aw_ready",
"~lsu|lsu>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_rden",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rd_addr_lo",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_addr_lo",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_fir_addr",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wr_data",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_trigger_match_m", "sink":"~lsu|lsu>io_lsu_trigger_match_m",
@ -80,232 +233,7 @@
"~lsu|lsu>io_trigger_pkt_any_3_match_pkt", "~lsu|lsu>io_trigger_pkt_any_3_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_2_tdata2", "~lsu|lsu>io_trigger_pkt_any_2_tdata2",
"~lsu|lsu>io_trigger_pkt_any_2_match_pkt", "~lsu|lsu>io_trigger_pkt_any_2_match_pkt",
"~lsu|lsu>io_lsu_pic_picm_rd_data", "~lsu|lsu>io_lsu_pic_picm_rd_data"
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wren",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy",
"sources":[
"~lsu|lsu>io_axi_ar_ready",
"~lsu|lsu>io_axi_aw_ready",
"~lsu|lsu>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_data_hi",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_addr_lo",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_store_stall_any",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata",
"sources":[
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_addr_hi",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_fastint_stall_any",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rd_addr_hi",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_result_m",
"sources":[
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_data_lo",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
] ]
}, },
{ {
@ -323,18 +251,12 @@
"~lsu|lsu>io_lsu_p_bits_dword", "~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half", "~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word", "~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz"
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error", "sink":"~lsu|lsu>io_lsu_result_corr_r",
"sources":[ "sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable", "~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi", "~lsu|lsu>io_dccm_rd_data_hi",
@ -343,58 +265,50 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_rden", "sink":"~lsu|lsu>io_lsu_store_stall_any",
"sources":[ "sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d", "~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword", "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
"~lsu|lsu>io_lsu_p_bits_half", ]
"~lsu|lsu>io_lsu_p_bits_word", },
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", {
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_fastint_stall_any",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wraddr",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_load_stall_any",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_offset_d", "~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword", "~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half", "~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word", "~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz"
"~lsu|lsu>io_dec_tlu_flush_lower_r", ]
"~lsu|lsu>io_dec_tlu_force_halt", },
"~lsu|lsu>io_lsu_pic_picm_rd_data", {
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_fir_error",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi", "~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo", "~lsu|lsu>io_dccm_rd_data_lo"
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
] ]
}, },
{ {
@ -416,40 +330,13 @@
"~lsu|lsu>io_lsu_p_bits_fast_int", "~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load", "~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_store", "~lsu|lsu>io_lsu_p_bits_store"
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rd_addr_lo", "sink":"~lsu|lsu>io_lsu_pic_picm_mken",
"sources":[ "sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wr_data",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d", "~lsu|lsu>io_dec_lsu_valid_raw_d",
@ -459,24 +346,72 @@
"~lsu|lsu>io_lsu_p_bits_half", "~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word", "~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid", "~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r", "~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int", "~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_p_bits_store", "~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_dec_tlu_force_halt", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wraddr", "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned",
"sources":[ "sources":[
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr", "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_error_pkt_r_bits_single_ecc_error",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_error_pkt_r_valid",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_load_stall_any",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_data_lo",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
@ -487,32 +422,16 @@
"~lsu|lsu>io_lsu_p_bits_dword", "~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half", "~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word", "~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata"
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr", "sink":"~lsu|lsu>io_lsu_error_pkt_r_bits_mscause",
"sources":[ "sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", "~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi", "~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo", "~lsu|lsu>io_dccm_rd_data_lo"
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
] ]
}, },
{ {

15878
lsu.fir
View File

File diff suppressed because it is too large Load Diff

9975
lsu.v
View File

File diff suppressed because it is too large Load Diff

393
lsu_dccm_ctl.anno.json Normal file
View File

@ -0,0 +1,393 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wren",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_lo_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_data_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_ecc_lo",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_lo",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_ecc_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wr_data",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dma_mem_wdata",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wren",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_commit_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_addr_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_picm_mask_data_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_data_ecc_lo_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_lo_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rden",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_hi_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_hi_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_data_ecc_hi_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_ld_data_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_lo_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_lo_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rden",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wraddr",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dma_mem_addr",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_data_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_ecc_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_ecc_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_hi_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_addr_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_mken",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rdata",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ldst_dual_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_addr_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rdaddr",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_ecc_error",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_double_ecc_error_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_ld_data_corr_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_addr_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_double_ecc_error_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_single_ecc_error_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_raw_fwd_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_single_ecc_error_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_raw_fwd_hi_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rvalid",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_dccm_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_dccm_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2435
lsu_dccm_ctl.fir Normal file
View File

File diff suppressed because it is too large Load Diff

1436
lsu_dccm_ctl.v Normal file
View File

File diff suppressed because it is too large Load Diff

372
lsu_lsc_ctl.anno.json Normal file
View File

@ -0,0 +1,372 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_store_data_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_picm_mask_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_store_data_bypass_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_fast_int",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_fir_addr",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_bits_mscause",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dma",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_stack",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_stack",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_valid",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_dccm_req",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_m_up",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_unsign",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_bits_addr",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_fir_error",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_fast_int",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_bits_inst_type",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_dccm_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_valid",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_fast_int",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_incr",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_by",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_fast_int",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_corr_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_lsc_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_lsc_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

926
lsu_lsc_ctl.fir Normal file
View File

@ -0,0 +1,926 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit lsu_lsc_ctl :
module lsu_addrcheck :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 365:27]
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 365:49]
wire start_addr_in_dccm_d : UInt<1> @[lib.scala 366:26]
node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 370:24]
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 370:39]
start_addr_in_dccm_d <= _T_2 @[lib.scala 370:16]
node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 365:27]
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 365:49]
wire end_addr_in_dccm_d : UInt<1> @[lib.scala 366:26]
node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 370:24]
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 370:39]
end_addr_in_dccm_d <= _T_5 @[lib.scala 370:16]
wire addr_in_iccm : UInt<1>
addr_in_iccm <= UInt<1>("h00")
node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37]
node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45]
addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18]
node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89]
node _T_9 = bits(_T_8, 31, 28) @[lib.scala 365:27]
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 365:49]
wire start_addr_in_pic_d : UInt<1> @[lib.scala 366:26]
node _T_10 = bits(_T_8, 31, 15) @[lib.scala 370:24]
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 370:39]
start_addr_in_pic_d <= _T_11 @[lib.scala 370:16]
node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83]
node _T_13 = bits(_T_12, 31, 28) @[lib.scala 365:27]
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 365:49]
wire end_addr_in_pic_d : UInt<1> @[lib.scala 366:26]
node _T_14 = bits(_T_12, 31, 15) @[lib.scala 370:24]
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 370:39]
end_addr_in_pic_d <= _T_15 @[lib.scala 370:16]
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60]
node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49]
node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55]
node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74]
node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109]
node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115]
node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91]
node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57]
io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32]
node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56]
io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32]
node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63]
node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33]
io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30]
node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51]
node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50]
node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50]
node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92]
node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62]
node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60]
node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137]
node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185]
node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158]
node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80]
node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56]
node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138]
node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116]
node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90]
node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148]
node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58]
node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58]
node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58]
node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99]
node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33]
node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49]
node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56]
node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121]
node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88]
node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30]
node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49]
node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56]
node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121]
node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88]
node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30]
node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153]
node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49]
node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56]
node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121]
node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88]
node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30]
node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153]
node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49]
node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56]
node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121]
node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88]
node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30]
node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153]
node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49]
node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56]
node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121]
node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88]
node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30]
node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153]
node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49]
node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56]
node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121]
node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88]
node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30]
node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153]
node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49]
node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56]
node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121]
node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88]
node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30]
node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153]
node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49]
node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56]
node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121]
node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88]
node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30]
node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153]
node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48]
node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57]
node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122]
node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89]
node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31]
node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49]
node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58]
node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123]
node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90]
node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32]
node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154]
node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49]
node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58]
node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123]
node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90]
node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32]
node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155]
node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49]
node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58]
node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123]
node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90]
node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32]
node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155]
node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49]
node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58]
node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123]
node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90]
node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32]
node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155]
node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49]
node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58]
node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123]
node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90]
node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32]
node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155]
node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49]
node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58]
node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123]
node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90]
node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32]
node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155]
node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49]
node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58]
node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123]
node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90]
node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32]
node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155]
node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7]
node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104]
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57]
node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70]
node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76]
node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92]
node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90]
node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51]
wire unmapped_access_fault_d : UInt<1>
unmapped_access_fault_d <= UInt<1>("h01")
wire mpu_access_fault_d : UInt<1>
mpu_access_fault_d <= UInt<1>("h01")
node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87]
node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64]
node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62]
node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57]
node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36]
node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34]
node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112]
node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29]
node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85]
node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29]
node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85]
unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29]
node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33]
node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64]
node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62]
mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29]
node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49]
node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70]
node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92]
node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118]
node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141]
node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139]
io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21]
node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60]
node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100]
node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144]
node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185]
node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164]
node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120]
node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80]
node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35]
node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53]
node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78]
node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61]
node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59]
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57]
node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90]
node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57]
node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113]
node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136]
node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134]
io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25]
node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111]
node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80]
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39]
node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50]
node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84]
node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113]
node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27]
io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21]
node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66]
node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64]
node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120]
node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118]
node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88]
node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142]
node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163]
io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31]
node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66]
node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36]
node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95]
node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116]
io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33]
reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60]
_T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60]
io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50]
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
module lsu_lsc_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
wire end_addr_pre_m : UInt<29>
end_addr_pre_m <= UInt<29>("h00")
wire end_addr_pre_r : UInt<29>
end_addr_pre_r <= UInt<29>("h00")
wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 93:29]
wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 94:29]
wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29]
wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 96:29]
wire _T : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 97:37]
_T.bits.addr <= UInt<32>("h00") @[lsu_lsc_ctl.scala 97:37]
_T.bits.mscause <= UInt<4>("h00") @[lsu_lsc_ctl.scala 97:37]
_T.bits.exc_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:37]
_T.bits.inst_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:37]
_T.bits.single_ecc_error <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:37]
_T.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:37]
lsu_error_pkt_m.bits.addr <= _T.bits.addr @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.bits.mscause <= _T.bits.mscause @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.bits.exc_type <= _T.bits.exc_type @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.bits.inst_type <= _T.bits.inst_type @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.bits.single_ecc_error <= _T.bits.single_ecc_error @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.valid <= _T.valid @[lsu_lsc_ctl.scala 97:20]
node _T_1 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 100:52]
node lsu_rs1_d = mux(_T_1, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 100:28]
node _T_2 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 101:44]
node _T_3 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15]
node _T_4 = mux(_T_3, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node lsu_offset_d = and(_T_2, _T_4) @[lsu_lsc_ctl.scala 101:51]
node _T_5 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 104:66]
node rs1_d = mux(_T_5, io.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 104:28]
node _T_6 = bits(rs1_d, 11, 0) @[lib.scala 92:31]
node _T_7 = cat(UInt<1>("h00"), _T_6) @[Cat.scala 29:58]
node _T_8 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60]
node _T_9 = cat(UInt<1>("h00"), _T_8) @[Cat.scala 29:58]
node _T_10 = add(_T_7, _T_9) @[lib.scala 92:39]
node _T_11 = tail(_T_10, 1) @[lib.scala 92:39]
node _T_12 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41]
node _T_13 = bits(_T_11, 12, 12) @[lib.scala 93:50]
node _T_14 = xor(_T_12, _T_13) @[lib.scala 93:46]
node _T_15 = not(_T_14) @[lib.scala 93:33]
node _T_16 = bits(_T_15, 0, 0) @[Bitwise.scala 72:15]
node _T_17 = mux(_T_16, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_18 = bits(rs1_d, 31, 12) @[lib.scala 93:63]
node _T_19 = and(_T_17, _T_18) @[lib.scala 93:58]
node _T_20 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25]
node _T_21 = not(_T_20) @[lib.scala 94:18]
node _T_22 = bits(_T_11, 12, 12) @[lib.scala 94:34]
node _T_23 = and(_T_21, _T_22) @[lib.scala 94:30]
node _T_24 = bits(_T_23, 0, 0) @[Bitwise.scala 72:15]
node _T_25 = mux(_T_24, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_26 = bits(rs1_d, 31, 12) @[lib.scala 94:47]
node _T_27 = add(_T_26, UInt<1>("h01")) @[lib.scala 94:54]
node _T_28 = tail(_T_27, 1) @[lib.scala 94:54]
node _T_29 = and(_T_25, _T_28) @[lib.scala 94:41]
node _T_30 = or(_T_19, _T_29) @[lib.scala 93:72]
node _T_31 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24]
node _T_32 = bits(_T_11, 12, 12) @[lib.scala 95:34]
node _T_33 = not(_T_32) @[lib.scala 95:31]
node _T_34 = and(_T_31, _T_33) @[lib.scala 95:29]
node _T_35 = bits(_T_34, 0, 0) @[Bitwise.scala 72:15]
node _T_36 = mux(_T_35, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_37 = bits(rs1_d, 31, 12) @[lib.scala 95:47]
node _T_38 = sub(_T_37, UInt<1>("h01")) @[lib.scala 95:54]
node _T_39 = tail(_T_38, 1) @[lib.scala 95:54]
node _T_40 = and(_T_36, _T_39) @[lib.scala 95:41]
node _T_41 = or(_T_30, _T_40) @[lib.scala 94:61]
node _T_42 = bits(_T_11, 11, 0) @[lib.scala 96:22]
node full_addr_d = cat(_T_41, _T_42) @[Cat.scala 29:58]
node _T_43 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15]
node _T_44 = mux(_T_43, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_45 = and(_T_44, UInt<3>("h01")) @[lsu_lsc_ctl.scala 109:58]
node _T_46 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_47 = mux(_T_46, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_48 = and(_T_47, UInt<3>("h03")) @[lsu_lsc_ctl.scala 110:40]
node _T_49 = or(_T_45, _T_48) @[lsu_lsc_ctl.scala 109:70]
node _T_50 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15]
node _T_51 = mux(_T_50, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_52 = and(_T_51, UInt<3>("h07")) @[lsu_lsc_ctl.scala 111:40]
node addr_offset_d = or(_T_49, _T_52) @[lsu_lsc_ctl.scala 110:52]
node _T_53 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 113:39]
node _T_54 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 113:52]
node _T_55 = cat(_T_53, _T_54) @[Cat.scala 29:58]
node _T_56 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_57 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 113:91]
node _T_58 = cat(_T_56, _T_57) @[Cat.scala 29:58]
node _T_59 = add(_T_55, _T_58) @[lsu_lsc_ctl.scala 113:60]
node end_addr_offset_d = tail(_T_59, 1) @[lsu_lsc_ctl.scala 113:60]
node _T_60 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 114:32]
node _T_61 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 114:70]
node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15]
node _T_63 = mux(_T_62, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
node _T_64 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 114:93]
node _T_65 = cat(_T_63, _T_64) @[Cat.scala 29:58]
node _T_66 = add(_T_60, _T_65) @[lsu_lsc_ctl.scala 114:39]
node full_end_addr_d = tail(_T_66, 1) @[lsu_lsc_ctl.scala 114:39]
io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 115:24]
inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 118:25]
addrcheck.clock <= clock
addrcheck.reset <= reset
addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 120:42]
addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 122:42]
addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 125:42]
node _T_67 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 126:50]
addrcheck.io.rs1_region_d <= _T_67 @[lsu_lsc_ctl.scala 126:42]
addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 127:42]
io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 128:42]
io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 129:42]
io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 130:42]
addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 137:42]
wire exc_mscause_r : UInt<4>
exc_mscause_r <= UInt<4>("h00")
wire fir_dccm_access_error_r : UInt<1>
fir_dccm_access_error_r <= UInt<1>("h00")
wire fir_nondccm_access_error_r : UInt<1>
fir_nondccm_access_error_r <= UInt<1>("h00")
wire access_fault_r : UInt<1>
access_fault_r <= UInt<1>("h00")
wire misaligned_fault_r : UInt<1>
misaligned_fault_r <= UInt<1>("h00")
wire lsu_fir_error_m : UInt<2>
lsu_fir_error_m <= UInt<2>("h00")
wire fir_dccm_access_error_m : UInt<1>
fir_dccm_access_error_m <= UInt<1>("h00")
wire fir_nondccm_access_error_m : UInt<1>
fir_nondccm_access_error_m <= UInt<1>("h00")
reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75]
access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 149:75]
reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75]
misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 150:75]
reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75]
exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 151:75]
reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75]
_T_68 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 152:75]
fir_dccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 152:38]
reg _T_69 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 153:75]
_T_69 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 153:75]
fir_nondccm_access_error_m <= _T_69 @[lsu_lsc_ctl.scala 153:38]
node _T_70 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 155:34]
io.lsu_exc_m <= _T_70 @[lsu_lsc_ctl.scala 155:16]
node _T_71 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 156:64]
node _T_72 = and(io.lsu_single_ecc_error_r, _T_71) @[lsu_lsc_ctl.scala 156:62]
node _T_73 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 156:111]
node _T_74 = and(_T_72, _T_73) @[lsu_lsc_ctl.scala 156:92]
node _T_75 = and(_T_74, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 156:136]
io.lsu_single_ecc_error_incr <= _T_75 @[lsu_lsc_ctl.scala 156:32]
node _T_76 = or(access_fault_r, misaligned_fault_r) @[lsu_lsc_ctl.scala 160:49]
node _T_77 = or(_T_76, io.lsu_double_ecc_error_r) @[lsu_lsc_ctl.scala 160:70]
node _T_78 = and(_T_77, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 160:99]
node _T_79 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 160:122]
node _T_80 = and(_T_78, _T_79) @[lsu_lsc_ctl.scala 160:120]
node _T_81 = eq(io.lsu_pkt_r.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 160:147]
node _T_82 = and(_T_80, _T_81) @[lsu_lsc_ctl.scala 160:145]
io.lsu_error_pkt_r.valid <= _T_82 @[lsu_lsc_ctl.scala 160:30]
node _T_83 = eq(io.lsu_error_pkt_r.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 161:77]
node _T_84 = and(io.lsu_single_ecc_error_r, _T_83) @[lsu_lsc_ctl.scala 161:75]
node _T_85 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 161:105]
node _T_86 = and(_T_84, _T_85) @[lsu_lsc_ctl.scala 161:103]
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_86 @[lsu_lsc_ctl.scala 161:46]
io.lsu_error_pkt_r.bits.inst_type <= io.lsu_pkt_r.bits.store @[lsu_lsc_ctl.scala 162:39]
node _T_87 = not(misaligned_fault_r) @[lsu_lsc_ctl.scala 163:42]
io.lsu_error_pkt_r.bits.exc_type <= _T_87 @[lsu_lsc_ctl.scala 163:39]
node _T_88 = eq(misaligned_fault_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 164:75]
node _T_89 = and(io.lsu_double_ecc_error_r, _T_88) @[lsu_lsc_ctl.scala 164:73]
node _T_90 = eq(access_fault_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 164:97]
node _T_91 = and(_T_89, _T_90) @[lsu_lsc_ctl.scala 164:95]
node _T_92 = bits(_T_91, 0, 0) @[lsu_lsc_ctl.scala 164:114]
node _T_93 = bits(exc_mscause_r, 3, 0) @[lsu_lsc_ctl.scala 164:144]
node _T_94 = mux(_T_92, UInt<4>("h01"), _T_93) @[lsu_lsc_ctl.scala 164:45]
io.lsu_error_pkt_r.bits.mscause <= _T_94 @[lsu_lsc_ctl.scala 164:39]
node _T_95 = bits(io.lsu_addr_r, 31, 0) @[lsu_lsc_ctl.scala 165:55]
io.lsu_error_pkt_r.bits.addr <= _T_95 @[lsu_lsc_ctl.scala 165:39]
node _T_96 = bits(fir_nondccm_access_error_r, 0, 0) @[lsu_lsc_ctl.scala 166:68]
node _T_97 = bits(fir_dccm_access_error_r, 0, 0) @[lsu_lsc_ctl.scala 166:113]
node _T_98 = and(io.lsu_pkt_r.bits.fast_int, io.lsu_double_ecc_error_r) @[lsu_lsc_ctl.scala 166:162]
node _T_99 = bits(_T_98, 0, 0) @[lsu_lsc_ctl.scala 166:191]
node _T_100 = mux(_T_99, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 166:133]
node _T_101 = mux(_T_97, UInt<2>("h02"), _T_100) @[lsu_lsc_ctl.scala 166:88]
node _T_102 = mux(_T_96, UInt<2>("h03"), _T_101) @[lsu_lsc_ctl.scala 166:40]
io.lsu_fir_error <= _T_102 @[lsu_lsc_ctl.scala 166:34]
reg _T_103 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 168:71]
_T_103 <= access_fault_m @[lsu_lsc_ctl.scala 168:71]
access_fault_r <= _T_103 @[lsu_lsc_ctl.scala 168:34]
reg _T_104 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 169:71]
_T_104 <= exc_mscause_m @[lsu_lsc_ctl.scala 169:71]
exc_mscause_r <= _T_104 @[lsu_lsc_ctl.scala 169:34]
reg _T_105 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 170:71]
_T_105 <= fir_dccm_access_error_m @[lsu_lsc_ctl.scala 170:71]
fir_dccm_access_error_r <= _T_105 @[lsu_lsc_ctl.scala 170:34]
reg _T_106 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 171:71]
_T_106 <= fir_nondccm_access_error_m @[lsu_lsc_ctl.scala 171:71]
fir_nondccm_access_error_r <= _T_106 @[lsu_lsc_ctl.scala 171:34]
reg _T_107 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 172:71]
_T_107 <= misaligned_fault_m @[lsu_lsc_ctl.scala 172:71]
misaligned_fault_r <= _T_107 @[lsu_lsc_ctl.scala 172:34]
dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:27]
dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:26]
dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 192:27]
dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 193:22]
dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 194:27]
dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 195:27]
node _T_108 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 196:30]
dma_pkt_d.bits.load <= _T_108 @[lsu_lsc_ctl.scala 196:27]
node _T_109 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56]
node _T_110 = eq(_T_109, UInt<3>("h00")) @[lsu_lsc_ctl.scala 197:62]
dma_pkt_d.bits.by <= _T_110 @[lsu_lsc_ctl.scala 197:27]
node _T_111 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56]
node _T_112 = eq(_T_111, UInt<3>("h01")) @[lsu_lsc_ctl.scala 198:62]
dma_pkt_d.bits.half <= _T_112 @[lsu_lsc_ctl.scala 198:27]
node _T_113 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56]
node _T_114 = eq(_T_113, UInt<3>("h02")) @[lsu_lsc_ctl.scala 199:62]
dma_pkt_d.bits.word <= _T_114 @[lsu_lsc_ctl.scala 199:27]
node _T_115 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 200:56]
node _T_116 = eq(_T_115, UInt<3>("h03")) @[lsu_lsc_ctl.scala 200:62]
dma_pkt_d.bits.dword <= _T_116 @[lsu_lsc_ctl.scala 200:27]
dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39]
dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39]
dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 203:39]
wire lsu_ld_datafn_r : UInt<32>
lsu_ld_datafn_r <= UInt<32>("h00")
wire lsu_ld_datafn_corr_r : UInt<32>
lsu_ld_datafn_corr_r <= UInt<32>("h00")
wire lsu_ld_datafn_m : UInt<32>
lsu_ld_datafn_m <= UInt<32>("h00")
node _T_117 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 209:50]
node _T_118 = mux(_T_117, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 209:26]
io.lsu_pkt_d.bits.store_data_bypass_m <= _T_118.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_118.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.store_data_bypass_d <= _T_118.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.dma <= _T_118.bits.dma @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.unsign <= _T_118.bits.unsign @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.store <= _T_118.bits.store @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.load <= _T_118.bits.load @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.dword <= _T_118.bits.dword @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.word <= _T_118.bits.word @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.half <= _T_118.bits.half @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.by <= _T_118.bits.by @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.stack <= _T_118.bits.stack @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.fast_int <= _T_118.bits.fast_int @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.valid <= _T_118.valid @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 211:20]
node _T_119 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:64]
node _T_120 = and(io.flush_m_up, _T_119) @[lsu_lsc_ctl.scala 213:61]
node _T_121 = eq(_T_120, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:45]
node _T_122 = and(io.lsu_p.valid, _T_121) @[lsu_lsc_ctl.scala 213:43]
node _T_123 = or(_T_122, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 213:90]
io.lsu_pkt_d.valid <= _T_123 @[lsu_lsc_ctl.scala 213:24]
node _T_124 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68]
node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 214:65]
node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49]
node _T_127 = and(io.lsu_pkt_d.valid, _T_126) @[lsu_lsc_ctl.scala 214:47]
lsu_pkt_m_in.valid <= _T_127 @[lsu_lsc_ctl.scala 214:24]
node _T_128 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 215:68]
node _T_129 = and(io.flush_m_up, _T_128) @[lsu_lsc_ctl.scala 215:65]
node _T_130 = eq(_T_129, UInt<1>("h00")) @[lsu_lsc_ctl.scala 215:49]
node _T_131 = and(io.lsu_pkt_m.valid, _T_130) @[lsu_lsc_ctl.scala 215:47]
lsu_pkt_r_in.valid <= _T_131 @[lsu_lsc_ctl.scala 215:24]
wire _T_132 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
reg _T_133 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_132)) @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65]
_T_133.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 217:65]
io.lsu_pkt_m.bits.store_data_bypass_m <= _T_133.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_133.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.store_data_bypass_d <= _T_133.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.dma <= _T_133.bits.dma @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.unsign <= _T_133.bits.unsign @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.store <= _T_133.bits.store @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.load <= _T_133.bits.load @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.dword <= _T_133.bits.dword @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.word <= _T_133.bits.word @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.half <= _T_133.bits.half @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.by <= _T_133.bits.by @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.stack <= _T_133.bits.stack @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.fast_int <= _T_133.bits.fast_int @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.valid <= _T_133.valid @[lsu_lsc_ctl.scala 217:28]
wire _T_134 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
reg _T_135 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_134)) @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 218:65]
_T_135.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 218:65]
io.lsu_pkt_r.bits.store_data_bypass_m <= _T_135.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_135.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.store_data_bypass_d <= _T_135.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.dma <= _T_135.bits.dma @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.unsign <= _T_135.bits.unsign @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.store <= _T_135.bits.store @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.load <= _T_135.bits.load @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.dword <= _T_135.bits.dword @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.word <= _T_135.bits.word @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.half <= _T_135.bits.half @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.by <= _T_135.bits.by @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.stack <= _T_135.bits.stack @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.fast_int <= _T_135.bits.fast_int @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.valid <= _T_135.valid @[lsu_lsc_ctl.scala 218:28]
reg _T_136 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65]
_T_136 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 219:65]
io.lsu_pkt_m.valid <= _T_136 @[lsu_lsc_ctl.scala 219:28]
reg _T_137 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 220:65]
_T_137 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 220:65]
io.lsu_pkt_r.valid <= _T_137 @[lsu_lsc_ctl.scala 220:28]
node _T_138 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 222:59]
node _T_139 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 222:100]
node _T_140 = cat(_T_139, UInt<3>("h00")) @[Cat.scala 29:58]
node dma_mem_wdata_shifted = dshr(_T_138, _T_140) @[lsu_lsc_ctl.scala 222:66]
node _T_141 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 223:63]
node _T_142 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 223:91]
node _T_143 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 223:122]
node store_data_d = mux(_T_141, _T_142, _T_143) @[lsu_lsc_ctl.scala 223:34]
node _T_144 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 224:73]
node _T_145 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 224:95]
node _T_146 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 224:114]
node store_data_m_in = mux(_T_144, _T_145, _T_146) @[lsu_lsc_ctl.scala 224:34]
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:72]
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 226:72]
reg _T_147 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62]
_T_147 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 227:62]
io.lsu_addr_m <= _T_147 @[lsu_lsc_ctl.scala 227:24]
reg _T_148 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:62]
_T_148 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 228:62]
io.lsu_addr_r <= _T_148 @[lsu_lsc_ctl.scala 228:24]
node _T_149 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
node _T_150 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:71]
node _T_151 = mux(_T_149, end_addr_pre_m, _T_150) @[lsu_lsc_ctl.scala 229:27]
node _T_152 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:128]
reg _T_153 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114]
_T_153 <= _T_152 @[lsu_lsc_ctl.scala 229:114]
node _T_154 = cat(_T_151, _T_153) @[Cat.scala 29:58]
io.end_addr_m <= _T_154 @[lsu_lsc_ctl.scala 229:17]
node _T_155 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
node _T_156 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:71]
node _T_157 = mux(_T_155, end_addr_pre_r, _T_156) @[lsu_lsc_ctl.scala 230:27]
node _T_158 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:128]
reg _T_159 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:114]
_T_159 <= _T_158 @[lsu_lsc_ctl.scala 230:114]
node _T_160 = cat(_T_157, _T_159) @[Cat.scala 29:58]
io.end_addr_r <= _T_160 @[lsu_lsc_ctl.scala 230:17]
node _T_161 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 231:41]
node _T_162 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 231:69]
node _T_163 = or(_T_162, io.clk_override) @[lsu_lsc_ctl.scala 231:87]
node _T_164 = bits(_T_163, 0, 0) @[lib.scala 8:44]
node _T_165 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr of rvclkhdr @[lib.scala 390:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 392:18]
rvclkhdr.io.en <= _T_164 @[lib.scala 393:17]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_164 : @[Reg.scala 28:19]
_T_166 <= _T_161 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
end_addr_pre_m <= _T_166 @[lsu_lsc_ctl.scala 231:18]
node _T_167 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:41]
node _T_168 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 232:69]
node _T_169 = or(_T_168, io.clk_override) @[lsu_lsc_ctl.scala 232:87]
node _T_170 = bits(_T_169, 0, 0) @[lib.scala 8:44]
node _T_171 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_1.io.en <= _T_170 @[lib.scala 393:17]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_172 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_170 : @[Reg.scala 28:19]
_T_172 <= _T_167 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
end_addr_pre_r <= _T_172 @[lsu_lsc_ctl.scala 232:18]
reg _T_173 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62]
_T_173 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 233:62]
io.addr_in_dccm_m <= _T_173 @[lsu_lsc_ctl.scala 233:24]
reg _T_174 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62]
_T_174 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 234:62]
io.addr_in_dccm_r <= _T_174 @[lsu_lsc_ctl.scala 234:24]
reg _T_175 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62]
_T_175 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 235:62]
io.addr_in_pic_m <= _T_175 @[lsu_lsc_ctl.scala 235:24]
reg _T_176 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
_T_176 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 236:62]
io.addr_in_pic_r <= _T_176 @[lsu_lsc_ctl.scala 236:24]
reg _T_177 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62]
_T_177 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 237:62]
io.addr_external_m <= _T_177 @[lsu_lsc_ctl.scala 237:24]
reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:66]
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 238:66]
node _T_178 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 239:77]
node _T_179 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_2.io.en <= _T_178 @[lib.scala 393:17]
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg bus_read_data_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_178 : @[Reg.scala 28:19]
bus_read_data_r <= io.bus_read_data_m @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
node _T_180 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 242:52]
io.lsu_fir_addr <= _T_180 @[lsu_lsc_ctl.scala 242:28]
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 244:28]
node _T_181 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 246:68]
node _T_182 = and(io.lsu_pkt_r.valid, _T_181) @[lsu_lsc_ctl.scala 246:41]
node _T_183 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:96]
node _T_184 = and(_T_182, _T_183) @[lsu_lsc_ctl.scala 246:94]
node _T_185 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:110]
node _T_186 = and(_T_184, _T_185) @[lsu_lsc_ctl.scala 246:108]
io.lsu_commit_r <= _T_186 @[lsu_lsc_ctl.scala 246:19]
node _T_187 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 247:52]
node _T_188 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 247:69]
node _T_189 = bits(_T_188, 0, 0) @[Bitwise.scala 72:15]
node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_191 = or(_T_187, _T_190) @[lsu_lsc_ctl.scala 247:59]
node _T_192 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 247:133]
node _T_193 = mux(_T_192, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 247:94]
node _T_194 = and(_T_191, _T_193) @[lsu_lsc_ctl.scala 247:89]
io.store_data_m <= _T_194 @[lsu_lsc_ctl.scala 247:29]
node _T_195 = bits(addr_external_r, 0, 0) @[lib.scala 8:44]
node _T_196 = mux(_T_195, bus_read_data_r, io.lsu_ld_data_r) @[lsu_lsc_ctl.scala 251:33]
lsu_ld_datafn_r <= _T_196 @[lsu_lsc_ctl.scala 251:27]
node _T_197 = bits(addr_external_r, 0, 0) @[lib.scala 8:44]
node _T_198 = mux(_T_197, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 252:33]
lsu_ld_datafn_corr_r <= _T_198 @[lsu_lsc_ctl.scala 252:27]
node _T_199 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 254:66]
node _T_200 = bits(_T_199, 0, 0) @[Bitwise.scala 72:15]
node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_202 = bits(lsu_ld_datafn_r, 7, 0) @[lsu_lsc_ctl.scala 254:125]
node _T_203 = cat(UInt<24>("h00"), _T_202) @[Cat.scala 29:58]
node _T_204 = and(_T_201, _T_203) @[lsu_lsc_ctl.scala 254:94]
node _T_205 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 255:43]
node _T_206 = bits(_T_205, 0, 0) @[Bitwise.scala 72:15]
node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_208 = bits(lsu_ld_datafn_r, 15, 0) @[lsu_lsc_ctl.scala 255:102]
node _T_209 = cat(UInt<16>("h00"), _T_208) @[Cat.scala 29:58]
node _T_210 = and(_T_207, _T_209) @[lsu_lsc_ctl.scala 255:71]
node _T_211 = or(_T_204, _T_210) @[lsu_lsc_ctl.scala 254:133]
node _T_212 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 256:17]
node _T_213 = and(_T_212, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 256:43]
node _T_214 = bits(_T_213, 0, 0) @[Bitwise.scala 72:15]
node _T_215 = mux(_T_214, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_216 = bits(lsu_ld_datafn_r, 7, 7) @[lsu_lsc_ctl.scala 256:102]
node _T_217 = bits(_T_216, 0, 0) @[Bitwise.scala 72:15]
node _T_218 = mux(_T_217, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_219 = bits(lsu_ld_datafn_r, 7, 0) @[lsu_lsc_ctl.scala 256:125]
node _T_220 = cat(_T_218, _T_219) @[Cat.scala 29:58]
node _T_221 = and(_T_215, _T_220) @[lsu_lsc_ctl.scala 256:71]
node _T_222 = or(_T_211, _T_221) @[lsu_lsc_ctl.scala 255:114]
node _T_223 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 257:17]
node _T_224 = and(_T_223, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 257:43]
node _T_225 = bits(_T_224, 0, 0) @[Bitwise.scala 72:15]
node _T_226 = mux(_T_225, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_227 = bits(lsu_ld_datafn_r, 15, 15) @[lsu_lsc_ctl.scala 257:101]
node _T_228 = bits(_T_227, 0, 0) @[Bitwise.scala 72:15]
node _T_229 = mux(_T_228, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_230 = bits(lsu_ld_datafn_r, 15, 0) @[lsu_lsc_ctl.scala 257:125]
node _T_231 = cat(_T_229, _T_230) @[Cat.scala 29:58]
node _T_232 = and(_T_226, _T_231) @[lsu_lsc_ctl.scala 257:71]
node _T_233 = or(_T_222, _T_232) @[lsu_lsc_ctl.scala 256:134]
node _T_234 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_236 = bits(lsu_ld_datafn_r, 31, 0) @[lsu_lsc_ctl.scala 258:60]
node _T_237 = and(_T_235, _T_236) @[lsu_lsc_ctl.scala 258:43]
node _T_238 = or(_T_233, _T_237) @[lsu_lsc_ctl.scala 257:134]
io.lsu_result_m <= _T_238 @[lsu_lsc_ctl.scala 254:27]
node _T_239 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 260:66]
node _T_240 = bits(_T_239, 0, 0) @[Bitwise.scala 72:15]
node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_242 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 260:130]
node _T_243 = cat(UInt<24>("h00"), _T_242) @[Cat.scala 29:58]
node _T_244 = and(_T_241, _T_243) @[lsu_lsc_ctl.scala 260:94]
node _T_245 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 261:43]
node _T_246 = bits(_T_245, 0, 0) @[Bitwise.scala 72:15]
node _T_247 = mux(_T_246, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_248 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 261:107]
node _T_249 = cat(UInt<16>("h00"), _T_248) @[Cat.scala 29:58]
node _T_250 = and(_T_247, _T_249) @[lsu_lsc_ctl.scala 261:71]
node _T_251 = or(_T_244, _T_250) @[lsu_lsc_ctl.scala 260:138]
node _T_252 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 262:17]
node _T_253 = and(_T_252, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 262:43]
node _T_254 = bits(_T_253, 0, 0) @[Bitwise.scala 72:15]
node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_256 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 262:107]
node _T_257 = bits(_T_256, 0, 0) @[Bitwise.scala 72:15]
node _T_258 = mux(_T_257, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_259 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 262:135]
node _T_260 = cat(_T_258, _T_259) @[Cat.scala 29:58]
node _T_261 = and(_T_255, _T_260) @[lsu_lsc_ctl.scala 262:71]
node _T_262 = or(_T_251, _T_261) @[lsu_lsc_ctl.scala 261:119]
node _T_263 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 263:17]
node _T_264 = and(_T_263, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 263:43]
node _T_265 = bits(_T_264, 0, 0) @[Bitwise.scala 72:15]
node _T_266 = mux(_T_265, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_267 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 263:106]
node _T_268 = bits(_T_267, 0, 0) @[Bitwise.scala 72:15]
node _T_269 = mux(_T_268, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_270 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 263:135]
node _T_271 = cat(_T_269, _T_270) @[Cat.scala 29:58]
node _T_272 = and(_T_266, _T_271) @[lsu_lsc_ctl.scala 263:71]
node _T_273 = or(_T_262, _T_272) @[lsu_lsc_ctl.scala 262:144]
node _T_274 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_276 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 264:65]
node _T_277 = and(_T_275, _T_276) @[lsu_lsc_ctl.scala 264:43]
node _T_278 = or(_T_273, _T_277) @[lsu_lsc_ctl.scala 263:144]
io.lsu_result_corr_r <= _T_278 @[lsu_lsc_ctl.scala 260:27]

1382
lsu_lsc_ctl.v Normal file
View File

File diff suppressed because it is too large Load Diff

2
src/main/scala/lib/param.scala
View File

@ -132,7 +132,7 @@ trait param {
val INST_ACCESS_MASK5 = 0xFFFFFFFF val INST_ACCESS_MASK5 = 0xFFFFFFFF
val INST_ACCESS_MASK6 = 0xFFFFFFFF val INST_ACCESS_MASK6 = 0xFFFFFFFF
val INST_ACCESS_MASK7 = 0xFFFFFFFF val INST_ACCESS_MASK7 = 0xFFFFFFFF
val LOAD_TO_USE_PLUS1 = 0x0 val LOAD_TO_USE_PLUS1 = 0x1
val LSU2DMA = 0x0 val LSU2DMA = 0x0
val LSU_BUS_ID = 0x1 val LSU_BUS_ID = 0x1
val LSU_BUS_PRTY = 0x2 val LSU_BUS_PRTY = 0x2

57
src/main/scala/lsu/lsu.scala
View File

@ -59,8 +59,13 @@ class lsu extends Module with RequireAsyncReset with param with lib {
val lsu_raw_fwd_hi_r = WireInit(0.U(1.W)) val lsu_raw_fwd_hi_r = WireInit(0.U(1.W))
val lsu_busm_clken = WireInit(0.U(1.W)) val lsu_busm_clken = WireInit(0.U(1.W))
val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W)) val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W))
val lsu_addr_d = WireInit(0.U(32.W))
val lsu_addr_m = WireInit(0.U(32.W))
val lsu_addr_r = WireInit(0.U(32.W))
val end_addr_d = WireInit(0.U(32.W))
val end_addr_m = WireInit(0.U(32.W))
val end_addr_r = WireInit(0.U(32.W))
val lsu_busreq_r = WireInit(Bool(),false.B)
val lsu_lsc_ctl = Module(new lsu_lsc_ctl()) val lsu_lsc_ctl = Module(new lsu_lsc_ctl())
io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m
@ -107,9 +112,9 @@ class lsu extends Module with RequireAsyncReset with param with lib {
// Bus signals // Bus signals
val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int
// Dual signals // Dual signals
val ldst_dual_d = lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2) val ldst_dual_d = lsu_addr_d(2) =/= end_addr_d(2)
val ldst_dual_m = lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2) val ldst_dual_m = lsu_addr_m(2) =/= end_addr_m(2)
val ldst_dual_r = lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2) val ldst_dual_r = lsu_addr_r(2) =/= end_addr_r(2)
// PMU signals // PMU signals
io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR)) io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR))
io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m
@ -145,7 +150,12 @@ class lsu extends Module with RequireAsyncReset with param with lib {
lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff
lsu_lsc_ctl.io.scan_mode := io.scan_mode lsu_lsc_ctl.io.scan_mode := io.scan_mode
//Outputs //Outputs
lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d
lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
end_addr_d := lsu_lsc_ctl.io.lsu_addr_d
end_addr_m := lsu_lsc_ctl.io.lsu_addr_m
end_addr_r := lsu_lsc_ctl.io.lsu_addr_r
io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr
io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r
io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr
@ -172,12 +182,12 @@ class lsu extends Module with RequireAsyncReset with param with lib {
dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r
dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r
dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
dccm_ctl.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d dccm_ctl.io.lsu_addr_d := lsu_addr_d
dccm_ctl.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m dccm_ctl.io.lsu_addr_m := lsu_addr_m(DCCM_BITS-1,0)
dccm_ctl.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r dccm_ctl.io.lsu_addr_r := lsu_addr_r
dccm_ctl.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d dccm_ctl.io.end_addr_d := end_addr_d(DCCM_BITS-1,0)
dccm_ctl.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m dccm_ctl.io.end_addr_m := end_addr_m(DCCM_BITS-1,0)
dccm_ctl.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r dccm_ctl.io.end_addr_r := end_addr_r(DCCM_BITS-1,0)
dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any
dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any
dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any
@ -228,10 +238,10 @@ class lsu extends Module with RequireAsyncReset with param with lib {
stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r
stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r
stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any
stbuf.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d stbuf.io.lsu_addr_d := lsu_addr_d
stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
stbuf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d stbuf.io.end_addr_d := end_addr_d
stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
@ -249,10 +259,10 @@ class lsu extends Module with RequireAsyncReset with param with lib {
ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable
ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r
ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
ecc.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r ecc.io.lsu_addr_r := lsu_addr_r
ecc.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r ecc.io.end_addr_r := end_addr_r
ecc.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m ecc.io.lsu_addr_m := lsu_addr_m
ecc.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m ecc.io.end_addr_m := end_addr_m
ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r
ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r
ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m
@ -319,11 +329,11 @@ class lsu extends Module with RequireAsyncReset with param with lib {
bus_intf.io.ldst_dual_d := ldst_dual_d bus_intf.io.ldst_dual_d := ldst_dual_d
bus_intf.io.ldst_dual_m := ldst_dual_m bus_intf.io.ldst_dual_m := ldst_dual_m
bus_intf.io.ldst_dual_r := ldst_dual_r bus_intf.io.ldst_dual_r := ldst_dual_r
bus_intf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m bus_intf.io.lsu_addr_m := lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid)
bus_intf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r bus_intf.io.lsu_addr_r := lsu_addr_r & Fill(32,lsu_busreq_r)
bus_intf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m bus_intf.io.end_addr_m := end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid)
bus_intf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r bus_intf.io.end_addr_r := end_addr_r & Fill(32,lsu_busreq_r)
bus_intf.io.store_data_r := dccm_ctl.io.store_data_r bus_intf.io.store_data_r := dccm_ctl.io.store_data_r & Fill(32,lsu_busreq_r)
bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt
@ -333,6 +343,7 @@ class lsu extends Module with RequireAsyncReset with param with lib {
bus_intf.io.flush_r := flush_r bus_intf.io.flush_r := flush_r
//Outputs //Outputs
io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff
lsu_busreq_r := bus_intf.io.lsu_busreq_r
io.axi <> bus_intf.io.axi io.axi <> bus_intf.io.axi
bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en

2
src/main/scala/lsu/lsu_dccm_ctl.scala
View File

@ -118,7 +118,7 @@ class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
val ld_single_ecc_error_lo_r_ff = WireInit(UInt(1.W),0.U) val ld_single_ecc_error_lo_r_ff = WireInit(UInt(1.W),0.U)
val ld_sec_addr_hi_r_ff = WireInit(UInt(DCCM_BITS.W),0.U) val ld_sec_addr_hi_r_ff = WireInit(UInt(DCCM_BITS.W),0.U)
val ld_sec_addr_lo_r_ff = WireInit(UInt(DCCM_BITS.W),0.U) val ld_sec_addr_lo_r_ff = WireInit(UInt(DCCM_BITS.W),0.U)
io.lsu_ld_data_m :=0.U
//Forwarding stbuf //Forwarding stbuf
if (LOAD_TO_USE_PLUS1 == 1){ if (LOAD_TO_USE_PLUS1 == 1){
io.dma_dccm_ctl.dccm_dma_rvalid := io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.load & io.lsu_pkt_r.bits.dma io.dma_dccm_ctl.dccm_dma_rvalid := io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.load & io.lsu_pkt_r.bits.dma

13
src/main/scala/lsu/lsu_lsc_ctl.scala
View File

@ -1,10 +1,8 @@
package lsu package lsu
import include._ import include.{lsu_error_pkt_t, _}
import lib._ import lib._
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import chisel3.experimental.chiselName import chisel3.experimental.chiselName
@chiselName @chiselName
class lsu_lsc_ctl extends Module with RequireAsyncReset with lib class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
@ -77,7 +75,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
val addr_in_pic_m = Output(UInt(1.W)) val addr_in_pic_m = Output(UInt(1.W))
val addr_in_pic_r = Output(UInt(1.W)) val addr_in_pic_r = Output(UInt(1.W))
val addr_external_m = Output(UInt(1.W)) val addr_external_m = Output(Bool())
// DMA slave // DMA slave
val dma_lsc_ctl = new dma_lsc_ctl() val dma_lsc_ctl = new dma_lsc_ctl()
@ -96,6 +94,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
val lsu_pkt_m_in = Wire(Valid(new lsu_pkt_t())) val lsu_pkt_m_in = Wire(Valid(new lsu_pkt_t()))
val lsu_pkt_r_in = Wire(Valid(new lsu_pkt_t())) val lsu_pkt_r_in = Wire(Valid(new lsu_pkt_t()))
val lsu_error_pkt_m = Wire(Valid(new lsu_error_pkt_t())) val lsu_error_pkt_m = Wire(Valid(new lsu_error_pkt_t()))
lsu_error_pkt_m := 0.U.asTypeOf(lsu_error_pkt_m)
val lsu_rs1_d = Mux(io.dec_lsu_valid_raw_d.asBool,io.lsu_exu.exu_lsu_rs1_d,io.dma_lsc_ctl.dma_mem_addr) val lsu_rs1_d = Mux(io.dec_lsu_valid_raw_d.asBool,io.lsu_exu.exu_lsu_rs1_d,io.dma_lsc_ctl.dma_mem_addr)
val lsu_offset_d = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d) val lsu_offset_d = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d)
@ -248,8 +247,8 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
if (LOAD_TO_USE_PLUS1 == 1){ if (LOAD_TO_USE_PLUS1 == 1){
//bus_read_data_r coming from bus interface, lsu_ld_data_r -> coming from dccm_ctl //bus_read_data_r coming from bus interface, lsu_ld_data_r -> coming from dccm_ctl
lsu_ld_datafn_r := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_r) lsu_ld_datafn_r := Mux(addr_external_r, bus_read_data_r,io.lsu_ld_data_r)
lsu_ld_datafn_corr_r := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_corr_r) lsu_ld_datafn_corr_r := Mux(addr_external_r, bus_read_data_r,io.lsu_ld_data_corr_r)
// this is really R stage but don't want to make all the changes to support M,R buses // this is really R stage but don't want to make all the changes to support M,R buses
io.lsu_result_m := ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) | io.lsu_result_m := ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) |
((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_r(15,0))) | ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_r(15,0))) |
@ -265,7 +264,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
} }
else { else {
lsu_ld_datafn_m := Mux(io.addr_external_m.asBool, io.bus_read_data_m,io.lsu_ld_data_m) lsu_ld_datafn_m := Mux(io.addr_external_m, io.bus_read_data_m,io.lsu_ld_data_m)
lsu_ld_datafn_corr_r := Mux(addr_external_r===1.U, bus_read_data_r,io.lsu_ld_data_corr_r) lsu_ld_datafn_corr_r := Mux(addr_external_r===1.U, bus_read_data_r,io.lsu_ld_data_corr_r)
io.lsu_result_m := ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) | io.lsu_result_m := ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) |
((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_m(15,0))) | ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_m(15,0))) |

BIN
target/scala-2.12/classes/exu/exu_div_ctl.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lib/param.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lsu/lsc_ctl$.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lsu/lsu.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lsu/lsu_dccm_ctl.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lsu/lsu_lsc_ctl.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lsu/lsu_main$.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lsu/lsu_main$delayedInit$body.class
View File

Binary file not shown.