Bus-buffer testing start
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3440
el2_lsu_bus_buffer.v
3440
el2_lsu_bus_buffer.v
File diff suppressed because it is too large
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@ -109,6 +109,9 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
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val data_hi = Output(UInt())
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val data_hi = Output(UInt())
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val data_lo = Output(UInt())
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val data_lo = Output(UInt())
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val data_en = Output(UInt())
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val data_en = Output(UInt())
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val Cmdptr0 = Output(UInt())
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val Cmdptr1 = Output(UInt())
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val WrPtr1_r = Output(UInt())
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})
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})
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def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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@ -252,7 +255,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
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val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), 0.U)
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val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), 0.U)
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val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), 0.U)
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val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), 0.U)
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val WrPtr0_r = WireInit(UInt(DEPTH_LOG2.W), 0.U)
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val WrPtr0_r = WireInit(UInt(DEPTH_LOG2.W), 0.U)
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io.WrPtr1_r := WrPtr1_r
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val ibuf_tag_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_tag, Mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r))
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val ibuf_tag_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_tag, Mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r))
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val ibuf_dualtag_in = WrPtr0_r
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val ibuf_dualtag_in = WrPtr0_r
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val ibuf_sz_in = Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half)
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val ibuf_sz_in = Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half)
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@ -290,6 +293,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
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val buf_nomerge = Wire(Vec(DEPTH, Bool()))
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val buf_nomerge = Wire(Vec(DEPTH, Bool()))
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buf_nomerge := buf_nomerge.map(i=> false.B)
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buf_nomerge := buf_nomerge.map(i=> false.B)
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val Cmdptr0 = WireInit(UInt(LSU_NUM_NBLOAD_WIDTH.W), 0.U)
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val Cmdptr0 = WireInit(UInt(LSU_NUM_NBLOAD_WIDTH.W), 0.U)
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io.Cmdptr0 := Cmdptr0
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val buf_sideeffect = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
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val buf_sideeffect = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
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val obuf_force_wr_en = WireInit(Bool(), false.B)
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val obuf_force_wr_en = WireInit(Bool(), false.B)
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val obuf_wr_en = WireInit(Bool(), false.B)
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val obuf_wr_en = WireInit(Bool(), false.B)
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@ -331,6 +335,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
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val obuf_merge_in = obuf_merge_en
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val obuf_merge_in = obuf_merge_en
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val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, Cmdptr0)
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val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, Cmdptr0)
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val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U)
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val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U)
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io.Cmdptr1 := Cmdptr1
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val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, Cmdptr1)
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val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, Cmdptr1)
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val obuf_cmd_done = WireInit(Bool(), false.B)
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val obuf_cmd_done = WireInit(Bool(), false.B)
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val bus_wcmd_sent = WireInit(Bool(), false.B)
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val bus_wcmd_sent = WireInit(Bool(), false.B)
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