Packets updated with Valid

This commit is contained in:
​Laraib Khan 2020-11-23 15:57:46 +05:00
parent 89e70f46c8
commit cf122545de
12 changed files with 12 additions and 16 deletions

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@ -81557,7 +81557,7 @@ circuit el2_swerv_wrapper :
module el2_dbg : module el2_dbg :
input clock : Clock input clock : Clock
input reset : AsyncReset input reset : AsyncReset
output io : {dbg_cmd_addr : UInt<32>, dbg_cmd_wrdata : UInt<32>, dbg_cmd_valid : UInt<1>, dbg_cmd_write : UInt<1>, dbg_cmd_type : UInt<2>, dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_dma_bubble : UInt<1>, flip dma_dbg_ready : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi_awvalid : UInt<1>, flip sb_axi_awready : UInt<1>, sb_axi_awid : UInt<1>, sb_axi_awaddr : UInt<32>, sb_axi_awregion : UInt<4>, sb_axi_awlen : UInt<8>, sb_axi_awsize : UInt<3>, sb_axi_awburst : UInt<2>, sb_axi_awlock : UInt<1>, sb_axi_awcache : UInt<4>, sb_axi_awprot : UInt<3>, sb_axi_awqos : UInt<4>, sb_axi_wvalid : UInt<1>, flip sb_axi_wready : UInt<1>, sb_axi_wdata : UInt<64>, sb_axi_wstrb : UInt<8>, sb_axi_wlast : UInt<1>, flip sb_axi_bvalid : UInt<1>, sb_axi_bready : UInt<1>, flip sb_axi_bresp : UInt<2>, sb_axi_arvalid : UInt<1>, flip sb_axi_arready : UInt<1>, sb_axi_arid : UInt<1>, sb_axi_araddr : UInt<32>, sb_axi_arregion : UInt<4>, sb_axi_arlen : UInt<8>, sb_axi_arsize : UInt<3>, sb_axi_arburst : UInt<2>, sb_axi_arlock : UInt<1>, sb_axi_arcache : UInt<4>, sb_axi_arprot : UInt<3>, sb_axi_arqos : UInt<4>, flip sb_axi_rvalid : UInt<1>, sb_axi_rready : UInt<1>, flip sb_axi_rdata : UInt<64>, flip sb_axi_rresp : UInt<2>, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : AsyncReset, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} output io : {dbg_cmd_addr : UInt<32>, dbg_cmd_wrdata : UInt<32>, dbg_cmd_valid : UInt<1>, dbg_cmd_write : UInt<1>, dbg_cmd_type : UInt<2>, dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_dma_bubble : UInt<1>, flip dma_dbg_ready : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi_awvalid : UInt<1>, flip sb_axi_awready : UInt<1>, sb_axi_awid : UInt<1>, sb_axi_awaddr : UInt<32>, sb_axi_awregion : UInt<4>, sb_axi_awlen : UInt<8>, sb_axi_awsize : UInt<3>, sb_axi_awburst : UInt<2>, sb_axi_awlock : UInt<1>, sb_axi_awcache : UInt<4>, sb_axi_awprot : UInt<3>, sb_axi_awqos : UInt<4>, sb_axi_wvalid : UInt<1>, flip sb_axi_wready : UInt<1>, sb_axi_wdata : UInt<64>, sb_axi_wstrb : UInt<8>, sb_axi_wlast : UInt<1>, flip sb_axi_bvalid : UInt<1>, sb_axi_bready : UInt<1>, flip sb_axi_bresp : UInt<2>, sb_axi_arvalid : UInt<1>, flip sb_axi_arready : UInt<1>, sb_axi_arid : UInt<1>, sb_axi_araddr : UInt<32>, sb_axi_arregion : UInt<4>, sb_axi_arlen : UInt<8>, sb_axi_arsize : UInt<3>, sb_axi_arburst : UInt<2>, sb_axi_arlock : UInt<1>, sb_axi_arcache : UInt<4>, sb_axi_arprot : UInt<3>, sb_axi_arqos : UInt<4>, flip sb_axi_rvalid : UInt<1>, sb_axi_rready : UInt<1>, flip sb_axi_rdata : UInt<64>, flip sb_axi_rresp : UInt<2>, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>}
wire dbg_state : UInt<3> wire dbg_state : UInt<3>
dbg_state <= UInt<3>("h00") dbg_state <= UInt<3>("h00")
@ -81636,7 +81636,7 @@ circuit el2_swerv_wrapper :
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_1.io.en <= sb_free_clken @[el2_lib.scala 485:16] rvclkhdr_1.io.en <= sb_free_clken @[el2_lib.scala 485:16]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
node _T_7 = asUInt(io.dbg_rst_l) @[el2_dbg.scala 130:41] node _T_7 = bits(io.dbg_rst_l, 0, 0) @[el2_dbg.scala 130:41]
node _T_8 = bits(dmcontrol_reg, 0, 0) @[el2_dbg.scala 130:60] node _T_8 = bits(dmcontrol_reg, 0, 0) @[el2_dbg.scala 130:60]
node _T_9 = or(_T_8, io.scan_mode) @[el2_dbg.scala 130:64] node _T_9 = or(_T_8, io.scan_mode) @[el2_dbg.scala 130:64]
node dbg_dm_rst_l = and(_T_7, _T_9) @[el2_dbg.scala 130:44] node dbg_dm_rst_l = and(_T_7, _T_9) @[el2_dbg.scala 130:44]
@ -109325,7 +109325,8 @@ circuit el2_swerv_wrapper :
dbg.io.sb_axi_rdata <= io.sb_axi_rdata @[el2_swerv.scala 595:23] dbg.io.sb_axi_rdata <= io.sb_axi_rdata @[el2_swerv.scala 595:23]
dbg.io.sb_axi_rresp <= io.sb_axi_rresp @[el2_swerv.scala 596:23] dbg.io.sb_axi_rresp <= io.sb_axi_rresp @[el2_swerv.scala 596:23]
dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[el2_swerv.scala 597:25] dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[el2_swerv.scala 597:25]
dbg.io.dbg_rst_l <= io.dbg_rst_l @[el2_swerv.scala 598:20] node _T_26 = asUInt(io.dbg_rst_l) @[el2_swerv.scala 598:42]
dbg.io.dbg_rst_l <= _T_26 @[el2_swerv.scala 598:20]
dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[el2_swerv.scala 599:23] dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[el2_swerv.scala 599:23]
dbg.io.scan_mode <= io.scan_mode @[el2_swerv.scala 600:20] dbg.io.scan_mode <= io.scan_mode @[el2_swerv.scala 600:20]
dma_ctrl.reset <= io.core_rst_l @[el2_swerv.scala 604:18] dma_ctrl.reset <= io.core_rst_l @[el2_swerv.scala 604:18]

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@ -59920,9 +59920,6 @@ initial begin
_RAND_20 = {1{`RANDOM}}; _RAND_20 = {1{`RANDOM}};
data0_reg = _RAND_20[31:0]; data0_reg = _RAND_20[31:0];
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
if (io_dbg_rst_l) begin
dm_temp_0 = 1'h0;
end
`endif // RANDOMIZE `endif // RANDOMIZE
end // initial end // initial
`ifdef FIRRTL_AFTER_INITIAL `ifdef FIRRTL_AFTER_INITIAL
@ -59986,6 +59983,11 @@ end // initial
end else if (dmcontrol_wren) begin end else if (dmcontrol_wren) begin
dm_temp <= _T_139; dm_temp <= _T_139;
end end
if (io_dbg_rst_l) begin
dm_temp_0 <= 1'h0;
end else if (dmcontrol_wren) begin
dm_temp_0 <= io_dmi_reg_wdata[0];
end
if (_T_29) begin if (_T_29) begin
dmstatus_havereset <= 1'h0; dmstatus_havereset <= 1'h0;
end else if (dmstatus_havereset_wren) begin end else if (dmstatus_havereset_wren) begin
@ -60161,13 +60163,6 @@ end // initial
data0_reg <= data0_din; data0_reg <= data0_din;
end end
end end
always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin
if (io_dbg_rst_l) begin
dm_temp_0 <= 1'h0;
end else if (dmcontrol_wren) begin
dm_temp_0 <= io_dmi_reg_wdata[0];
end
end
endmodule endmodule
module el2_exu_alu_ctl( module el2_exu_alu_ctl(
input clock, input clock,

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@ -342,7 +342,7 @@ class el2_swerv_wrapper extends Module with el2_lib with RequireAsyncReset {
val dma_hresp = Output(Bool()) val dma_hresp = Output(Bool())
*/ */
}) })
val mem = Module(new waleed.el2_mem()) val mem = Module(new quasar.el2_mem())
val dmi_wrapper = Module(new dmi_wrapper()) val dmi_wrapper = Module(new dmi_wrapper())
val swerv = Module(new el2_swerv()) val swerv = Module(new el2_swerv())
dmi_wrapper.io.trst_n := io.jtag_trst_n dmi_wrapper.io.trst_n := io.jtag_trst_n

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@ -55,7 +55,7 @@ class Mem_bundle extends Bundle with el2_lib {
val iccm_rd_data = Output(UInt(64.W)) val iccm_rd_data = Output(UInt(64.W))
} }
object waleed extends el2_lib { object quasar extends el2_lib {
class el2_mem extends BlackBox(Map("DCCM_BITS" -> DCCM_BITS, class el2_mem extends BlackBox(Map("DCCM_BITS" -> DCCM_BITS,
"DCCM_FDATA_WIDTH" -> DCCM_FDATA_WIDTH, "DCCM_FDATA_WIDTH" -> DCCM_FDATA_WIDTH,
"ICCM_BITS" -> ICCM_BITS, "ICCM_BITS" -> ICCM_BITS,
@ -92,7 +92,7 @@ object waleed extends el2_lib {
} }
class blackbox_mem extends Module with el2_lib { class blackbox_mem extends Module with el2_lib {
val io = IO(new Mem_bundle) val io = IO(new Mem_bundle)
val it = Module(new waleed.el2_mem) val it = Module(new quasar.el2_mem)
io <> it.io io <> it.io
} }