Bus-buffer testing start
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1f02deb8ed
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@ -168,8 +168,8 @@
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_tag_m",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r"
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
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]
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},
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{
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Load Diff
2170
el2_lsu_bus_buffer.v
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el2_lsu_bus_buffer.v
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Load Diff
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@ -419,11 +419,9 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
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obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)}
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val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
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val found_array1 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
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(io.lsu_busreq_r & (WrPtr0_r === i.U)) |
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(io.ldst_dual_r & (WrPtr1_r === i.U)))) -> i.U)
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WrPtr0_m := MuxCase(0.U, found_array1)
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WrPtr0_m := MuxCase(0.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
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(io.lsu_busreq_r & ((WrPtr0_r === i.U) |
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(io.ldst_dual_r & (WrPtr1_r === i.U)))))) -> i.U))
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io.buf_state := buf_state.reduce(Cat(_,_))
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val WrPtr1_m = MuxCase(0.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
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