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LSU with Bundling

This commit is contained in:
​Laraib Khan 2020-12-07 12:27:31 +05:00
parent 439c0adebc
commit d48d2bb461
196 changed files with 100677 additions and 100552 deletions
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2642
el2_dec.anno.json
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19170
el2_dec.fir
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11568
el2_dec.v
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727
el2_dec_tlu_ctl.anno.json
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@ -1,71 +1,105 @@
[ [
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_br_error", "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_leak_one_wb",
"sources":[ "sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_ifc_dec_tlu_flush_noredir_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r" "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r",
] "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_resume_ack",
}, "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
{ "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"class":"firrtl.transforms.CombinationalPath", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_commit_cmt", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger" "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_way", "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_extint",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_way_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_wr_pause_r",
"sources":[ "sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_fail",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_done",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_hist_r"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rddata_d", "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rddata_d",
@ -84,19 +118,63 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_kill_writeb_r", "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_ifc_dec_tlu_flush_noredir_wb",
"sources":[ "sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger" "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_way",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_way_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_dec_tlu_fence_i_wb",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
] ]
}, },
{ {
@ -108,19 +186,44 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_fence_i_r", "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_path_r",
"sources":[ "sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_rst_vec",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_pc_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_nmi_vec",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_addr",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_npc_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf" "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_exc_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
] ]
}, },
{ {
@ -130,6 +233,42 @@
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted" "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_presync_d", "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_presync_d",
@ -141,64 +280,9 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error", "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_dec_tlu_flush_lower_wb",
"sources":[ "sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb"
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_extint",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_fail",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_done",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
] ]
}, },
{ {
@ -208,246 +292,6 @@
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted" "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_leak_one_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_noredir_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_resume_ack",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_postsync_d",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_path_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_rst_vec",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_pc_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_nmi_vec",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_addr",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_npc_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_exc_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_legal_d",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_noredir_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_hist",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_hist_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_err_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt3",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_valid",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_mp_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_pmu_i0_br_ataken"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_middle",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_middle_r"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r", "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
@ -462,16 +306,16 @@
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
@ -480,10 +324,173 @@
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_dec_tlu_i0_commit_cmt",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_kill_writeb_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_postsync_d",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_legal_d",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_valid",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_mp_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_pmu_i0_br_ataken"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_dec_tlu_flush_err_wb",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_wr_pause_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_middle_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt3",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{ {
"class":"logger.LogLevelAnnotation", "class":"logger.LogLevelAnnotation",
"globalLogLevel":{ "globalLogLevel":{

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el2_dec_tlu_ctl.fir
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el2_dec_tlu_ctl.v
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el2_dma_ctrl.anno.json
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@ -1,30 +1,32 @@
[ [
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_stall_any",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_write", "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_write",
"sources":[ "sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write", "~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req", "~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req", "~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready", "~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready" "~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_write", "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_read",
"sources":[ "sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req", "~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write", "~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready" "~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
] ]
}, },
{ {
@ -32,49 +34,28 @@
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_stall_any", "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_stall_any",
"sources":[ "sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty", "~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write" "~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req", "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"sources":[ "sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready", "~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_addr", "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
"sources":[ "sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write" "~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_read", "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"sources":[ "sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req", "~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_read",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_sz",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
] ]
}, },
{ {
@ -82,7 +63,41 @@
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req", "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"sources":[ "sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready", "~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write" "~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_write",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_read",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_stall_any",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
] ]
}, },
{ {

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el2_dma_ctrl.fir
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el2_dma_ctrl.v
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el2_ifu.anno.json
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@ -1,40 +1,108 @@
[ [
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_ecc_error", "sink":"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_ifu_pmu_instr_aligned",
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d"
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_rd_en", "sink":"~el2_ifu|el2_ifu>io_iccm_rw_addr",
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_dma_mem_addr",
"~el2_ifu|el2_ifu>io_dec_tlu_force_halt", "~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_mrac_ff", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", "~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", "~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data", "~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d" "~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_data",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_rd_en",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_en",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_tag_valid",
"sources":[
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall",
"sources":[
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_addr",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
] ]
}, },
{ {
@ -43,159 +111,25 @@
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_dma_iccm_req", "~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_dma_mem_write", "~el2_ifu|el2_ifu>io_dma_mem_write",
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", "~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data", "~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d" "~el2_ifu|el2_ifu>io_ifu_r_bits_id",
] "~el2_ifu|el2_ifu>io_ifu_r_valid",
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_premux_data",
"sources":[
"~el2_ifu|el2_ifu>io_iccm_rd_data",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en", "~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d"
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_ready",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_addr",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_way",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_rd_en",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_rd_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_ic_error_start",
"sources":[
"~el2_ifu|el2_ifu>io_ic_eccerr",
"~el2_ifu|el2_ifu>io_ic_tag_perr",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data",
"sources":[
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_wr_data",
"sources":[
"~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_dma_mem_wdata",
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data"
] ]
}, },
{ {
@ -208,33 +142,145 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_en", "sink":"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start",
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wr_valid" "~el2_ifu|el2_ifu>io_ic_eccerr",
"~el2_ifu|el2_ifu>io_ic_tag_perr",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_rw_addr", "sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array",
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_dma_mem_addr", "~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
"~el2_ifu|el2_ifu>io_dma_iccm_req", ]
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err",
"sources":[
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", "~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", ]
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r", },
"~el2_ifu|el2_ifu>io_dec_i0_decode_d", {
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "class":"firrtl.transforms.CombinationalPath",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", "sink":"~el2_ifu|el2_ifu>io_ic_rd_en",
"~el2_ifu|el2_ifu>io_ic_rd_data" "sources":[
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_mrac_ff",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_ready",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_wr_data",
"sources":[
"~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_dma_mem_wdata",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data",
"sources":[
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_way",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
] ]
}, },
{ {
@ -243,99 +289,58 @@
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_dma_mem_write", "~el2_ifu|el2_ifu>io_dma_mem_write",
"~el2_ifu|el2_ifu>io_dma_iccm_req", "~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", "~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_pmu_instr_aligned",
"sources":[
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_iccm_rd_ecc_single_err",
"sources":[
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_pmu_fetch_stall",
"sources":[
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data", "~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_ifu_bus_clk_en"
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_tag_valid", "sink":"~el2_ifu|el2_ifu>io_ic_premux_data",
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_exu_flush_final" "~el2_ifu|el2_ifu>io_iccm_rd_data",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_rw_addr", "sink":"~el2_ifu|el2_ifu>io_ic_rw_addr",
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable" "~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_data",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wrdata"
] ]
}, },
{ {

75470
el2_ifu.fir
View File

File diff suppressed because it is too large Load Diff

28867
el2_ifu.v
View File

File diff suppressed because it is too large Load Diff

771
el2_lsu.anno.json
View File

@ -1,15 +1,4 @@
[ [
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_dma_rdata",
"sources":[
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_single_ecc_error_incr", "sink":"~el2_lsu|el2_lsu>io_lsu_single_ecc_error_incr",
@ -22,327 +11,33 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_rdaddr", "sink":"~el2_lsu|el2_lsu>io_lsu_dma_dccm_ready",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_lo",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rden",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_mken",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_lo",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_ready",
"sources":[ "sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d" "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_trxn", "sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_lo",
"sources":[ "sources":[
"~el2_lsu|el2_lsu>io_lsu_axi_arready", "~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_axi_awready", "~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_axi_wready" "~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
] "~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_wr_data",
"sources":[
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_load_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d", "~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword", "~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half", "~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word", "~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz", "~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", "~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_dma_ecc_error",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_store_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi", "~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo", "~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_hi",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_fastint_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_busy",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_axi_arready",
"~el2_lsu|el2_lsu>io_lsu_axi_awready",
"~el2_lsu|el2_lsu>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_result_m",
"sources":[
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_lo",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_wraddr",
"sources":[
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_hi",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_valid_m",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m", "sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m",
@ -367,13 +62,359 @@
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_pkt", "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_pkt",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2", "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_pkt", "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_pkt",
"~el2_lsu|el2_lsu>io_picm_rd_data", "~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi", "~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo", "~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_hi",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_lo",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rden",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_lo",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_trxn",
"sources":[
"~el2_lsu|el2_lsu>io_axi_rchannel_lsu_axi_arready",
"~el2_lsu|el2_lsu>io_axi_wchannel_lsu_axi_awready",
"~el2_lsu|el2_lsu>io_axi_wchannel_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wren",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_load_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pic_picm_wren",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_fastint_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pic_picm_rdaddr",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_hi",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pic_picm_wraddr",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pic_picm_mken",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_valid_m",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pic_picm_rden",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_busy",
"sources":[
"~el2_lsu|el2_lsu>io_axi_rchannel_lsu_axi_arready",
"~el2_lsu|el2_lsu>io_axi_wchannel_lsu_axi_awready",
"~el2_lsu|el2_lsu>io_axi_wchannel_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pic_picm_wr_data",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_misaligned", "sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_misaligned",
@ -390,69 +431,9 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wren", "sink":"~el2_lsu|el2_lsu>io_lsu_result_m",
"sources":[ "sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req", "~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_rden",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_hi",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi", "~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo", "~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
@ -461,24 +442,44 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_wren", "sink":"~el2_lsu|el2_lsu>io_lsu_store_stall_any",
"sources":[ "sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dma_mem_write", "~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r", "~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", "~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr", "~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_hi",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d", "~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword", "~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half", "~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word", "~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz", "~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data", "~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi", "~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo", "~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r" "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
] ]
}, },
{ {

13391
el2_lsu.fir
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7033
el2_lsu.v
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2
el2_pic_ctrl.anno.json
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@ -1,7 +1,7 @@
[ [
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_pic_ctrl|el2_pic_ctrl>io_picm_rd_data", "sink":"~el2_pic_ctrl|el2_pic_ctrl>io_lsu_pic_picm_rd_data",
"sources":[ "sources":[
"~el2_pic_ctrl|el2_pic_ctrl>io_extintsrc_req" "~el2_pic_ctrl|el2_pic_ctrl>io_extintsrc_req"
] ]

6486
el2_pic_ctrl.fir
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2462
el2_pic_ctrl.v
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534
src/main/scala/dec/el2_dec.scala
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@ -1,21 +1,87 @@
package dec package dec
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import exu._
import ifu._
import lsu._
import include._ import include._
import lib._ import lib._
//class aln_ib extends Bundle with el2_lib{
// val ifu_i0_icaf = Output(Bool())
// val ifu_i0_icaf_type = Output(UInt(2.W))
// val ifu_i0_icaf_f1 = Output(Bool())
// val ifu_i0_dbecc = Output(Bool())
// val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
// val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
// val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
// val ifu_i0_valid = Output(Bool())
// val ifu_i0_instr = Output(UInt(32.W))
// val ifu_i0_pc = Output(UInt(31.W))
// val ifu_i0_pc4 = Output(Bool())
// val i0_brp = Valid(new el2_br_pkt_t)
//}
//class aln_dec extends Bundle{
// val dec_i0_decode_d = Input(Bool()) // Dec
// val ifu_i0_cinst = Output(UInt(16.W)) // Dec
//}
//class dec_aln extends Bundle with el2_lib {
// val aln_dec = new aln_dec
// val aln_ib = new aln_ib
// val ifu_pmu_instr_aligned = Output(Bool()) // TLU
//}
//
//
//class dec_ifc extends Bundle{
// val dec_tlu_flush_noredir_wb = Input(Bool())
// val dec_tlu_mrac_ff = Input(UInt(32.W))
// val ifu_pmu_fetch_stall = Output(Bool())
//}
//class dec_bp extends Bundle{
// val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t))
// val dec_tlu_flush_lower_wb = Input(Bool())/////////////
// val dec_tlu_flush_leak_one_wb = Input(Bool())
// val dec_tlu_bpred_disable = Input(Bool())
//}
//
//class dec_mem_ctrl extends Bundle with el2_lib{
// val dec_tlu_flush_lower_wb = Input(Bool())
// val dec_tlu_flush_err_wb = Input(Bool())
// val dec_tlu_i0_commit_cmt = Input(Bool())
// val dec_tlu_force_halt = Input(Bool())
// val dec_tlu_fence_i_wb = Input(Bool())
// val dec_tlu_ic_diag_pkt = Input(new el2_cache_debug_pkt_t)
// val dec_tlu_core_ecc_disable = Input(Bool())
//
// val ifu_pmu_ic_miss = Output(Bool())
// val ifu_pmu_ic_hit = Output(Bool())
// val ifu_pmu_bus_error = Output(Bool())
// val ifu_pmu_bus_busy = Output(Bool())
// val ifu_pmu_bus_trxn = Output(Bool())
// val ifu_ic_error_start = Output(Bool())
// val ifu_iccm_rd_ecc_single_err = Output(Bool())
// val ifu_ic_debug_rd_data = Output(UInt(71.W))
// val ifu_ic_debug_rd_data_valid = Output(Bool())
// val ifu_miss_state_idle = Output(Bool())
//}
//class ifu_dec extends Bundle{
// val dec_aln = Flipped(new dec_aln)
// val dec_mem_ctrl = Flipped(new dec_mem_ctrl)
// val dec_ifc = Flipped(new dec_ifc)
// val dec_bp = Flipped(new dec_bp )
//}
//
class el2_dec_IO extends Bundle with el2_lib { class el2_dec_IO extends Bundle with el2_lib {
//val clk = Input(Clock()) //val clk = Input(Clock())
val free_clk = Input(Clock()) val free_clk = Input(Clock())
val active_clk = Input(Clock()) val active_clk = Input(Clock())
val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
// val dec_extint_stall = Output(Bool())
val dec_extint_stall = Output(Bool()) // val dec_i0_decode_d = Output(Bool())
val dec_i0_decode_d = Output(Bool())
val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating
// val rst_l = Input(Bool()) // reset, active low // val rst_l = Input(Bool()) // reset, active low
val rst_vec = Input(UInt(31.W)) // [31:1] reset vector, from core pins val rst_vec = Input(UInt(31.W)) // [31:1] reset vector, from core pins
@ -40,27 +106,28 @@ class el2_dec_IO extends Bundle with el2_lib {
val mpc_debug_run_ack = Output(Bool()) // Run ack val mpc_debug_run_ack = Output(Bool()) // Run ack
val debug_brkpt_status = Output(Bool()) // debug breakpoint val debug_brkpt_status = Output(Bool()) // debug breakpoint
val exu_pmu_i0_br_misp = Input(Bool()) // slot 0 branch misp // val exu_pmu_i0_br_misp = Input(Bool()) // slot 0 branch misp
val exu_pmu_i0_br_ataken = Input(Bool()) // slot 0 branch actual taken // val exu_pmu_i0_br_ataken = Input(Bool()) // slot 0 branch actual taken
val exu_pmu_i0_pc4 = Input(Bool()) // slot 0 4 byte branch // val exu_pmu_i0_pc4 = Input(Bool()) // slot 0 4 byte branch
val lsu_dec = Flipped (new lsu_dec)
val lsu_tlu = Flipped (new lsu_tlu)
val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m //val dctl_busbuff = Flipped (new dctl_busbuff)***********************************
val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag // val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m
val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r // val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag // val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r
val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back // val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error // val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back
val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag // val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error
val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data // val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
// val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data
val lsu_pmu_bus_trxn = Input(Bool()) // D side bus transaction // val tlu_busbuff = Flipped (new tlu_busbuff)******************
val lsu_pmu_bus_misaligned = Input(Bool()) // D side bus misaligned // val lsu_pmu_bus_trxn = Input(Bool()) // D side bus transaction
val lsu_pmu_bus_error = Input(Bool()) // D side bus error // val lsu_pmu_bus_misaligned = Input(Bool()) // D side bus misaligned
val lsu_pmu_bus_busy = Input(Bool()) // D side bus busy // val lsu_pmu_bus_error = Input(Bool()) // D side bus error
// val lsu_pmu_bus_busy = Input(Bool()) // D side bus busy
val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned
val lsu_pmu_load_external_m = Input(Bool()) // D side bus load // val lsu_pmu_load_external_m = Input(Bool()) // D side bus load
val lsu_pmu_store_external_m = Input(Bool()) // D side bus store // val lsu_pmu_store_external_m = Input(Bool()) // D side bus store
val dma_pmu_dccm_read = Input(Bool()) // DMA DCCM read val dma_pmu_dccm_read = Input(Bool()) // DMA DCCM read
val dma_pmu_dccm_write = Input(Bool()) // DMA DCCM write val dma_pmu_dccm_write = Input(Bool()) // DMA DCCM write
val dma_pmu_any_read = Input(Bool()) // DMA read val dma_pmu_any_read = Input(Bool()) // DMA read
@ -69,16 +136,16 @@ class el2_dec_IO extends Bundle with el2_lib {
val lsu_fir_addr = Input(UInt(31.W)) //[31:1] Fast int address val lsu_fir_addr = Input(UInt(31.W)) //[31:1] Fast int address
val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error
val ifu_pmu_instr_aligned = Input(Bool()) // aligned instructions // val ifu_pmu_instr_aligned = Input(Bool()) // aligned instructions
val ifu_pmu_fetch_stall = Input(Bool()) // fetch unit stalled // val ifu_pmu_fetch_stall = Input(Bool()) // fetch unit stalled
val ifu_pmu_ic_miss = Input(Bool()) // icache miss // val ifu_pmu_ic_miss = Input(Bool()) // icache miss
val ifu_pmu_ic_hit = Input(Bool()) // icache hit // val ifu_pmu_ic_hit = Input(Bool()) // icache hit
val ifu_pmu_bus_error = Input(Bool()) // Instruction side bus error // val ifu_pmu_bus_error = Input(Bool()) // Instruction side bus error
val ifu_pmu_bus_busy = Input(Bool()) // Instruction side bus busy // val ifu_pmu_bus_busy = Input(Bool()) // Instruction side bus busy
val ifu_pmu_bus_trxn = Input(Bool()) // Instruction side bus transaction // val ifu_pmu_bus_trxn = Input(Bool()) // Instruction side bus transaction
//
val ifu_ic_error_start = Input(Bool()) // IC single bit error // val ifu_ic_error_start = Input(Bool()) // IC single bit error
val ifu_iccm_rd_ecc_single_err = Input(Bool()) // ICCM single bit error // val ifu_iccm_rd_ecc_single_err = Input(Bool()) // ICCM single bit error
val lsu_trigger_match_m = Input(UInt(4.W)) val lsu_trigger_match_m = Input(UInt(4.W))
val dbg_cmd_valid = Input(Bool()) // debugger abstract command valid val dbg_cmd_valid = Input(Bool()) // debugger abstract command valid
@ -88,29 +155,29 @@ class el2_dec_IO extends Bundle with el2_lib {
val dbg_cmd_wrdata = Input(UInt(2.W)) // command write data, for fence/fence_i val dbg_cmd_wrdata = Input(UInt(2.W)) // command write data, for fence/fence_i
val ifu_i0_icaf = Input(Bool()) // icache access fault // val ifu_i0_icaf = Input(Bool()) // icache access fault
val ifu_i0_icaf_type = Input(UInt(2.W)) // val ifu_i0_icaf_type = Input(UInt(2.W))
//
val ifu_i0_icaf_f1 = Input(Bool()) // i0 has access fault on second fetch group // val ifu_i0_icaf_f1 = Input(Bool()) // i0 has access fault on second fetch group
val ifu_i0_dbecc = Input(Bool()) // icache/iccm double-bit error // val ifu_i0_dbecc = Input(Bool()) // icache/iccm double-bit error
val lsu_idle_any = Input(Bool()) // lsu idle for halting val lsu_idle_any = Input(Bool()) // lsu idle for halting
val i0_brp = Flipped(Valid(new el2_br_pkt_t)) // branch packet // val i0_brp = Flipped(Valid(new el2_br_pkt_t)) // branch packet
val ifu_i0_bp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // BP index // val ifu_i0_bp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // BP index
val ifu_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR // val ifu_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
val ifu_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag // val ifu_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
val lsu_error_pkt_r = Flipped(Valid(new el2_lsu_error_pkt_t)) // LSU exception/error packet val lsu_error_pkt_r = Flipped(Valid(new el2_lsu_error_pkt_t)) // LSU exception/error packet
val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter
val lsu_imprecise_error_load_any = Input(Bool()) // LSU imprecise load bus error // val lsu_imprecise_error_load_any = Input(Bool()) // LSU imprecise load bus error
val lsu_imprecise_error_store_any = Input(Bool()) // LSU imprecise store bus error // val lsu_imprecise_error_store_any = Input(Bool()) // LSU imprecise store bus error
val lsu_imprecise_error_addr_any = Input(UInt(32.W)) // LSU imprecise bus error address // val lsu_imprecise_error_addr_any = Input(UInt(32.W)) // LSU imprecise bus error address
val exu_div_result = Input(UInt(32.W)) // final div result val exu_div_result = Input(UInt(32.W)) // final div result
val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR
val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instruction // val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instruction
val lsu_result_m = Input(UInt(32.W)) // load result val lsu_result_m = Input(UInt(32.W)) // load result
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data
@ -121,18 +188,18 @@ class el2_dec_IO extends Bundle with el2_lib {
val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error
val exu_flush_final = Input(Bool()) // slot0 flush // val exu_flush_final = Input(Bool()) // slot0 flush
val exu_npc_r = Input(UInt(31.W)) // next PC // val exu_npc_r = Input(UInt(31.W)) // next PC
val exu_i0_result_x = Input(UInt(32.W)) // alu result x // val exu_i0_result_x = Input(UInt(32.W)) // alu result x
val ifu_i0_valid = Input(Bool()) // fetch valids to instruction buffer // val ifu_i0_valid = Input(Bool()) // fetch valids to instruction buffer
val ifu_i0_instr = Input(UInt(32.W)) // fetch inst's to instruction buffer // val ifu_i0_instr = Input(UInt(32.W)) // fetch inst's to instruction buffer
val ifu_i0_pc = Input(UInt(31.W)) // pc's for instruction buffer // val ifu_i0_pc = Input(UInt(31.W)) // pc's for instruction buffer
val ifu_i0_pc4 = Input(Bool()) // indication of 4B or 2B for corresponding inst // val ifu_i0_pc4 = Input(Bool()) // indication of 4B or 2B for corresponding inst
val exu_i0_pc_x = Input(UInt(31.W)) // pc's for e1 from the alu's // val exu_i0_pc_x = Input(UInt(31.W)) // pc's for e1 from the alu's
val mexintpend = Input(Bool()) // External interrupt pending val mexintpend = Input(Bool()) // External interrupt pending
val timer_int = Input(Bool()) // Timer interrupt pending (from pin) val timer_int = Input(Bool()) // Timer interrupt pending (from pin)
@ -145,26 +212,26 @@ class el2_dec_IO extends Bundle with el2_lib {
val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC, Current priv level val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC, Current priv level
val dec_tlu_meipt = Output(UInt(4.W)) // to PIC val dec_tlu_meipt = Output(UInt(4.W)) // to PIC
val ifu_ic_debug_rd_data = Input(UInt(71.W)) // diagnostic icache read data // val ifu_ic_debug_rd_data = Input(UInt(71.W)) // diagnostic icache read data
val ifu_ic_debug_rd_data_valid = Input(Bool()) // diagnostic icache read data valid // val ifu_ic_debug_rd_data_valid = Input(Bool()) // diagnostic icache read data valid
val dec_tlu_ic_diag_pkt = Output(new el2_cache_debug_pkt_t) // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics // val dec_tlu_ic_diag_pkt = Output(new el2_cache_debug_pkt_t) // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
// Debug start // Debug start
val dbg_halt_req = Input(Bool()) // DM requests a halt val dbg_halt_req = Input(Bool()) // DM requests a halt
val dbg_resume_req = Input(Bool()) // DM requests a resume val dbg_resume_req = Input(Bool()) // DM requests a resume
val ifu_miss_state_idle = Input(Bool()) // I-side miss buffer empty // val ifu_miss_state_idle = Input(Bool()) // I-side miss buffer empty
val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command
val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode
val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge
val dec_tlu_flush_noredir_r = Output(Bool()) // Tell fetch to idle on this flush // val dec_tlu_flush_noredir_r = Output(Bool()) // Tell fetch to idle on this flush
val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC
val dec_tlu_flush_leak_one_r = Output(Bool()) // single step // val dec_tlu_flush_leak_one_r = Output(Bool()) // single step
val dec_tlu_flush_err_r = Output(Bool()) // iside perr/ecc rfpc // val dec_tlu_flush_err_r = Output(Bool()) // iside perr/ecc rfpc
val dec_tlu_meihap = Output(UInt(30.W)) // Fast ext int base // val dec_tlu_meihap = Output(UInt(30.W)) // Fast ext int base
val dec_debug_wdata_rs1_d = Output(Bool()) // insert debug write data into rs1 at decode // val dec_debug_wdata_rs1_d = Output(Bool()) // insert debug write data into rs1 at decode
val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data
@ -173,85 +240,85 @@ class el2_dec_IO extends Bundle with el2_lib {
val trigger_pkt_any = Output(Vec(4,new el2_trigger_pkt_t)) // info needed by debug trigger blocks val trigger_pkt_any = Output(Vec(4,new el2_trigger_pkt_t)) // info needed by debug trigger blocks
val dec_tlu_force_halt = Output(Bool()) // halt has been forced // val dec_tlu_force_halt = Output(Bool()) // halt has been forced
// Debug end // Debug end
// branch info from pipe0 for errors or counter updates // branch info from pipe0 for errors or counter updates
val exu_i0_br_hist_r = Input(UInt(2.W)) // history // val exu_i0_br_hist_r = Input(UInt(2.W)) // history
val exu_i0_br_error_r = Input(Bool()) // error // val exu_i0_br_error_r = Input(Bool()) // error
val exu_i0_br_start_error_r = Input(Bool()) // start error // val exu_i0_br_start_error_r = Input(Bool()) // start error
val exu_i0_br_valid_r = Input(Bool()) // valid // val exu_i0_br_valid_r = Input(Bool()) // valid
val exu_i0_br_mp_r = Input(Bool()) // mispredict // val exu_i0_br_mp_r = Input(Bool()) // mispredict
val exu_i0_br_middle_r = Input(Bool()) // middle of bank // val exu_i0_br_middle_r = Input(Bool()) // middle of bank
//
val exu_i0_br_way_r = Input(Bool()) // way hit or repl val exu_i0_br_way_r = Input(Bool()) // way hit or repl
val dec_i0_rs1_en_d = Output(Bool()) // Qualify GPR RS1 data // val dec_i0_rs1_en_d = Output(Bool()) // Qualify GPR RS1 data
val dec_i0_rs2_en_d = Output(Bool()) // Qualify GPR RS2 data // val dec_i0_rs2_en_d = Output(Bool()) // Qualify GPR RS2 data
val gpr_i0_rs1_d = Output(UInt(32.W)) // gpr rs1 data // val gpr_i0_rs1_d = Output(UInt(32.W)) // gpr rs1 data
val gpr_i0_rs2_d = Output(UInt(32.W)) // gpr rs2 data // val gpr_i0_rs2_d = Output(UInt(32.W)) // gpr rs2 data
val dec_i0_immed_d = Output(UInt(32.W)) // immediate data // val dec_i0_immed_d = Output(UInt(32.W)) // immediate data
val dec_i0_br_immed_d = Output(UInt(12.W)) // br immediate data // val dec_i0_br_immed_d = Output(UInt(12.W)) // br immediate data
//
// val i0_ap = Output(new el2_alu_pkt_t)// alu packet
//
// val dec_i0_alu_decode_d = Output(Bool()) // schedule on D-stage alu
val i0_ap = Output(new el2_alu_pkt_t)// alu packet // val dec_i0_select_pc_d = Output(Bool()) // select pc onto rs1 for jal's
val dec_i0_alu_decode_d = Output(Bool()) // schedule on D-stage alu // val dec_i0_pc_d = Output(UInt(31.W)) // pc's at decode
// val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // rs1 bypass enable
// val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // rs2 bypass enable
val dec_i0_select_pc_d = Output(Bool()) // select pc onto rs1 for jal's // val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // rs1 bypass data
// val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // rs2 bypass data
val dec_i0_pc_d = Output(UInt(31.W)) // pc's at decode
val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // rs1 bypass enable
val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // rs2 bypass enable
val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // rs1 bypass data
val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // rs2 bypass data
val lsu_p = Valid(new el2_lsu_pkt_t) // lsu packet val lsu_p = Valid(new el2_lsu_pkt_t) // lsu packet
val mul_p = Valid(new el2_mul_pkt_t) // mul packet // val mul_p = Valid(new el2_mul_pkt_t) // mul packet
val div_p = Valid(new el2_div_pkt_t) // div packet // val div_p = Valid(new el2_div_pkt_t) // div packet
val dec_div_cancel = Output(Bool()) // cancel divide operation // val dec_div_cancel = Output(Bool()) // cancel divide operation
val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses
val dec_csr_ren_d = Output(Bool()) // csr read enable // val dec_csr_ren_d = Output(Bool()) // csr read enable
val dec_tlu_flush_lower_r = Output(Bool()) // tlu flush due to late mp, exception, rfpc, or int // val dec_tlu_flush_lower_r = Output(Bool()) // tlu flush due to late mp, exception, rfpc, or int
val dec_tlu_flush_path_r = Output(UInt(31.W)) // tlu flush target // val dec_tlu_flush_path_r = Output(UInt(31.W)) // tlu flush target
val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state
val dec_tlu_fence_i_r = Output(Bool()) // flush is a fence_i rfnpc, flush icache // val dec_tlu_fence_i_r = Output(Bool()) // flush is a fence_i rfnpc, flush icache
val pred_correct_npc_x = Output(UInt(31.W)) // npc if prediction is correct at e2 stage // val pred_correct_npc_x = Output(UInt(31.W)) // npc if prediction is correct at e2 stage
val dec_tlu_br0_r_pkt = Valid(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet // val dec_tlu_br0_r_pkt = Valid(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet
val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc
val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
val dec_i0_predict_p_d = Valid(new el2_predict_pkt_t) // prediction packet to alus // val dec_i0_predict_p_d = Valid(new el2_predict_pkt_t) // prediction packet to alus
val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr // val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr
val i0_predict_index_d = Output(UInt((BHT_ADDR_HI-BHT_ADDR_LO+1).W)) // DEC predict index // val i0_predict_index_d = Output(UInt((BHT_ADDR_HI-BHT_ADDR_LO+1).W)) // DEC predict index
val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag // val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag
val dec_lsu_valid_raw_d = Output(Bool()) val dec_lsu_valid_raw_d = Output(Bool())
val dec_tlu_mrac_ff = Output(UInt(32.W)) // CSR for memory region control // val dec_tlu_mrac_ff = Output(UInt(32.W)) // CSR for memory region control
val dec_data_en = Output(UInt(2.W)) // clock-gate control logic // val dec_data_en = Output(UInt(2.W)) // clock-gate control logic
val dec_ctl_en = Output(UInt(2.W)) // val dec_ctl_en = Output(UInt(2.W))
val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction // val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction
val rv_trace_pkt = Output(new el2_trace_pkt_t) // trace packet val rv_trace_pkt = Output(new el2_trace_pkt_t) // trace packet
// feature disable from mfdc // feature disable from mfdc
val dec_tlu_external_ldfwd_disable = Output(Bool()) // disable external load forwarding // val dec_tlu_external_ldfwd_disable = Output(Bool()) // disable external load forwarding
val dec_tlu_sideeffect_posted_disable = Output(Bool()) // disable posted stores to side-effect address // val dec_tlu_sideeffect_posted_disable = Output(Bool()) // disable posted stores to side-effect address
val dec_tlu_core_ecc_disable = Output(Bool()) // disable core ECC // val dec_tlu_core_ecc_disable = Output(Bool()) // disable core ECC
val dec_tlu_bpred_disable = Output(Bool()) // disable branch prediction // val dec_tlu_bpred_disable = Output(Bool()) // disable branch prediction
val dec_tlu_wb_coalescing_disable = Output(Bool()) // disable writebuffer coalescing // val dec_tlu_wb_coalescing_disable = Output(Bool()) // disable writebuffer coalescing
val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16] val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16]
// clock gating overrides from mcgc // clock gating overrides from mcgc
@ -263,9 +330,10 @@ class el2_dec_IO extends Bundle with el2_lib {
val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating
val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating
val dec_tlu_i0_commit_cmt = Output(Bool()) // committed i0 instruction // val dec_tlu_i0_commit_cmt = Output(Bool()) // committed i0 instruction
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val ifu_dec = Flipped(new ifu_dec)
val dec_exu = Flipped(new dec_exu)
} }
class el2_dec extends Module with param with RequireAsyncReset{ class el2_dec extends Module with param with RequireAsyncReset{
@ -288,36 +356,38 @@ class el2_dec extends Module with param with RequireAsyncReset{
val tlu = Module(new el2_dec_tlu_ctl) val tlu = Module(new el2_dec_tlu_ctl)
val dec_trigger = Module(new el2_dec_trigger) val dec_trigger = Module(new el2_dec_trigger)
io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d // io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d
//instbuff.io <> io // error "Connection between left (el2_dec_ib_ctl_IO(IO io in el2_dec_ib_ctl)) and source (el2_dec_IO(" //instbuff.io <> io // error "Connection between left (el2_dec_ib_ctl_IO(IO io in el2_dec_ib_ctl)) and source (el2_dec_IO("
//--------------------------------------------------------------------------// //--------------------------------------------------------------------------//
//connections for el2_dec_Ib //connections for el2_dec_Ib
//inputs //inputs
instbuff.io.ifu_ib <> io.ifu_dec.dec_aln.aln_ib
instbuff.io.ib_exu <> io.dec_exu.ib_exu
instbuff.io.dbg_cmd_valid := io.dbg_cmd_valid instbuff.io.dbg_cmd_valid := io.dbg_cmd_valid
instbuff.io.dbg_cmd_write := io.dbg_cmd_write instbuff.io.dbg_cmd_write := io.dbg_cmd_write
instbuff.io.dbg_cmd_type := io.dbg_cmd_type instbuff.io.dbg_cmd_type := io.dbg_cmd_type
instbuff.io.dbg_cmd_addr := io.dbg_cmd_addr instbuff.io.dbg_cmd_addr := io.dbg_cmd_addr
instbuff.io.i0_brp := io.i0_brp // instbuff.io.ifu_ib.i0_brp := io.ifu_dec.ifu_ib.i0_brp
instbuff.io.ifu_i0_bp_index := io.ifu_i0_bp_index // instbuff.io.ifu_ib.ifu_i0_bp_index := io.ifu_dec.ifu_ib.ifu_i0_bp_index
instbuff.io.ifu_i0_bp_fghr := io.ifu_i0_bp_fghr // instbuff.io.ifu_ib.ifu_i0_bp_fghr := io.ifu_dec.ifu_ib.ifu_i0_bp_fghr
instbuff.io.ifu_i0_bp_btag := io.ifu_i0_bp_btag // instbuff.io.ifu_ib.ifu_i0_bp_btag := io.ifu_dec.ifu_ib.ifu_i0_bp_btag
instbuff.io.ifu_i0_pc4 := io.ifu_i0_pc4 // instbuff.io.ifu_ib.ifu_i0_pc4 := io.ifu_dec.ifu_ib.ifu_i0_pc4
instbuff.io.ifu_i0_valid := io.ifu_i0_valid // instbuff.io.ifu_ib.ifu_i0_valid := io.ifu_dec.ifu_ib.ifu_i0_valid
instbuff.io.ifu_i0_icaf := io.ifu_i0_icaf // instbuff.io.ifu_ib.ifu_i0_icaf := io.ifu_dec.ifu_ib.ifu_i0_icaf
instbuff.io.ifu_i0_icaf_type := io.ifu_i0_icaf_type // instbuff.io.ifu_ib.ifu_i0_icaf_type := io.ifu_dec.ifu_ib.ifu_i0_icaf_type
instbuff.io.ifu_i0_icaf_f1 := io.ifu_i0_icaf_f1 // instbuff.io.ifu_ib.ifu_i0_icaf_f1 := io.ifu_dec.ifu_ib.ifu_i0_icaf_f1
instbuff.io.ifu_i0_dbecc := io.ifu_i0_dbecc // instbuff.io.ifu_ib.ifu_i0_dbecc := io.ifu_dec.ifu_ib.ifu_i0_dbecc
instbuff.io.ifu_i0_instr := io.ifu_i0_instr // instbuff.io.ifu_ib.ifu_i0_instr := io.ifu_dec.ifu_ib.ifu_i0_instr
instbuff.io.ifu_i0_pc := io.ifu_i0_pc // instbuff.io.ifu_ib.ifu_i0_pc := io.ifu_dec.ifu_ib.ifu_i0_pc
//outputs //outputs
io.dec_debug_wdata_rs1_d := instbuff.io.dec_debug_wdata_rs1_d // io.dec_debug_wdata_rs1_d := instbuff.io.dec_debug_wdata_rs1_d
//--------------------------------------------------------------------------// //--------------------------------------------------------------------------//
//connections for dec_trigger //connections for dec_trigger
//dec_trigger.io <> io //dec_trigger.io <> io
//inputs //inputs
dec_trigger.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d dec_trigger.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d
dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any
//output //output
val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
@ -327,24 +397,29 @@ class el2_dec extends Module with param with RequireAsyncReset{
//connections for el2_dec_decode //connections for el2_dec_decode
// decode.io <> io // decode.io <> io
//inputs //inputs
decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec
decode.io.decode_exu<> io.dec_exu.decode_exu
decode.io.dec_alu<> io.dec_exu.dec_alu
decode.io.dec_div<> io.dec_exu.dec_div
decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
decode.io.dec_tlu_force_halt := tlu.io.dec_tlu_force_halt decode.io.dec_tlu_force_halt := tlu.io.tlu_mem.dec_tlu_force_halt
decode.io.ifu_i0_cinst := io.ifu_i0_cinst // decode.io.ifu_decode.ifu_i0_cinst := io.ifu_dec.ifu_decode.ifu_i0_cinst
decode.io.lsu_nonblock_load_valid_m := io.lsu_nonblock_load_valid_m decode.io.dctl_busbuff <> io.lsu_dec.dctl_busbuff
decode.io.lsu_nonblock_load_tag_m := io.lsu_nonblock_load_tag_m // decode.io.lsu_nonblock_load_valid_m := io.lsu_nonblock_load_valid_m
decode.io.lsu_nonblock_load_inv_r := io.lsu_nonblock_load_inv_r // decode.io.lsu_nonblock_load_tag_m := io.lsu_nonblock_load_tag_m
decode.io.lsu_nonblock_load_inv_tag_r := io.lsu_nonblock_load_inv_tag_r // decode.io.lsu_nonblock_load_inv_r := io.lsu_nonblock_load_inv_r
decode.io.lsu_nonblock_load_data_valid := io.lsu_nonblock_load_data_valid // decode.io.lsu_nonblock_load_inv_tag_r := io.lsu_nonblock_load_inv_tag_r
decode.io.lsu_nonblock_load_data_error := io.lsu_nonblock_load_data_error // decode.io.lsu_nonblock_load_data_valid := io.lsu_nonblock_load_data_valid
decode.io.lsu_nonblock_load_data_tag := io.lsu_nonblock_load_data_tag // decode.io.lsu_nonblock_load_data_error := io.lsu_nonblock_load_data_error
decode.io.lsu_nonblock_load_data := io.lsu_nonblock_load_data // decode.io.lsu_nonblock_load_data_tag := io.lsu_nonblock_load_data_tag
// decode.io.lsu_nonblock_load_data := io.lsu_nonblock_load_data
decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d
decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable
decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m
decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_bus_misaligned decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_misaligned_m
decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
decode.io.dec_tlu_flush_leak_one_r := tlu.io.dec_tlu_flush_leak_one_r decode.io.dec_tlu_flush_leak_one_r := tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb
decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d
decode.io.dbg_cmd_wrdata := io.dbg_cmd_wrdata decode.io.dbg_cmd_wrdata := io.dbg_cmd_wrdata
decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d
@ -355,30 +430,30 @@ class el2_dec extends Module with param with RequireAsyncReset{
decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index
decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr
decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag
decode.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d decode.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d
decode.io.lsu_idle_any := io.lsu_idle_any decode.io.lsu_idle_any := io.lsu_idle_any
decode.io.lsu_load_stall_any := io.lsu_load_stall_any decode.io.lsu_load_stall_any := io.lsu_load_stall_any
decode.io.lsu_store_stall_any := io.lsu_store_stall_any decode.io.lsu_store_stall_any := io.lsu_store_stall_any
decode.io.dma_dccm_stall_any := io.dma_dccm_stall_any decode.io.dma_dccm_stall_any := io.dma_dccm_stall_any
decode.io.exu_div_wren := io.exu_div_wren decode.io.exu_div_wren := io.exu_div_wren
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb decode.io.dec_tlu_flush_lower_wb := tlu.io.tlu_bp.dec_tlu_flush_lower_wb
decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
decode.io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r
decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc4_d decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc4_d
decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
decode.io.exu_csr_rs1_x := io.exu_csr_rs1_x // decode.io.exu_csr_rs1_x := io.exu_csr_rs1_x
decode.io.lsu_result_m := io.lsu_result_m decode.io.lsu_result_m := io.lsu_result_m
decode.io.lsu_result_corr_r := io.lsu_result_corr_r decode.io.lsu_result_corr_r := io.lsu_result_corr_r
decode.io.exu_flush_final := io.exu_flush_final // decode.io.exu_flush_final := io.exu_flush_final
decode.io.exu_i0_pc_x := io.exu_i0_pc_x // decode.io.exu_i0_pc_x := io.exu_i0_pc_x
decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d
decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
decode.io.exu_i0_result_x := io.exu_i0_result_x // decode.io.exu_i0_result_x := io.exu_i0_result_x
//decode.io.clk := io.clk //decode.io.clk := io.clk
decode.io.free_clk := io.free_clk decode.io.free_clk := io.free_clk
decode.io.active_clk := io.active_clk decode.io.active_clk := io.active_clk
@ -386,35 +461,38 @@ class el2_dec extends Module with param with RequireAsyncReset{
// decode.io.rst_l := io.rst_l // decode.io.rst_l := io.rst_l
decode.io.scan_mode := io.scan_mode decode.io.scan_mode := io.scan_mode
//outputs //outputs
io.dec_extint_stall := decode.io.dec_extint_stall //
// io.ifu_dec.dec_aln <> decode.io.dec_aln
// io.dec_extint_stall := decode.io.dec_extint_stall
dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer
dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer
io.dec_i0_rs1_en_d := decode.io.dec_i0_rs1_en_d // io.dec_i0_rs1_en_d := decode.io.dec_i0_rs1_en_d
io.dec_i0_rs2_en_d := decode.io.dec_i0_rs2_en_d // io.dec_i0_rs2_en_d := decode.io.dec_i0_rs2_en_d
io.dec_i0_immed_d := decode.io.dec_i0_immed_d // io.dec_i0_immed_d := decode.io.dec_i0_immed_d
io.dec_i0_br_immed_d := decode.io.dec_i0_br_immed_d // io.dec_i0_br_immed_d := decode.io.dec_i0_br_immed_d
io.i0_ap := decode.io.i0_ap // io.i0_ap := decode.io.i0_ap
io.dec_i0_decode_d := decode.io.dec_i0_decode_d // io.ifu_dec.dec_aln.dec_i0_decode_d := decode.io.dec_aln.dec_i0_decode_d
io.dec_i0_alu_decode_d := decode.io.dec_i0_alu_decode_d // io.dec_i0_alu_decode_d := decode.io.dec_i0_alu_decode_d
io.dec_i0_rs1_bypass_data_d := decode.io.dec_i0_rs1_bypass_data_d // io.dec_i0_rs1_bypass_data_d := decode.io.dec_i0_rs1_bypass_data_d
io.dec_i0_rs2_bypass_data_d := decode.io.dec_i0_rs2_bypass_data_d // io.dec_i0_rs2_bypass_data_d := decode.io.dec_i0_rs2_bypass_data_d
io.dec_i0_select_pc_d := decode.io.dec_i0_select_pc_d // io.dec_i0_select_pc_d := decode.io.dec_i0_select_pc_d
io.dec_i0_rs1_bypass_en_d := decode.io.dec_i0_rs1_bypass_en_d // io.dec_i0_rs1_bypass_en_d := decode.io.dec_i0_rs1_bypass_en_d
io.dec_i0_rs2_bypass_en_d := decode.io.dec_i0_rs2_bypass_en_d // io.dec_i0_rs2_bypass_en_d := decode.io.dec_i0_rs2_bypass_en_d
io.lsu_p := decode.io.lsu_p io.lsu_p := decode.io.lsu_p
io.mul_p := decode.io.mul_p // io.mul_p := decode.io.mul_p
io.div_p := decode.io.div_p // io.div_p := decode.io.div_p
io.dec_div_cancel := decode.io.dec_div_cancel // io.dec_div_cancel := decode.io.dec_div_cancel
io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d
io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d
io.dec_csr_ren_d := decode.io.dec_csr_ren_d // io.dec_csr_ren_d := decode.io.dec_csr_ren_d
io.pred_correct_npc_x := decode.io.pred_correct_npc_x // io.pred_correct_npc_x := decode.io.pred_correct_npc_x
io.dec_i0_predict_p_d := decode.io.dec_i0_predict_p_d // io.dec_i0_predict_p_d := decode.io.dec_i0_predict_p_d
io.i0_predict_fghr_d := decode.io.i0_predict_fghr_d // io.i0_predict_fghr_d := decode.io.i0_predict_fghr_d
io.i0_predict_index_d := decode.io.i0_predict_index_d // io.i0_predict_index_d := decode.io.i0_predict_index_d
io.i0_predict_btag_d := decode.io.i0_predict_btag_d // io.i0_predict_btag_d := decode.io.i0_predict_btag_d
io.dec_data_en := decode.io.dec_data_en // io.dec_data_en := decode.io.dec_data_en
io.dec_ctl_en := decode.io.dec_ctl_en // io.dec_ctl_en := decode.io.dec_ctl_en
io.dec_pause_state_cg := decode.io.dec_pause_state_cg io.dec_pause_state_cg := decode.io.dec_pause_state_cg
//--------------------------------------------------------------------------// //--------------------------------------------------------------------------//
@ -429,7 +507,7 @@ class el2_dec extends Module with param with RequireAsyncReset{
gpr.io.wd0 := decode.io.dec_i0_wdata_r gpr.io.wd0 := decode.io.dec_i0_wdata_r
gpr.io.wen1 := decode.io.dec_nonblock_load_wen gpr.io.wen1 := decode.io.dec_nonblock_load_wen
gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr
gpr.io.wd1 := io.lsu_nonblock_load_data gpr.io.wd1 := io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data
gpr.io.wen2 := io.exu_div_wren gpr.io.wen2 := io.exu_div_wren
gpr.io.waddr2 := decode.io.div_waddr_wb gpr.io.waddr2 := decode.io.div_waddr_wb
gpr.io.wd2 := io.exu_div_result gpr.io.wd2 := io.exu_div_result
@ -437,8 +515,7 @@ class el2_dec extends Module with param with RequireAsyncReset{
//gpr.io.rst_l := io.rst_l //gpr.io.rst_l := io.rst_l
gpr.io.scan_mode := io.scan_mode gpr.io.scan_mode := io.scan_mode
// outputs // outputs
io.gpr_i0_rs1_d := gpr.io.rd0 io.dec_exu.gpr_exu := gpr.io.gpr_exu
io.gpr_i0_rs2_d := gpr.io.rd1
//--------------------------------------------------------------------------// //--------------------------------------------------------------------------//
@ -446,6 +523,10 @@ class el2_dec extends Module with param with RequireAsyncReset{
//connection for dec_tlu //connection for dec_tlu
// tlu.io <> io // tlu.io <> io
//inputs //inputs
tlu.io.tlu_mem <> io.ifu_dec.dec_mem_ctrl
tlu.io.tlu_ifc <> io.ifu_dec.dec_ifc
tlu.io.tlu_bp <> io.ifu_dec.dec_bp
tlu.io.tlu_exu <> io.dec_exu.tlu_exu
//tlu.io.clk := io.clk //tlu.io.clk := io.clk
tlu.io.active_clk := io.active_clk tlu.io.active_clk := io.active_clk
tlu.io.free_clk := io.free_clk tlu.io.free_clk := io.free_clk
@ -457,13 +538,13 @@ class el2_dec extends Module with param with RequireAsyncReset{
tlu.io.i_cpu_halt_req := io.i_cpu_halt_req tlu.io.i_cpu_halt_req := io.i_cpu_halt_req
tlu.io.i_cpu_run_req := io.i_cpu_run_req tlu.io.i_cpu_run_req := io.i_cpu_run_req
tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any
tlu.io.ifu_pmu_instr_aligned := io.ifu_pmu_instr_aligned tlu.io.ifu_pmu_instr_aligned := io.ifu_dec.dec_aln.ifu_pmu_instr_aligned
tlu.io.ifu_pmu_fetch_stall := io.ifu_pmu_fetch_stall // tlu.io.ifu_tlu.ifu_pmu_fetch_stall := io.ifu_dec.ifu_tlu.ifu_pmu_fetch_stall
tlu.io.ifu_pmu_ic_miss := io.ifu_pmu_ic_miss // tlu.io.ifu_tlu.ifu_pmu_ic_miss := io.ifu_dec.ifu_tlu.ifu_pmu_ic_miss
tlu.io.ifu_pmu_ic_hit := io.ifu_pmu_ic_hit // tlu.io.ifu_tlu.ifu_pmu_ic_hit := io.ifu_dec.ifu_tlu.ifu_pmu_ic_hit
tlu.io.ifu_pmu_bus_error := io.ifu_pmu_bus_error // tlu.io.ifu_tlu.ifu_pmu_bus_error := io.ifu_dec.ifu_tlu.ifu_pmu_bus_error
tlu.io.ifu_pmu_bus_busy := io.ifu_pmu_bus_busy // tlu.io.ifu_tlu.ifu_pmu_bus_busy := io.ifu_dec.ifu_tlu.ifu_pmu_bus_busy
tlu.io.ifu_pmu_bus_trxn := io.ifu_pmu_bus_trxn // tlu.io.ifu_tlu.ifu_pmu_bus_trxn := io.ifu_dec.ifu_tlu.ifu_pmu_bus_trxn
tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded
tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall
tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall
@ -471,15 +552,23 @@ class el2_dec extends Module with param with RequireAsyncReset{
tlu.io.lsu_store_stall_any := io.lsu_store_stall_any tlu.io.lsu_store_stall_any := io.lsu_store_stall_any
tlu.io.dma_dccm_stall_any := io.dma_dccm_stall_any tlu.io.dma_dccm_stall_any := io.dma_dccm_stall_any
tlu.io.dma_iccm_stall_any := io.dma_iccm_stall_any tlu.io.dma_iccm_stall_any := io.dma_iccm_stall_any
tlu.io.exu_pmu_i0_br_misp := io.exu_pmu_i0_br_misp // tlu.io.exu_pmu_i0_br_misp := io.exu_pmu_i0_br_misp
tlu.io.exu_pmu_i0_br_ataken := io.exu_pmu_i0_br_ataken // tlu.io.exu_pmu_i0_br_ataken := io.exu_pmu_i0_br_ataken
tlu.io.exu_pmu_i0_pc4 := io.exu_pmu_i0_pc4 // tlu.io.exu_pmu_i0_pc4 := io.exu_pmu_i0_pc4
tlu.io.lsu_pmu_bus_trxn := io.lsu_pmu_bus_trxn io.lsu_dec.tlu_busbuff <> tlu.io.tlu_busbuff
tlu.io.lsu_pmu_bus_misaligned := io.lsu_pmu_bus_misaligned io.lsu_tlu <> tlu.io.lsu_tlu
tlu.io.lsu_pmu_bus_error := io.lsu_pmu_bus_error // tlu.io.lsu_pmu_bus_trxn := io.lsu_pmu_bus_trxn
tlu.io.lsu_pmu_bus_busy := io.lsu_pmu_bus_busy // tlu.io.lsu_pmu_bus_misaligned := io.lsu_pmu_bus_misaligned
tlu.io.lsu_pmu_load_external_m := io.lsu_pmu_load_external_m // tlu.io.lsu_pmu_bus_error := io.lsu_pmu_bus_error
tlu.io.lsu_pmu_store_external_m := io.lsu_pmu_store_external_m // tlu.io.lsu_pmu_bus_busy := io.lsu_pmu_bus_busy
// tlu.io.lsu_imprecise_error_store_any := io.lsu_imprecise_error_store_any
// tlu.io.lsu_imprecise_error_load_any := io.lsu_imprecise_error_load_any
// tlu.io.lsu_imprecise_error_addr_any := io.lsu_imprecise_error_addr_any
// io.dec_tlu_external_ldfwd_disable := tlu.io.dec_tlu_external_ldfwd_disable
// io.dec_tlu_sideeffect_posted_disable := tlu.io.dec_tlu_sideeffect_posted_disable
// io.dec_tlu_wb_coalescing_disable := tlu.io.dec_tlu_wb_coalescing_disable
// tlu.io.lsu_pmu_load_external_m := io.lsu_pmu_load_external_m
// tlu.io.lsu_pmu_store_external_m := io.lsu_pmu_store_external_m
tlu.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read tlu.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read
tlu.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write tlu.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write
tlu.io.dma_pmu_any_read := io.dma_pmu_any_read tlu.io.dma_pmu_any_read := io.dma_pmu_any_read
@ -490,9 +579,7 @@ class el2_dec extends Module with param with RequireAsyncReset{
tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r
tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr
tlu.io.dec_pause_state := decode.io.dec_pause_state tlu.io.dec_pause_state := decode.io.dec_pause_state
tlu.io.lsu_imprecise_error_store_any := io.lsu_imprecise_error_store_any
tlu.io.lsu_imprecise_error_load_any := io.lsu_imprecise_error_load_any
tlu.io.lsu_imprecise_error_addr_any := io.lsu_imprecise_error_addr_any
tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
@ -501,27 +588,27 @@ class el2_dec extends Module with param with RequireAsyncReset{
tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
tlu.io.exu_npc_r := io.exu_npc_r // tlu.io.exu_npc_r := io.exu_npc_r
tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
tlu.io.dec_i0_decode_d := decode.io.dec_i0_decode_d tlu.io.dec_i0_decode_d := decode.io.dec_aln.dec_i0_decode_d
tlu.io.exu_i0_br_hist_r := io.exu_i0_br_hist_r // tlu.io.exu_i0_br_hist_r := io.exu_i0_br_hist_r
tlu.io.exu_i0_br_error_r := io.exu_i0_br_error_r // tlu.io.exu_i0_br_error_r := io.exu_i0_br_error_r
tlu.io.exu_i0_br_start_error_r := io.exu_i0_br_start_error_r // tlu.io.exu_i0_br_start_error_r := io.exu_i0_br_start_error_r
tlu.io.exu_i0_br_valid_r := io.exu_i0_br_valid_r // tlu.io.exu_i0_br_valid_r := io.exu_i0_br_valid_r
tlu.io.exu_i0_br_mp_r := io.exu_i0_br_mp_r // tlu.io.exu_i0_br_mp_r := io.exu_i0_br_mp_r
tlu.io.exu_i0_br_middle_r := io.exu_i0_br_middle_r // tlu.io.exu_i0_br_middle_r := io.exu_i0_br_middle_r
tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r
tlu.io.dbg_halt_req := io.dbg_halt_req tlu.io.dbg_halt_req := io.dbg_halt_req
tlu.io.dbg_resume_req := io.dbg_resume_req tlu.io.dbg_resume_req := io.dbg_resume_req
tlu.io.ifu_miss_state_idle := io.ifu_miss_state_idle // tlu.io.ifu_tlu.ifu_miss_state_idle := io.ifu_dec.ifu_tlu.ifu_miss_state_idle
tlu.io.lsu_idle_any := io.lsu_idle_any tlu.io.lsu_idle_any := io.lsu_idle_any
tlu.io.dec_div_active := decode.io.dec_div_active tlu.io.dec_div_active := decode.io.dec_div_active
tlu.io.ifu_ic_error_start := io.ifu_ic_error_start // tlu.io.ifu_tlu.ifu_ic_error_start := io.ifu_dec.ifu_tlu.ifu_ic_error_start
tlu.io.ifu_iccm_rd_ecc_single_err := io.ifu_iccm_rd_ecc_single_err // tlu.io.ifu_tlu.ifu_iccm_rd_ecc_single_err := io.ifu_dec.ifu_tlu.ifu_iccm_rd_ecc_single_err
tlu.io.ifu_ic_debug_rd_data := io.ifu_ic_debug_rd_data // tlu.io.ifu_tlu.ifu_ic_debug_rd_data := io.ifu_dec.ifu_tlu.ifu_ic_debug_rd_data
tlu.io.ifu_ic_debug_rd_data_valid := io.ifu_ic_debug_rd_data_valid // tlu.io.ifu_tlu.ifu_ic_debug_rd_data_valid := io.ifu_dec.ifu_tlu.ifu_ic_debug_rd_data_valid
tlu.io.pic_claimid := io.pic_claimid tlu.io.pic_claimid := io.pic_claimid
tlu.io.pic_pl := io.pic_pl tlu.io.pic_pl := io.pic_pl
tlu.io.mhwakeup := io.mhwakeup tlu.io.mhwakeup := io.mhwakeup
@ -533,18 +620,22 @@ class el2_dec extends Module with param with RequireAsyncReset{
tlu.io.mpc_debug_run_req := io.mpc_debug_run_req tlu.io.mpc_debug_run_req := io.mpc_debug_run_req
tlu.io.mpc_reset_run_req := io.mpc_reset_run_req tlu.io.mpc_reset_run_req := io.mpc_reset_run_req
//outputs //outputs
// io.ifu_dec.dec_mem_ctrl <> tlu.io.tlu_mem
// io.ifu_dec.dec_ifc <> tlu.io.tlu_ifc
// io.ifu_dec.dec_bp <> tlu.io.tlu_bp
io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done
io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail
io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted
io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode
io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack
io.dec_tlu_flush_noredir_r := tlu.io.dec_tlu_flush_noredir_r // io.ifu_dec.tlu_ifc.dec_tlu_flush_noredir_wb := tlu.io.tlu_ifc.dec_tlu_flush_noredir_wb
io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only
io.dec_tlu_flush_leak_one_r := tlu.io.dec_tlu_flush_leak_one_r // io.ifu_dec.tlu_bp.dec_tlu_flush_leak_one_wb := tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb
io.dec_tlu_flush_err_r := tlu.io.dec_tlu_flush_err_r // io.ifu_dec.tlu_mem.dec_tlu_flush_err_wb := tlu.io.tlu_mem.dec_tlu_flush_err_wb
io.dec_tlu_meihap := tlu.io.dec_tlu_meihap // io.dec_tlu_meihap := tlu.io.dec_tlu_meihap
io.trigger_pkt_any := tlu.io.trigger_pkt_any io.trigger_pkt_any := tlu.io.trigger_pkt_any
io.dec_tlu_ic_diag_pkt := tlu.io.dec_tlu_ic_diag_pkt // io.ifu_dec.tlu_mem.dec_tlu_ic_diag_pkt := tlu.io.tlu_mem.dec_tlu_ic_diag_pkt
io.o_cpu_halt_status := tlu.io.o_cpu_halt_status io.o_cpu_halt_status := tlu.io.o_cpu_halt_status
io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack
io.o_cpu_run_ack := tlu.io.o_cpu_run_ack io.o_cpu_run_ack := tlu.io.o_cpu_run_ack
@ -554,14 +645,14 @@ class el2_dec extends Module with param with RequireAsyncReset{
io.debug_brkpt_status := tlu.io.debug_brkpt_status io.debug_brkpt_status := tlu.io.debug_brkpt_status
io.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl io.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl
io.dec_tlu_meipt := tlu.io.dec_tlu_meipt io.dec_tlu_meipt := tlu.io.dec_tlu_meipt
io.dec_tlu_br0_r_pkt := tlu.io.dec_tlu_br0_r_pkt // io.ifu_dec.tlu_bp.dec_tlu_br0_r_pkt := tlu.io.tlu_bp.dec_tlu_br0_r_pkt
io.dec_tlu_i0_commit_cmt := tlu.io.dec_tlu_i0_commit_cmt // io.ifu_dec.tlu_mem.dec_tlu_i0_commit_cmt := tlu.io.tlu_mem.dec_tlu_i0_commit_cmt
io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r // io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r
io.dec_tlu_flush_path_r := tlu.io.dec_tlu_flush_path_r // io.dec_tlu_flush_path_r := tlu.io.dec_tlu_flush_path_r
io.dec_tlu_fence_i_r := tlu.io.dec_tlu_fence_i_r // io.ifu_dec.tlu_mem.dec_tlu_fence_i_wb := tlu.io.tlu_mem.dec_tlu_fence_i_wb
io.dec_tlu_mrac_ff := tlu.io.dec_tlu_mrac_ff // io.ifu_dec.tlu_ifc.dec_tlu_mrac_ff := tlu.io.tlu_ifc.dec_tlu_mrac_ff
io.dec_tlu_force_halt := tlu.io.dec_tlu_force_halt // io.ifu_dec.tlu_mem.dec_tlu_force_halt := tlu.io.tlu_mem.dec_tlu_force_halt
io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0 io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0
io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1 io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1
io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2 io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2
@ -571,11 +662,6 @@ class el2_dec extends Module with param with RequireAsyncReset{
dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1 dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1
dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1 dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1
dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1 dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1
io.dec_tlu_external_ldfwd_disable := tlu.io.dec_tlu_external_ldfwd_disable
io.dec_tlu_sideeffect_posted_disable := tlu.io.dec_tlu_sideeffect_posted_disable
io.dec_tlu_core_ecc_disable := tlu.io.dec_tlu_core_ecc_disable
io.dec_tlu_bpred_disable := tlu.io.dec_tlu_bpred_disable
io.dec_tlu_wb_coalescing_disable := tlu.io.dec_tlu_wb_coalescing_disable
io.dec_tlu_dma_qos_prty := tlu.io.dec_tlu_dma_qos_prty io.dec_tlu_dma_qos_prty := tlu.io.dec_tlu_dma_qos_prty
io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override
io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override

317
src/main/scala/dec/el2_dec_decode_ctl.scala
View File

@ -1,27 +1,34 @@
package dec package dec
import chisel3._ import chisel3._
import scala.collection._ import scala.collection._
import chisel3.util._ import chisel3.util._
import include._ import include._
import lib._ import lib._
import exu._
import ifu._
import lsu._
class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val io = IO(new Bundle{ val io = IO(new Bundle{
val decode_exu = Flipped(new decode_exu)
val dec_alu = Flipped(new dec_alu)
val dec_div = Flipped(new dec_div)
val dctl_busbuff = Flipped(new dctl_busbuff())
val dec_tlu_flush_extint = Input(Bool()) val dec_tlu_flush_extint = Input(Bool())
val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event
val dec_extint_stall = Output(Bool()) // val dec_extint_stall = Output(Bool())
val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction
val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder
val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder
val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m // val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m
val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag // val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r // val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r
val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag // val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back // val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back
val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error // val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error
val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag // val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data // val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data
val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches
val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r
val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only
@ -55,43 +62,43 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B
val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb
val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation
val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instr // val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instr
val lsu_result_m = Input(UInt(32.W)) // load result val lsu_result_m = Input(UInt(32.W)) // load result
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing
val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D // val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D
val exu_i0_pc_x = Input(UInt(31.W)) // pcs at e1 // val exu_i0_pc_x = Input(UInt(31.W)) // pcs at e1
val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode
val dec_ib0_valid_d = Input(Bool()) // inst valid at decode val dec_ib0_valid_d = Input(Bool()) // inst valid at decode
val exu_i0_result_x = Input(UInt(32.W)) // from primary alu's // val exu_i0_result_x = Input(UInt(32.W)) // from primary alu's
val free_clk = Input(Clock()) val free_clk = Input(Clock())
val active_clk = Input(Clock()) // clk except for halt / pause val active_clk = Input(Clock()) // clk except for halt / pause
val clk_override = Input(Bool()) // test stuff val clk_override = Input(Bool()) // test stuff
val dec_i0_rs1_en_d = Output(Bool()) // rs1 enable at decode // val dec_i0_rs1_en_d = Output(Bool()) // rs1 enable at decode
val dec_i0_rs2_en_d = Output(Bool()) // val dec_i0_rs2_en_d = Output(Bool())
val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source
val dec_i0_rs2_d = Output(UInt(5.W)) val dec_i0_rs2_d = Output(UInt(5.W))
val dec_i0_immed_d = Output(UInt(32.W)) // 32b immediate data decode // val dec_i0_immed_d = Output(UInt(32.W)) // 32b immediate data decode
val dec_i0_br_immed_d = Output(UInt(12.W)) // 12b branch immediate // val dec_i0_br_immed_d = Output(UInt(12.W)) // 12b branch immediate
val i0_ap = Output(new el2_alu_pkt_t) // alu packets // val i0_ap = Output(new el2_alu_pkt_t) // alu packets
val dec_i0_decode_d = Output(Bool()) // i0 decode // val dec_i0_decode_d = Output(Bool()) // i0 decode
val dec_i0_alu_decode_d = Output(Bool()) // decode to D-stage alu // val dec_i0_alu_decode_d = Output(Bool()) // decode to D-stage alu
val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // i0 rs1 bypass data // val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // i0 rs1 bypass data
val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // i0 rs2 bypass data // val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // i0 rs2 bypass data
val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's
val dec_i0_wen_r = Output(Bool()) // i0 write enable val dec_i0_wen_r = Output(Bool()) // i0 write enable
val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data
val dec_i0_select_pc_d = Output(Bool()) // i0 select pc for rs1 - branches // val dec_i0_select_pc_d = Output(Bool()) // i0 select pc for rs1 - branches
val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // i0 rs1 bypass enable // val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // i0 rs1 bypass enable
val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // i0 rs2 bypass enable // val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // i0 rs2 bypass enable
val lsu_p = Valid(new el2_lsu_pkt_t) // load/store packet val lsu_p = Valid(new el2_lsu_pkt_t) // load/store packet
val mul_p = Valid(new el2_mul_pkt_t) // multiply packet // val mul_p = Valid(new el2_mul_pkt_t) // multiply packet
val div_p = Valid(new el2_div_pkt_t) // divide packet // val div_p = Valid(new el2_div_pkt_t) // divide packet
val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR
val dec_div_cancel = Output(Bool()) // cancel the divide operation // val dec_div_cancel = Output(Bool()) // cancel the divide operation
val dec_lsu_valid_raw_d = Output(Bool()) val dec_lsu_valid_raw_d = Output(Bool())
val dec_lsu_offset_d = Output(UInt(12.W)) val dec_lsu_offset_d = Output(UInt(12.W))
val dec_csr_ren_d = Output(Bool()) // valid csr decode // val dec_csr_ren_d = Output(Bool()) // valid csr decode
val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal
val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal
val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr
@ -103,13 +110,14 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val dec_tlu_packet_r = Output(new el2_trap_pkt_t) // trap packet val dec_tlu_packet_r = Output(new el2_trap_pkt_t) // trap packet
val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc
val dec_illegal_inst = Output(UInt(32.W)) // illegal inst val dec_illegal_inst = Output(UInt(32.W)) // illegal inst
val pred_correct_npc_x = Output(UInt(31.W)) // npc e2 if the prediction is correct // val pred_correct_npc_x = Output(UInt(31.W)) // npc e2 if the prediction is correct
val dec_i0_predict_p_d = Valid(new el2_predict_pkt_t) // i0 predict packet decode
val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // i0 predict fghr // val dec_i0_predict_p_d = Valid(new el2_predict_pkt_t) // i0 predict packet decode
val i0_predict_index_d = Output(UInt(((BHT_ADDR_HI-BHT_ADDR_LO)+1).W)) // i0 predict index // val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // i0 predict fghr
val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // i0_predict branch tag // val i0_predict_index_d = Output(UInt(((BHT_ADDR_HI-BHT_ADDR_LO)+1).W)) // i0 predict index
val dec_data_en = Output(UInt(2.W)) // clock-gating logic // val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // i0_predict branch tag
val dec_ctl_en = Output(UInt(2.W)) // val dec_data_en = Output(UInt(2.W)) // clock-gating logic
// val dec_ctl_en = Output(UInt(2.W))
val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded
val dec_pmu_decode_stall = Output(Bool()) // decode is stalled val dec_pmu_decode_stall = Output(Bool()) // decode is stalled
val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall
@ -120,10 +128,12 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating
val dec_div_active = Output(Bool()) // non-block divide is active val dec_div_active = Output(Bool()) // non-block divide is active
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
})
val dec_aln = Flipped(new aln_dec)
})
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// //packets zero initialization // //packets zero initialization
io.mul_p := 0.U.asTypeOf(io.mul_p) io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p)
// Vals defined // Vals defined
val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U) val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U)
val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U) val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U)
@ -207,15 +217,14 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val i0_result_r = WireInit(UInt(32.W), 0.U) val i0_result_r = WireInit(UInt(32.W), 0.U)
////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////
// Start - Data gating {{ // Start - Data gating {{
val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk
(tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk (tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk
(io.dec_tlu_flush_extint ^ io.dec_extint_stall) | (io.dec_tlu_flush_extint ^ io.decode_exu.dec_extint_stall) |
(leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk (leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk
(leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk (leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk
(pause_state_in ^ pause_state ) | // replaces free_clk (pause_state_in ^ pause_state ) | // replaces free_clk
(ps_stall_in ^ postsync_stall ) | // replaces free_clk (ps_stall_in ^ postsync_stall ) | // replaces free_clk
(io.exu_flush_final ^ flush_final_r ) | // replaces free_clk (io.dec_alu.exu_flush_final ^ flush_final_r ) | // replaces free_clk
(illegal_lockout_in ^ illegal_lockout ) // replaces active_clk (illegal_lockout_in ^ illegal_lockout ) // replaces active_clk
@ -224,30 +233,30 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
// End - Data gating }} // End - Data gating }}
val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode
io.dec_i0_predict_p_d.bits.misp :=0.U io.decode_exu.dec_i0_predict_p_d.bits.misp :=0.U
io.dec_i0_predict_p_d.bits.ataken :=0.U io.decode_exu.dec_i0_predict_p_d.bits.ataken :=0.U
io.dec_i0_predict_p_d.bits.boffset :=0.U io.decode_exu.dec_i0_predict_p_d.bits.boffset :=0.U
io.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error io.decode_exu.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error
io.dec_i0_predict_p_d.bits.pja := i0_pja io.decode_exu.dec_i0_predict_p_d.bits.pja := i0_pja
io.dec_i0_predict_p_d.bits.pret := i0_pret io.decode_exu.dec_i0_predict_p_d.bits.pret := i0_pret
io.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett io.decode_exu.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett
io.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d io.decode_exu.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d
io.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist io.decode_exu.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist
io.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d io.decode_exu.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d
val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw) val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
// no toffset error for a pret // no toffset error for a pret
val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw
val i0_ret_error = i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw; val i0_ret_error = i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw;
val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
io.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode io.decode_exu.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode
io.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode io.decode_exu.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode
io.i0_predict_index_d := io.dec_i0_bp_index io.decode_exu.i0_predict_index_d := io.dec_i0_bp_index
io.i0_predict_btag_d := io.dec_i0_bp_btag io.decode_exu.i0_predict_btag_d := io.dec_i0_bp_btag
val i0_br_error_all = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode val i0_br_error_all = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode
io.dec_i0_predict_p_d.bits.toffset := i0_br_offset io.decode_exu.dec_i0_predict_p_d.bits.toffset := i0_br_offset
io.i0_predict_fghr_d := io.dec_i0_bp_fghr io.decode_exu.i0_predict_fghr_d := io.dec_i0_bp_fghr
io.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way io.decode_exu.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way
// end // end
// on br error turn anything into a nop // on br error turn anything into a nop
@ -268,54 +277,54 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
} }
val i0 = io.dec_i0_instr_d val i0 = io.dec_i0_instr_d
io.dec_i0_select_pc_d := i0_dp.pc; io.decode_exu.dec_i0_select_pc_d := i0_dp.pc
// branches that can be predicted // branches that can be predicted
val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret; val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
val i0_ap_pc2 = !io.dec_i0_pc4_d val i0_ap_pc2 = !io.dec_i0_pc4_d
val i0_ap_pc4 = io.dec_i0_pc4_d val i0_ap_pc4 = io.dec_i0_pc4_d
io.i0_ap.predict_nt := i0_predict_nt io.decode_exu.i0_ap.predict_nt := i0_predict_nt
io.i0_ap.predict_t := i0_predict_t io.decode_exu.i0_ap.predict_t := i0_predict_t
io.i0_ap.add := i0_dp.add
io.i0_ap.sub := i0_dp.sub
io.i0_ap.land := i0_dp.land
io.i0_ap.lor := i0_dp.lor
io.i0_ap.lxor := i0_dp.lxor
io.i0_ap.sll := i0_dp.sll
io.i0_ap.srl := i0_dp.srl
io.i0_ap.sra := i0_dp.sra
io.i0_ap.slt := i0_dp.slt
io.i0_ap.unsign := i0_dp.unsign
io.i0_ap.beq := i0_dp.beq
io.i0_ap.bne := i0_dp.bne
io.i0_ap.blt := i0_dp.blt
io.i0_ap.bge := i0_dp.bge
io.i0_ap.csr_write := i0_csr_write_only_d
io.i0_ap.csr_imm := i0_dp.csr_imm
io.i0_ap.jal := i0_jal
io.decode_exu.i0_ap.add := i0_dp.add
io.decode_exu.i0_ap.sub := i0_dp.sub
io.decode_exu.i0_ap.land := i0_dp.land
io.decode_exu.i0_ap.lor := i0_dp.lor
io.decode_exu.i0_ap.lxor := i0_dp.lxor
io.decode_exu.i0_ap.sll := i0_dp.sll
io.decode_exu.i0_ap.srl := i0_dp.srl
io.decode_exu.i0_ap.sra := i0_dp.sra
io.decode_exu.i0_ap.slt := i0_dp.slt
io.decode_exu.i0_ap.unsign := i0_dp.unsign
io.decode_exu.i0_ap.beq := i0_dp.beq
io.decode_exu.i0_ap.bne := i0_dp.bne
io.decode_exu.i0_ap.blt := i0_dp.blt
io.decode_exu.i0_ap.bge := i0_dp.bge
io.decode_exu.i0_ap.csr_write := i0_csr_write_only_d
io.decode_exu.i0_ap.csr_imm := i0_dp.csr_imm
io.decode_exu.i0_ap.jal := i0_jal
// non block load cam logic // non block load cam logic
// val found=Wire(UInt(1.W)) // val found=Wire(UInt(1.W))
cam_wen := Mux1H((0 until LSU_NUM_NBLOAD).map(i=>(0 to i).map(j=> if(i==j) !cam(j).valid else cam(j).valid).reduce(_.asBool&_.asBool).asBool -> (cam_write << i))) cam_wen := Mux1H((0 until LSU_NUM_NBLOAD).map(i=>(0 to i).map(j=> if(i==j) !cam(j).valid else cam(j).valid).reduce(_.asBool&_.asBool).asBool -> (cam_write << i)))
cam_write := io.lsu_nonblock_load_valid_m cam_write := io.dctl_busbuff.lsu_nonblock_load_valid_m
val cam_write_tag = io.lsu_nonblock_load_tag_m(LSU_NUM_NBLOAD_WIDTH-1,0) val cam_write_tag = io.dctl_busbuff.lsu_nonblock_load_tag_m(LSU_NUM_NBLOAD_WIDTH-1,0)
val cam_inv_reset = io.lsu_nonblock_load_inv_r val cam_inv_reset = io.dctl_busbuff.lsu_nonblock_load_inv_r
val cam_inv_reset_tag = io.lsu_nonblock_load_inv_tag_r val cam_inv_reset_tag = io.dctl_busbuff.lsu_nonblock_load_inv_tag_r
val cam_data_reset = io.lsu_nonblock_load_data_valid | io.lsu_nonblock_load_data_error val cam_data_reset = io.dctl_busbuff.lsu_nonblock_load_data_valid | io.dctl_busbuff.lsu_nonblock_load_data_error
val cam_data_reset_tag = io.lsu_nonblock_load_data_tag val cam_data_reset_tag = io.dctl_busbuff.lsu_nonblock_load_data_tag
val nonblock_load_rd = Mux(x_d.bits.i0load.asBool, x_d.bits.i0rd, 0.U(5.W)) // rd data val nonblock_load_rd = Mux(x_d.bits.i0load.asBool, x_d.bits.i0rd, 0.U(5.W)) // rd data
val load_data_tag = io.lsu_nonblock_load_data_tag val load_data_tag = io.dctl_busbuff.lsu_nonblock_load_data_tag
// case of multiple loads to same dest ie. x1 ... you have to invalidate the older one // case of multiple loads to same dest ie. x1 ... you have to invalidate the older one
// don't writeback a nonblock load // don't writeback a nonblock load
val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)} val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.dctl_busbuff.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)}
val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.bits.i0load val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.bits.i0load
for(i <- 0 until LSU_NUM_NBLOAD){ for(i <- 0 until LSU_NUM_NBLOAD){
cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid
@ -336,7 +345,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
}.otherwise{ }.otherwise{
cam_in(i) := cam(i) cam_in(i) := cam(i)
} }
when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).bits.tag) && cam(i).valid===1.U){ when(nonblock_load_valid_m_delay===1.U && (io.dctl_busbuff.lsu_nonblock_load_inv_tag_r === cam(i).bits.tag) && cam(i).valid===1.U){
cam_in(i).bits.wb := 1.U cam_in(i).bits.wb := 1.U
} }
// force debug halt forces cam valids to 0; highest priority // force debug halt forces cam valids to 0; highest priority
@ -351,12 +360,12 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
io.dec_nonblock_load_waddr:=0.U(5.W) io.dec_nonblock_load_waddr:=0.U(5.W)
// cancel if any younger inst (including another nonblock) committing this cycle // cancel if any younger inst (including another nonblock) committing this cycle
val nonblock_load_cancel = ((r_d_in.bits.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r) val nonblock_load_cancel = ((r_d_in.bits.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r)
io.dec_nonblock_load_wen := (io.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel) io.dec_nonblock_load_wen := (io.dctl_busbuff.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel)
val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs2_en_d) val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.dctl_busbuff.lsu_nonblock_load_valid_m & io.decode_exu.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.dctl_busbuff.lsu_nonblock_load_valid_m & io.decode_exu.dec_i0_rs2_en_d)
i0_nonblock_load_stall := i0_nonblock_boundary_stall i0_nonblock_load_stall := i0_nonblock_boundary_stall
val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).bits.rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs2)) val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).bits.rd), io.decode_exu.dec_i0_rs1_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs1), io.decode_exu.dec_i0_rs2_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs2))
val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) ) val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) )
io.dec_nonblock_load_waddr:=waddr io.dec_nonblock_load_waddr:=waddr
i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall
@ -399,7 +408,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
leak1_i1_stall_in := (io.dec_tlu_flush_leak_one_r | (leak1_i1_stall & !io.dec_tlu_flush_lower_r)) leak1_i1_stall_in := (io.dec_tlu_flush_leak_one_r | (leak1_i1_stall & !io.dec_tlu_flush_lower_r))
leak1_i1_stall := withClock(data_gate_clk){RegNext(leak1_i1_stall_in,0.U)} leak1_i1_stall := withClock(data_gate_clk){RegNext(leak1_i1_stall_in,0.U)}
leak1_mode := leak1_i1_stall leak1_mode := leak1_i1_stall
leak1_i0_stall_in := ((io.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r)) leak1_i0_stall_in := ((io.dec_aln.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r))
leak1_i0_stall := withClock(data_gate_clk){RegNext(leak1_i0_stall_in,0.U)} leak1_i0_stall := withClock(data_gate_clk){RegNext(leak1_i0_stall_in,0.U)}
// 12b jal's can be predicted - these are calls // 12b jal's can be predicted - these are calls
@ -420,19 +429,19 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
i0_jal := i0_dp.jal & !i0_pcall_case & !i0_pja_case & !i0_pret_case i0_jal := i0_dp.jal & !i0_pcall_case & !i0_pja_case & !i0_pret_case
/////////////////////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////////////////////
io.div_p.valid := div_decode_d io.dec_div.div_p.valid := div_decode_d
io.div_p.bits.unsign := i0_dp.unsign io.dec_div.div_p.bits.unsign := i0_dp.unsign
io.div_p.bits.rem := i0_dp.rem io.dec_div.div_p.bits.rem := i0_dp.rem
io.mul_p.valid := mul_decode_d io.decode_exu.mul_p.valid := mul_decode_d
io.mul_p.bits.rs1_sign := i0_dp.rs1_sign io.decode_exu.mul_p.bits.rs1_sign := i0_dp.rs1_sign
io.mul_p.bits.rs2_sign := i0_dp.rs2_sign io.decode_exu.mul_p.bits.rs2_sign := i0_dp.rs2_sign
io.mul_p.bits.low := i0_dp.low io.decode_exu.mul_p.bits.low := i0_dp.low
io.dec_extint_stall := withClock(data_gate_clk){RegNext(io.dec_tlu_flush_extint,0.U)} io.decode_exu.dec_extint_stall := withClock(data_gate_clk){RegNext(io.dec_tlu_flush_extint,0.U)}
io.lsu_p := 0.U.asTypeOf(io.lsu_p) io.lsu_p := 0.U.asTypeOf(io.lsu_p)
when (io.dec_extint_stall){ when (io.decode_exu.dec_extint_stall){
io.lsu_p.bits.load := 1.U(1.W) io.lsu_p.bits.load := 1.U(1.W)
io.lsu_p.bits.word := 1.U(1.W) io.lsu_p.bits.word := 1.U(1.W)
io.lsu_p.bits.fast_int := 1.U(1.W) io.lsu_p.bits.fast_int := 1.U(1.W)
@ -451,7 +460,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
} }
////////////////////////////////////// //////////////////////////////////////
io.dec_csr_ren_d := i0_dp.csr_read //H: assigning csr read enable signal decoded from decode_ctl going as input to EXU io.dec_alu.dec_csr_ren_d := i0_dp.csr_read //H: assigning csr read enable signal decoded from decode_ctl going as input to EXU
csr_ren_qual_d := i0_dp.csr_read & i0_legal_decode_d.asBool //csr_ren_qual_d assigned as csr_read above csr_ren_qual_d := i0_dp.csr_read & i0_legal_decode_d.asBool //csr_ren_qual_d assigned as csr_read above
val i0_csr_write = i0_dp.csr_write & !io.dec_debug_fence_d val i0_csr_write = i0_dp.csr_write & !io.dec_debug_fence_d
@ -485,14 +494,14 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val csr_mask_x = Mux1H(Seq( val csr_mask_x = Mux1H(Seq(
csr_imm_x.asBool -> Cat(repl(27,0.U),csrimm_x(4,0)), csr_imm_x.asBool -> Cat(repl(27,0.U),csrimm_x(4,0)),
!csr_imm_x.asBool -> io.exu_csr_rs1_x)) !csr_imm_x.asBool -> io.decode_exu.exu_csr_rs1_x))
val write_csr_data_x = Mux1H(Seq( val write_csr_data_x = Mux1H(Seq(
csr_clr_x -> (csr_rddata_x & (~csr_mask_x).asUInt), csr_clr_x -> (csr_rddata_x & (~csr_mask_x).asUInt),
csr_set_x -> (csr_rddata_x | csr_mask_x), csr_set_x -> (csr_rddata_x | csr_mask_x),
csr_write_x -> ( csr_mask_x))) csr_write_x -> ( csr_mask_x)))
// pause instruction // pause instruction
val clear_pause = (io.dec_tlu_flush_lower_r & !io.dec_tlu_flush_pause_r) | (pause_state & (write_csr_data === 0.U(31.W))) // if 0 or 1 then exit pause state - 1 cycle pause val clear_pause = (io.dec_tlu_flush_lower_r & !io.dec_tlu_flush_pause_r) | (pause_state & (write_csr_data === Cat(Fill(31,0.U),write_csr_data(0)))) // if 0 or 1 then exit pause state - 1 cycle pause
pause_state_in := (io.dec_tlu_wr_pause_r | pause_state) & !clear_pause pause_state_in := (io.dec_tlu_wr_pause_r | pause_state) & !clear_pause
pause_state := withClock(data_gate_clk){RegNext(pause_state_in, 0.U)} pause_state := withClock(data_gate_clk){RegNext(pause_state_in, 0.U)}
io.dec_pause_state := pause_state io.dec_pause_state := pause_state
@ -528,17 +537,17 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val any_csr_d = i0_dp.csr_read | i0_csr_write val any_csr_d = i0_dp.csr_read | i0_csr_write
io.dec_csr_any_unq_d := any_csr_d io.dec_csr_any_unq_d := any_csr_d
val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d) val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d)
val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.ifu_i0_cinst)) val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.dec_aln.ifu_i0_cinst))
// illegal inst handling // illegal inst handling
val shift_illegal = io.dec_i0_decode_d & !i0_legal//lm: valid but not legal val shift_illegal = io.dec_aln.dec_i0_decode_d & !i0_legal//lm: valid but not legal
val illegal_inst_en = shift_illegal & !illegal_lockout val illegal_inst_en = shift_illegal & !illegal_lockout
io.dec_illegal_inst := rvdffe(i0_inst_d,illegal_inst_en,clock,io.scan_mode) io.dec_illegal_inst := rvdffe(i0_inst_d,illegal_inst_en,clock,io.scan_mode)
illegal_lockout_in := (shift_illegal | illegal_lockout) & !flush_final_r illegal_lockout_in := (shift_illegal | illegal_lockout) & !flush_final_r
illegal_lockout := withClock(data_gate_clk){RegNext(illegal_lockout_in, 0.U)} illegal_lockout := withClock(data_gate_clk){RegNext(illegal_lockout_in, 0.U)}
val i0_div_prior_div_stall = i0_dp.div & io.dec_div_active val i0_div_prior_div_stall = i0_dp.div & io.dec_div_active
//stalls signals //stalls signals
val i0_block_raw_d = (i0_dp.csr_read & prior_csr_write) | io.dec_extint_stall | pause_stall | val i0_block_raw_d = (i0_dp.csr_read & prior_csr_write) | io.decode_exu.dec_extint_stall | pause_stall |
leak1_i0_stall | io.dec_tlu_debug_stall | postsync_stall | presync_stall | leak1_i0_stall | io.dec_tlu_debug_stall | postsync_stall | presync_stall |
((i0_dp.fence | debug_fence) & !lsu_idle) | i0_nonblock_load_stall | ((i0_dp.fence | debug_fence) & !lsu_idle) | i0_nonblock_load_stall |
i0_load_block_d | i0_nonblock_div_stall | i0_div_prior_div_stall i0_load_block_d | i0_nonblock_div_stall | i0_div_prior_div_stall
@ -549,13 +558,13 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val i0_exublock_d = i0_block_raw_d val i0_exublock_d = i0_block_raw_d
//decode valid //decode valid
io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r io.dec_aln.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
val i0_exudecode_d = io.dec_ib0_valid_d & !i0_exublock_d & !io.dec_tlu_flush_lower_r & !flush_final_r val i0_exudecode_d = io.dec_ib0_valid_d & !i0_exublock_d & !io.dec_tlu_flush_lower_r & !flush_final_r
val i0_exulegal_decode_d = i0_exudecode_d & i0_legal val i0_exulegal_decode_d = i0_exudecode_d & i0_legal
// performance monitor signals // performance monitor signals
io.dec_pmu_instr_decoded := io.dec_i0_decode_d io.dec_pmu_instr_decoded := io.dec_aln.dec_i0_decode_d
io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_i0_decode_d io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_aln.dec_i0_decode_d
io.dec_pmu_postsync_stall := postsync_stall.asBool io.dec_pmu_postsync_stall := postsync_stall.asBool
io.dec_pmu_presync_stall := presync_stall.asBool io.dec_pmu_presync_stall := presync_stall.asBool
@ -567,9 +576,9 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
presync_stall := (i0_presync & prior_inflight_eff) presync_stall := (i0_presync & prior_inflight_eff)
postsync_stall := withClock(data_gate_clk){RegNext(ps_stall_in, 0.U)} postsync_stall := withClock(data_gate_clk){RegNext(ps_stall_in, 0.U)}
// illegals will postsync // illegals will postsync
ps_stall_in := (io.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x) ps_stall_in := (io.dec_aln.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x)
io.dec_i0_alu_decode_d := i0_exulegal_decode_d & i0_dp.alu io.dec_alu.dec_i0_alu_decode_d := i0_exulegal_decode_d & i0_dp.alu
lsu_decode_d := i0_legal_decode_d & i0_dp.lsu lsu_decode_d := i0_legal_decode_d & i0_dp.lsu
mul_decode_d := i0_exulegal_decode_d & i0_dp.mul mul_decode_d := i0_exulegal_decode_d & i0_dp.mul
@ -590,7 +599,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
d_t.pmu_divide := 0.U(1.W) d_t.pmu_divide := 0.U(1.W)
d_t.pmu_lsu_misaligned := 0.U(1.W) d_t.pmu_lsu_misaligned := 0.U(1.W)
d_t.i0trigger := io.dec_i0_trigger_match_d & repl(4,io.dec_i0_decode_d) d_t.i0trigger := io.dec_i0_trigger_match_d & repl(4,io.dec_aln.dec_i0_decode_d)
x_t := rvdffe(d_t,i0_x_ctl_en.asBool,clock,io.scan_mode) x_t := rvdffe(d_t,i0_x_ctl_en.asBool,clock,io.scan_mode)
@ -613,16 +622,16 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
io.dec_tlu_packet_r.pmu_divide := r_d.bits.i0div & r_d.valid io.dec_tlu_packet_r.pmu_divide := r_d.bits.i0div & r_d.valid
// end tlu stuff // end tlu stuff
flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)} flush_final_r := withClock(data_gate_clk){RegNext(io.dec_alu.exu_flush_final, 0.U)}
io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r io.dec_aln.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
i0r.rs1 := i0(19,15) //H: assigning reg packets the instructions bits i0r.rs1 := i0(19,15) //H: assigning reg packets the instructions bits
i0r.rs2 := i0(24,20) i0r.rs2 := i0(24,20)
i0r.rd := i0(11,7) i0r.rd := i0(11,7)
io.dec_i0_rs1_en_d := i0_dp.rs1 & (i0r.rs1 =/= 0.U(5.W)) // if rs1_en=0 then read will be all 0's io.decode_exu.dec_i0_rs1_en_d := i0_dp.rs1 & (i0r.rs1 =/= 0.U(5.W)) // if rs1_en=0 then read will be all 0's
io.dec_i0_rs2_en_d := i0_dp.rs2 & (i0r.rs2 =/= 0.U(5.W)) io.decode_exu.dec_i0_rs2_en_d := i0_dp.rs2 & (i0r.rs2 =/= 0.U(5.W))
val i0_rd_en_d = i0_dp.rd & (i0r.rd =/= 0.U(5.W)) val i0_rd_en_d = i0_dp.rd & (i0r.rd =/= 0.U(5.W))
io.dec_i0_rs1_d := i0r.rs1//H:assiging packets to output signals leading to gprfile io.dec_i0_rs1_d := i0r.rs1//H:assiging packets to output signals leading to gprfile
io.dec_i0_rs2_d := i0r.rs2 io.dec_i0_rs2_d := i0r.rs2
@ -630,7 +639,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val i0_jalimm20 = i0_dp.jal & i0_dp.imm20 // H:jal (used at line 915) val i0_jalimm20 = i0_dp.jal & i0_dp.imm20 // H:jal (used at line 915)
val i0_uiimm20 = !i0_dp.jal & i0_dp.imm20 val i0_uiimm20 = !i0_dp.jal & i0_dp.imm20
io.dec_i0_immed_d := Mux1H(Seq( io.decode_exu.dec_i0_immed_d := Mux1H(Seq(
i0_dp.csr_read -> io.dec_csr_rddata_d, i0_dp.csr_read -> io.dec_csr_rddata_d,
!i0_dp.csr_read -> i0_immed_d)) !i0_dp.csr_read -> i0_immed_d))
@ -641,7 +650,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
i0_uiimm20 -> Cat(i0(31,12),repl(12,0.U)), i0_uiimm20 -> Cat(i0(31,12),repl(12,0.U)),
(i0_csr_write_only_d & i0_dp.csr_imm).asBool -> Cat(repl(27,0.U),i0(19,15)))) // for csr's that only write (i0_csr_write_only_d & i0_dp.csr_imm).asBool -> Cat(repl(27,0.U),i0(19,15)))) // for csr's that only write
i0_legal_decode_d := io.dec_i0_decode_d & i0_legal i0_legal_decode_d := io.dec_aln.dec_i0_decode_d & i0_legal
i0_d_c.mul := i0_dp.mul & i0_legal_decode_d i0_d_c.mul := i0_dp.mul & i0_legal_decode_d
i0_d_c.load := i0_dp.load & i0_legal_decode_d i0_d_c.load := i0_dp.load & i0_legal_decode_d
@ -649,7 +658,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c, i0_x_ctl_en.asBool)} val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c, i0_x_ctl_en.asBool)}
val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c, i0_r_ctl_en.asBool)} val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c, i0_r_ctl_en.asBool)}
i0_pipe_en := Cat(io.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)}) i0_pipe_en := Cat(io.dec_aln.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)})
i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override) i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override)
i0_r_ctl_en := (i0_pipe_en(2,1).orR | io.clk_override) i0_r_ctl_en := (i0_pipe_en(2,1).orR | io.clk_override)
@ -659,19 +668,19 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
i0_wb_data_en := ( i0_pipe_en(1) | io.clk_override) i0_wb_data_en := ( i0_pipe_en(1) | io.clk_override)
i0_wb1_data_en := ( i0_pipe_en(0) | io.clk_override) i0_wb1_data_en := ( i0_pipe_en(0) | io.clk_override)
io.dec_data_en := Cat(i0_x_data_en, i0_r_data_en) io.decode_exu.dec_data_en := Cat(i0_x_data_en, i0_r_data_en)
io.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en) io.decode_exu.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en)
d_d.bits.i0rd := i0r.rd d_d.bits.i0rd := i0r.rd
d_d.bits.i0v := i0_rd_en_d & i0_legal_decode_d d_d.bits.i0v := i0_rd_en_d & i0_legal_decode_d
d_d.valid := io.dec_i0_decode_d // has flush_final_r d_d.valid := io.dec_aln.dec_i0_decode_d // has flush_final_r
d_d.bits.i0load := i0_dp.load & i0_legal_decode_d d_d.bits.i0load := i0_dp.load & i0_legal_decode_d
d_d.bits.i0store := i0_dp.store & i0_legal_decode_d d_d.bits.i0store := i0_dp.store & i0_legal_decode_d
d_d.bits.i0div := i0_dp.div & i0_legal_decode_d d_d.bits.i0div := i0_dp.div & i0_legal_decode_d
d_d.bits.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d d_d.bits.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d
d_d.bits.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d d_d.bits.csrwonly := i0_csr_write_only_d & io.dec_aln.dec_i0_decode_d
d_d.bits.csrwaddr := i0(31,20) d_d.bits.csrwaddr := i0(31,20)
x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode) x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode)
@ -698,19 +707,19 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode) val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode)
if ( LOAD_TO_USE_PLUS1 == 1 ) { if ( LOAD_TO_USE_PLUS1 == 1 ) {
i0_result_x := io.exu_i0_result_x i0_result_x := io.decode_exu.exu_i0_result_x
i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw) i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw)
} }
else { else {
i0_result_x := Mux((x_d.bits.i0v & x_d.bits.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x) i0_result_x := Mux((x_d.bits.i0v & x_d.bits.i0load).asBool,io.lsu_result_m,io.decode_exu.exu_i0_result_x)
i0_result_r := i0_result_r_raw i0_result_r := i0_result_r_raw
} }
// correct lsu load data - don't use for bypass, do pass down the pipe // correct lsu load data - don't use for bypass, do pass down the pipe
i0_result_corr_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw) i0_result_corr_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw)
io.dec_i0_br_immed_d := Mux((io.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2)) io.dec_alu.dec_i0_br_immed_d := Mux((io.decode_exu.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2))
val last_br_immed_d = WireInit(UInt(12.W),0.U) val last_br_immed_d = WireInit(UInt(12.W),0.U)
last_br_immed_d := Mux((io.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset) last_br_immed_d := Mux((io.decode_exu.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset)
val last_br_immed_x = WireInit(UInt(12.W),0.U) val last_br_immed_x = WireInit(UInt(12.W),0.U)
last_br_immed_x := rvdffe(last_br_immed_d,i0_x_data_en.asBool,clock,io.scan_mode) last_br_immed_x := rvdffe(last_br_immed_d,i0_x_data_en.asBool,clock,io.scan_mode)
@ -727,7 +736,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val nonblock_div_cancel = (io.dec_div_active & div_flush) | val nonblock_div_cancel = (io.dec_div_active & div_flush) |
(io.dec_div_active & !div_e1_to_r & (r_d.bits.i0rd === io.div_waddr_wb) & i0_wen_r) (io.dec_div_active & !div_e1_to_r & (r_d.bits.i0rd === io.div_waddr_wb) & i0_wen_r)
io.dec_div_cancel := nonblock_div_cancel.asBool io.dec_div.dec_div_cancel := nonblock_div_cancel.asBool
val i0_div_decode_d = i0_legal_decode_d & i0_dp.div val i0_div_decode_d = i0_legal_decode_d & i0_dp.div
val div_active_in = i0_div_decode_d | (io.dec_div_active & !io.exu_div_wren & !nonblock_div_cancel) val div_active_in = i0_div_decode_d | (io.dec_div_active & !io.exu_div_wren & !nonblock_div_cancel)
@ -735,8 +744,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
io.dec_div_active := withClock(io.free_clk){RegNext(div_active_in, 0.U)} io.dec_div_active := withClock(io.free_clk){RegNext(div_active_in, 0.U)}
// nonblocking div scheme // nonblocking div scheme
i0_nonblock_div_stall := (io.dec_i0_rs1_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs1)) | i0_nonblock_div_stall := (io.decode_exu.dec_i0_rs1_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs1)) |
(io.dec_i0_rs2_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs2)) (io.decode_exu.dec_i0_rs2_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs2))
io.div_waddr_wb := RegEnable(i0r.rd,0.U,i0_div_decode_d.asBool) io.div_waddr_wb := RegEnable(i0r.rd,0.U,i0_div_decode_d.asBool)
///div end ///div end
@ -754,22 +763,22 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val i0_pc_wb = rvdffe(io.dec_tlu_i0_pc_r,i0_wb_en.asBool,clock,io.scan_mode) val i0_pc_wb = rvdffe(io.dec_tlu_i0_pc_r,i0_wb_en.asBool,clock,io.scan_mode)
io.dec_i0_pc_wb1 := rvdffe(i0_pc_wb,i0_wb1_en.asBool,clock,io.scan_mode) io.dec_i0_pc_wb1 := rvdffe(i0_pc_wb,i0_wb1_en.asBool,clock,io.scan_mode)
val dec_i0_pc_r = rvdffe(io.exu_i0_pc_x,i0_r_data_en.asBool,clock,io.scan_mode) val dec_i0_pc_r = rvdffe(io.dec_alu.exu_i0_pc_x,i0_r_data_en.asBool,clock,io.scan_mode)
io.dec_tlu_i0_pc_r := dec_i0_pc_r io.dec_tlu_i0_pc_r := dec_i0_pc_r
//end tracing //end tracing
val temp_pred_correct_npc_x = rvbradder(Cat(io.exu_i0_pc_x,0.U),Cat(last_br_immed_x,0.U)) val temp_pred_correct_npc_x = rvbradder(Cat(io.dec_alu.exu_i0_pc_x,0.U),Cat(last_br_immed_x,0.U))
io.pred_correct_npc_x := temp_pred_correct_npc_x(31,1) io.decode_exu.pred_correct_npc_x := temp_pred_correct_npc_x(31,1)
// scheduling logic for primary alu's // scheduling logic for primary alu's
val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs1) val i0_rs1_depend_i0_x = io.decode_exu.dec_i0_rs1_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs1)
val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs1) val i0_rs1_depend_i0_r = io.decode_exu.dec_i0_rs1_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs1)
val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs2) val i0_rs2_depend_i0_x = io.decode_exu.dec_i0_rs2_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs2)
val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs2) val i0_rs2_depend_i0_r = io.decode_exu.dec_i0_rs2_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs2)
// order the producers as follows: , i0_x, i0_r, i0_wb // order the producers as follows: , i0_x, i0_r, i0_wb
i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d))) i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d)))
i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U)) i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U))
@ -791,35 +800,35 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
} }
// add nonblock load rs1/rs2 bypass cases // add nonblock load rs1/rs2 bypass cases
val i0_rs1_nonblock_load_bypass_en_d = io.dec_i0_rs1_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs1) val i0_rs1_nonblock_load_bypass_en_d = io.decode_exu.dec_i0_rs1_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs1)
val i0_rs2_nonblock_load_bypass_en_d = io.dec_i0_rs2_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs2) val i0_rs2_nonblock_load_bypass_en_d = io.decode_exu.dec_i0_rs2_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs2)
// bit 2 is priority match, bit 0 lowest priority , i0_x, i0_r // bit 2 is priority match, bit 0 lowest priority , i0_x, i0_r
i0_rs1bypass := Cat((i0_rs1_depth_d(0) &(i0_rs1_class_d.alu | i0_rs1_class_d.mul)),(i0_rs1_depth_d(0) & (i0_rs1_class_d.load)), (i0_rs1_depth_d(1) & (i0_rs1_class_d.alu | i0_rs1_class_d.mul | i0_rs1_class_d.load))) i0_rs1bypass := Cat((i0_rs1_depth_d(0) &(i0_rs1_class_d.alu | i0_rs1_class_d.mul)),(i0_rs1_depth_d(0) & (i0_rs1_class_d.load)), (i0_rs1_depth_d(1) & (i0_rs1_class_d.alu | i0_rs1_class_d.mul | i0_rs1_class_d.load)))
i0_rs2bypass := Cat((i0_rs2_depth_d(0) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul)),(i0_rs2_depth_d(0) & (i0_rs2_class_d.load)),(i0_rs2_depth_d(1) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul | i0_rs2_class_d.load))) i0_rs2bypass := Cat((i0_rs2_depth_d(0) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul)),(i0_rs2_depth_d(0) & (i0_rs2_class_d.load)),(i0_rs2_depth_d(1) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul | i0_rs2_class_d.load)))
io.dec_i0_rs1_bypass_en_d := Cat(i0_rs1bypass(2),(i0_rs1bypass(1) | i0_rs1bypass(0) | (!i0_rs1bypass(2) & i0_rs1_nonblock_load_bypass_en_d))) io.decode_exu.dec_i0_rs1_bypass_en_d := Cat(i0_rs1bypass(2),(i0_rs1bypass(1) | i0_rs1bypass(0) | (!i0_rs1bypass(2) & i0_rs1_nonblock_load_bypass_en_d)))
io.dec_i0_rs2_bypass_en_d := Cat(i0_rs2bypass(2),(i0_rs2bypass(1) | i0_rs2bypass(0) | (!i0_rs2bypass(2) & i0_rs2_nonblock_load_bypass_en_d))) io.decode_exu.dec_i0_rs2_bypass_en_d := Cat(i0_rs2bypass(2),(i0_rs2bypass(1) | i0_rs2bypass(0) | (!i0_rs2bypass(2) & i0_rs2_nonblock_load_bypass_en_d)))
io.dec_i0_rs1_bypass_data_d := Mux1H(Seq( io.decode_exu.dec_i0_rs1_bypass_data_d := Mux1H(Seq(
i0_rs1bypass(1).asBool -> io.lsu_result_m, i0_rs1bypass(1).asBool -> io.lsu_result_m,
i0_rs1bypass(0).asBool -> i0_result_r, i0_rs1bypass(0).asBool -> i0_result_r,
(!i0_rs1bypass(1) & !i0_rs1bypass(0) & i0_rs1_nonblock_load_bypass_en_d).asBool -> io.lsu_nonblock_load_data, (!i0_rs1bypass(1) & !i0_rs1bypass(0) & i0_rs1_nonblock_load_bypass_en_d).asBool -> io.dctl_busbuff.lsu_nonblock_load_data,
)) ))
io.dec_i0_rs2_bypass_data_d := Mux1H(Seq( io.decode_exu.dec_i0_rs2_bypass_data_d := Mux1H(Seq(
i0_rs2bypass(1).asBool -> io.lsu_result_m, i0_rs2bypass(1).asBool -> io.lsu_result_m,
i0_rs2bypass(0).asBool -> i0_result_r, i0_rs2bypass(0).asBool -> i0_result_r,
(!i0_rs2bypass(1) & !i0_rs2bypass(0) & i0_rs2_nonblock_load_bypass_en_d).asBool -> io.lsu_nonblock_load_data, (!i0_rs2bypass(1) & !i0_rs2bypass(0) & i0_rs2_nonblock_load_bypass_en_d).asBool -> io.dctl_busbuff.lsu_nonblock_load_data,
)) ))
io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dma_dccm_stall_any & !i0_block_raw_d) | io.dec_extint_stall) io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dma_dccm_stall_any & !i0_block_raw_d) | io.decode_exu.dec_extint_stall)
io.dec_lsu_offset_d := Mux1H(Seq( io.dec_lsu_offset_d := Mux1H(Seq(
(!io.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20), (!io.decode_exu.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20),
(!io.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7)))) (!io.decode_exu.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7))))
} }
object dec_decode extends App{ object dec_decode extends App{
println(chisel3.Driver.emitVerilog(new el2_dec_decode_ctl)) println(chisel3.Driver.emitVerilog(new el2_dec_decode_ctl))
} }

101
src/main/scala/dec/el2_dec_gpr_ctl.scala
View File

@ -1,69 +1,72 @@
package dec package dec
import chisel3._ import chisel3._
import scala.collection._ import scala.collection._
import chisel3.util._ import chisel3.util._
import exu.gpr_exu
import include._ import include._
import lib._ import lib._
class el2_dec_gpr_ctl extends Module with el2_lib with RequireAsyncReset{ class el2_dec_gpr_ctl extends Module with el2_lib with RequireAsyncReset{
val io =IO(new el2_dec_gpr_ctl_IO) val io =IO(new el2_dec_gpr_ctl_IO)
val w0v =Wire(Vec(32,UInt(1.W))) val w0v =Wire(Vec(32,UInt(1.W)))
w0v := (0 until 32).map(i => 0.U) w0v := (0 until 32).map(i => 0.U)
val w1v =Wire(Vec(32,UInt(1.W))) val w1v =Wire(Vec(32,UInt(1.W)))
w1v := (0 until 32).map(i => 0.U) w1v := (0 until 32).map(i => 0.U)
val w2v =Wire(Vec(32,UInt(1.W))) val w2v =Wire(Vec(32,UInt(1.W)))
w2v := (0 until 32).map(i => 0.U) w2v := (0 until 32).map(i => 0.U)
val gpr_in =Wire(Vec(32,UInt(32.W))) val gpr_in =Wire(Vec(32,UInt(32.W)))
gpr_in := (0 until 32).map(i => 0.U) gpr_in := (0 until 32).map(i => 0.U)
val gpr_out =Wire(Vec(32,UInt(32.W))) val gpr_out =Wire(Vec(32,UInt(32.W)))
gpr_out := (0 until 32).map(i => 0.U) gpr_out := (0 until 32).map(i => 0.U)
val gpr_wr_en =WireInit(UInt(32.W),0.U) val gpr_wr_en =WireInit(UInt(32.W),0.U)
w0v(0):=0.U w0v(0):=0.U
w1v(0):=0.U w1v(0):=0.U
w2v(0):=0.U w2v(0):=0.U
gpr_out(0):=0.U gpr_out(0):=0.U
gpr_in(0):=0.U gpr_in(0):=0.U
io.rd0:=0.U io.gpr_exu.gpr_i0_rs1_d:=0.U
io.rd1:=0.U io.gpr_exu.gpr_i0_rs2_d:=0.U
// GPR Write logic // GPR Write logic
for (j <-1 until 32){ for (j <-1 until 32){
w0v(j) := io.wen0 & (io.waddr0===j.asUInt) w0v(j) := io.wen0 & (io.waddr0===j.asUInt)
w1v(j) := io.wen1 & (io.waddr1===j.asUInt) w1v(j) := io.wen1 & (io.waddr1===j.asUInt)
w2v(j) := io.wen2 & (io.waddr2===j.asUInt) w2v(j) := io.wen2 & (io.waddr2===j.asUInt)
gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2) gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2)
} }
gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_)) gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_))
// GPR Write Enables for power savings // GPR Write Enables for power savings
for (j <-1 until 32){ for (j <-1 until 32){
gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode) gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode)
} }
// GPR Read logic // GPR Read logic
io.rd0:=Mux1H((1 until 32).map(i => (io.raddr0===i.U).asBool -> gpr_out(i))) io.gpr_exu.gpr_i0_rs1_d:=Mux1H((1 until 32).map(i => (io.raddr0===i.U).asBool -> gpr_out(i)))
io.rd1:=Mux1H((1 until 32).map(i => (io.raddr1===i.U).asBool -> gpr_out(i))) io.gpr_exu.gpr_i0_rs2_d:=Mux1H((1 until 32).map(i => (io.raddr1===i.U).asBool -> gpr_out(i)))
} }
class el2_dec_gpr_ctl_IO extends Bundle{ class el2_dec_gpr_ctl_IO extends Bundle{
val raddr0=Input(UInt(5.W)) // logical read addresses val raddr0=Input(UInt(5.W)) // logical read addresses
val raddr1=Input(UInt(5.W)) val raddr1=Input(UInt(5.W))
val wen0=Input(UInt(1.W)) // write enable val wen0=Input(UInt(1.W)) // write enable
val waddr0=Input(UInt(5.W)) // write address val waddr0=Input(UInt(5.W)) // write address
val wd0=Input(UInt(32.W)) // write data val wd0=Input(UInt(32.W)) // write data
val wen1=Input(UInt(1.W)) // write enable val wen1=Input(UInt(1.W)) // write enable
val waddr1=Input(UInt(5.W)) // write address val waddr1=Input(UInt(5.W)) // write address
val wd1=Input(UInt(32.W)) // write data val wd1=Input(UInt(32.W)) // write data
val wen2=Input(UInt(1.W)) // write enable val wen2=Input(UInt(1.W)) // write enable
val waddr2=Input(UInt(5.W)) // write address val waddr2=Input(UInt(5.W)) // write address
val wd2=Input(UInt(32.W)) // write data val wd2=Input(UInt(32.W)) // write data
val rd0=Output(UInt(32.W)) // read data // val gpr_i0_rs1_d=Output(UInt(32.W)) // read data
val rd1=Output(UInt(32.W)) // val gpr_i0_rs2_d=Output(UInt(32.W))
val scan_mode=Input(Bool()) val scan_mode=Input(Bool())
val gpr_exu = Flipped(new gpr_exu)
} }
object gpr_gen extends App{ object gpr_gen extends App{
println(chisel3.Driver.emitVerilog(new el2_dec_gpr_ctl)) println(chisel3.Driver.emitVerilog(new el2_dec_gpr_ctl))
} }

59
src/main/scala/dec/el2_dec_ib_ctl.scala
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@ -2,19 +2,21 @@ package dec
import include._ import include._
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import exu._
import ifu.aln_ib
import lib._ import lib._
class el2_dec_ib_ctl extends Module with param{ class el2_dec_ib_ctl extends Module with param{
val io=IO(new el2_dec_ib_ctl_IO) val io=IO(new el2_dec_ib_ctl_IO)
io.dec_i0_icaf_f1_d :=io.ifu_i0_icaf_f1 io.dec_i0_icaf_f1_d :=io.ifu_ib.ifu_i0_icaf_f1
io.dec_i0_dbecc_d :=io.ifu_i0_dbecc io.dec_i0_dbecc_d :=io.ifu_ib.ifu_i0_dbecc
io.dec_i0_icaf_d :=io.ifu_i0_icaf io.dec_i0_icaf_d :=io.ifu_ib.ifu_i0_icaf
io.dec_i0_pc_d :=io.ifu_i0_pc io.ib_exu.dec_i0_pc_d :=io.ifu_ib.ifu_i0_pc
io.dec_i0_pc4_d :=io.ifu_i0_pc4 io.dec_i0_pc4_d :=io.ifu_ib.ifu_i0_pc4
io.dec_i0_icaf_type_d :=io.ifu_i0_icaf_type io.dec_i0_icaf_type_d :=io.ifu_ib.ifu_i0_icaf_type
io.dec_i0_brp :=io.i0_brp io.dec_i0_brp :=io.ifu_ib.i0_brp
io.dec_i0_bp_index :=io.ifu_i0_bp_index io.dec_i0_bp_index :=io.ifu_ib.ifu_i0_bp_index
io.dec_i0_bp_fghr :=io.ifu_i0_bp_fghr io.dec_i0_bp_fghr :=io.ifu_ib.ifu_i0_bp_fghr
io.dec_i0_bp_btag :=io.ifu_i0_bp_btag io.dec_i0_bp_btag :=io.ifu_ib.ifu_i0_bp_btag
// GPR accesses // GPR accesses
// put reg to read on rs1 // put reg to read on rs1
@ -41,45 +43,36 @@ class el2_dec_ib_ctl extends Module with param{
val dcsr = io.dbg_cmd_addr(11,0) val dcsr = io.dbg_cmd_addr(11,0)
val ib0_debug_in =Mux1H(Seq( val ib0_debug_in =Mux1H(Seq(
debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U), debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U),
debug_write_gpr.asBool -> Cat("b00000000000000000110".U,dreg,"b0110011".U), debug_write_gpr.asBool -> Cat("b00000000000000000110".U(20.W),dreg,"b0110011".U(7.W)),
debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U), debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U(20.W)),
debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U) debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U(20.W))
)) ))
// machine is in halted state, pipe empty, write will always happen next cycle // machine is in halted state, pipe empty, write will always happen next cycle
io.dec_debug_wdata_rs1_d := debug_write_gpr | debug_write_csr io.ib_exu.dec_debug_wdata_rs1_d := debug_write_gpr | debug_write_csr
// special fence csr for use only in debug mode // special fence csr for use only in debug mode
io.dec_debug_fence_d := debug_write_csr & (dcsr === 0x7C4.U) io.dec_debug_fence_d := debug_write_csr & (dcsr === 0x7C4.U)
io.dec_ib0_valid_d := io.ifu_i0_valid | debug_valid io.dec_ib0_valid_d := io.ifu_ib.ifu_i0_valid | debug_valid
io.dec_i0_instr_d := Mux(debug_valid.asBool,ib0_debug_in,io.ifu_i0_instr) io.dec_i0_instr_d := Mux(debug_valid.asBool,ib0_debug_in,io.ifu_ib.ifu_i0_instr)
} }
class el2_dec_ib_ctl_IO extends Bundle with param{ class el2_dec_ib_ctl_IO extends Bundle with param{
val dbg_cmd_valid =Input(UInt(1.W)) // valid dbg cmd val dbg_cmd_valid =Input(UInt(1.W)) // valid dbg cmd
val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write
val dbg_cmd_type =Input(UInt(2.W)) // dbg type val dbg_cmd_type =Input(UInt(2.W)) // dbg type
val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0 val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0
val i0_brp =Flipped(Valid(new el2_br_pkt_t)) // i0 branch packet from aligner val ifu_ib = Flipped(new aln_ib)
val ifu_i0_bp_index =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size) val ib_exu = Flipped(new ib_exu)
val ifu_i0_bp_fghr =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR
val ifu_i0_bp_btag =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag
val ifu_i0_pc4 =Input(UInt(1.W)) // i0 is 4B inst else 2B
val ifu_i0_valid =Input(UInt(1.W)) // i0 valid from ifu
val ifu_i0_icaf =Input(UInt(1.W)) // i0 instruction access fault
val ifu_i0_icaf_type =Input(UInt(2.W)) // i0 instruction access fault type
val ifu_i0_icaf_f1 =Input(UInt(1.W)) // i0 has access fault on second fetch group
val ifu_i0_dbecc =Input(UInt(1.W)) // i0 double-bit error
val ifu_i0_instr =Input(UInt(32.W)) // i0 instruction from the aligner
val ifu_i0_pc =Input(UInt(31.W)) // i0 pc from the aligner
val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid
val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type
val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode
val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode // val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode
val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B
val dec_i0_brp =Valid(new el2_br_pkt_t) // i0 branch packet at decode val dec_i0_brp =Valid(new el2_br_pkt_t) // i0 branch packet at decode
val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
@ -88,9 +81,9 @@ class el2_dec_ib_ctl_IO extends Bundle with param{
val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode
val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group
val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode
val dec_debug_wdata_rs1_d =Output(UInt(1.W)) // put debug write data onto rs1 source: machine is halted // val dec_debug_wdata_rs1_d =Output(UInt(1.W)) // put debug write data onto rs1 source: machine is halted
val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst
} }
object ib_gen extends App{ object ib_gen extends App{
println(chisel3.Driver.emitVerilog(new el2_dec_ib_ctl)) chisel3.Driver.emitVerilog(new el2_dec_ib_ctl)
} }

4629
src/main/scala/dec/el2_dec_tlu_ctl.scala
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File diff suppressed because it is too large Load Diff

2
src/main/scala/dec/el2_dec_trigger.scala
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@ -16,5 +16,5 @@ class el2_dec_trigger extends Module with el2_lib {
} }
object dec_trig extends App { object dec_trig extends App {
println(chisel3.Driver.emitVerilog(new el2_dec_trigger)) chisel3.Driver execute(args, () => new el2_dec_trigger())
} }

13
src/main/scala/dec/test.scala Normal file
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@ -0,0 +1,13 @@
package dec
import chisel3._
import chisel3.util._
class test extends Module{
val io = IO(new Bundle{
val in = Input(UInt(3.W))
val out = Output(UInt())
})
io.out := Cat(io.in, "b100000000000010101".U)
}
object test extends App{
println(chisel3.Driver.emitVerilog(new test))
}

69
src/main/scala/el2_dma_ctrl.scala
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@ -2,6 +2,7 @@ import chisel3._
import chisel3.util._ import chisel3.util._
import scala.collection._ import scala.collection._
import lib._ import lib._
import lsu._
class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset { class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle { val io = IO(new Bundle {
@ -9,6 +10,7 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
val dma_bus_clk_en = Input(Bool()) // slave bus clock enable val dma_bus_clk_en = Input(Bool()) // slave bus clock enable
val clk_override = Input(Bool()) val clk_override = Input(Bool())
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val lsu_dma = Flipped(new lsu_dma)
// Debug signals // Debug signals
val dbg_cmd_addr = Input(UInt(32.W)) val dbg_cmd_addr = Input(UInt(32.W))
@ -25,17 +27,17 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
val dma_dbg_rddata = Output(UInt(32.W)) val dma_dbg_rddata = Output(UInt(32.W))
// Core side signals // Core side signals
val dma_dccm_req = Output(Bool()) // DMA dccm request (only one of dccm/iccm will be set) // val dma_dccm_req = Output(Bool()) // DMA dccm request (only one of dccm/iccm will be set)
val dma_iccm_req = Output(Bool()) // DMA iccm request val dma_iccm_req = Output(Bool()) // DMA iccm request
val dma_mem_tag = Output(UInt(3.W)) // DMA Buffer entry number // val dma_mem_tag = Output(UInt(3.W)) // DMA Buffer entry number
val dma_mem_addr = Output(UInt(32.W))// DMA request address // val dma_mem_addr = Output(UInt(32.W))// DMA request address
val dma_mem_sz = Output(UInt(3.W)) // DMA request size // val dma_mem_sz = Output(UInt(3.W)) // DMA request size
val dma_mem_write = Output(Bool()) // DMA write to dccm/iccm // val dma_mem_write = Output(Bool()) // DMA write to dccm/iccm
val dma_mem_wdata = Output(UInt(64.W))// DMA write data // val dma_mem_wdata = Output(UInt(64.W))// DMA write data
val dccm_dma_rvalid = Input(Bool()) // dccm data valid for DMA read // val dccm_dma_rvalid = Input(Bool()) // dccm data valid for DMA read
val dccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read // val dccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read
val dccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req // val dccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req
val dccm_dma_rdata = Input(UInt(64.W)) // dccm data for DMA read // val dccm_dma_rdata = Input(UInt(64.W)) // dccm data for DMA read
val iccm_dma_rvalid = Input(Bool()) // iccm data valid for DMA read val iccm_dma_rvalid = Input(Bool()) // iccm data valid for DMA read
val iccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read val iccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read
val iccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req val iccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req
@ -43,7 +45,7 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
val dma_dccm_stall_any = Output(Bool()) // stall dccm pipe (bubble) so that DMA can proceed val dma_dccm_stall_any = Output(Bool()) // stall dccm pipe (bubble) so that DMA can proceed
val dma_iccm_stall_any = Output(Bool()) // stall iccm pipe (bubble) so that DMA can proceed val dma_iccm_stall_any = Output(Bool()) // stall iccm pipe (bubble) so that DMA can proceed
val dccm_ready = Input(Bool()) // dccm ready to accept DMA request // val dccm_ready = Input(Bool()) // dccm ready to accept DMA request
val iccm_ready = Input(Bool()) // iccm ready to accept DMA request val iccm_ready = Input(Bool()) // iccm ready to accept DMA request
val dec_tlu_dma_qos_prty = Input(UInt(3.W)) // DMA QoS priority coming from MFDC [18:15] val dec_tlu_dma_qos_prty = Input(UInt(3.W)) // DMA QoS priority coming from MFDC [18:15]
@ -261,23 +263,23 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
fifo_cmd_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent.asBool & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1).asBool)) & (i.U === WrPtr)).asUInt).reverse.reduce(Cat(_,_)) fifo_cmd_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent.asBool & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1).asBool)) & (i.U === WrPtr)).asUInt).reverse.reduce(Cat(_,_))
fifo_data_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1) & io.dbg_cmd_write)) & (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) | (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).reverse.reduce(Cat(_,_)) fifo_data_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1) & io.dbg_cmd_write)) & (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) | (io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).reverse.reduce(Cat(_,_))
fifo_pend_en := (0 until DMA_BUF_DEPTH).map(i => ((io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_)) fifo_pend_en := (0 until DMA_BUF_DEPTH).map(i => ((io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
fifo_error_en := (0 until DMA_BUF_DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) & (i.U === RdPtr)) | ((io.dccm_dma_rvalid & io.dccm_dma_ecc_error) & (i.U === io.dccm_dma_rtag)) | ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_)) fifo_error_en := (0 until DMA_BUF_DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) & (i.U === RdPtr)) | ((io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
fifo_error_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((((fifo_error_in(i)(1,0).orR) & fifo_error_en(i)) | (fifo_error(i).orR)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_)) fifo_error_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((((fifo_error_in(i)(1,0).orR) & fifo_error_en(i)) | (fifo_error(i).orR)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
fifo_done_en := (0 until DMA_BUF_DEPTH).map(i => (((fifo_error(i).orR | fifo_error_en(i) | ((io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write)) & (i.U === RdPtr)) | (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_)) fifo_done_en := (0 until DMA_BUF_DEPTH).map(i => (((fifo_error(i).orR | fifo_error_en(i) | ((io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write)) & (i.U === RdPtr)) | (io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
fifo_done_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_)) fifo_done_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
fifo_reset := (0 until DMA_BUF_DEPTH).map(i => ((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr))).reverse.reduce(Cat(_,_)) fifo_reset := (0 until DMA_BUF_DEPTH).map(i => ((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr))).reverse.reduce(Cat(_,_))
(0 until DMA_BUF_DEPTH).map(i => fifo_error_in(i) := (Mux(io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag), Cat(0.U, io.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), (Cat(0.U, io.iccm_dma_ecc_error)), (Cat((dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error)))))) (0 until DMA_BUF_DEPTH).map(i => fifo_error_in(i) := (Mux(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag), Cat(0.U, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), (Cat(0.U, io.iccm_dma_ecc_error)), (Cat((dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error))))))
(0 until DMA_BUF_DEPTH).map(i => fifo_data_in(i) := (Mux(fifo_error_en(i) & (fifo_error_in(i).orR), Cat(Fill(32, 0.U), fifo_addr(i)), Mux(io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag), io.dccm_dma_rdata, Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), io.iccm_dma_rdata, Mux(io.dbg_cmd_valid, Fill(2, io.dbg_cmd_wrdata), bus_cmd_wdata(63,0))))))) (0 until DMA_BUF_DEPTH).map(i => fifo_data_in(i) := (Mux(fifo_error_en(i) & (fifo_error_in(i).orR), Cat(Fill(32, 0.U), fifo_addr(i)), Mux(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag), io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), io.iccm_dma_rdata, Mux(io.dbg_cmd_valid, Fill(2, io.dbg_cmd_wrdata), bus_cmd_wdata(63,0)))))))
fifo_valid := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_cmd_en(i), 1.U, fifo_valid(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_)) fifo_valid := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_cmd_en(i), 1.U, fifo_valid(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
@ -321,7 +323,7 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
val WrPtrEn = fifo_cmd_en.orR val WrPtrEn = fifo_cmd_en.orR
val RdPtrEn = (io.dma_dccm_req | io.dma_iccm_req | (dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error)) val RdPtrEn = (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.dma_iccm_req | (dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error))
val RspPtrEn = (io.dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) val RspPtrEn = (io.dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en)
@ -362,12 +364,12 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
((dma_mem_sz_int(2,0) === 2.U) & (dma_mem_addr_int(1, 0).orR)) | // W size but unaligned ((dma_mem_sz_int(2,0) === 2.U) & (dma_mem_addr_int(1, 0).orR)) | // W size but unaligned
((dma_mem_sz_int(2,0) === 3.U) & (dma_mem_addr_int(2, 0).orR)) | // DW size but unaligned ((dma_mem_sz_int(2,0) === 3.U) & (dma_mem_addr_int(2, 0).orR)) | // DW size but unaligned
(dma_mem_addr_in_iccm & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt ) | // ICCM access not word size (dma_mem_addr_in_iccm & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt ) | // ICCM access not word size
(dma_mem_addr_in_dccm & io.dma_mem_write & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt) | // DCCM write not word size (dma_mem_addr_in_dccm & io.lsu_dma.dma_lsc_ctl.dma_mem_write & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt) | // DCCM write not word size
(io.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)), (io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)),
(dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)), (dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)),
(dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)), (dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)),
(dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)))) =/= 15.U)) | // Write byte enables not aligned for word store (dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)))) =/= 15.U)) | // Write byte enables not aligned for word store
(io.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store (io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store
//Dbg outputs //Dbg outputs
@ -390,7 +392,7 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
// Nack counter, stall the lsu pipe if 7 nacks // Nack counter, stall the lsu pipe if 7 nacks
dma_nack_count_csr := io.dec_tlu_dma_qos_prty dma_nack_count_csr := io.dec_tlu_dma_qos_prty
val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.dma_dccm_req | io.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.dma_dccm_req | io.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U)) val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U))
dma_nack_count := withClock(dma_free_clk) { dma_nack_count := withClock(dma_free_clk) {
RegEnable(dma_nack_count_d(2,0), 0.U, dma_mem_req.asBool) RegEnable(dma_nack_count_d(2,0), 0.U, dma_mem_req.asBool)
@ -399,23 +401,23 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
// Core outputs // Core outputs
dma_mem_req := fifo_valid(RdPtr) & !fifo_rpend(RdPtr) & !fifo_done(RdPtr) & !(dma_address_error | dma_alignment_error | dma_dbg_cmd_error) dma_mem_req := fifo_valid(RdPtr) & !fifo_rpend(RdPtr) & !fifo_done(RdPtr) & !(dma_address_error | dma_alignment_error | dma_dbg_cmd_error)
io.dma_dccm_req := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & io.dccm_ready; io.lsu_dma.dma_lsc_ctl.dma_dccm_req := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & io.lsu_dma.dccm_ready;
io.dma_iccm_req := dma_mem_req & dma_mem_addr_in_iccm & io.iccm_ready; io.dma_iccm_req := dma_mem_req & dma_mem_addr_in_iccm & io.iccm_ready;
io.dma_mem_tag := RdPtr io.lsu_dma.dma_mem_tag := RdPtr
dma_mem_addr_int := fifo_addr(RdPtr) dma_mem_addr_int := fifo_addr(RdPtr)
dma_mem_sz_int := fifo_sz(RdPtr) dma_mem_sz_int := fifo_sz(RdPtr)
io.dma_mem_addr := Mux(io.dma_mem_write & (dma_mem_byteen(7,0) === "hf0".U), Cat(dma_mem_addr_int(31, 3), 1.U, dma_mem_addr_int(1, 0)), dma_mem_addr_int(31,0)) io.lsu_dma.dma_lsc_ctl.dma_mem_addr := Mux(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_byteen(7,0) === "hf0".U), Cat(dma_mem_addr_int(31, 3), 1.U, dma_mem_addr_int(1, 0)), dma_mem_addr_int(31,0))
io.dma_mem_sz := Mux(io.dma_mem_write & ((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U)), 2.U, dma_mem_sz_int(2,0)) io.lsu_dma.dma_lsc_ctl.dma_mem_sz := Mux(io.lsu_dma.dma_lsc_ctl.dma_mem_write & ((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U)), 2.U, dma_mem_sz_int(2,0))
dma_mem_byteen := fifo_byteen(RdPtr) dma_mem_byteen := fifo_byteen(RdPtr)
io.dma_mem_write := fifo_write(RdPtr) io.lsu_dma.dma_lsc_ctl.dma_mem_write := fifo_write(RdPtr)
io.dma_mem_wdata := fifo_data(RdPtr) io.lsu_dma.dma_lsc_ctl.dma_mem_wdata := fifo_data(RdPtr)
// PMU outputs // PMU outputs
io.dma_pmu_dccm_read := io.dma_dccm_req & !io.dma_mem_write; io.dma_pmu_dccm_read := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
io.dma_pmu_dccm_write := io.dma_dccm_req & io.dma_mem_write; io.dma_pmu_dccm_write := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write
io.dma_pmu_any_read := (io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write; io.dma_pmu_any_read := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
io.dma_pmu_any_write := (io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write; io.dma_pmu_any_write := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write
// Inputs // Inputs
@ -550,6 +552,9 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
bus_posted_write_done := 0.U bus_posted_write_done := 0.U
bus_rsp_valid := (io.dma_axi_bvalid | io.dma_axi_rvalid) bus_rsp_valid := (io.dma_axi_bvalid | io.dma_axi_rvalid)
bus_rsp_sent := ((io.dma_axi_bvalid & io.dma_axi_bready) | (io.dma_axi_rvalid & io.dma_axi_rready)) bus_rsp_sent := ((io.dma_axi_bvalid & io.dma_axi_bready) | (io.dma_axi_rvalid & io.dma_axi_rready))
io.lsu_dma.dma_dccm_ctl.dma_mem_addr := io.lsu_dma.dma_lsc_ctl.dma_mem_addr
io.lsu_dma.dma_dccm_ctl.dma_mem_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata
} }
object dma extends App{ object dma extends App{
println(chisel3.Driver.emitVerilog(new el2_dma_ctrl)) println(chisel3.Driver.emitVerilog(new el2_dma_ctrl))

36
src/main/scala/el2_mem.scala
View File

@ -2,21 +2,37 @@ package el2_mem
import chisel3._ import chisel3._
import chisel3.util.HasBlackBoxResource import chisel3.util.HasBlackBoxResource
import lib._ import lib._
class mem_lsu extends Bundle with el2_lib{
val dccm_wren = Input(Bool())
val dccm_rden = Input(Bool())
val dccm_wr_addr_lo = Input(UInt(DCCM_BITS.W))
val dccm_wr_addr_hi = Input(UInt(DCCM_BITS.W))
val dccm_rd_addr_lo = Input(UInt(DCCM_BITS.W))
val dccm_rd_addr_hi = Input(UInt(DCCM_BITS.W))
val dccm_wr_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
val dccm_wr_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
}
class Mem_bundle extends Bundle with el2_lib { class Mem_bundle extends Bundle with el2_lib {
val clk = Input(Clock()) val clk = Input(Clock())
val rst_l = Input(AsyncReset()) val rst_l = Input(AsyncReset())
val dccm_clk_override = Input(Bool()) val dccm_clk_override = Input(Bool())
val icm_clk_override = Input(Bool()) val icm_clk_override = Input(Bool())
val dec_tlu_core_ecc_disable = Input(Bool()) val dec_tlu_core_ecc_disable = Input(Bool())
val dccm_wren = Input(Bool()) val mem_lsu = new mem_lsu
val dccm_rden = Input(Bool()) // val dccm_wren = Input(Bool())
val dccm_wr_addr_lo = Input(UInt(DCCM_BITS.W)) // val dccm_rden = Input(Bool())
val dccm_wr_addr_hi = Input(UInt(DCCM_BITS.W)) // val dccm_wr_addr_lo = Input(UInt(DCCM_BITS.W))
val dccm_rd_addr_lo = Input(UInt(DCCM_BITS.W)) // val dccm_wr_addr_hi = Input(UInt(DCCM_BITS.W))
val dccm_rd_addr_hi = Input(UInt(DCCM_BITS.W)) // val dccm_rd_addr_lo = Input(UInt(DCCM_BITS.W))
val dccm_wr_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_rd_addr_hi = Input(UInt(DCCM_BITS.W))
val dccm_wr_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_wr_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_wr_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
// val dccm_rd_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
val iccm_rw_addr = Input(UInt((ICCM_BITS-1).W)) val iccm_rw_addr = Input(UInt((ICCM_BITS-1).W))
val iccm_buf_correct_ecc = Input(Bool()) val iccm_buf_correct_ecc = Input(Bool())
@ -44,7 +60,7 @@ class Mem_bundle extends Bundle with el2_lib {
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val iccm_rd_data_ecc = Output(UInt(78.W)) val iccm_rd_data_ecc = Output(UInt(78.W))
val dccm_rd_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_rd_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
val ic_rd_data = Output(UInt(64.W)) val ic_rd_data = Output(UInt(64.W))
val ictag_debug_rd_data = Output(UInt(26.W)) val ictag_debug_rd_data = Output(UInt(26.W))
val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W)) val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W))

38
src/main/scala/el2_pic_ctl.scala
View File

@ -2,6 +2,7 @@ import chisel3._
import chisel3.util._ import chisel3.util._
import include._ import include._
import lib._ import lib._
import lsu._
import chisel3.experimental.chiselName import chisel3.experimental.chiselName
@chiselName @chiselName
class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib { class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib {
@ -11,19 +12,20 @@ class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib {
val active_clk = Input(Clock () ) val active_clk = Input(Clock () )
val clk_override = Input(Bool () ) val clk_override = Input(Bool () )
val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W)) val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W))
val picm_rdaddr = Input(UInt(32.W)) val lsu_pic = Flipped(new lsu_pic)
val picm_wraddr = Input(UInt(32.W)) // val picm_rdaddr = Input(UInt(32.W))
val picm_wr_data = Input(UInt(32.W)) // val picm_wraddr = Input(UInt(32.W))
val picm_wren = Input(Bool()) // val picm_wr_data = Input(UInt(32.W))
val picm_rden = Input(Bool()) // val picm_wren = Input(Bool())
val picm_mken = Input(Bool()) // val picm_rden = Input(Bool())
val meicurpl = Input(UInt(4.W)) // val picm_mken = Input(Bool())
val meipt = Input(UInt(4.W)) val meicurpl = Input(UInt(4.W))
val meipt = Input(UInt(4.W))
val mexintpend = Output(Bool()) val mexintpend = Output(Bool())
val claimid = Output(UInt(8.W)) val claimid = Output(UInt(8.W))
val pl = Output(UInt(4.W)) val pl = Output(UInt(4.W))
val picm_rd_data = Output(UInt(32.W)) // val picm_rd_data = Output(UInt(32.W))
val mhwakeup = Output(Bool()) val mhwakeup = Output(Bool())
//val level_intpend_w_prior_en = Output(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(INTPRIORITY_BITS.W)))) //val level_intpend_w_prior_en = Output(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(INTPRIORITY_BITS.W))))
@ -104,12 +106,12 @@ class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib {
val pic_int_c1_clk = Wire(Clock()) val pic_int_c1_clk = Wire(Clock())
val gw_config_c1_clk = Wire(Clock()) val gw_config_c1_clk = Wire(Clock())
withClock(pic_raddr_c1_clk) {picm_raddr_ff := RegNext(io.picm_rdaddr,0.U)} withClock(pic_raddr_c1_clk) {picm_raddr_ff := RegNext(io.lsu_pic.picm_rdaddr,0.U)}
withClock(pic_data_c1_clk) {picm_waddr_ff := RegNext (io.picm_wraddr,0.U)} withClock(pic_data_c1_clk) {picm_waddr_ff := RegNext (io.lsu_pic.picm_wraddr,0.U)}
withClock(io.active_clk) {picm_wren_ff := RegNext(io.picm_wren,0.U)} withClock(io.active_clk) {picm_wren_ff := RegNext(io.lsu_pic.picm_wren,0.U)}
withClock(io.active_clk) {picm_rden_ff := RegNext(io.picm_rden,0.U)} withClock(io.active_clk) {picm_rden_ff := RegNext(io.lsu_pic.picm_rden,0.U)}
withClock(io.active_clk) {picm_mken_ff := RegNext(io.picm_mken,0.U)} withClock(io.active_clk) {picm_mken_ff := RegNext(io.lsu_pic.picm_mken,0.U)}
withClock(pic_data_c1_clk) {picm_wr_data_ff := RegNext(io.picm_wr_data,0.U)} withClock(pic_data_c1_clk) {picm_wr_data_ff := RegNext(io.lsu_pic.picm_wr_data,0.U)}
val temp_raddr_intenable_base_match = ~(picm_raddr_ff ^ INTENABLE_BASE_ADDR.asUInt) val temp_raddr_intenable_base_match = ~(picm_raddr_ff ^ INTENABLE_BASE_ADDR.asUInt)
val raddr_intenable_base_match = temp_raddr_intenable_base_match(31,NUM_LEVELS+2).andR//// (31,NUM_LEVELS+2) val raddr_intenable_base_match = temp_raddr_intenable_base_match(31,NUM_LEVELS+2).andR//// (31,NUM_LEVELS+2)
@ -128,8 +130,8 @@ class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib {
// ---- Clock gating section ------ // ---- Clock gating section ------
// c1 clock enables // c1 clock enables
val pic_raddr_c1_clken = io.picm_mken | io.picm_rden | io.clk_override val pic_raddr_c1_clken = io.lsu_pic.picm_mken | io.lsu_pic.picm_rden | io.clk_override
val pic_data_c1_clken = io.picm_wren | io.clk_override val pic_data_c1_clken = io.lsu_pic.picm_wren | io.clk_override
val pic_pri_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intpriority_base_match & picm_rden_ff) | io.clk_override val pic_pri_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intpriority_base_match & picm_rden_ff) | io.clk_override
val pic_int_c1_clken = (waddr_intenable_base_match & picm_wren_ff) | (raddr_intenable_base_match & picm_rden_ff) | io.clk_override val pic_int_c1_clken = (waddr_intenable_base_match & picm_wren_ff) | (raddr_intenable_base_match & picm_rden_ff) | io.clk_override
val gw_config_c1_clken = (waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff) | io.clk_override val gw_config_c1_clken = (waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff) | io.clk_override
@ -308,7 +310,7 @@ class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib {
(picm_mken_ff & mask(0)).asBool -> Fill(32,0.U) )) (picm_mken_ff & mask(0)).asBool -> Fill(32,0.U) ))
io.picm_rd_data := Mux(picm_bypass_ff.asBool, picm_wr_data_ff, picm_rd_data_in) io.lsu_pic.picm_rd_data := Mux(picm_bypass_ff.asBool, picm_wr_data_ff, picm_rd_data_in)
val address = picm_raddr_ff(14,0) val address = picm_raddr_ff(14,0)
mask := 1.U(4.W) mask := 1.U(4.W)

45
src/main/scala/el2_swerv.scala
View File

@ -7,6 +7,7 @@ import lsu._
import lib._ import lib._
import include._ import include._
import dbg._ import dbg._
import el2_mem._
class el2_swerv_bundle extends Bundle with el2_lib{ class el2_swerv_bundle extends Bundle with el2_lib{
val dbg_rst_l = Input(AsyncReset()) val dbg_rst_l = Input(AsyncReset())
val rst_vec = Input(UInt(31.W)) val rst_vec = Input(UInt(31.W))
@ -40,17 +41,18 @@ class el2_swerv_bundle extends Bundle with el2_lib{
val dec_tlu_perfcnt1 = Output(Bool()) val dec_tlu_perfcnt1 = Output(Bool())
val dec_tlu_perfcnt2 = Output(Bool()) val dec_tlu_perfcnt2 = Output(Bool())
val dec_tlu_perfcnt3 = Output(Bool()) val dec_tlu_perfcnt3 = Output(Bool())
val dccm_wren = Output(Bool()) val swerv_mem = Flipped(new mem_lsu)
val dccm_rden = Output(Bool()) // val dccm_wren = Output(Bool())
val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W)) // val dccm_rden = Output(Bool())
val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W)) // val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W)) // val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W)) // val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
// val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
val iccm_rw_addr = Output(UInt((ICCM_BITS-1).W)) val iccm_rw_addr = Output(UInt((ICCM_BITS-1).W))
val iccm_wren = Output(Bool()) val iccm_wren = Output(Bool())
@ -549,8 +551,8 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
lsu.io.dec_lsu_valid_raw_d := dec.io.dec_lsu_valid_raw_d lsu.io.dec_lsu_valid_raw_d := dec.io.dec_lsu_valid_raw_d
lsu.io.dec_tlu_mrac_ff := dec.io.dec_tlu_mrac_ff lsu.io.dec_tlu_mrac_ff := dec.io.dec_tlu_mrac_ff
lsu.io.trigger_pkt_any <> dec.io.trigger_pkt_any lsu.io.trigger_pkt_any <> dec.io.trigger_pkt_any
lsu.io.dccm_rd_data_lo := io.dccm_rd_data_lo // lsu.io.dccm_rd_data_lo := io.dccm_rd_data_lo
lsu.io.dccm_rd_data_hi := io.dccm_rd_data_hi // lsu.io.dccm_rd_data_hi := io.dccm_rd_data_hi
lsu.io.lsu_axi_awready := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_awready) lsu.io.lsu_axi_awready := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_awready)
lsu.io.lsu_axi_wready := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_wready) lsu.io.lsu_axi_wready := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_wready)
lsu.io.lsu_axi_bvalid := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_bvalid) lsu.io.lsu_axi_bvalid := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_bvalid)
@ -685,14 +687,17 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
io.dec_tlu_perfcnt2 := dec.io.dec_tlu_perfcnt2 io.dec_tlu_perfcnt2 := dec.io.dec_tlu_perfcnt2
io.dec_tlu_perfcnt3 := dec.io.dec_tlu_perfcnt3 io.dec_tlu_perfcnt3 := dec.io.dec_tlu_perfcnt3
// LSU Outputs // LSU Outputs
io.dccm_wren := lsu.io.dccm_wren io.swerv_mem <> lsu.io.lsu_mem
io.dccm_rden := lsu.io.dccm_rden // io.dccm_wren := lsu.io.dccm_wren
io.dccm_wr_addr_lo := lsu.io.dccm_wr_addr_lo // io.dccm_rden := lsu.io.dccm_rden
io.dccm_wr_addr_hi := lsu.io.dccm_wr_addr_hi // io.dccm_wr_addr_lo := lsu.io.dccm_wr_addr_lo
io.dccm_rd_addr_lo := lsu.io.dccm_rd_addr_lo // io.dccm_wr_addr_hi := lsu.io.dccm_wr_addr_hi
io.dccm_rd_addr_hi := lsu.io.dccm_rd_addr_hi // io.dccm_rd_addr_lo := lsu.io.dccm_rd_addr_lo
io.dccm_wr_data_lo := lsu.io.dccm_wr_data_lo // io.dccm_rd_addr_hi := lsu.io.dccm_rd_addr_hi
io.dccm_wr_data_hi := lsu.io.dccm_wr_data_hi // io.dccm_wr_data_lo := lsu.io.dccm_wr_data_lo
// io.dccm_wr_data_hi := lsu.io.dccm_wr_data_hi
// lsu.io.dccm_rd_data_lo := io.dccm_rd_data_lo
// lsu.io.dccm_rd_data_hi := io.dccm_rd_data_hi
// IFU Outputs // IFU Outputs
io.iccm_rw_addr := ifu.io.iccm_rw_addr io.iccm_rw_addr := ifu.io.iccm_rw_addr
io.iccm_wren := ifu.io.iccm_wren io.iccm_wren := ifu.io.iccm_wren

1409
src/main/scala/el2_swerv_wrapper.scala
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281
src/main/scala/exu/el2_exu.scala
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@ -5,70 +5,110 @@ import chisel3.util._
import include._ import include._
import lib._ import lib._
import chisel3.experimental.chiselName import chisel3.experimental.chiselName
import lsu._
@chiselName @chiselName
class dec_alu extends Bundle {
val dec_i0_alu_decode_d = Input(UInt(1.W)) // Valid
val dec_csr_ren_d = Input(Bool()) // extra decode
val dec_i0_br_immed_d = Input(UInt(12.W)) // Branch offset
val exu_flush_final = Output(UInt(1.W)) // Branch flush or flush entire pipeline
val exu_i0_pc_x = Output(UInt(31.W)) // flopped PC
}
class dec_div extends Bundle {
val div_p =Flipped(Valid(new el2_div_pkt_t)) // DEC {valid, unsigned, rem}
val dec_div_cancel =Input(UInt(1.W)) // Cancel the divide operation
}
class tlu_exu extends Bundle with el2_lib{
val dec_tlu_meihap =Input(UInt(30.W)) // External stall mux data
val dec_tlu_flush_lower_r =Input(UInt(1.W)) // Flush divide and secondary ALUs
val dec_tlu_flush_path_r =Input(UInt(31.W)) // Redirect target
val exu_i0_br_hist_r =Output(UInt(2.W)) // to DEC I0 branch history
val exu_i0_br_error_r =Output(UInt(1.W)) // to DEC I0 branch error
val exu_i0_br_start_error_r =Output(UInt(1.W)) // to DEC I0 branch start error
val exu_i0_br_index_r =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // to DEC I0 branch index
val exu_i0_br_valid_r =Output(UInt(1.W)) // to DEC I0 branch valid
val exu_i0_br_mp_r =Output(UInt(1.W)) // to DEC I0 branch mispredict
val exu_i0_br_middle_r =Output(UInt(1.W)) // to DEC I0 branch middle
val exu_pmu_i0_br_misp =Output(UInt(1.W)) // to PMU - I0 E4 branch mispredict
val exu_pmu_i0_br_ataken =Output(UInt(1.W)) // to PMU - I0 E4 taken
val exu_pmu_i0_pc4 =Output(UInt(1.W)) // to PMU - I0 E4 PC
val exu_npc_r =Output(UInt(31.W)) // Divide NPC
}
class ib_exu extends Bundle {
val dec_i0_pc_d =Input(UInt(31.W)) // Instruction PC
val dec_debug_wdata_rs1_d =Input(UInt(1.W)) // Debug select to primary I0 RS1
}
class gpr_exu extends Bundle{
val gpr_i0_rs1_d =Input(UInt(32.W)) // DEC data gpr
val gpr_i0_rs2_d =Input(UInt(32.W)) // DEC data gpr
}
class decode_exu extends Bundle with el2_lib{
val dec_data_en =Input(UInt(2.W)) // Clock enable {x,r}, one cycle pulse
val dec_ctl_en =Input(UInt(2.W)) // Clock enable {x,r}, two cycle pulse
val i0_ap =Input(new el2_alu_pkt_t) // DEC alu {valid,predecodes}
val dec_i0_predict_p_d =Flipped(Valid(new el2_predict_pkt_t)) // DEC branch predict packet
val i0_predict_fghr_d =Input(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr
val i0_predict_index_d =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // DEC predict index
val i0_predict_btag_d =Input(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag
val dec_i0_rs1_en_d =Input(UInt(1.W)) // Qualify GPR RS1 data
val dec_i0_rs2_en_d =Input(UInt(1.W)) // Qualify GPR RS2 data
val dec_i0_immed_d =Input(UInt(32.W)) // DEC data immediate
val dec_i0_rs1_bypass_data_d=Input(UInt(32.W)) // DEC bypass data
val dec_i0_rs2_bypass_data_d=Input(UInt(32.W)) // DEC bypass data
val dec_i0_select_pc_d =Input(UInt(1.W)) // PC select to RS1
val dec_i0_rs1_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
val dec_i0_rs2_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
val mul_p =Flipped(Valid(new el2_mul_pkt_t)) // DEC {valid, operand signs, low, operand bypass}
val pred_correct_npc_x =Input(UInt(31.W)) // DEC NPC for correctly predicted branch
val dec_extint_stall =Input(Bool()) // External stall mux select
val exu_i0_result_x =Output(UInt(32.W)) // Primary ALU result to DEC
val exu_csr_rs1_x =Output(UInt(32.W)) // RS1 source for a CSR instruction
}
class dec_exu extends Bundle with el2_lib{
val dec_alu = new dec_alu
val dec_div = new dec_div
val decode_exu = new decode_exu
val tlu_exu = new tlu_exu
val ib_exu = new ib_exu
val gpr_exu = new gpr_exu
// val gpr_div = new gpr_div
//////////////////
}
class el2_exu extends Module with el2_lib with RequireAsyncReset{ class el2_exu extends Module with el2_lib with RequireAsyncReset{
val io=IO(new Bundle{ val io=IO(new Bundle{
val scan_mode =Input(Bool()) // Scan control val dec_exu = new dec_exu
val dec_data_en =Input(UInt(2.W)) // Clock enable {x,r}, one cycle pulse val exu_div_result =Output(UInt(32.W)) // Divide result
val dec_ctl_en =Input(UInt(2.W)) // Clock enable {x,r}, two cycle pulse val exu_div_wren =Output(UInt(1.W)) // Divide write enable to GPR
val dbg_cmd_wrdata =Input(UInt(32.W)) // Debug data to primary I0 RS1
val i0_ap =Input(new el2_alu_pkt_t) // DEC alu {valid,predecodes}
val dec_debug_wdata_rs1_d =Input(UInt(1.W)) // Debug select to primary I0 RS1
val dec_i0_predict_p_d =Flipped(Valid(new el2_predict_pkt_t)) // DEC branch predict packet
val i0_predict_fghr_d =Input(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr
val i0_predict_index_d =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // DEC predict index
val i0_predict_btag_d =Input(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag
val dec_i0_rs1_en_d =Input(UInt(1.W)) // Qualify GPR RS1 data
val dec_i0_rs2_en_d =Input(UInt(1.W)) // Qualify GPR RS2 data
val gpr_i0_rs1_d =Input(UInt(32.W)) // DEC data gpr
val gpr_i0_rs2_d =Input(UInt(32.W)) // DEC data gpr
val dec_i0_immed_d =Input(UInt(32.W)) // DEC data immediate
val dec_i0_rs1_bypass_data_d=Input(UInt(32.W)) // DEC bypass data
val dec_i0_rs2_bypass_data_d=Input(UInt(32.W)) // DEC bypass data
val dec_i0_br_immed_d =Input(UInt(12.W)) // Branch immediate
val dec_i0_alu_decode_d =Input(UInt(1.W)) // Valid to X-stage ALU
val dec_i0_select_pc_d =Input(UInt(1.W)) // PC select to RS1
val dec_i0_pc_d =Input(UInt(31.W)) // Instruction PC
val dec_i0_rs1_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
val dec_i0_rs2_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
val dec_csr_ren_d =Input(UInt(1.W)) // Clear I0 RS1 primary
val mul_p =Flipped(Valid(new el2_mul_pkt_t)) // DEC {valid, operand signs, low, operand bypass}
val div_p =Flipped(Valid(new el2_div_pkt_t)) // DEC {valid, unsigned, rem}
val dec_div_cancel =Input(UInt(1.W)) // Cancel the divide operation
val pred_correct_npc_x =Input(UInt(31.W)) // DEC NPC for correctly predicted branch
val dec_tlu_flush_lower_r =Input(UInt(1.W)) // Flush divide and secondary ALUs
val dec_tlu_flush_path_r =Input(UInt(31.W)) // Redirect target
val dec_extint_stall =Input(UInt(1.W)) // External stall mux select
val dec_tlu_meihap =Input(UInt(30.W)) // External stall mux data
val exu_lsu_rs1_d =Output(UInt(32.W)) // LSU operand
val exu_lsu_rs2_d =Output(UInt(32.W)) // LSU operand
val exu_flush_final =Output(UInt(1.W)) // Pipe is being flushed this cycle
val exu_flush_path_final =Output(UInt(31.W)) // Target for the oldest flush source
val exu_i0_result_x =Output(UInt(32.W)) // Primary ALU result to DEC
val exu_i0_pc_x =Output(UInt(31.W)) // Primary PC result to DEC
val exu_csr_rs1_x =Output(UInt(32.W)) // RS1 source for a CSR instruction
val exu_npc_r =Output(UInt(31.W)) // Divide NPC
val exu_i0_br_hist_r =Output(UInt(2.W)) // to DEC I0 branch history
val exu_i0_br_error_r =Output(UInt(1.W)) // to DEC I0 branch error
val exu_i0_br_start_error_r =Output(UInt(1.W)) // to DEC I0 branch start error
val exu_i0_br_index_r =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // to DEC I0 branch index
val exu_i0_br_valid_r =Output(UInt(1.W)) // to DEC I0 branch valid
val exu_i0_br_mp_r =Output(UInt(1.W)) // to DEC I0 branch mispredict
val exu_i0_br_middle_r =Output(UInt(1.W)) // to DEC I0 branch middle
val exu_i0_br_fghr_r =Output(UInt(BHT_GHR_SIZE.W)) // to DEC I0 branch fghr val exu_i0_br_fghr_r =Output(UInt(BHT_GHR_SIZE.W)) // to DEC I0 branch fghr
val exu_i0_br_way_r =Output(UInt(1.W)) // to DEC I0 branch way val exu_i0_br_way_r =Output(UInt(1.W)) // to DEC I0 branch way
val scan_mode =Input(Bool()) // Scan control
val dbg_cmd_wrdata =Input(UInt(32.W)) // Debug data to primary I0 RS1
val lsu_exu = Flipped(new lsu_exu)
// val dec_i0_br_immed_d =Input(UInt(12.W)) // Branch immediate
// val dec_i0_alu_decode_d =Input(UInt(1.W)) // Valid to X-stage ALU
// val dec_csr_ren_d =Input(UInt(1.W)) // Clear I0 RS1 primary
// val exu_lsu_rs1_d =Output(UInt(32.W)) // LSU operand
// val exu_lsu_rs2_d =Output(UInt(32.W)) // LSU operand
// val exu_flush_final =Output(UInt(1.W)) // Pipe is being flushed this cycle
val exu_flush_path_final =Output(UInt(31.W)) // Target for the oldest flush source
// val exu_i0_pc_x =Output(UInt(31.W)) // Primary PC result to DEC
val exu_mp_pkt =Valid(new el2_predict_pkt_t) // Mispredict branch packet val exu_mp_pkt =Valid(new el2_predict_pkt_t) // Mispredict branch packet
val exu_mp_eghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict global history val exu_mp_eghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict global history
val exu_mp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict fghr val exu_mp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict fghr
val exu_mp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // Mispredict index val exu_mp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // Mispredict index
val exu_mp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // Mispredict btag val exu_mp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // Mispredict btag
val exu_pmu_i0_br_misp =Output(UInt(1.W)) // to PMU - I0 E4 branch mispredict
val exu_pmu_i0_br_ataken =Output(UInt(1.W)) // to PMU - I0 E4 taken
val exu_pmu_i0_pc4 =Output(UInt(1.W)) // to PMU - I0 E4 PC
val exu_div_result =Output(UInt(32.W)) // Divide result
val exu_div_wren =Output(UInt(1.W)) // Divide write enable to GPR
}) })
val PREDPIPESIZE = BTB_ADDR_HI - BTB_ADDR_LO + BHT_GHR_SIZE + BTB_BTAG_SIZE +1 val PREDPIPESIZE = BTB_ADDR_HI - BTB_ADDR_LO + BHT_GHR_SIZE + BTB_BTAG_SIZE +1
@ -96,15 +136,15 @@ class el2_exu extends Module with el2_lib with RequireAsyncReset{
io.exu_mp_pkt.valid :=0.U io.exu_mp_pkt.valid :=0.U
i0_pp_r.bits.toffset := 0.U i0_pp_r.bits.toffset := 0.U
val x_data_en = io.dec_data_en(1) val x_data_en = io.dec_exu.decode_exu.dec_data_en(1)
val r_data_en = io.dec_data_en(0) val r_data_en = io.dec_exu.decode_exu.dec_data_en(0)
val x_ctl_en = io.dec_ctl_en(1) val x_ctl_en = io.dec_exu.decode_exu.dec_ctl_en(1)
val r_ctl_en = io.dec_ctl_en(0) val r_ctl_en = io.dec_exu.decode_exu.dec_ctl_en(0)
val predpipe_d = Cat(io.i0_predict_fghr_d, io.i0_predict_index_d, io.i0_predict_btag_d) val predpipe_d = Cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d, io.dec_exu.decode_exu.i0_predict_btag_d)
val i0_flush_path_x =rvdffe(i0_flush_path_d,x_data_en.asBool,clock,io.scan_mode) val i0_flush_path_x =rvdffe(i0_flush_path_d,x_data_en.asBool,clock,io.scan_mode)
io.exu_csr_rs1_x :=rvdffe(csr_rs1_in_d,x_data_en.asBool,clock,io.scan_mode) io.dec_exu.decode_exu.exu_csr_rs1_x :=rvdffe(csr_rs1_in_d,x_data_en.asBool,clock,io.scan_mode)
i0_predict_p_x :=rvdffe(i0_predict_p_d,x_data_en.asBool,clock,io.scan_mode) i0_predict_p_x :=rvdffe(i0_predict_p_d,x_data_en.asBool,clock,io.scan_mode)
val predpipe_x =rvdffe(predpipe_d,x_data_en.asBool,clock,io.scan_mode) val predpipe_x =rvdffe(predpipe_d,x_data_en.asBool,clock,io.scan_mode)
val predpipe_r =rvdffe(predpipe_x ,r_data_en.asBool,clock,io.scan_mode) val predpipe_r =rvdffe(predpipe_x ,r_data_en.asBool,clock,io.scan_mode)
@ -114,150 +154,147 @@ class el2_exu extends Module with el2_lib with RequireAsyncReset{
val i0_taken_x =rvdffe(i0_taken_d ,x_ctl_en.asBool,clock,io.scan_mode) val i0_taken_x =rvdffe(i0_taken_d ,x_ctl_en.asBool,clock,io.scan_mode)
val i0_valid_x =rvdffe(i0_valid_d ,x_ctl_en.asBool,clock,io.scan_mode) val i0_valid_x =rvdffe(i0_valid_d ,x_ctl_en.asBool,clock,io.scan_mode)
i0_pp_r :=rvdffe(i0_predict_p_x,r_ctl_en.asBool,clock,io.scan_mode) i0_pp_r :=rvdffe(i0_predict_p_x,r_ctl_en.asBool,clock,io.scan_mode)
val pred_temp1 =rvdffe(io.pred_correct_npc_x(5,0) ,r_ctl_en.asBool,clock,io.scan_mode) val pred_temp1 =rvdffe(io.dec_exu.decode_exu.pred_correct_npc_x(5,0) ,r_ctl_en.asBool,clock,io.scan_mode)
val i0_pred_correct_upper_r =rvdffe(i0_pred_correct_upper_x ,r_ctl_en.asBool,clock,io.scan_mode) val i0_pred_correct_upper_r =rvdffe(i0_pred_correct_upper_x ,r_ctl_en.asBool,clock,io.scan_mode)
val i0_flush_path_upper_r =rvdffe(i0_flush_path_x ,r_data_en.asBool,clock,io.scan_mode) val i0_flush_path_upper_r =rvdffe(i0_flush_path_x ,r_data_en.asBool,clock,io.scan_mode)
val pred_temp2 =rvdffe(io.pred_correct_npc_x(30,6) ,r_data_en.asBool,clock,io.scan_mode) val pred_temp2 =rvdffe(io.dec_exu.decode_exu.pred_correct_npc_x(30,6) ,r_data_en.asBool,clock,io.scan_mode)
pred_correct_npc_r :=Cat(pred_temp2,pred_temp1) pred_correct_npc_r :=Cat(pred_temp2,pred_temp1)
when (BHT_SIZE.asUInt===32.U || BHT_SIZE.asUInt===64.U){ when (BHT_SIZE.asUInt===32.U || BHT_SIZE.asUInt===64.U){
ghr_d :=RegEnable(ghr_d_ns,0.U,data_gate_en.asBool) ghr_d :=RegEnable(ghr_d_ns,0.U,data_gate_en.asBool)
mul_valid_x :=RegEnable(io.mul_p.valid,0.U,data_gate_en.asBool) mul_valid_x :=RegEnable(io.dec_exu.decode_exu.mul_p.valid,0.U,data_gate_en.asBool)
flush_lower_ff :=RegEnable(io.dec_tlu_flush_lower_r,0.U,data_gate_en.asBool) flush_lower_ff :=RegEnable(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r,0.U,data_gate_en.asBool)
}.otherwise{ }.otherwise{
ghr_d :=rvdffe(ghr_d_ns ,data_gate_en.asBool,clock,io.scan_mode) ghr_d :=rvdffe(ghr_d_ns ,data_gate_en.asBool,clock,io.scan_mode)
mul_valid_x :=rvdffe(io.mul_p.valid ,data_gate_en.asBool,clock,io.scan_mode) mul_valid_x :=rvdffe(io.dec_exu.decode_exu.mul_p.valid ,data_gate_en.asBool,clock,io.scan_mode)
flush_lower_ff :=rvdffe(io.dec_tlu_flush_lower_r ,data_gate_en.asBool,clock,io.scan_mode) flush_lower_ff :=rvdffe(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r ,data_gate_en.asBool,clock,io.scan_mode)
} }
data_gate_en := (ghr_d_ns =/= ghr_d) | ( io.mul_p.valid =/= mul_valid_x) | ( io.dec_tlu_flush_lower_r =/= flush_lower_ff) data_gate_en := (ghr_d_ns =/= ghr_d) | ( io.dec_exu.decode_exu.mul_p.valid =/= mul_valid_x) | ( io.dec_exu.tlu_exu.dec_tlu_flush_lower_r =/= flush_lower_ff)
val i0_rs1_bypass_en_d = io.dec_i0_rs1_bypass_en_d(0) | io.dec_i0_rs1_bypass_en_d(1) val i0_rs1_bypass_en_d = io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(0) | io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(1)
val i0_rs2_bypass_en_d = io.dec_i0_rs2_bypass_en_d(0) | io.dec_i0_rs2_bypass_en_d(1) val i0_rs2_bypass_en_d = io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(0) | io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(1)
val i0_rs1_bypass_data_d = Mux1H(Seq( val i0_rs1_bypass_data_d = Mux1H(Seq(
io.dec_i0_rs1_bypass_en_d(0).asBool -> io.dec_i0_rs1_bypass_data_d, io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d,
io.dec_i0_rs1_bypass_en_d(1).asBool -> io.exu_i0_result_x io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(1).asBool -> io.dec_exu.decode_exu.exu_i0_result_x
)) ))
val i0_rs2_bypass_data_d = Mux1H(Seq( val i0_rs2_bypass_data_d = Mux1H(Seq(
io.dec_i0_rs2_bypass_en_d(0).asBool -> io.dec_i0_rs2_bypass_data_d, io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d,
io.dec_i0_rs2_bypass_en_d(1).asBool -> io.exu_i0_result_x io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(1).asBool -> io.dec_exu.decode_exu.exu_i0_result_x
)) ))
val i0_rs1_d = Mux1H(Seq( val i0_rs1_d = Mux1H(Seq(
i0_rs1_bypass_en_d.asBool -> i0_rs1_bypass_data_d, i0_rs1_bypass_en_d.asBool -> i0_rs1_bypass_data_d,
(!i0_rs1_bypass_en_d & io.dec_i0_select_pc_d).asBool -> Cat(io.dec_i0_pc_d,0.U(1.W)), (!i0_rs1_bypass_en_d & io.dec_exu.decode_exu.dec_i0_select_pc_d).asBool -> Cat(io.dec_exu.ib_exu.dec_i0_pc_d,0.U(1.W)),
(!i0_rs1_bypass_en_d & io.dec_debug_wdata_rs1_d).asBool -> io.dbg_cmd_wrdata, (!i0_rs1_bypass_en_d & io.dec_exu.ib_exu.dec_debug_wdata_rs1_d).asBool -> io.dbg_cmd_wrdata,
(!i0_rs1_bypass_en_d & !io.dec_debug_wdata_rs1_d & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d (!i0_rs1_bypass_en_d & !io.dec_exu.ib_exu.dec_debug_wdata_rs1_d & io.dec_exu.decode_exu.dec_i0_rs1_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d
)) ))
val i0_rs2_d = Mux1H(Seq( val i0_rs2_d = Mux1H(Seq(
(!i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d, (!i0_rs2_bypass_en_d & io.dec_exu.decode_exu.dec_i0_rs2_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d,
(!i0_rs2_bypass_en_d).asBool -> io.dec_i0_immed_d, (!i0_rs2_bypass_en_d).asBool -> io.dec_exu.decode_exu.dec_i0_immed_d,
(i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d (i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d
)) ))
dontTouch(i0_rs2_d) dontTouch(i0_rs2_d)
io.exu_lsu_rs1_d:=Mux1H(Seq( io.lsu_exu.exu_lsu_rs1_d:=Mux1H(Seq(
(!i0_rs1_bypass_en_d & !io.dec_extint_stall & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d, (!i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs1_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d,
(i0_rs1_bypass_en_d & !io.dec_extint_stall).asBool -> i0_rs1_bypass_data_d, (i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall).asBool -> i0_rs1_bypass_data_d,
(io.dec_extint_stall).asBool -> Cat(io.dec_tlu_meihap,0.U(2.W)) (io.dec_exu.decode_exu.dec_extint_stall).asBool -> Cat(io.dec_exu.tlu_exu.dec_tlu_meihap,0.U(2.W))
)) ))
io.exu_lsu_rs2_d:=Mux1H(Seq( io.lsu_exu.exu_lsu_rs2_d:=Mux1H(Seq(
(!i0_rs2_bypass_en_d & !io.dec_extint_stall & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d, (!i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs2_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d,
(i0_rs2_bypass_en_d & !io.dec_extint_stall).asBool -> i0_rs2_bypass_data_d (i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall).asBool -> i0_rs2_bypass_data_d
)) ))
val muldiv_rs1_d=Mux1H(Seq( val muldiv_rs1_d=Mux1H(Seq(
(!i0_rs1_bypass_en_d & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d, (!i0_rs1_bypass_en_d & io.dec_exu.decode_exu.dec_i0_rs1_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d,
(i0_rs1_bypass_en_d).asBool -> i0_rs1_bypass_data_d (i0_rs1_bypass_en_d).asBool -> i0_rs1_bypass_data_d
)) ))
val muldiv_rs2_d=Mux1H(Seq( val muldiv_rs2_d=Mux1H(Seq(
(!i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d, (!i0_rs2_bypass_en_d & io.dec_exu.decode_exu.dec_i0_rs2_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d,
(!i0_rs2_bypass_en_d).asBool -> io.dec_i0_immed_d, (!i0_rs2_bypass_en_d).asBool -> io.dec_exu.decode_exu.dec_i0_immed_d,
(i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d (i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d
)) ))
csr_rs1_in_d := Mux( io.dec_csr_ren_d.asBool, i0_rs1_d, io.exu_csr_rs1_x) csr_rs1_in_d := Mux( io.dec_exu.dec_alu.dec_csr_ren_d.asBool, i0_rs1_d, io.dec_exu.decode_exu.exu_csr_rs1_x)
val i_alu=Module(new el2_exu_alu_ctl) val i_alu=Module(new el2_exu_alu_ctl)
i_alu.io.dec_alu <> io.dec_exu.dec_alu
i_alu.io.scan_mode :=io.scan_mode i_alu.io.scan_mode :=io.scan_mode
i_alu.io.enable :=x_ctl_en i_alu.io.enable :=x_ctl_en
i_alu.io.pp_in :=i0_predict_newp_d i_alu.io.pp_in :=i0_predict_newp_d
i_alu.io.valid_in :=io.dec_i0_alu_decode_d
i_alu.io.flush_upper_x :=i0_flush_upper_x i_alu.io.flush_upper_x :=i0_flush_upper_x
i_alu.io.flush_lower_r :=io.dec_tlu_flush_lower_r i_alu.io.dec_tlu_flush_lower_r :=io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
i_alu.io.a_in :=i0_rs1_d.asSInt i_alu.io.a_in :=i0_rs1_d.asSInt
i_alu.io.b_in :=i0_rs2_d i_alu.io.b_in :=i0_rs2_d
i_alu.io.pc_in :=io.dec_i0_pc_d i_alu.io.dec_i0_pc_d :=io.dec_exu.ib_exu.dec_i0_pc_d
i_alu.io.brimm_in :=io.dec_i0_br_immed_d i_alu.io.i0_ap :=io.dec_exu.decode_exu.i0_ap
i_alu.io.ap :=io.i0_ap
i_alu.io.csr_ren_in :=io.dec_csr_ren_d
val alu_result_x =i_alu.io.result_ff val alu_result_x =i_alu.io.result_ff
i0_flush_upper_d :=i_alu.io.flush_upper_out i0_flush_upper_d :=i_alu.io.flush_upper_out
io.exu_flush_final :=i_alu.io.flush_final_out
i0_flush_path_d :=i_alu.io.flush_path_out i0_flush_path_d :=i_alu.io.flush_path_out
i0_predict_p_d :=i_alu.io.predict_p_out i0_predict_p_d :=i_alu.io.predict_p_out
i0_pred_correct_upper_d :=i_alu.io.pred_correct_out i0_pred_correct_upper_d :=i_alu.io.pred_correct_out
io.exu_i0_pc_x :=i_alu.io.pc_ff
val i_mul=Module(new el2_exu_mul_ctl) val i_mul=Module(new el2_exu_mul_ctl)
i_mul.io.scan_mode :=io.scan_mode i_mul.io.scan_mode :=io.scan_mode
i_mul.io.mul_p :=io.mul_p i_mul.io.mul_p :=io.dec_exu.decode_exu.mul_p
i_mul.io.rs1_in :=muldiv_rs1_d i_mul.io.rs1_in :=muldiv_rs1_d
i_mul.io.rs2_in :=muldiv_rs2_d i_mul.io.rs2_in :=muldiv_rs2_d
val mul_result_x =i_mul.io.result_x val mul_result_x =i_mul.io.result_x
val i_div=Module(new el2_exu_div_ctl) val i_div=Module(new el2_exu_div_ctl)
i_div.io.dec_div <> io.dec_exu.dec_div
i_div.io.scan_mode :=io.scan_mode i_div.io.scan_mode :=io.scan_mode
i_div.io.cancel :=io.dec_div_cancel // i_div.io.dec_div_cancel :=io.dec_exu.dec_div.dec_div_cancel
i_div.io.dp :=io.div_p // i_div.io.div_p :=io.dec_exu.dec_div.div_p
i_div.io.dividend :=muldiv_rs1_d i_div.io.dividend :=muldiv_rs1_d
i_div.io.divisor :=muldiv_rs2_d i_div.io.divisor :=muldiv_rs2_d
io.exu_div_wren :=i_div.io.finish_dly io.exu_div_wren :=i_div.io.exu_div_wren
io.exu_div_result :=i_div.io.out io.exu_div_result :=i_div.io.exu_div_result
io.exu_i0_result_x := Mux(mul_valid_x.asBool, mul_result_x, alu_result_x) io.dec_exu.decode_exu.exu_i0_result_x := Mux(mul_valid_x.asBool, mul_result_x, alu_result_x)
i0_predict_newp_d := io.dec_i0_predict_p_d i0_predict_newp_d := io.dec_exu.decode_exu.dec_i0_predict_p_d
i0_predict_newp_d.bits.boffset := io.dec_i0_pc_d(0) // from the start of inst i0_predict_newp_d.bits.boffset := io.dec_exu.ib_exu.dec_i0_pc_d(0) // from the start of inst
io.exu_pmu_i0_br_misp := i0_pp_r.bits.misp io.dec_exu.tlu_exu.exu_pmu_i0_br_misp := i0_pp_r.bits.misp
io.exu_pmu_i0_br_ataken := i0_pp_r.bits.ataken io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken := i0_pp_r.bits.ataken
io.exu_pmu_i0_pc4 := i0_pp_r.bits.pc4 io.dec_exu.tlu_exu.exu_pmu_i0_pc4 := i0_pp_r.bits.pc4
i0_valid_d := i0_predict_p_d.valid & io.dec_i0_alu_decode_d & !io.dec_tlu_flush_lower_r i0_valid_d := i0_predict_p_d.valid & io.dec_exu.dec_alu.dec_i0_alu_decode_d & !io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
i0_taken_d := (i0_predict_p_d.bits.ataken & io.dec_i0_alu_decode_d) i0_taken_d := (i0_predict_p_d.bits.ataken & io.dec_exu.dec_alu.dec_i0_alu_decode_d)
// maintain GHR at D // maintain GHR at D
ghr_d_ns:=Mux1H(Seq( ghr_d_ns:=Mux1H(Seq(
(!io.dec_tlu_flush_lower_r & i0_valid_d).asBool -> Cat(ghr_d(BHT_GHR_SIZE-2,0),i0_taken_d), (!io.dec_exu.tlu_exu.dec_tlu_flush_lower_r & i0_valid_d).asBool -> Cat(ghr_d(BHT_GHR_SIZE-2,0),i0_taken_d),
(!io.dec_tlu_flush_lower_r & !i0_valid_d).asBool -> ghr_d, (!io.dec_exu.tlu_exu.dec_tlu_flush_lower_r & !i0_valid_d).asBool -> ghr_d,
(io.dec_tlu_flush_lower_r).asBool -> ghr_x (io.dec_exu.tlu_exu.dec_tlu_flush_lower_r).asBool -> ghr_x
)) ))
// maintain GHR at X // maintain GHR at X
ghr_x_ns:=Mux(i0_valid_x===1.U, Cat(ghr_x(BHT_GHR_SIZE-2,0),i0_taken_x), ghr_x ) ghr_x_ns:=Mux(i0_valid_x===1.U, Cat(ghr_x(BHT_GHR_SIZE-2,0),i0_taken_x), ghr_x )
io.exu_i0_br_valid_r := i0_pp_r.valid io.dec_exu.tlu_exu.exu_i0_br_valid_r := i0_pp_r.valid
io.exu_i0_br_mp_r := i0_pp_r.bits.misp io.dec_exu.tlu_exu.exu_i0_br_mp_r := i0_pp_r.bits.misp
io.exu_i0_br_way_r := i0_pp_r.bits.way io.exu_i0_br_way_r := i0_pp_r.bits.way
io.exu_i0_br_hist_r := i0_pp_r.bits.hist io.dec_exu.tlu_exu.exu_i0_br_hist_r := i0_pp_r.bits.hist
io.exu_i0_br_error_r := i0_pp_r.bits.br_error io.dec_exu.tlu_exu.exu_i0_br_error_r := i0_pp_r.bits.br_error
io.exu_i0_br_middle_r := i0_pp_r.bits.pc4 ^ i0_pp_r.bits.boffset io.dec_exu.tlu_exu.exu_i0_br_middle_r := i0_pp_r.bits.pc4 ^ i0_pp_r.bits.boffset
io.exu_i0_br_start_error_r := i0_pp_r.bits.br_start_error io.dec_exu.tlu_exu.exu_i0_br_start_error_r := i0_pp_r.bits.br_start_error
io.exu_i0_br_fghr_r := predpipe_r(PREDPIPESIZE-1,BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO+1) io.exu_i0_br_fghr_r := predpipe_r(PREDPIPESIZE-1,BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO+1)
io.exu_i0_br_index_r := predpipe_r(BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO,BTB_BTAG_SIZE) io.dec_exu.tlu_exu.exu_i0_br_index_r := predpipe_r(BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO,BTB_BTAG_SIZE)
final_predict_mp := Mux(i0_flush_upper_x===1.U,i0_predict_p_x,0.U.asTypeOf(i0_predict_p_x)) final_predict_mp := Mux(i0_flush_upper_x===1.U,i0_predict_p_x,0.U.asTypeOf(i0_predict_p_x))
val final_predpipe_mp = Mux(i0_flush_upper_x===1.U,predpipe_x,0.U) val final_predpipe_mp = Mux(i0_flush_upper_x===1.U,predpipe_x,0.U)
val after_flush_eghr = Mux((i0_flush_upper_x===1.U & !(io.dec_tlu_flush_lower_r===1.U)), ghr_d, ghr_x) val after_flush_eghr = Mux((i0_flush_upper_x===1.U & !(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r===1.U)), ghr_d, ghr_x)
io.exu_mp_pkt.bits.way := final_predict_mp.bits.way io.exu_mp_pkt.bits.way := final_predict_mp.bits.way
@ -274,8 +311,8 @@ class el2_exu extends Module with el2_lib with RequireAsyncReset{
io.exu_mp_index := final_predpipe_mp(PREDPIPESIZE-BHT_GHR_SIZE-1,BTB_BTAG_SIZE) io.exu_mp_index := final_predpipe_mp(PREDPIPESIZE-BHT_GHR_SIZE-1,BTB_BTAG_SIZE)
io.exu_mp_btag := final_predpipe_mp(BTB_BTAG_SIZE-1,0) io.exu_mp_btag := final_predpipe_mp(BTB_BTAG_SIZE-1,0)
io.exu_mp_eghr := final_predpipe_mp(PREDPIPESIZE-1,BTB_ADDR_HI-BTB_ADDR_LO+BTB_BTAG_SIZE+1) // mp ghr for bht write io.exu_mp_eghr := final_predpipe_mp(PREDPIPESIZE-1,BTB_ADDR_HI-BTB_ADDR_LO+BTB_BTAG_SIZE+1) // mp ghr for bht write
io.exu_flush_path_final := Mux(io.dec_tlu_flush_lower_r.asBool, io.dec_tlu_flush_path_r, i0_flush_path_d) io.exu_flush_path_final := Mux(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r.asBool, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, i0_flush_path_d)
io.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r) io.dec_exu.tlu_exu.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r)
} }
object exu_gen extends App{ object exu_gen extends App{

80
src/main/scala/exu/el2_exu_alu_ctl.scala
View File

@ -5,41 +5,39 @@ import chisel3.util._
import include._ import include._
import lib._ import lib._
class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
val io = IO(new Bundle{ val io = IO(new Bundle{
////////// Inputs ///////// ////////// Inputs /////////
// val clk = Input(Clock()) // Top level clock // val clk = Input(Clock()) // Top level clock
// val rst_l = Input(UInt(1.W)) // Reset // val rst_l = Input(UInt(1.W)) // Reset
val scan_mode = Input(UInt(1.W)) // Scan control val dec_alu = new dec_alu
val flush_upper_x = Input(UInt(1.W)) // Branch flush from previous cycle
val flush_lower_r = Input(UInt(1.W)) // Master flush of entire pipeline val dec_i0_pc_d = Input(UInt(31.W)) // for pc=pc+2,4 calculations
val enable = Input(Bool()) // Clock enable val scan_mode = Input(UInt(1.W)) // Scan control
val valid_in = Input(UInt(1.W)) // Valid val flush_upper_x = Input(UInt(1.W)) // Branch flush from previous cycle
val ap = Input( new el2_alu_pkt_t ) // predecodes val dec_tlu_flush_lower_r = Input(UInt(1.W)) // Master flush of entire pipeline
val csr_ren_in = Input(UInt(1.W)) // extra decode val enable = Input(Bool()) // Clock enable
val a_in = Input(SInt(32.W)) // A operand val i0_ap = Input( new el2_alu_pkt_t ) // predecodes
val b_in = Input(UInt(32.W)) // B operand val a_in = Input(SInt(32.W)) // A operand
val pc_in = Input(UInt(31.W)) // for pc=pc+2,4 calculations val b_in = Input(UInt(32.W)) // B operand
val pp_in = Flipped(Valid(new el2_predict_pkt_t)) // Predicted branch structure val pp_in = Flipped(Valid(new el2_predict_pkt_t)) // Predicted branch structure
val brimm_in = Input(UInt(12.W)) // Branch offset
////////// Outputs ///////// ////////// Outputs /////////
val result_ff = Output(UInt(32.W)) // final result val result_ff = Output(UInt(32.W)) // final result
val flush_upper_out = Output(UInt(1.W)) // Branch flush val flush_upper_out = Output(UInt(1.W)) // Branch flush
val flush_final_out = Output(UInt(1.W)) // Branch flush or flush entire pipeline
val flush_path_out = Output(UInt(31.W)) // Branch flush PC val flush_path_out = Output(UInt(31.W)) // Branch flush PC
val pc_ff = Output(UInt(31.W)) // flopped PC
val pred_correct_out = Output(UInt(1.W)) // NPC control val pred_correct_out = Output(UInt(1.W)) // NPC control
val predict_p_out = Valid(new el2_predict_pkt_t) // Predicted branch structure val predict_p_out = Valid(new el2_predict_pkt_t) // Predicted branch structure
}) })
io.pc_ff := rvdffe(io.pc_in,io.enable,clock,io.scan_mode.asBool) // any PC is run through here - doesn't have to be alu io.dec_alu.exu_i0_pc_x := rvdffe(io.dec_i0_pc_d,io.enable,clock,io.scan_mode.asBool) // any PC is run through here - doesn't have to be alu
val result = WireInit(UInt(32.W),0.U) val result = WireInit(UInt(32.W),0.U)
io.result_ff := rvdffe(result,io.enable,clock,io.scan_mode.asBool) io.result_ff := rvdffe(result,io.enable,clock,io.scan_mode.asBool)
val bm = Mux( io.ap.sub.asBool, ~io.b_in, io.b_in) //H:b modified val bm = Mux( io.i0_ap.sub.asBool, ~io.b_in, io.b_in) //H:b modified
val aout = WireInit(UInt(33.W),0.U) val aout = WireInit(UInt(33.W),0.U)
aout := Mux(io.ap.sub.asBool,(Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W),~io.b_in) + Cat(0.U(32.W),io.ap.sub)), (Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W), io.b_in) + Cat(0.U(32.W),io.ap.sub))) aout := Mux(io.i0_ap.sub.asBool,(Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W),~io.b_in) + Cat(0.U(32.W),io.i0_ap.sub)), (Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W), io.b_in) + Cat(0.U(32.W),io.i0_ap.sub)))
val cout = aout(32) val cout = aout(32)
val ov = (!io.a_in(31) & !bm(31) & aout(31)) | ( io.a_in(31) & bm(31) & !aout(31) ) //overflow check from last bits val ov = (!io.a_in(31) & !bm(31) & aout(31)) | ( io.a_in(31) & bm(31) & !aout(31) ) //overflow check from last bits
@ -47,26 +45,26 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
val eq = (io.a_in === io.b_in.asSInt) val eq = (io.a_in === io.b_in.asSInt)
val ne = ~eq val ne = ~eq
val neg = aout(31)// check for the last signed bit (for neg) val neg = aout(31)// check for the last signed bit (for neg)
val lt = (!io.ap.unsign & (neg ^ ov)) | ( io.ap.unsign & !cout) //if alu packet sends unsigned and there is no cout(i.e no overflow and unsigned pkt) val lt = (!io.i0_ap.unsign & (neg ^ ov)) | ( io.i0_ap.unsign & !cout) //if alu packet sends unsigned and there is no cout(i.e no overflow and unsigned pkt)
val ge = !lt // if not less then val ge = !lt // if not less then
val lout = Mux1H(Seq( val lout = Mux1H(Seq(
io.csr_ren_in.asBool -> io.b_in.asSInt, //read enable read rs2 io.dec_alu.dec_csr_ren_d.asBool -> io.b_in.asSInt, //read enable read rs2
io.ap.land.asBool -> (io.a_in & io.b_in.asSInt), //and rs1 and 2 io.i0_ap.land.asBool -> (io.a_in & io.b_in.asSInt), //and rs1 and 2
io.ap.lor.asBool -> (io.a_in | io.b_in.asSInt), io.i0_ap.lor.asBool -> (io.a_in | io.b_in.asSInt),
io.ap.lxor.asBool -> (io.a_in ^ io.b_in.asSInt))) io.i0_ap.lxor.asBool -> (io.a_in ^ io.b_in.asSInt)))
val shift_amount = Mux1H(Seq ( val shift_amount = Mux1H(Seq (
io.ap.sll.asBool -> (32.U(6.W) - Cat(0.U(1.W),io.b_in(4,0))), // [5] unused io.i0_ap.sll.asBool -> (32.U(6.W) - Cat(0.U(1.W),io.b_in(4,0))), // [5] unused
io.ap.srl.asBool -> Cat(0.U(1.W),io.b_in(4,0)) , io.i0_ap.srl.asBool -> Cat(0.U(1.W),io.b_in(4,0)) ,
io.ap.sra.asBool -> Cat(0.U(1.W),io.b_in(4,0)) )) io.i0_ap.sra.asBool -> Cat(0.U(1.W),io.b_in(4,0)) ))
val shift_mask = WireInit(UInt(32.W),0.U) val shift_mask = WireInit(UInt(32.W),0.U)
shift_mask := ( "hffffffff".U(32.W) << (repl(5,io.ap.sll) & io.b_in(4,0)) ) shift_mask := ( "hffffffff".U(32.W) << (repl(5,io.i0_ap.sll) & io.b_in(4,0)) )
val shift_extend = WireInit(UInt(63.W),0.U) val shift_extend = WireInit(UInt(63.W),0.U)
shift_extend := Cat((repl(31,io.ap.sra) & repl(31,io.a_in(31))) | (repl(31,io.ap.sll) & io.a_in(30,0)),io.a_in) shift_extend := Cat((repl(31,io.i0_ap.sra) & repl(31,io.a_in(31))) | (repl(31,io.i0_ap.sll) & io.a_in(30,0)),io.a_in)
val shift_long = WireInit(UInt(63.W),0.U) val shift_long = WireInit(UInt(63.W),0.U)
shift_long := ( shift_extend >> shift_amount(4,0) ); // 62-32 unused shift_long := ( shift_extend >> shift_amount(4,0) ); // 62-32 unused
@ -74,48 +72,48 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
val sout = ( shift_long(31,0) & shift_mask(31,0) ); //incase of sra shift_mask is 1 val sout = ( shift_long(31,0) & shift_mask(31,0) ); //incase of sra shift_mask is 1
val sel_shift = io.ap.sll | io.ap.srl | io.ap.sra val sel_shift = io.i0_ap.sll | io.i0_ap.srl | io.i0_ap.sra
val sel_adder = (io.ap.add | io.ap.sub) & !io.ap.slt val sel_adder = (io.i0_ap.add | io.i0_ap.sub) & !io.i0_ap.slt
val sel_pc = io.ap.jal | io.pp_in.bits.pcall | io.pp_in.bits.pja | io.pp_in.bits.pret val sel_pc = io.i0_ap.jal | io.pp_in.bits.pcall | io.pp_in.bits.pja | io.pp_in.bits.pret
val csr_write_data = Mux(io.ap.csr_imm.asBool, io.b_in.asSInt, io.a_in) val csr_write_data = Mux(io.i0_ap.csr_imm.asBool, io.b_in.asSInt, io.a_in)
val slt_one = io.ap.slt & lt val slt_one = io.i0_ap.slt & lt
// for a conditional br pcout[] will be the opposite of the branch prediction // for a conditional br pcout[] will be the opposite of the branch prediction
// for jal or pcall, it will be the link address pc+2 or pc+4 // for jal or pcall, it will be the link address pc+2 or pc+4
val pcout = rvbradder(Cat(io.pc_in,0.U),Cat(io.brimm_in,0.U)) val pcout = rvbradder(Cat(io.dec_i0_pc_d,0.U),Cat(io.dec_alu.dec_i0_br_immed_d,0.U))
result := lout(31,0) | Cat(0.U(31.W),slt_one) | (Mux1H(Seq( result := lout(31,0) | Cat(0.U(31.W),slt_one) | (Mux1H(Seq(
sel_shift.asBool -> sout(31,0), sel_shift.asBool -> sout(31,0),
sel_adder.asBool -> aout(31,0), sel_adder.asBool -> aout(31,0),
sel_pc.asBool -> pcout, sel_pc.asBool -> pcout,
io.ap.csr_write.asBool -> csr_write_data(31,0)))) io.i0_ap.csr_write.asBool -> csr_write_data(31,0))))
// *** branch handling *** // *** branch handling ***
val any_jal = io.ap.jal | //jal val any_jal = io.i0_ap.jal | //jal
io.pp_in.bits.pcall | //branch is a call inst io.pp_in.bits.pcall | //branch is a call inst
io.pp_in.bits.pja | //branch is a jump always io.pp_in.bits.pja | //branch is a jump always
io.pp_in.bits.pret //return inst io.pp_in.bits.pret //return inst
val actual_taken = (io.ap.beq & eq) | (io.ap.bne & ne.asUInt) | (io.ap.blt & lt) | (io.ap.bge & ge) | any_jal val actual_taken = (io.i0_ap.beq & eq) | (io.i0_ap.bne & ne.asUInt) | (io.i0_ap.blt & lt) | (io.i0_ap.bge & ge) | any_jal
// pred_correct is for the npc logic // pred_correct is for the npc logic
// pred_correct indicates not to use the flush_path // pred_correct indicates not to use the flush_path
// for any_jal pred_correct==0 // for any_jal pred_correct==0
io.pred_correct_out := (io.valid_in & io.ap.predict_nt & !actual_taken & !any_jal) | (io.valid_in & io.ap.predict_t & actual_taken & !any_jal) io.pred_correct_out := (io.dec_alu.dec_i0_alu_decode_d & io.i0_ap.predict_nt & !actual_taken & !any_jal) | (io.dec_alu.dec_i0_alu_decode_d & io.i0_ap.predict_t & actual_taken & !any_jal)
// for any_jal adder output is the flush path // for any_jal adder output is the flush path
io.flush_path_out := Mux(any_jal.asBool, aout(31,1), pcout(31,1)) io.flush_path_out := Mux(any_jal.asBool, aout(31,1), pcout(31,1))
// pcall and pret are included here // pcall and pret are included here
val cond_mispredict = (io.ap.predict_t & !actual_taken) | (io.ap.predict_nt & actual_taken.asUInt) val cond_mispredict = (io.i0_ap.predict_t & !actual_taken) | (io.i0_ap.predict_nt & actual_taken.asUInt)
// target mispredicts on ret's // target mispredicts on ret's
val target_mispredict = io.pp_in.bits.pret & (io.pp_in.bits.prett =/= aout(31,1)) //predicted return target != aout val target_mispredict = io.pp_in.bits.pret & (io.pp_in.bits.prett =/= aout(31,1)) //predicted return target != aout
io.flush_upper_out := (io.ap.jal | cond_mispredict | target_mispredict) & io.valid_in & !io.flush_upper_x & !io.flush_lower_r io.flush_upper_out := (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x & !io.dec_tlu_flush_lower_r
//there was no entire pipe flush (& previous cycle flush ofc(why check?)) therfore signAL 1 to flush instruction before X stage //there was no entire pipe flush (& previous cycle flush ofc(why check?)) therfore signAL 1 to flush instruction before X stage
io.flush_final_out := ( (io.ap.jal | cond_mispredict | target_mispredict) & io.valid_in & !io.flush_upper_x ) | io.flush_lower_r io.dec_alu.exu_flush_final := ( (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x ) | io.dec_tlu_flush_lower_r
//there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe //there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe
val newhist = WireInit(UInt(2.W),0.U) val newhist = WireInit(UInt(2.W),0.U)
@ -123,7 +121,7 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
(!io.pp_in.bits.hist(1) & !actual_taken) | (io.pp_in.bits.hist(1) & actual_taken)) //newhist[0] (!io.pp_in.bits.hist(1) & !actual_taken) | (io.pp_in.bits.hist(1) & actual_taken)) //newhist[0]
io.predict_p_out := io.pp_in io.predict_p_out := io.pp_in
io.predict_p_out.bits.misp := !io.flush_upper_x & !io.flush_lower_r & (cond_mispredict | target_mispredict)// if 1 tells that it was a misprediction becauseprevious cycle was not a flush and these was no master flush(lower pipe flush) and ifu predicted taken but actually its nt io.predict_p_out.bits.misp := !io.flush_upper_x & !io.dec_tlu_flush_lower_r & (cond_mispredict | target_mispredict)// if 1 tells that it was a misprediction becauseprevious cycle was not a flush and these was no master flush(lower pipe flush) and ifu predicted taken but actually its nt
io.predict_p_out.bits.ataken := actual_taken; // send a control signal telling it branch taken or not io.predict_p_out.bits.ataken := actual_taken; // send a control signal telling it branch taken or not
io.predict_p_out.bits.hist := newhist io.predict_p_out.bits.hist := newhist
} }

45
src/main/scala/exu/el2_exu_div_ctl.scala
View File

@ -10,13 +10,14 @@ import lib._
class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib { class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
val io = IO(new Bundle{ val io = IO(new Bundle{
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val dp = Flipped(Valid(new el2_div_pkt_t )) // val div_p = Flipped(Valid(new el2_div_pkt_t ))
val dividend = Input(UInt(32.W)) val dividend = Input(UInt(32.W))
val divisor = Input(UInt(32.W)) val divisor = Input(UInt(32.W))
val cancel = Input(UInt(1.W)) // val dec_div_cancel = Input(UInt(1.W))
val out = Output(UInt(32.W)) val exu_div_result = Output(UInt(32.W))
val finish_dly = Output(UInt(1.W)) val exu_div_wren = Output(UInt(1.W))
val dec_div = new dec_div
}) })
// val exu_div_clk = Wire(Clock()) // val exu_div_clk = Wire(Clock())
val run_state = WireInit(0.U(1.W)) val run_state = WireInit(0.U(1.W))
@ -47,11 +48,11 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
val dividend_eff = WireInit(0.U(32.W)) val dividend_eff = WireInit(0.U(32.W))
val a_shift = WireInit(0.U(33.W)) val a_shift = WireInit(0.U(33.W))
io.out := 0.U // io.exu_div_result := 0.U
io.finish_dly := 0.U // io.exu_div_wren := 0.U
val valid_x = valid_ff_x & !io.cancel val valid_x = valid_ff_x & !io.dec_div.dec_div_cancel
// START - short circuit logic for small numbers {{ // START - short circuit logic for small numbers {{
// small number divides - any 4b / 4b is done in 1 cycle (divisor != 0) // small number divides - any 4b / 4b is done in 1 cycle (divisor != 0)
@ -157,13 +158,13 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
// *** End Short *** }} // *** End Short *** }}
val finish = smallnum_case | Mux(!rem_ff ,count === 32.U(6.W) ,count === 33.U(6.W)) val finish = smallnum_case | Mux(!rem_ff ,count === 32.U(6.W) ,count === 33.U(6.W))
val div_clken = io.dp.valid | run_state | finish | finish_ff val div_clken = io.dec_div.div_p.valid | run_state | finish | finish_ff
val run_in = (io.dp.valid | run_state) & !finish & !io.cancel val run_in = (io.dec_div.div_p.valid | run_state) & !finish & !io.dec_div.dec_div_cancel
count_in := Fill(6,(run_state & !finish & !io.cancel & !shortq_enable)) & (count + Cat(0.U,shortq_shift_ff) + (1.U)(6.W)) count_in := Fill(6,(run_state & !finish & !io.dec_div.dec_div_cancel & !shortq_enable)) & (count + Cat(0.U,shortq_shift_ff) + (1.U)(6.W))
//io.test := count_in //io.test := count_in
io.finish_dly := finish_ff & !io.cancel io.exu_div_wren := finish_ff & !io.dec_div.dec_div_cancel
val sign_eff = !io.dp.bits.unsign & (io.divisor =/= 0.U(32.W)) val sign_eff = !io.dec_div.div_p.bits.unsign & (io.divisor =/= 0.U(32.W))
q_in := Mux1H(Seq( q_in := Mux1H(Seq(
@ -171,7 +172,7 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
(run_state & (valid_ff_x | shortq_enable_ff)).asBool -> (Cat(dividend_eff(31,0),!a_in(32)) << shortq_shift_ff) , (run_state & (valid_ff_x | shortq_enable_ff)).asBool -> (Cat(dividend_eff(31,0),!a_in(32)) << shortq_shift_ff) ,
(run_state & !(valid_ff_x | shortq_enable_ff)).asBool -> Cat(q_ff(31,0),!a_in(32)) (run_state & !(valid_ff_x | shortq_enable_ff)).asBool -> Cat(q_ff(31,0),!a_in(32))
)) ))
val qff_enable = io.dp.valid | (run_state & !shortq_enable) val qff_enable = io.dec_div.div_p.valid | (run_state & !shortq_enable)
dividend_eff := Mux((sign_ff & dividend_neg_ff).asBool, rvtwoscomp(q_ff(31,0)),q_ff(31,0)) dividend_eff := Mux((sign_ff & dividend_neg_ff).asBool, rvtwoscomp(q_ff(31,0)),q_ff(31,0))
@ -182,7 +183,7 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
(!rem_correct & !shortq_enable_ff).asBool -> Cat(a_ff(31,0), q_ff(32)) , (!rem_correct & !shortq_enable_ff).asBool -> Cat(a_ff(31,0), q_ff(32)) ,
(!rem_correct & shortq_enable_ff).asBool -> Cat(0.U(9.W),a_eff_shift(55,32)) (!rem_correct & shortq_enable_ff).asBool -> Cat(0.U(9.W),a_eff_shift(55,32))
)) ))
val aff_enable = io.dp.valid | (run_state & !shortq_enable & (count =/= 33.U(6.W))) | rem_correct val aff_enable = io.dec_div.div_p.valid | (run_state & !shortq_enable & (count =/= 33.U(6.W))) | rem_correct
a_shift := Fill(33,run_state) & a_eff a_shift := Fill(33,run_state) & a_eff
a_in := Fill(33,run_state) & (a_shift + m_eff + Cat(0.U(32.W),!add)) a_in := Fill(33,run_state) & (a_shift + m_eff + Cat(0.U(32.W),!add))
val m_already_comp = divisor_neg_ff & sign_ff val m_already_comp = divisor_neg_ff & sign_ff
@ -192,7 +193,7 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
val q_ff_eff = Mux((sign_ff & (dividend_neg_ff ^ divisor_neg_ff)).asBool,rvtwoscomp(q_ff(31,0)), q_ff(31,0)) val q_ff_eff = Mux((sign_ff & (dividend_neg_ff ^ divisor_neg_ff)).asBool,rvtwoscomp(q_ff(31,0)), q_ff(31,0))
val a_ff_eff = Mux((sign_ff & dividend_neg_ff ).asBool, rvtwoscomp(a_ff(31,0)), a_ff(31,0)) val a_ff_eff = Mux((sign_ff & dividend_neg_ff ).asBool, rvtwoscomp(a_ff(31,0)), a_ff(31,0))
io.out := Mux1H(Seq( io.exu_div_result := Mux1H(Seq(
smallnum_case_ff.asBool -> Cat(0.U(28.W), smallnum_ff), smallnum_case_ff.asBool -> Cat(0.U(28.W), smallnum_ff),
rem_ff.asBool -> a_ff_eff , rem_ff.asBool -> a_ff_eff ,
(!smallnum_case_ff & !rem_ff).asBool -> q_ff_eff (!smallnum_case_ff & !rem_ff).asBool -> q_ff_eff
@ -201,14 +202,14 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
val exu_div_cgc = rvclkhdr(clock,div_clken.asBool,io.scan_mode) val exu_div_cgc = rvclkhdr(clock,div_clken.asBool,io.scan_mode)
withClock(exu_div_cgc) { withClock(exu_div_cgc) {
valid_ff_x := RegNext(io.dp.valid & !io.cancel, 0.U) valid_ff_x := RegNext(io.dec_div.div_p.valid & !io.dec_div.dec_div_cancel, 0.U)
finish_ff := RegNext(finish & !io.cancel, 0.U) finish_ff := RegNext(finish & !io.dec_div.dec_div_cancel, 0.U)
run_state := RegNext(run_in, 0.U) run_state := RegNext(run_in, 0.U)
count := RegNext(count_in, 0.U) count := RegNext(count_in, 0.U)
dividend_neg_ff := RegEnable(io.dividend(31), 0.U, io.dp.valid.asBool) dividend_neg_ff := RegEnable(io.dividend(31), 0.U, io.dec_div.div_p.valid.asBool)
divisor_neg_ff := RegEnable(io.divisor(31), 0.U, io.dp.valid.asBool) divisor_neg_ff := RegEnable(io.divisor(31), 0.U, io.dec_div.div_p.valid.asBool)
sign_ff := RegEnable(sign_eff, 0.U, io.dp.valid.asBool) sign_ff := RegEnable(sign_eff, 0.U, io.dec_div.div_p.valid.asBool)
rem_ff := RegEnable(io.dp.bits.rem, 0.U, io.dp.valid.asBool) rem_ff := RegEnable(io.dec_div.div_p.bits.rem, 0.U, io.dec_div.div_p.valid.asBool)
smallnum_case_ff := RegNext(smallnum_case, 0.U) smallnum_case_ff := RegNext(smallnum_case, 0.U)
smallnum_ff := RegNext(smallnum, 0.U) smallnum_ff := RegNext(smallnum, 0.U)
shortq_enable_ff := RegNext(shortq_enable, 0.U) shortq_enable_ff := RegNext(shortq_enable, 0.U)
@ -216,7 +217,7 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
} }
q_ff := rvdffe(q_in, qff_enable.asBool,clock,io.scan_mode) q_ff := rvdffe(q_in, qff_enable.asBool,clock,io.scan_mode)
a_ff := rvdffe(a_in, aff_enable.asBool,clock,io.scan_mode) a_ff := rvdffe(a_in, aff_enable.asBool,clock,io.scan_mode)
m_ff := rvdffe(Cat(!io.dp.bits.unsign & io.divisor(31), io.divisor), io.dp.valid.asBool,clock,io.scan_mode) m_ff := rvdffe(Cat(!io.dec_div.div_p.bits.unsign & io.divisor(31), io.divisor), io.dec_div.div_p.valid.asBool,clock,io.scan_mode)
} }
object div_main extends App{ object div_main extends App{

207
src/main/scala/ifu/el2_ifu.scala
View File

@ -4,58 +4,28 @@ import chisel3.internal.naming.chiselName
import chisel3.util._ import chisel3.util._
import lib._ import lib._
import include._ import include._
class ifu_dec extends Bundle{
val dec_aln = new dec_aln
val dec_mem_ctrl = new dec_mem_ctrl
val dec_ifc = new dec_ifc
val dec_bp = new dec_bp
}
class exu_ifu extends Bundle{
val exu_bp = new exu_bp()
val exu_ifc = new exu_ifc
}
@chiselName
class el2_ifu extends Module with el2_lib with RequireAsyncReset { class el2_ifu extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{ val io = IO(new Bundle{
val free_clk = Input(Clock()) val free_clk = Input(Clock())
val active_clk = Input(Clock()) val active_clk = Input(Clock())
val dec_i0_decode_d = Input(Bool()) val ifu_dec = new ifu_dec
val exu_flush_final = Input(Bool()) val exu_ifu = new exu_ifu
val dec_tlu_i0_commit_cmt = Input(Bool())
val dec_tlu_flush_err_wb = Input(Bool())
val dec_tlu_flush_noredir_wb = Input(Bool())
val exu_flush_path_final = Input(UInt(31.W))
val dec_tlu_mrac_ff = Input(UInt(32.W))
val dec_tlu_fence_i_wb = Input(Bool())
val dec_tlu_flush_leak_one_wb = Input(Bool())
val dec_tlu_bpred_disable = Input(Bool())
val dec_tlu_core_ecc_disable = Input(Bool())
val dec_tlu_force_halt = Input(Bool())
// AXI Write Channel // AXI Write Channel
val ifu_axi_awvalid = Output(Bool()) val ifu = new axi_channels()
val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_awaddr = Output(UInt(32.W))
val ifu_axi_awregion = Output(UInt(4.W))
val ifu_axi_awlen = Output(UInt(8.W))
val ifu_axi_awsize = Output(UInt(3.W))
val ifu_axi_awburst = Output(UInt(2.W))
val ifu_axi_awlock = Output(Bool())
val ifu_axi_awcache = Output(UInt(4.W))
val ifu_axi_awprot = Output(UInt(3.W))
val ifu_axi_awqos = Output(UInt(4.W))
val ifu_axi_wvalid = Output(Bool())
val ifu_axi_wdata = Output(UInt(64.W))
val ifu_axi_wstrb = Output(UInt(8.W))
val ifu_axi_wlast = Output(Bool())
val ifu_axi_bready = Output(Bool())
// AXI Read Channel
val ifu_axi_arvalid = Output(Bool())
val ifu_axi_arready = Input(Bool())
val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_araddr = Output(UInt(32.W))
val ifu_axi_arregion = Output(UInt(4.W))
val ifu_axi_arlen = Output(UInt(8.W))
val ifu_axi_arsize = Output(UInt(3.W))
val ifu_axi_arburst = Output(UInt(2.W))
val ifu_axi_arlock = Output(Bool())
val ifu_axi_arcache = Output(UInt(4.W))
val ifu_axi_arprot = Output(UInt(3.W))
val ifu_axi_arqos = Output(UInt(4.W))
val ifu_axi_rvalid = Input(Bool())
val ifu_axi_rready = Output(Bool())
val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
val ifu_axi_rdata = Input(UInt(64.W))
val ifu_axi_rresp = Input(UInt(2.W))
val ifu_bus_clk_en = Input(Bool()) val ifu_bus_clk_en = Input(Bool())
// DMA signals // DMA signals
val dma_iccm_req = Input(Bool()) val dma_iccm_req = Input(Bool())
val dma_mem_addr = Input(UInt(32.W)) val dma_mem_addr = Input(UInt(32.W))
@ -64,15 +34,14 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
val dma_mem_wdata = Input(UInt(64.W)) val dma_mem_wdata = Input(UInt(64.W))
val dma_mem_tag = Input(UInt(3.W)) val dma_mem_tag = Input(UInt(3.W))
val dma_iccm_stall_any = Input(Bool()) val dma_iccm_stall_any = Input(Bool())
// ICCM // ICCM
val iccm_dma_ecc_error = Output(Bool()) val iccm_dma_ecc_error = Output(Bool())
val iccm_dma_rvalid = Output(Bool()) val iccm_dma_rvalid = Output(Bool())
val iccm_dma_rdata = Output(UInt(64.W)) val iccm_dma_rdata = Output(UInt(64.W))
val iccm_dma_rtag = Output(UInt(3.W)) val iccm_dma_rtag = Output(UInt(3.W))
val iccm_ready = Output(Bool()) val iccm_ready = Output(Bool())
val ifu_pmu_instr_aligned = Output(Bool())
val ifu_pmu_fetch_stall = Output(Bool())
val ifu_ic_error_start = Output(Bool())
// I$ // I$
val ic_rw_addr = Output(UInt(31.W)) val ic_rw_addr = Output(UInt(31.W))
val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W)) val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W))
@ -82,7 +51,6 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
val ic_debug_rd_data = Input(UInt(71.W)) val ic_debug_rd_data = Input(UInt(71.W))
val ictag_debug_rd_data = Input(UInt(26.W)) val ictag_debug_rd_data = Input(UInt(26.W))
val ic_debug_wr_data = Output(UInt(71.W)) val ic_debug_wr_data = Output(UInt(71.W))
val ifu_ic_debug_rd_data = Output(UInt(71.W))
val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W)) val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W)) val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_premux_data = Output(UInt(64.W)) val ic_premux_data = Output(UInt(64.W))
@ -95,6 +63,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W)) val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W)) val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_perr = Input(Bool()) val ic_tag_perr = Input(Bool())
// ICCM cont'd // ICCM cont'd
val iccm_rw_addr = Output(UInt((ICCM_BITS-1).W)) val iccm_rw_addr = Output(UInt((ICCM_BITS-1).W))
val iccm_wren = Output(Bool()) val iccm_wren = Output(Bool())
@ -103,42 +72,9 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
val iccm_wr_size = Output(UInt(3.W)) val iccm_wr_size = Output(UInt(3.W))
val iccm_rd_data = Input(UInt(64.W)) val iccm_rd_data = Input(UInt(64.W))
val iccm_rd_data_ecc = Input(UInt(78.W)) val iccm_rd_data_ecc = Input(UInt(78.W))
val ifu_iccm_rd_ecc_single_err = Output(Bool())
// Performance counter // Performance counter
val ifu_pmu_ic_miss = Output(Bool())
val ifu_pmu_ic_hit = Output(Bool())
val ifu_pmu_bus_error = Output(Bool())
val ifu_pmu_bus_busy = Output(Bool())
val ifu_pmu_bus_trxn = Output(Bool())
//
val ifu_i0_icaf = Output(Bool())
val ifu_i0_icaf_type = Output(UInt(2.W))
val ifu_i0_valid = Output(Bool())
val ifu_i0_icaf_f1 = Output(Bool())
val ifu_i0_dbecc = Output(Bool())
val iccm_dma_sb_error = Output(Bool()) val iccm_dma_sb_error = Output(Bool())
val ifu_i0_instr = Output(UInt(32.W))
val ifu_i0_pc = Output(UInt(31.W))
val ifu_i0_pc4 = Output(Bool())
val ifu_miss_state_idle = Output(Bool())
// Aligner branch data
val i0_brp = Valid(new el2_br_pkt_t)
val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
// BP Inputs
val exu_mp_pkt = Flipped(Valid(new el2_predict_pkt_t))
val exu_mp_eghr = Input(UInt(BHT_GHR_SIZE.W))
val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W))
val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index
val exu_mp_btag = Input(UInt(BTB_BTAG_SIZE.W))
val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t))
val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu
val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
val dec_tlu_flush_lower_wb = Input(Bool())
val ifu_i0_cinst = Output(UInt(16.W))
val dec_tlu_ic_diag_pkt = Input(new el2_cache_debug_pkt_t)
val ifu_ic_debug_rd_data_valid = Output(Bool())
val iccm_buf_correct_ecc = Output(Bool()) val iccm_buf_correct_ecc = Output(Bool())
val iccm_correction_state = Output(Bool()) val iccm_correction_state = Output(Bool())
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
@ -147,6 +83,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
val bp_ctl_ch = Module(new el2_ifu_bp_ctl) val bp_ctl_ch = Module(new el2_ifu_bp_ctl)
val aln_ctl_ch = Module(new el2_ifu_aln_ctl) val aln_ctl_ch = Module(new el2_ifu_aln_ctl)
val ifc_ctl_ch = Module(new el2_ifu_ifc_ctl) val ifc_ctl_ch = Module(new el2_ifu_ifc_ctl)
// IFC wiring Inputs // IFC wiring Inputs
ifc_ctl_ch.io.active_clk := io.active_clk ifc_ctl_ch.io.active_clk := io.active_clk
ifc_ctl_ch.io.free_clk := io.free_clk ifc_ctl_ch.io.free_clk := io.free_clk
@ -154,18 +91,14 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
ifc_ctl_ch.io.ic_hit_f := mem_ctl_ch.io.ic_hit_f ifc_ctl_ch.io.ic_hit_f := mem_ctl_ch.io.ic_hit_f
ifc_ctl_ch.io.ifu_fb_consume1 := aln_ctl_ch.io.ifu_fb_consume1 ifc_ctl_ch.io.ifu_fb_consume1 := aln_ctl_ch.io.ifu_fb_consume1
ifc_ctl_ch.io.ifu_fb_consume2 := aln_ctl_ch.io.ifu_fb_consume2 ifc_ctl_ch.io.ifu_fb_consume2 := aln_ctl_ch.io.ifu_fb_consume2
ifc_ctl_ch.io.dec_tlu_flush_noredir_wb := io.dec_tlu_flush_noredir_wb ifc_ctl_ch.io.dec_ifc <> io.ifu_dec.dec_ifc
ifc_ctl_ch.io.exu_flush_final := io.exu_flush_final ifc_ctl_ch.io.exu_ifc <> io.exu_ifu.exu_ifc
ifc_ctl_ch.io.exu_flush_path_final := io.exu_flush_path_final
ifc_ctl_ch.io.ifu_bp_hit_taken_f := bp_ctl_ch.io.ifu_bp_hit_taken_f ifc_ctl_ch.io.ifu_bp_hit_taken_f := bp_ctl_ch.io.ifu_bp_hit_taken_f
ifc_ctl_ch.io.ifu_bp_btb_target_f := bp_ctl_ch.io.ifu_bp_btb_target_f ifc_ctl_ch.io.ifu_bp_btb_target_f := bp_ctl_ch.io.ifu_bp_btb_target_f
ifc_ctl_ch.io.ic_dma_active := mem_ctl_ch.io.ic_dma_active ifc_ctl_ch.io.ic_dma_active := mem_ctl_ch.io.ic_dma_active
ifc_ctl_ch.io.ic_write_stall := mem_ctl_ch.io.ic_write_stall ifc_ctl_ch.io.ic_write_stall := mem_ctl_ch.io.ic_write_stall
ifc_ctl_ch.io.dma_iccm_stall_any := io.dma_iccm_stall_any ifc_ctl_ch.io.dma_iccm_stall_any := io.dma_iccm_stall_any
ifc_ctl_ch.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff
ifc_ctl_ch.io.ifu_ic_mb_empty := mem_ctl_ch.io.ifu_ic_mb_empty ifc_ctl_ch.io.ifu_ic_mb_empty := mem_ctl_ch.io.ifu_ic_mb_empty
// Input complete
// ALN wiring Inputs // ALN wiring Inputs
aln_ctl_ch.io.scan_mode := io.scan_mode aln_ctl_ch.io.scan_mode := io.scan_mode
@ -183,8 +116,8 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
aln_ctl_ch.io.ifu_bp_way_f := bp_ctl_ch.io.ifu_bp_way_f aln_ctl_ch.io.ifu_bp_way_f := bp_ctl_ch.io.ifu_bp_way_f
aln_ctl_ch.io.ifu_bp_valid_f := bp_ctl_ch.io.ifu_bp_valid_f aln_ctl_ch.io.ifu_bp_valid_f := bp_ctl_ch.io.ifu_bp_valid_f
aln_ctl_ch.io.ifu_bp_ret_f := bp_ctl_ch.io.ifu_bp_ret_f aln_ctl_ch.io.ifu_bp_ret_f := bp_ctl_ch.io.ifu_bp_ret_f
aln_ctl_ch.io.exu_flush_final := io.exu_flush_final aln_ctl_ch.io.exu_flush_final := io.exu_ifu.exu_ifc.exu_flush_final
aln_ctl_ch.io.dec_i0_decode_d := io.dec_i0_decode_d aln_ctl_ch.io.dec_aln <> io.ifu_dec.dec_aln
aln_ctl_ch.io.ifu_fetch_data_f := mem_ctl_ch.io.ic_data_f aln_ctl_ch.io.ifu_fetch_data_f := mem_ctl_ch.io.ic_data_f
aln_ctl_ch.io.ifu_fetch_val := mem_ctl_ch.io.ifu_fetch_val aln_ctl_ch.io.ifu_fetch_val := mem_ctl_ch.io.ifu_fetch_val
aln_ctl_ch.io.ifu_fetch_pc := ifc_ctl_ch.io.ifc_fetch_addr_f aln_ctl_ch.io.ifu_fetch_pc := ifc_ctl_ch.io.ifc_fetch_addr_f
@ -195,27 +128,14 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
bp_ctl_ch.io.ic_hit_f := mem_ctl_ch.io.ic_hit_f bp_ctl_ch.io.ic_hit_f := mem_ctl_ch.io.ic_hit_f
bp_ctl_ch.io.ifc_fetch_addr_f := ifc_ctl_ch.io.ifc_fetch_addr_f bp_ctl_ch.io.ifc_fetch_addr_f := ifc_ctl_ch.io.ifc_fetch_addr_f
bp_ctl_ch.io.ifc_fetch_req_f := ifc_ctl_ch.io.ifc_fetch_req_f bp_ctl_ch.io.ifc_fetch_req_f := ifc_ctl_ch.io.ifc_fetch_req_f
bp_ctl_ch.io.dec_tlu_br0_r_pkt := io.dec_tlu_br0_r_pkt bp_ctl_ch.io.dec_bp <> io.ifu_dec.dec_bp
bp_ctl_ch.io.exu_i0_br_fghr_r := io.exu_i0_br_fghr_r bp_ctl_ch.io.exu_bp <> io.exu_ifu.exu_bp
bp_ctl_ch.io.exu_i0_br_index_r := io.exu_i0_br_index_r
bp_ctl_ch.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
bp_ctl_ch.io.dec_tlu_flush_leak_one_wb := io.dec_tlu_flush_leak_one_wb
bp_ctl_ch.io.dec_tlu_bpred_disable := io.dec_tlu_bpred_disable
bp_ctl_ch.io.exu_mp_pkt <> io.exu_mp_pkt
bp_ctl_ch.io.exu_mp_eghr := io.exu_mp_eghr
bp_ctl_ch.io.exu_mp_fghr := io.exu_mp_fghr
bp_ctl_ch.io.exu_mp_index := io.exu_mp_index
bp_ctl_ch.io.exu_mp_btag := io.exu_mp_btag
bp_ctl_ch.io.exu_flush_final := io.exu_flush_final
// mem-ctl wiring // mem-ctl wiring
mem_ctl_ch.io.free_clk := io.free_clk mem_ctl_ch.io.free_clk := io.free_clk
mem_ctl_ch.io.active_clk := io.active_clk mem_ctl_ch.io.active_clk := io.active_clk
mem_ctl_ch.io.exu_flush_final := io.exu_flush_final mem_ctl_ch.io.exu_flush_final := io.exu_ifu.exu_ifc.exu_flush_final
mem_ctl_ch.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb mem_ctl_ch.io.dec_mem_ctrl <> io.ifu_dec.dec_mem_ctrl
mem_ctl_ch.io.dec_tlu_flush_err_wb := io.dec_tlu_flush_err_wb
mem_ctl_ch.io.dec_tlu_i0_commit_cmt := io.dec_tlu_i0_commit_cmt
mem_ctl_ch.io.dec_tlu_force_halt := io.dec_tlu_force_halt
mem_ctl_ch.io.ifc_fetch_addr_bf := ifc_ctl_ch.io.ifc_fetch_addr_bf mem_ctl_ch.io.ifc_fetch_addr_bf := ifc_ctl_ch.io.ifc_fetch_addr_bf
mem_ctl_ch.io.ifc_fetch_uncacheable_bf := ifc_ctl_ch.io.ifc_fetch_uncacheable_bf mem_ctl_ch.io.ifc_fetch_uncacheable_bf := ifc_ctl_ch.io.ifc_fetch_uncacheable_bf
mem_ctl_ch.io.ifc_fetch_req_bf := ifc_ctl_ch.io.ifc_fetch_req_bf mem_ctl_ch.io.ifc_fetch_req_bf := ifc_ctl_ch.io.ifc_fetch_req_bf
@ -223,14 +143,9 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
mem_ctl_ch.io.ifc_iccm_access_bf := ifc_ctl_ch.io.ifc_iccm_access_bf mem_ctl_ch.io.ifc_iccm_access_bf := ifc_ctl_ch.io.ifc_iccm_access_bf
mem_ctl_ch.io.ifc_region_acc_fault_bf := ifc_ctl_ch.io.ifc_region_acc_fault_bf mem_ctl_ch.io.ifc_region_acc_fault_bf := ifc_ctl_ch.io.ifc_region_acc_fault_bf
mem_ctl_ch.io.ifc_dma_access_ok := ifc_ctl_ch.io.ifc_dma_access_ok mem_ctl_ch.io.ifc_dma_access_ok := ifc_ctl_ch.io.ifc_dma_access_ok
mem_ctl_ch.io.dec_tlu_fence_i_wb := io.dec_tlu_fence_i_wb
mem_ctl_ch.io.ifu_bp_hit_taken_f := bp_ctl_ch.io.ifu_bp_hit_taken_f mem_ctl_ch.io.ifu_bp_hit_taken_f := bp_ctl_ch.io.ifu_bp_hit_taken_f
mem_ctl_ch.io.ifu_bp_inst_mask_f := bp_ctl_ch.io.ifu_bp_inst_mask_f mem_ctl_ch.io.ifu_bp_inst_mask_f := bp_ctl_ch.io.ifu_bp_inst_mask_f
mem_ctl_ch.io.ifu_axi_arready := io.ifu_axi_arready mem_ctl_ch.io.ifu_axi <> io.ifu
mem_ctl_ch.io.ifu_axi_rvalid := io.ifu_axi_rvalid
mem_ctl_ch.io.ifu_axi_rid := io.ifu_axi_rid
mem_ctl_ch.io.ifu_axi_rdata := io.ifu_axi_rdata
mem_ctl_ch.io.ifu_axi_rresp := io.ifu_axi_rresp
mem_ctl_ch.io.ifu_bus_clk_en := io.ifu_bus_clk_en mem_ctl_ch.io.ifu_bus_clk_en := io.ifu_bus_clk_en
mem_ctl_ch.io.dma_iccm_req := io.dma_iccm_req mem_ctl_ch.io.dma_iccm_req := io.dma_iccm_req
mem_ctl_ch.io.dma_mem_addr := io.dma_mem_addr mem_ctl_ch.io.dma_mem_addr := io.dma_mem_addr
@ -248,55 +163,21 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
mem_ctl_ch.io.iccm_rd_data := io.iccm_rd_data mem_ctl_ch.io.iccm_rd_data := io.iccm_rd_data
mem_ctl_ch.io.iccm_rd_data_ecc := io.iccm_rd_data_ecc mem_ctl_ch.io.iccm_rd_data_ecc := io.iccm_rd_data_ecc
mem_ctl_ch.io.ifu_fetch_val := mem_ctl_ch.io.ic_fetch_val_f mem_ctl_ch.io.ifu_fetch_val := mem_ctl_ch.io.ic_fetch_val_f
mem_ctl_ch.io.dec_tlu_ic_diag_pkt <> io.dec_tlu_ic_diag_pkt
mem_ctl_ch.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable
mem_ctl_ch.io.scan_mode := io.scan_mode mem_ctl_ch.io.scan_mode := io.scan_mode
// Connecting the final outputs // Connecting the final outputs
io.ifu_axi_awvalid := mem_ctl_ch.io.ifu_axi_awvalid
io.ifu_axi_awid := mem_ctl_ch.io.ifu_axi_awid
io.ifu_axi_awaddr := mem_ctl_ch.io.ifu_axi_awaddr
io.ifu_axi_awregion := mem_ctl_ch.io.ifu_axi_awregion
io.ifu_axi_awlen := mem_ctl_ch.io.ifu_axi_awlen
io.ifu_axi_awsize := mem_ctl_ch.io.ifu_axi_awsize
io.ifu_axi_awburst := mem_ctl_ch.io.ifu_axi_awburst
io.ifu_axi_awlock := mem_ctl_ch.io.ifu_axi_awlock
io.ifu_axi_awcache := mem_ctl_ch.io.ifu_axi_awcache
io.ifu_axi_awprot := mem_ctl_ch.io.ifu_axi_awprot
io.ifu_axi_awqos := mem_ctl_ch.io.ifu_axi_awqos
io.ifu_axi_wvalid := mem_ctl_ch.io.ifu_axi_wvalid
io.ifu_axi_wdata := mem_ctl_ch.io.ifu_axi_wdata
io.ifu_axi_wstrb := mem_ctl_ch.io.ifu_axi_wstrb
io.ifu_axi_wlast := mem_ctl_ch.io.ifu_axi_wlast
io.ifu_axi_bready := mem_ctl_ch.io.ifu_axi_bready
// AXI Read Channel
io.ifu_axi_arvalid := mem_ctl_ch.io.ifu_axi_arvalid
io.ifu_axi_arid := mem_ctl_ch.io.ifu_axi_arid
io.ifu_axi_araddr := mem_ctl_ch.io.ifu_axi_araddr
io.ifu_axi_arregion := mem_ctl_ch.io.ifu_axi_arregion
io.ifu_axi_arlen := mem_ctl_ch.io.ifu_axi_arlen
io.ifu_axi_arsize := mem_ctl_ch.io.ifu_axi_arsize
io.ifu_axi_arburst := mem_ctl_ch.io.ifu_axi_arburst
io.ifu_axi_arlock := mem_ctl_ch.io.ifu_axi_arlock
io.ifu_axi_arcache := mem_ctl_ch.io.ifu_axi_arcache
io.ifu_axi_arprot := mem_ctl_ch.io.ifu_axi_arprot
io.ifu_axi_arqos := mem_ctl_ch.io.ifu_axi_arqos
io.ifu_axi_rready := mem_ctl_ch.io.ifu_axi_rready
io.iccm_dma_ecc_error := mem_ctl_ch.io.iccm_dma_ecc_error io.iccm_dma_ecc_error := mem_ctl_ch.io.iccm_dma_ecc_error
io.iccm_dma_rvalid := mem_ctl_ch.io.iccm_dma_rvalid io.iccm_dma_rvalid := mem_ctl_ch.io.iccm_dma_rvalid
io.iccm_dma_rdata := mem_ctl_ch.io.iccm_dma_rdata io.iccm_dma_rdata := mem_ctl_ch.io.iccm_dma_rdata
io.iccm_dma_rtag := mem_ctl_ch.io.iccm_dma_rtag io.iccm_dma_rtag := mem_ctl_ch.io.iccm_dma_rtag
io.iccm_ready := mem_ctl_ch.io.iccm_ready io.iccm_ready := mem_ctl_ch.io.iccm_ready
io.ifu_pmu_instr_aligned := aln_ctl_ch.io.ifu_pmu_instr_aligned
io.ifu_pmu_fetch_stall := ifc_ctl_ch.io.ifu_pmu_fetch_stall
io.ifu_ic_error_start := mem_ctl_ch.io.ic_error_start
// I$ // I$
io.ic_rw_addr := mem_ctl_ch.io.ic_rw_addr io.ic_rw_addr := mem_ctl_ch.io.ic_rw_addr
io.ic_wr_en := mem_ctl_ch.io.ic_wr_en io.ic_wr_en := mem_ctl_ch.io.ic_wr_en
io.ic_rd_en := mem_ctl_ch.io.ic_rd_en io.ic_rd_en := mem_ctl_ch.io.ic_rd_en
io.ic_wr_data := mem_ctl_ch.io.ic_wr_data io.ic_wr_data := mem_ctl_ch.io.ic_wr_data
io.ic_debug_wr_data := mem_ctl_ch.io.ic_debug_wr_data io.ic_debug_wr_data := mem_ctl_ch.io.ic_debug_wr_data
io.ifu_ic_debug_rd_data := mem_ctl_ch.io.ifu_ic_debug_rd_data
io.ic_sel_premux_data := mem_ctl_ch.io.ic_sel_premux_data io.ic_sel_premux_data := mem_ctl_ch.io.ic_sel_premux_data
io.ic_debug_addr := mem_ctl_ch.io.ic_debug_addr io.ic_debug_addr := mem_ctl_ch.io.ic_debug_addr
io.ic_debug_rd_en := mem_ctl_ch.io.ic_debug_rd_en io.ic_debug_rd_en := mem_ctl_ch.io.ic_debug_rd_en
@ -309,36 +190,16 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
io.iccm_rden := mem_ctl_ch.io.iccm_rden io.iccm_rden := mem_ctl_ch.io.iccm_rden
io.iccm_wr_data := mem_ctl_ch.io.iccm_wr_data io.iccm_wr_data := mem_ctl_ch.io.iccm_wr_data
io.iccm_wr_size := mem_ctl_ch.io.iccm_wr_size io.iccm_wr_size := mem_ctl_ch.io.iccm_wr_size
io.ifu_iccm_rd_ecc_single_err := mem_ctl_ch.io.iccm_rd_ecc_single_err
// Performance counter // Performance counter
io.ifu_pmu_ic_miss := mem_ctl_ch.io.ifu_pmu_ic_miss
io.ifu_pmu_ic_hit := mem_ctl_ch.io.ifu_pmu_ic_hit
io.ifu_pmu_bus_error := mem_ctl_ch.io.ifu_pmu_bus_error
io.ifu_pmu_bus_busy := mem_ctl_ch.io.ifu_pmu_bus_busy
io.ifu_pmu_bus_trxn := mem_ctl_ch.io.ifu_pmu_bus_trxn
//
io.ifu_i0_icaf := aln_ctl_ch.io.ifu_i0_icaf
io.ifu_i0_icaf_type := aln_ctl_ch.io.ifu_i0_icaf_type
io.ifu_i0_valid := aln_ctl_ch.io.ifu_i0_valid
io.ifu_i0_icaf_f1 := aln_ctl_ch.io.ifu_i0_icaf_f1
io.ifu_i0_dbecc := aln_ctl_ch.io.ifu_i0_dbecc
io.iccm_dma_sb_error := mem_ctl_ch.io.iccm_dma_sb_error io.iccm_dma_sb_error := mem_ctl_ch.io.iccm_dma_sb_error
io.ifu_i0_instr := aln_ctl_ch.io.ifu_i0_instr
io.ifu_i0_pc := aln_ctl_ch.io.ifu_i0_pc
io.ifu_i0_pc4 := aln_ctl_ch.io.ifu_i0_pc4
io.ifu_miss_state_idle := mem_ctl_ch.io.ifu_miss_state_idle
// Aligner branch data // Aligner branch data
io.i0_brp := aln_ctl_ch.io.i0_brp
io.ifu_i0_bp_index := aln_ctl_ch.io.ifu_i0_bp_index
io.ifu_i0_bp_fghr := aln_ctl_ch.io.ifu_i0_bp_fghr
io.ifu_i0_bp_btag := aln_ctl_ch.io.ifu_i0_bp_btag
io.ifu_i0_cinst := aln_ctl_ch.io.ifu_i0_cinst
io.ifu_ic_debug_rd_data_valid := mem_ctl_ch.io.ifu_ic_debug_rd_data_valid
io.iccm_buf_correct_ecc := mem_ctl_ch.io.iccm_buf_correct_ecc io.iccm_buf_correct_ecc := mem_ctl_ch.io.iccm_buf_correct_ecc
io.iccm_correction_state := mem_ctl_ch.io.iccm_correction_state io.iccm_correction_state := mem_ctl_ch.io.iccm_correction_state
io.ic_premux_data := mem_ctl_ch.io.ic_premux_data io.ic_premux_data := mem_ctl_ch.io.ic_premux_data
} }
object ifu_comp extends App { object ifu_top extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu())) println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu()))
} }

115
src/main/scala/ifu/el2_ifu_aln_ctl.scala
View File

@ -3,6 +3,29 @@ import lib._
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import include._ import include._
class aln_ib extends Bundle with el2_lib{
val ifu_i0_icaf = Output(Bool())
val ifu_i0_icaf_type = Output(UInt(2.W))
val ifu_i0_icaf_f1 = Output(Bool())
val ifu_i0_dbecc = Output(Bool())
val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
val ifu_i0_valid = Output(Bool())
val ifu_i0_instr = Output(UInt(32.W))
val ifu_i0_pc = Output(UInt(31.W))
val ifu_i0_pc4 = Output(Bool())
val i0_brp = Valid(new el2_br_pkt_t)
}
class aln_dec extends Bundle{
val dec_i0_decode_d = Input(Bool()) // Dec
val ifu_i0_cinst = Output(UInt(16.W)) // Dec
}
class dec_aln extends Bundle with el2_lib {
val aln_dec = new aln_dec
val aln_ib = new aln_ib
val ifu_pmu_instr_aligned = Output(Bool()) // TLU
}
class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset { class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{ val io = IO(new Bundle{
@ -22,43 +45,30 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
val ifu_bp_valid_f = Input(UInt(2.W)) val ifu_bp_valid_f = Input(UInt(2.W))
val ifu_bp_ret_f = Input(UInt(2.W)) val ifu_bp_ret_f = Input(UInt(2.W))
val exu_flush_final = Input(Bool()) val exu_flush_final = Input(Bool())
val dec_i0_decode_d = Input(Bool()) val dec_aln = new dec_aln
val ifu_fetch_data_f = Input(UInt(32.W)) val ifu_fetch_data_f = Input(UInt(32.W))
val ifu_fetch_val = Input(UInt(2.W)) val ifu_fetch_val = Input(UInt(2.W))
val ifu_fetch_pc = Input(UInt(31.W)) val ifu_fetch_pc = Input(UInt(31.W))
///////////////////////////////////////////////// /////////////////////////////////////////////////
val ifu_i0_valid = Output(Bool())
val ifu_i0_icaf = Output(Bool())
val ifu_i0_icaf_type = Output(UInt(2.W))
val ifu_i0_icaf_f1 = Output(Bool())
val ifu_i0_dbecc = Output(Bool())
val ifu_i0_instr = Output(UInt(32.W))
val ifu_i0_pc = Output(UInt(31.W))
val ifu_i0_pc4 = Output(Bool())
val ifu_fb_consume1 = Output(Bool()) val ifu_fb_consume1 = Output(Bool())
val ifu_fb_consume2 = Output(Bool()) val ifu_fb_consume2 = Output(Bool())
val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
val ifu_pmu_instr_aligned = Output(Bool())
val ifu_i0_cinst = Output(UInt(16.W))
val i0_brp = Valid(new el2_br_pkt_t)
}) })
io.ifu_i0_valid := 0.U io.dec_aln.aln_ib.ifu_i0_valid := 0.U
io.ifu_i0_icaf := 0.U io.dec_aln.aln_ib.ifu_i0_icaf := 0.U
io.ifu_i0_icaf_type := 0.U io.dec_aln.aln_ib.ifu_i0_icaf_type := 0.U
io.ifu_i0_icaf_f1 := 0.U io.dec_aln.aln_ib.ifu_i0_icaf_f1 := 0.U
io.ifu_i0_dbecc := 0.U io.dec_aln.aln_ib.ifu_i0_dbecc := 0.U
io.ifu_i0_instr := 0.U io.dec_aln.aln_ib.ifu_i0_instr := 0.U
io.ifu_i0_pc := 0.U io.dec_aln.aln_ib.ifu_i0_pc := 0.U
io.ifu_i0_pc4 := 0.U io.dec_aln.aln_ib.ifu_i0_pc4 := 0.U
io.ifu_fb_consume1 := 0.U io.ifu_fb_consume1 := 0.U
io.ifu_fb_consume2 := 0.U io.ifu_fb_consume2 := 0.U
io.ifu_i0_bp_index := 0.U io.dec_aln.aln_ib.ifu_i0_bp_index := 0.U
io.ifu_i0_bp_fghr := 0.U io.dec_aln.aln_ib.ifu_i0_bp_fghr := 0.U
io.ifu_i0_bp_btag := 0.U io.dec_aln.aln_ib.ifu_i0_bp_btag := 0.U
io.ifu_pmu_instr_aligned := 0.U io.dec_aln.ifu_pmu_instr_aligned := 0.U
io.ifu_i0_cinst := 0.U io.dec_aln.aln_dec.ifu_i0_cinst := 0.U
val MHI = 46+BHT_GHR_SIZE // 54 val MHI = 46+BHT_GHR_SIZE // 54
val MSIZE = 47+BHT_GHR_SIZE // 55 val MSIZE = 47+BHT_GHR_SIZE // 55
val BRDATA_SIZE = 12 val BRDATA_SIZE = 12
@ -337,35 +347,35 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc)) val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc))
io.ifu_i0_pc := f0pc io.dec_aln.aln_ib.ifu_i0_pc := f0pc
val firstpc = f0pc val firstpc = f0pc
io.ifu_i0_pc4 := first4B io.dec_aln.aln_ib.ifu_i0_pc4 := first4B
io.ifu_i0_cinst := aligndata(15,0) io.dec_aln.aln_dec.ifu_i0_cinst := aligndata(15,0)
first4B := aligndata(1,0) === 3.U first4B := aligndata(1,0) === 3.U
val first2B = ~first4B val first2B = ~first4B
io.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0))) io.dec_aln.aln_ib.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
io.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0))) io.dec_aln.aln_ib.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
io.ifu_i0_icaf_type := Mux((first4B & !f0val(1) & f0val(0) & !alignicaf(0) & !aligndbecc(0)).asBool, f1ictype, f0ictype) io.dec_aln.aln_ib.ifu_i0_icaf_type := Mux((first4B & !f0val(1) & f0val(0) & !alignicaf(0) & !aligndbecc(0)).asBool, f1ictype, f0ictype)
val icaf_eff = alignicaf(1) | aligndbecc(1) val icaf_eff = alignicaf(1) | aligndbecc(1)
io.ifu_i0_icaf_f1 := first4B & icaf_eff & alignfromf1 io.dec_aln.aln_ib.ifu_i0_icaf_f1 := first4B & icaf_eff & alignfromf1
io.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0))) io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0)))
val ifirst = aligndata val ifirst = aligndata
val decompressed = Module(new el2_ifu_compress_ctl()) val decompressed = Module(new el2_ifu_compress_ctl())
io.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout)) io.dec_aln.aln_ib.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout))
val firstpc_hash = el2_btb_addr_hash(f0pc) val firstpc_hash = el2_btb_addr_hash(f0pc)
@ -375,39 +385,39 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
val secondbrtag_hash = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(secondpc) else el2_btb_tag_hash(secondpc) val secondbrtag_hash = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(secondpc) else el2_btb_tag_hash(secondpc)
io.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0)) io.dec_aln.aln_ib.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
io.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1)) io.dec_aln.aln_ib.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1))
val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1)) val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
io.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1)) io.dec_aln.aln_ib.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1))
io.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)), io.dec_aln.aln_ib.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
(first2B & alignhist0(0)) | (first4B & alignhist0(1))) (first2B & alignhist0(0)) | (first4B & alignhist0(1)))
val i0_ends_f1 = first4B & alignfromf1 val i0_ends_f1 = first4B & alignfromf1
io.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset) io.dec_aln.aln_ib.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
io.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett) io.dec_aln.aln_ib.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
io.i0_brp.bits.br_start_error := (first4B & alignval(1) & alignbrend(0)) io.dec_aln.aln_ib.i0_brp.bits.br_start_error := (first4B & alignval(1) & alignbrend(0))
io.i0_brp.bits.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0)) io.dec_aln.aln_ib.i0_brp.bits.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
io.i0_brp.bits.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B) io.dec_aln.aln_ib.i0_brp.bits.br_error := (io.dec_aln.aln_ib.i0_brp.valid & i0_brp_pc4 & first2B) | (io.dec_aln.aln_ib.i0_brp.valid & !i0_brp_pc4 & first4B)
io.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash) io.dec_aln.aln_ib.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
io.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr) io.dec_aln.aln_ib.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr)
io.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash) io.dec_aln.aln_ib.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash)
decompressed.io.din := aligndata decompressed.io.din := aligndata
val i0_shift = io.dec_i0_decode_d & ~error_stall val i0_shift = io.dec_aln.aln_dec.dec_i0_decode_d & ~error_stall
io.ifu_pmu_instr_aligned := i0_shift io.dec_aln.ifu_pmu_instr_aligned := i0_shift
shift_2B := i0_shift & first2B shift_2B := i0_shift & first2B
shift_4B := i0_shift & first4B shift_4B := i0_shift & first4B
@ -416,6 +426,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
f1_shift_2B := f0val(0) & !f0val(1) & shift_4B f1_shift_2B := f0val(0) & !f0val(1) & shift_4B
} }
object ifu_aln extends App {
object ifc_aln extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_aln_ctl())) println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_aln_ctl()))
} }

94
src/main/scala/ifu/el2_ifu_bp_ctl.scala
View File

@ -6,6 +6,23 @@ import chisel3.util._
import chisel3.experimental.chiselName import chisel3.experimental.chiselName
@chiselName @chiselName
class dec_bp extends Bundle{
val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t))
val dec_tlu_flush_lower_wb = Input(Bool())
val dec_tlu_flush_leak_one_wb = Input(Bool())
val dec_tlu_bpred_disable = Input(Bool())
}
class exu_bp extends Bundle with el2_lib {
val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu
val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Way from where the btb got a hit
val exu_mp_pkt = Flipped(Valid(new el2_predict_pkt_t))
val exu_mp_eghr = Input(UInt(BHT_GHR_SIZE.W))
val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W))
val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index
val exu_mp_btag = Input(UInt(BTB_BTAG_SIZE.W))
val exu_flush_final = Input(Bool())
}
class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset { class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val io = IO (new Bundle { val io = IO (new Bundle {
val active_clk = Input(Clock()) val active_clk = Input(Clock())
@ -13,19 +30,9 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val ifc_fetch_addr_f = Input(UInt(31.W)) val ifc_fetch_addr_f = Input(UInt(31.W))
val ifc_fetch_req_f = Input(Bool()) // Fetch request generated by the IFC val ifc_fetch_req_f = Input(Bool()) // Fetch request generated by the IFC
// Decode packet containing information if its a brnach or not // Decode packet containing information if its a brnach or not
val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t)) val dec_bp = new dec_bp()
val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu val exu_bp = new exu_bp()
val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Way from where the btb got a hit
val dec_tlu_flush_lower_wb = Input(Bool())
val dec_tlu_flush_leak_one_wb = Input(Bool())
val dec_tlu_bpred_disable = Input(Bool())
// Exu misprediction packet // Exu misprediction packet
val exu_mp_pkt = Flipped(Valid(new el2_predict_pkt_t))
val exu_mp_eghr = Input(UInt(BHT_GHR_SIZE.W))
val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W))
val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index
val exu_mp_btag = Input(UInt(BTB_BTAG_SIZE.W))
val exu_flush_final = Input(Bool())
// Signals to the IFU containing information about brnach // Signals to the IFU containing information about brnach
val ifu_bp_hit_taken_f = Output(Bool()) val ifu_bp_hit_taken_f = Output(Bool())
val ifu_bp_btb_target_f = Output(UInt(31.W)) val ifu_bp_btb_target_f = Output(UInt(31.W))
@ -39,7 +46,6 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val ifu_bp_valid_f = Output(UInt(2.W)) val ifu_bp_valid_f = Output(UInt(2.W))
val ifu_bp_poffset_f = Output(UInt(12.W)) val ifu_bp_poffset_f = Output(UInt(12.W))
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val test = Output(UInt())
}) })
val TAG_START = 16+BTB_BTAG_SIZE val TAG_START = 16+BTB_BTAG_SIZE
@ -65,31 +71,30 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val btb_bank0_rd_data_way1_p1_f = WireInit(UInt((TAG_START+1).W), 0.U) val btb_bank0_rd_data_way1_p1_f = WireInit(UInt((TAG_START+1).W), 0.U)
val eoc_mask = WireInit(Bool(), 0.U) val eoc_mask = WireInit(Bool(), 0.U)
val btb_lru_b0_f = WireInit(UInt(LRU_SIZE.W), init = 0.U) val btb_lru_b0_f = WireInit(UInt(LRU_SIZE.W), init = 0.U)
io.test := btb_lru_b0_f
val dec_tlu_way_wb = WireInit(Bool(), 0.U) val dec_tlu_way_wb = WireInit(Bool(), 0.U)
///////////////////////////////////////////////////////// /////////////////////////////////////////////////////////
// Misprediction packet // Misprediction packet
val exu_mp_valid = io.exu_mp_pkt.bits.misp & !leak_one_f val exu_mp_valid = io.exu_bp.exu_mp_pkt.bits.misp & !leak_one_f
val exu_mp_boffset = io.exu_mp_pkt.bits.boffset val exu_mp_boffset = io.exu_bp.exu_mp_pkt.bits.boffset
val exu_mp_pc4 = io.exu_mp_pkt.bits.pc4 val exu_mp_pc4 = io.exu_bp.exu_mp_pkt.bits.pc4
val exu_mp_call = io.exu_mp_pkt.bits.pcall val exu_mp_call = io.exu_bp.exu_mp_pkt.bits.pcall
val exu_mp_ret = io.exu_mp_pkt.bits.pret val exu_mp_ret = io.exu_bp.exu_mp_pkt.bits.pret
val exu_mp_ja = io.exu_mp_pkt.bits.pja val exu_mp_ja = io.exu_bp.exu_mp_pkt.bits.pja
val exu_mp_way = io.exu_mp_pkt.bits.way val exu_mp_way = io.exu_bp.exu_mp_pkt.bits.way
val exu_mp_hist = io.exu_mp_pkt.bits.hist val exu_mp_hist = io.exu_bp.exu_mp_pkt.bits.hist
val exu_mp_tgt = io.exu_mp_pkt.bits.toffset val exu_mp_tgt = io.exu_bp.exu_mp_pkt.bits.toffset
val exu_mp_addr = io.exu_mp_index val exu_mp_addr = io.exu_bp.exu_mp_index
val exu_mp_ataken = io.exu_mp_pkt.bits.ataken val exu_mp_ataken = io.exu_bp.exu_mp_pkt.bits.ataken
// Its a commit or update packet // Its a commit or update packet
val dec_tlu_br0_v_wb = io.dec_tlu_br0_r_pkt.valid val dec_tlu_br0_v_wb = io.dec_bp.dec_tlu_br0_r_pkt.valid
val dec_tlu_br0_hist_wb = io.dec_tlu_br0_r_pkt.bits.hist val dec_tlu_br0_hist_wb = io.dec_bp.dec_tlu_br0_r_pkt.bits.hist
val dec_tlu_br0_addr_wb = io.exu_i0_br_index_r val dec_tlu_br0_addr_wb = io.exu_bp.exu_i0_br_index_r
val dec_tlu_br0_error_wb = io.dec_tlu_br0_r_pkt.bits.br_error val dec_tlu_br0_error_wb = io.dec_bp.dec_tlu_br0_r_pkt.bits.br_error
val dec_tlu_br0_middle_wb = io.dec_tlu_br0_r_pkt.bits.middle val dec_tlu_br0_middle_wb = io.dec_bp.dec_tlu_br0_r_pkt.bits.middle
val dec_tlu_br0_way_wb = io.dec_tlu_br0_r_pkt.bits.way val dec_tlu_br0_way_wb = io.dec_bp.dec_tlu_br0_r_pkt.bits.way
val dec_tlu_br0_start_error_wb = io.dec_tlu_br0_r_pkt.bits.br_start_error val dec_tlu_br0_start_error_wb = io.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error
val exu_i0_br_fghr_wb = io.exu_i0_br_fghr_r val exu_i0_br_fghr_wb = io.exu_bp.exu_i0_br_fghr_r
dec_tlu_error_wb := dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb dec_tlu_error_wb := dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb
btb_error_addr_wb := dec_tlu_br0_addr_wb btb_error_addr_wb := dec_tlu_br0_addr_wb
@ -123,16 +128,16 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val fetch_rd_tag_p1_f = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(Cat(fetch_addr_p1_f,0.U)) else el2_btb_tag_hash(Cat(fetch_addr_p1_f,0.U)) val fetch_rd_tag_p1_f = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(Cat(fetch_addr_p1_f,0.U)) else el2_btb_tag_hash(Cat(fetch_addr_p1_f,0.U))
// There is a misprediction and the exu is writing back // There is a misprediction and the exu is writing back
val fetch_mp_collision_f = (io.exu_mp_btag === fetch_rd_tag_f) & exu_mp_valid & io.ifc_fetch_req_f & (exu_mp_addr === btb_rd_addr_f) val fetch_mp_collision_f = (io.exu_bp.exu_mp_btag === fetch_rd_tag_f) & exu_mp_valid & io.ifc_fetch_req_f & (exu_mp_addr === btb_rd_addr_f)
val fetch_mp_collision_p1_f = (io.exu_mp_btag === fetch_rd_tag_p1_f) & exu_mp_valid & io.ifc_fetch_req_f & (exu_mp_addr === btb_rd_addr_p1_f) val fetch_mp_collision_p1_f = (io.exu_bp.exu_mp_btag === fetch_rd_tag_p1_f) & exu_mp_valid & io.ifc_fetch_req_f & (exu_mp_addr === btb_rd_addr_p1_f)
val leak_one_f_d1 = withClock(io.active_clk) {RegNext(leak_one_f, init = 0.U)} val leak_one_f_d1 = withClock(io.active_clk) {RegNext(leak_one_f, init = 0.U)}
val dec_tlu_way_wb_f = withClock(io.active_clk) {RegNext(dec_tlu_way_wb, init = 0.U)} val dec_tlu_way_wb_f = withClock(io.active_clk) {RegNext(dec_tlu_way_wb, init = 0.U)}
val exu_mp_way_f = withClock(io.active_clk) {RegNext(exu_mp_way, init = 0.U)} val exu_mp_way_f = withClock(io.active_clk) {RegNext(exu_mp_way, init = 0.U)}
val exu_flush_final_d1 = withClock(io.active_clk) {RegNext(io.exu_flush_final, init = 0.U)} val exu_flush_final_d1 = withClock(io.active_clk) {RegNext(io.exu_bp.exu_flush_final, init = 0.U)}
// If there is a flush from the lower pipe wait until the flush gets deasserted from the (decode) side // If there is a flush from the lower pipe wait until the flush gets deasserted from the (decode) side
leak_one_f := (io.dec_tlu_flush_leak_one_wb & io.dec_tlu_flush_lower_wb) | (leak_one_f_d1 & io.dec_tlu_flush_lower_wb) leak_one_f := (io.dec_bp.dec_tlu_flush_leak_one_wb & io.dec_bp.dec_tlu_flush_lower_wb) | (leak_one_f_d1 & !io.dec_bp.dec_tlu_flush_lower_wb)
// For a tag to match the branch should be valid tag should match and a fetch request should be generated // For a tag to match the branch should be valid tag should match and a fetch request should be generated
// Also there should be no bank conflict or leak-one // Also there should be no bank conflict or leak-one
@ -145,10 +150,10 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
// Similar to above matches // Similar to above matches
val tag_match_way0_p1_f = btb_bank0_rd_data_way0_p1_f(BV) & (btb_bank0_rd_data_way0_p1_f(TAG_START,17) === fetch_rd_tag_p1_f) & val tag_match_way0_p1_f = btb_bank0_rd_data_way0_p1_f(BV) & (btb_bank0_rd_data_way0_p1_f(TAG_START,17) === fetch_rd_tag_p1_f) &
!(dec_tlu_way_wb_f & branch_error_bank_conflict_f) & io.ifc_fetch_req_f & !leak_one_f !(dec_tlu_way_wb_f & branch_error_bank_conflict_p1_f) & io.ifc_fetch_req_f & !leak_one_f
// Similar to above matches // Similar to above matches
val tag_match_way1_p1_f = btb_bank0_rd_data_way1_p1_f(BV) & (btb_bank0_rd_data_way1_p1_f(TAG_START,17) === fetch_rd_tag_p1_f) & val tag_match_way1_p1_f = btb_bank0_rd_data_way1_p1_f(BV) & (btb_bank0_rd_data_way1_p1_f(TAG_START,17) === fetch_rd_tag_p1_f) &
!(dec_tlu_way_wb_f & branch_error_bank_conflict_f) & io.ifc_fetch_req_f & !leak_one_f !(dec_tlu_way_wb_f & branch_error_bank_conflict_p1_f) & io.ifc_fetch_req_f & !leak_one_f
// Reordering to avoid multiple hit // Reordering to avoid multiple hit
val tag_match_way0_expanded_f = Cat(tag_match_way0_f & (btb_bank0_rd_data_way0_f(BOFF) ^ btb_bank0_rd_data_way0_f(PC4)), val tag_match_way0_expanded_f = Cat(tag_match_way0_f & (btb_bank0_rd_data_way0_f(BOFF) ^ btb_bank0_rd_data_way0_f(PC4)),
@ -270,7 +275,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
btb_sel_f(0).asBool-> btb_vbank0_rd_data_f(16,1))) btb_sel_f(0).asBool-> btb_vbank0_rd_data_f(16,1)))
// No lower flush or bp-disabple and a fetch request is generated with virtual way hit // No lower flush or bp-disabple and a fetch request is generated with virtual way hit
io.ifu_bp_hit_taken_f := (vwayhit_f & hist1_raw).orR & io.ifc_fetch_req_f & !leak_one_f_d1 & !io.dec_tlu_bpred_disable io.ifu_bp_hit_taken_f := (vwayhit_f & hist1_raw).orR & io.ifc_fetch_req_f & !leak_one_f_d1 & !io.dec_bp.dec_tlu_bpred_disable
// If the prediction is a call or ret btb entry then do not check the bht just force a taken with data from the RAS // If the prediction is a call or ret btb entry then do not check the bht just force a taken with data from the RAS
val bht_force_taken_f = Cat( btb_vbank1_rd_data_f(CALL) | btb_vbank1_rd_data_f(RET) , val bht_force_taken_f = Cat( btb_vbank1_rd_data_f(CALL) | btb_vbank1_rd_data_f(RET) ,
@ -322,7 +327,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
(num_valids===1.U).asBool->Cat(fghr(BHT_GHR_SIZE-2,0), final_h), (num_valids===1.U).asBool->Cat(fghr(BHT_GHR_SIZE-2,0), final_h),
(num_valids===0.U).asBool->Cat(fghr(BHT_GHR_SIZE-1,0)))) (num_valids===0.U).asBool->Cat(fghr(BHT_GHR_SIZE-1,0))))
val exu_flush_ghr = io.exu_mp_fghr val exu_flush_ghr = io.exu_bp.exu_mp_fghr
val fghr_ns = Wire(UInt(BHT_GHR_SIZE.W)) val fghr_ns = Wire(UInt(BHT_GHR_SIZE.W))
// If there is a exu-flush use its ghr // If there is a exu-flush use its ghr
@ -339,7 +344,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
io.ifu_bp_hist0_f := hist0_raw io.ifu_bp_hist0_f := hist0_raw
io.ifu_bp_pc4_f := pc4_raw io.ifu_bp_pc4_f := pc4_raw
io.ifu_bp_valid_f := vwayhit_f & ~Fill(2, io.dec_tlu_bpred_disable) io.ifu_bp_valid_f := vwayhit_f & ~Fill(2, io.dec_bp.dec_tlu_bpred_disable)
io.ifu_bp_ret_f := pret_raw io.ifu_bp_ret_f := pret_raw
// block fetch to calculate if there is a hit with fetch request and a taken branch then compute the branch offset // block fetch to calculate if there is a hit with fetch request and a taken branch then compute the branch offset
@ -390,7 +395,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
rets_out := (0 until RET_STACK_SIZE).map(i=>rvdffe(rets_in(i), rsenable(i).asBool, clock, io.scan_mode)) rets_out := (0 until RET_STACK_SIZE).map(i=>rvdffe(rets_in(i), rsenable(i).asBool, clock, io.scan_mode))
val btb_valid = exu_mp_valid & (!dec_tlu_error_wb) val btb_valid = exu_mp_valid & (!dec_tlu_error_wb)
val btb_wr_tag = io.exu_mp_btag val btb_wr_tag = io.exu_bp.exu_mp_btag
// Making the data to write into the BTB according the structure discribed above // Making the data to write into the BTB according the structure discribed above
val btb_wr_data = Cat(btb_wr_tag, exu_mp_tgt, exu_mp_pc4, exu_mp_boffset, exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid) val btb_wr_data = Cat(btb_wr_tag, exu_mp_tgt, exu_mp_pc4, exu_mp_boffset, exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid)
@ -411,7 +416,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val bht_wr_data2 = dec_tlu_br0_hist_wb val bht_wr_data2 = dec_tlu_br0_hist_wb
// Hash each read and write address // Hash each read and write address
val mp_hashed = el2_btb_ghr_hash(Cat(exu_mp_addr,0.U(2.W)), io.exu_mp_eghr) val mp_hashed = el2_btb_ghr_hash(Cat(exu_mp_addr,0.U(2.W)), io.exu_bp.exu_mp_eghr)
val br0_hashed_wb = el2_btb_ghr_hash(Cat(dec_tlu_br0_addr_wb,0.U(2.W)), exu_i0_br_fghr_wb) val br0_hashed_wb = el2_btb_ghr_hash(Cat(dec_tlu_br0_addr_wb,0.U(2.W)), exu_i0_br_fghr_wb)
val bht_rd_addr_hashed_f = el2_btb_ghr_hash(Cat(btb_rd_addr_f,0.U(2.W)), fghr) val bht_rd_addr_hashed_f = el2_btb_ghr_hash(Cat(btb_rd_addr_f,0.U(2.W)), fghr)
val bht_rd_addr_hashed_p1_f = el2_btb_ghr_hash(Cat(btb_rd_addr_p1_f,0.U(2.W)), fghr) val bht_rd_addr_hashed_p1_f = el2_btb_ghr_hash(Cat(btb_rd_addr_p1_f,0.U(2.W)), fghr)
@ -471,4 +476,3 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
object ifu_bp extends App { object ifu_bp extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl())) println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl()))
} }

7
src/main/scala/ifu/el2_ifu_compress_ctl.scala
View File

@ -172,7 +172,6 @@ class el2_ifu_compress_ctl extends Module with el2_lib{
io.dout:= l3 & repl(32, legal) io.dout:= l3 & repl(32, legal)
} }
object compress extends App {
object ifu_compress extends App { (new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl())
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl())) }
}

64
src/main/scala/ifu/el2_ifu_ifc_ctl.scala
View File

@ -3,6 +3,17 @@ import lib._
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
class dec_ifc extends Bundle{
val dec_tlu_flush_noredir_wb = Input(Bool())
val dec_tlu_mrac_ff = Input(UInt(32.W))
val ifu_pmu_fetch_stall = Output(Bool())
}
class exu_ifc extends Bundle{
val exu_flush_final = Input(Bool())
val exu_flush_path_final = Input(UInt(31.W))
}
class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset { class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{ val io = IO(new Bundle{
val free_clk = Input(Clock()) val free_clk = Input(Clock())
@ -12,21 +23,18 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
val ifu_ic_mb_empty = Input(Bool()) val ifu_ic_mb_empty = Input(Bool())
val ifu_fb_consume1 = Input(Bool()) val ifu_fb_consume1 = Input(Bool())
val ifu_fb_consume2 = Input(Bool()) val ifu_fb_consume2 = Input(Bool())
val dec_tlu_flush_noredir_wb = Input(Bool()) val exu_ifc = new exu_ifc()
val exu_flush_final = Input(Bool())
val exu_flush_path_final = Input(UInt(31.W))
val ifu_bp_hit_taken_f = Input(Bool()) val ifu_bp_hit_taken_f = Input(Bool())
val ifu_bp_btb_target_f = Input(UInt(31.W)) val ifu_bp_btb_target_f = Input(UInt(31.W))
val ic_dma_active = Input(Bool()) val ic_dma_active = Input(Bool())
val ic_write_stall = Input(Bool()) val ic_write_stall = Input(Bool())
val dma_iccm_stall_any = Input(Bool()) val dma_iccm_stall_any = Input(Bool())
val dec_tlu_mrac_ff = Input(UInt(32.W)) val dec_ifc = new dec_ifc()
val ifc_fetch_addr_f = Output(UInt(31.W)) val ifc_fetch_addr_f = Output(UInt(31.W))
val ifc_fetch_addr_bf = Output(UInt(31.W)) val ifc_fetch_addr_bf = Output(UInt(31.W))
val ifc_fetch_req_f = Output(Bool()) val ifc_fetch_req_f = Output(Bool())
val ifu_pmu_fetch_stall = Output(Bool())
val ifc_fetch_uncacheable_bf = Output(Bool()) val ifc_fetch_uncacheable_bf = Output(Bool())
val ifc_fetch_req_bf = Output(Bool()) val ifc_fetch_req_bf = Output(Bool())
val ifc_fetch_req_bf_raw = Output(Bool()) val ifc_fetch_req_bf_raw = Output(Bool())
@ -64,15 +72,15 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
miss_a := withClock(io.free_clk) {RegNext(miss_f, init=0.U)} miss_a := withClock(io.free_clk) {RegNext(miss_f, init=0.U)}
val sel_last_addr_bf = !io.exu_flush_final & (!io.ifc_fetch_req_f | !io.ic_hit_f) val sel_last_addr_bf = !io.exu_ifc.exu_flush_final & (!io.ifc_fetch_req_f | !io.ic_hit_f)
val sel_btb_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f val sel_btb_addr_bf = !io.exu_ifc.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f
val sel_next_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f val sel_next_addr_bf = !io.exu_ifc.exu_flush_final & io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f
// TODO: Make an assertion for the 1H-Mux under here // TODO: Make an assertion for the 1H-Mux under here
io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_ifc.exu_flush_final.asBool -> io.exu_ifc.exu_flush_path_final, // Replay PC
sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC
sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC
sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4 sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
val address_upper = io.ifc_fetch_addr_f(30,1)+1.U val address_upper = io.ifc_fetch_addr_f(30,1)+1.U
fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-2) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0) fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-2) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
@ -82,17 +90,17 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
io.ifc_fetch_req_bf_raw := ~idle io.ifc_fetch_req_bf_raw := ~idle
io.ifc_fetch_req_bf := io.ifc_fetch_req_bf_raw & !(fb_full_f_ns & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) & io.ifc_fetch_req_bf := io.ifc_fetch_req_bf_raw & !(fb_full_f_ns & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) &
!dma_stall & !io.ic_write_stall & !io.dec_tlu_flush_noredir_wb !dma_stall & !io.ic_write_stall & !io.dec_ifc.dec_tlu_flush_noredir_wb
fetch_bf_en := io.exu_flush_final | io.ifc_fetch_req_f fetch_bf_en := io.exu_ifc.exu_flush_final | io.ifc_fetch_req_f
miss_f := io.ifc_fetch_req_f & !io.ic_hit_f & !io.exu_flush_final miss_f := io.ifc_fetch_req_f & !io.ic_hit_f & !io.exu_ifc.exu_flush_final
mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_flush_final) & !dma_stall & !miss_f & !miss_a mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_ifc.exu_flush_final) & !dma_stall & !miss_f & !miss_a
goto_idle := io.exu_flush_final & io.dec_tlu_flush_noredir_wb goto_idle := io.exu_ifc.exu_flush_final & io.dec_ifc.dec_tlu_flush_noredir_wb
leave_idle := io.exu_flush_final & !io.dec_tlu_flush_noredir_wb & idle leave_idle := io.exu_ifc.exu_flush_final & !io.dec_ifc.dec_tlu_flush_noredir_wb & idle
val next_state_1 = (!state(1) & state(0) & miss_f & !goto_idle) | val next_state_1 = (!state(1) & state(0) & miss_f & !goto_idle) |
(state(1) & !mb_empty_mod & !goto_idle) (state(1) & !mb_empty_mod & !goto_idle)
@ -101,7 +109,7 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
state := withClock(io.active_clk) {RegNext(Cat(next_state_1, next_state_0), init = 0.U)} state := withClock(io.active_clk) {RegNext(Cat(next_state_1, next_state_0), init = 0.U)}
flush_fb := io.exu_flush_final flush_fb := io.exu_ifc.exu_flush_final
fb_right := ( io.ifu_fb_consume1 & !io.ifu_fb_consume2 & (!io.ifc_fetch_req_f | miss_f)) | fb_right := ( io.ifu_fb_consume1 & !io.ifu_fb_consume2 & (!io.ifc_fetch_req_f | miss_f)) |
(io.ifu_fb_consume2 & io.ifc_fetch_req_f) (io.ifu_fb_consume2 & io.ifc_fetch_req_f)
@ -123,8 +131,8 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
val fb_full_f = withClock(io.active_clk) {RegNext(fb_full_f_ns, init = 0.U)} val fb_full_f = withClock(io.active_clk) {RegNext(fb_full_f_ns, init = 0.U)}
fb_write_f := withClock(io.active_clk) {RegNext(fb_write_ns, 0.U)} fb_write_f := withClock(io.active_clk) {RegNext(fb_write_ns, 0.U)}
io.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw & io.dec_ifc.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw &
((fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall)) ((fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_ifc.exu_flush_final)) | dma_stall))
val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE) val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE)
rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U)) rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U))
@ -132,18 +140,16 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
io.ifc_iccm_access_bf := iccm_acc_in_range_bf io.ifc_iccm_access_bf := iccm_acc_in_range_bf
io.ifc_dma_access_ok := ( (!io.ifc_iccm_access_bf | io.ifc_dma_access_ok := ( (!io.ifc_iccm_access_bf |
(fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) | (fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) |
(wfm & !io.ifc_fetch_req_bf) | idle ) & !io.exu_flush_final) | dma_iccm_stall_any_f (wfm & !io.ifc_fetch_req_bf) | idle ) & !io.exu_ifc.exu_flush_final) | dma_iccm_stall_any_f
io.ifc_region_acc_fault_bf := !iccm_acc_in_range_bf & iccm_acc_in_region_bf io.ifc_region_acc_fault_bf := !iccm_acc_in_range_bf & iccm_acc_in_region_bf
io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U)) io.ifc_fetch_uncacheable_bf := ~io.dec_ifc.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U))
io.ifc_fetch_req_f := withClock(io.active_clk){RegNext(io.ifc_fetch_req_bf, init=0.U)} io.ifc_fetch_req_f := withClock(io.active_clk){RegNext(io.ifc_fetch_req_bf, init=0.U)}
io.ifc_fetch_addr_f := rvdffe(io.ifc_fetch_addr_bf, io.exu_flush_final|io.ifc_fetch_req_f, clock, io.scan_mode) io.ifc_fetch_addr_f := rvdffe(io.ifc_fetch_addr_bf, io.exu_ifc.exu_flush_final|io.ifc_fetch_req_f, clock, io.scan_mode)
//rvdffe(io.ifc_fetch_addr_bf,(io.exu_flush_final|io.ifc_fetch_req_f).asBool,clock,io.scan_mode)
} }
object ifu_ifc extends App { object ifc_ctl extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctl())) println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctl()))
} }

593
src/main/scala/ifu/el2_ifu_mem_ctl.scala
View File

@ -6,15 +6,78 @@ import lib._
import include._ import include._
import scala.math.pow import scala.math.pow
class axi_channels extends Bundle with el2_lib{
val aw = Decoupled(new write_addr())
val w = Decoupled(new write_data())
val b = Flipped(Decoupled(new write_resp()))
val ar = Decoupled(new read_addr())
val r = Flipped(Decoupled(new read_data()))
}
class read_addr extends Bundle with el2_lib { // read_address
val id = UInt(LSU_BUS_TAG.W)
val addr = UInt(32.W)
val region = UInt(4.W)
val len = UInt(8.W)
val size = UInt(3.W)
val burst = UInt(2.W)
val lock = Bool()
val cache = UInt(4.W)
val prot = UInt(3.W)
val qos = UInt(4.W)
}
class read_data extends Bundle with el2_lib { // read_data
val id = UInt(LSU_BUS_TAG.W)
val data = UInt(64.W)
val resp = UInt(2.W)
val last = Bool()
}
class write_addr extends Bundle with el2_lib { // write_address
val id = UInt(LSU_BUS_TAG.W)
val addr = UInt(32.W)
val region = UInt(4.W)
val len = UInt(8.W)
val size = UInt(3.W)
val burst = UInt(2.W)
val lock = Bool()
val cache = UInt(4.W)
val prot = UInt(3.W)
val qos = UInt(4.W)
}
class write_data extends Bundle with el2_lib{ // write_data
val data = UInt(64.W)
val strb = UInt(8.W)
val last = Bool()
}
class write_resp extends Bundle with el2_lib{ // write_response
val resp = UInt(2.W)
val id = UInt(LSU_BUS_TAG.W)
}
@chiselName @chiselName
class mem_ctl_bundle extends Bundle with el2_lib{ class dec_mem_ctrl extends Bundle with el2_lib{
val free_clk = Input(Clock())
val active_clk = Input(Clock())
val exu_flush_final = Input(Bool())
val dec_tlu_flush_lower_wb = Input(Bool()) val dec_tlu_flush_lower_wb = Input(Bool())
val dec_tlu_flush_err_wb = Input(Bool()) val dec_tlu_flush_err_wb = Input(Bool())
val dec_tlu_i0_commit_cmt = Input(Bool()) val dec_tlu_i0_commit_cmt = Input(Bool())
val dec_tlu_force_halt = Input(Bool()) val dec_tlu_force_halt = Input(Bool())
val dec_tlu_fence_i_wb = Input(Bool())
val dec_tlu_ic_diag_pkt = Input(new el2_cache_debug_pkt_t)
val dec_tlu_core_ecc_disable = Input(Bool())
val ifu_pmu_ic_miss = Output(Bool())
val ifu_pmu_ic_hit = Output(Bool())
val ifu_pmu_bus_error = Output(Bool())
val ifu_pmu_bus_busy = Output(Bool())
val ifu_pmu_bus_trxn = Output(Bool())
val ifu_ic_error_start = Output(Bool())
val ifu_iccm_rd_ecc_single_err = Output(Bool())
val ifu_ic_debug_rd_data = Output(UInt(71.W))
val ifu_ic_debug_rd_data_valid = Output(Bool())
val ifu_miss_state_idle = Output(Bool())
}
class mem_ctl_bundle extends Bundle with el2_lib{
val free_clk = Input(Clock())
val active_clk = Input(Clock())
val exu_flush_final = Input(Bool())
val dec_mem_ctrl = new dec_mem_ctrl
val ifc_fetch_addr_bf = Input(UInt(31.W)) val ifc_fetch_addr_bf = Input(UInt(31.W))
val ifc_fetch_uncacheable_bf = Input(Bool()) val ifc_fetch_uncacheable_bf = Input(Bool())
val ifc_fetch_req_bf = Input(Bool()) val ifc_fetch_req_bf = Input(Bool())
@ -22,14 +85,9 @@ class mem_ctl_bundle extends Bundle with el2_lib{
val ifc_iccm_access_bf = Input(Bool()) val ifc_iccm_access_bf = Input(Bool())
val ifc_region_acc_fault_bf = Input(Bool()) val ifc_region_acc_fault_bf = Input(Bool())
val ifc_dma_access_ok = Input(Bool()) val ifc_dma_access_ok = Input(Bool())
val dec_tlu_fence_i_wb = Input(Bool())
val ifu_bp_hit_taken_f = Input(Bool()) val ifu_bp_hit_taken_f = Input(Bool())
val ifu_bp_inst_mask_f = Input(Bool()) val ifu_bp_inst_mask_f = Input(Bool())
val ifu_axi_arready = Input(Bool()) val ifu_axi = new axi_channels()
val ifu_axi_rvalid = Input(Bool())
val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
val ifu_axi_rdata = Input(UInt(64.W))
val ifu_axi_rresp = Input(UInt(2.W))
val ifu_bus_clk_en = Input(Bool()) val ifu_bus_clk_en = Input(Bool())
val dma_iccm_req = Input(Bool()) val dma_iccm_req = Input(Bool())
val dma_mem_addr = Input(UInt(32.W)) val dma_mem_addr = Input(UInt(32.W))
@ -47,48 +105,11 @@ class mem_ctl_bundle extends Bundle with el2_lib{
val iccm_rd_data = Input(UInt(64.W)) val iccm_rd_data = Input(UInt(64.W))
val iccm_rd_data_ecc = Input(UInt(78.W)) val iccm_rd_data_ecc = Input(UInt(78.W))
val ifu_fetch_val = Input(UInt(2.W)) val ifu_fetch_val = Input(UInt(2.W))
val dec_tlu_ic_diag_pkt = Input(new el2_cache_debug_pkt_t)
val ifu_miss_state_idle = Output(Bool())
val ifu_ic_mb_empty = Output(Bool()) val ifu_ic_mb_empty = Output(Bool())
val ic_dma_active = Output(Bool()) val ic_dma_active = Output(Bool())
val ic_write_stall = Output(Bool()) val ic_write_stall = Output(Bool())
val ifu_pmu_ic_miss = Output(Bool())
val ifu_pmu_ic_hit = Output(Bool())
val ifu_pmu_bus_error = Output(Bool())
val ifu_pmu_bus_busy = Output(Bool())
val ifu_pmu_bus_trxn = Output(Bool())
val ifu_axi_awvalid = Output(Bool())
val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_awaddr = Output(UInt(32.W))
val ifu_axi_awregion = Output(UInt(4.W))
val ifu_axi_awlen = Output(UInt(8.W))
val ifu_axi_awsize = Output(UInt(3.W))
val ifu_axi_awburst = Output(UInt(2.W))
val ifu_axi_awlock = Output(Bool())
val ifu_axi_awcache = Output(UInt(4.W))
val ifu_axi_awprot = Output(UInt(3.W))
val ifu_axi_awqos = Output(UInt(4.W))
val ifu_axi_wvalid = Output(Bool())
val ifu_axi_wdata = Output(UInt(64.W))
val ifu_axi_wstrb = Output(UInt(8.W))
val ifu_axi_wlast = Output(Bool())
val ifu_axi_bready = Output(Bool())
val ifu_axi_arvalid = Output(Bool())
val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_araddr = Output(UInt(32.W))
val ifu_axi_arregion = Output(UInt(4.W))
val ifu_axi_arlen = Output(UInt(8.W))
val ifu_axi_arsize = Output(UInt(3.W))
val ifu_axi_arburst = Output(UInt(2.W))
val ifu_axi_arlock = Output(Bool())
val ifu_axi_arcache = Output(UInt(4.W))
val ifu_axi_arprot = Output(UInt(3.W))
val ifu_axi_arqos = Output(UInt(4.W))
val ifu_axi_rready = Output(Bool())
val iccm_dma_ecc_error = Output(Bool()) val iccm_dma_ecc_error = Output(Bool())
val iccm_dma_rvalid = Output(Bool()) val iccm_dma_rvalid = Output(Bool())
val iccm_dma_rdata = Output(UInt(64.W)) val iccm_dma_rdata = Output(UInt(64.W))
@ -99,7 +120,6 @@ class mem_ctl_bundle extends Bundle with el2_lib{
val ic_rd_en = Output(Bool()) val ic_rd_en = Output(Bool())
val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W))) val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
val ic_debug_wr_data = Output(UInt(71.W)) val ic_debug_wr_data = Output(UInt(71.W))
val ifu_ic_debug_rd_data = Output(UInt(71.W))
val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W)) val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W))
val ic_debug_rd_en = Output(Bool()) val ic_debug_rd_en = Output(Bool())
val ic_debug_wr_en = Output(Bool()) val ic_debug_wr_en = Output(Bool())
@ -114,44 +134,39 @@ class mem_ctl_bundle extends Bundle with el2_lib{
val ic_hit_f = Output(Bool()) val ic_hit_f = Output(Bool())
val ic_access_fault_f = Output(Bool()) val ic_access_fault_f = Output(Bool())
val ic_access_fault_type_f = Output(UInt(2.W)) val ic_access_fault_type_f = Output(UInt(2.W))
val iccm_rd_ecc_single_err = Output(Bool())
val iccm_rd_ecc_double_err = Output(Bool()) val iccm_rd_ecc_double_err = Output(Bool())
val ic_error_start = Output(Bool())
val ifu_async_error_start = Output(Bool()) val ifu_async_error_start = Output(Bool())
val iccm_dma_sb_error = Output(Bool()) val iccm_dma_sb_error = Output(Bool())
val ic_fetch_val_f = Output(UInt(2.W)) val ic_fetch_val_f = Output(UInt(2.W))
val ic_data_f = Output(UInt(32.W)) val ic_data_f = Output(UInt(32.W))
val ic_premux_data = Output(UInt(64.W)) val ic_premux_data = Output(UInt(64.W))
val ic_sel_premux_data = Output(Bool()) val ic_sel_premux_data = Output(Bool())
val dec_tlu_core_ecc_disable = Input(Bool())
val ifu_ic_debug_rd_data_valid = Output(Bool())
val iccm_buf_correct_ecc = Output(Bool()) val iccm_buf_correct_ecc = Output(Bool())
val iccm_correction_state = Output(Bool()) val iccm_correction_state = Output(Bool())
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
} }
class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset { class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val io = IO(new mem_ctl_bundle) val io = IO(new mem_ctl_bundle)
io.ifu_axi_wvalid := 0.U io.ifu_axi.w.valid := 0.U
io.ifu_axi_wdata := 0.U io.ifu_axi.w.bits.data := 0.U
io.ifu_axi_awqos := 0.U io.ifu_axi.aw.bits.qos := 0.U
io.ifu_axi_awaddr := 0.U io.ifu_axi.aw.bits.addr := 0.U
io.ifu_axi_awprot := 0.U io.ifu_axi.aw.bits.prot := 0.U
io.ifu_axi_awlen := 0.U io.ifu_axi.aw.bits.len := 0.U
io.ifu_axi_arlock := 0.U io.ifu_axi.ar.bits.lock := 0.U
io.ifu_axi_awregion := 0.U io.ifu_axi.aw.bits.region := 0.U
io.ifu_axi_awid := 0.U io.ifu_axi.aw.bits.id := 0.U
io.ifu_axi_awvalid := 0.U io.ifu_axi.aw.valid := 0.U
io.ifu_axi_wstrb := 0.U io.ifu_axi.w.bits.strb := 0.U
io.ifu_axi_awcache := 0.U io.ifu_axi.aw.bits.cache := 0.U
io.ifu_axi_arqos := 0.U io.ifu_axi.ar.bits.qos := 0.U
io.ifu_axi_awlock := 0.U io.ifu_axi.aw.bits.lock := 0.U
io.ifu_axi_bready := 0.U io.ifu_axi.b.ready := 0.U
io.ifu_axi_arlen := 0.U io.ifu_axi.ar.bits.len := 0.U
io.ifu_axi_awsize := 0.U io.ifu_axi.aw.bits.size := 0.U
io.ifu_axi_arprot := 0.U io.ifu_axi.ar.bits.prot := 0.U
io.ifu_axi_awburst := 0.U io.ifu_axi.aw.bits.burst := 0.U
io.ifu_axi_wlast := 0.U io.ifu_axi.w.bits.last := 0.U
val idle_C :: crit_byp_ok_C :: hit_u_miss_C :: miss_wait_C :: crit_wrd_rdy_C :: scnd_miss_C :: stream_C :: stall_scnd_miss_C :: Nil = Enum(8) val idle_C :: crit_byp_ok_C :: hit_u_miss_C :: miss_wait_C :: crit_wrd_rdy_C :: scnd_miss_C :: stream_C :: stall_scnd_miss_C :: Nil = Enum(8)
val err_stop_idle_C :: err_fetch1_C :: err_fetch2_C :: err_stop_fetch_C :: Nil = Enum(4) val err_stop_idle_C :: err_fetch1_C :: err_fetch2_C :: err_stop_fetch_C :: Nil = Enum(4)
val err_idle_C :: ic_wff_C :: ecc_wff_C :: ecc_cor_C :: dma_sb_err_C :: Nil = Enum(5) val err_idle_C :: ic_wff_C :: ecc_wff_C :: ecc_cor_C :: dma_sb_err_C :: Nil = Enum(5)
@ -189,8 +204,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val debug_c1_clk = rvclkhdr(clock, debug_c1_clken, io.scan_mode) val debug_c1_clk = rvclkhdr(clock, debug_c1_clken, io.scan_mode)
val fetch_bf_f_c1_clk = rvclkhdr(clock, fetch_bf_f_c1_clken, io.scan_mode) val fetch_bf_f_c1_clk = rvclkhdr(clock, fetch_bf_f_c1_clken, io.scan_mode)
io.iccm_dma_sb_error := iccm_single_ecc_error.orR() & dma_iccm_req_f.asBool() io.iccm_dma_sb_error := iccm_single_ecc_error.orR() & dma_iccm_req_f.asBool()
io.ifu_async_error_start := io.iccm_rd_ecc_single_err | io.ic_error_start io.ifu_async_error_start := io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err | io.dec_mem_ctrl.ifu_ic_error_start
io.ic_dma_active := iccm_correct_ecc | (perr_state === dma_sb_err_C) | (err_stop_state === err_stop_fetch_C) | err_stop_fetch | io.dec_tlu_flush_err_wb io.ic_dma_active := iccm_correct_ecc | (perr_state === dma_sb_err_C) | (err_stop_state === err_stop_fetch_C) | err_stop_fetch | io.dec_mem_ctrl.dec_tlu_flush_err_wb
val scnd_miss_req_in = ifu_bus_rsp_valid & bus_ifu_bus_clk_en & ifu_bus_rsp_ready & (bus_new_data_beat_count.andR) & val scnd_miss_req_in = ifu_bus_rsp_valid & bus_ifu_bus_clk_en & ifu_bus_rsp_ready & (bus_new_data_beat_count.andR) &
!uncacheable_miss_ff & ((miss_state === scnd_miss_C)|(miss_nxtstate === scnd_miss_C)) & !io.exu_flush_final !uncacheable_miss_ff & ((miss_state === scnd_miss_C)|(miss_nxtstate === scnd_miss_C)) & !io.exu_flush_final
@ -200,45 +215,45 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
switch(miss_state){ switch(miss_state){
is (idle_C){ is (idle_C){
miss_nxtstate := Mux((ic_act_miss_f & !io.exu_flush_final).asBool, crit_byp_ok_C, hit_u_miss_C) miss_nxtstate := Mux((ic_act_miss_f & !io.exu_flush_final).asBool, crit_byp_ok_C, hit_u_miss_C)
miss_state_en := ic_act_miss_f & !io.dec_tlu_force_halt} miss_state_en := ic_act_miss_f & !io.dec_mem_ctrl.dec_tlu_force_halt}
is (crit_byp_ok_C){ is (crit_byp_ok_C){
miss_nxtstate := Mux((io.dec_tlu_force_halt | (ic_byp_hit_f & (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) & uncacheable_miss_ff)).asBool, idle_C, miss_nxtstate := Mux((io.dec_mem_ctrl.dec_tlu_force_halt | (ic_byp_hit_f & (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) & uncacheable_miss_ff)).asBool, idle_C,
Mux((ic_byp_hit_f & !last_data_recieved_ff & uncacheable_miss_ff).asBool, miss_wait_C, Mux((ic_byp_hit_f & !last_data_recieved_ff & uncacheable_miss_ff).asBool, miss_wait_C,
Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & uncacheable_miss_ff).asBool, crit_wrd_rdy_C, Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & uncacheable_miss_ff).asBool, crit_wrd_rdy_C,
Mux(((bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C, Mux(((bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
Mux((ic_byp_hit_f & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C, Mux((ic_byp_hit_f & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C,
Mux((bus_ifu_wr_en_ff & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C, Mux((bus_ifu_wr_en_ff & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C,
Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C, Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C)))))))) Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C))))))))
miss_state_en := io.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff) miss_state_en := io.dec_mem_ctrl.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff)
} }
is (crit_wrd_rdy_C){ is (crit_wrd_rdy_C){
miss_nxtstate := idle_C miss_nxtstate := idle_C
miss_state_en := io.exu_flush_final | flush_final_f | ic_byp_hit_f | io.dec_tlu_force_halt miss_state_en := io.exu_flush_final | flush_final_f | ic_byp_hit_f | io.dec_mem_ctrl.dec_tlu_force_halt
} }
is (stream_C){ is (stream_C){
miss_nxtstate := Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f)&(!(bus_ifu_wr_en_ff & last_beat)) & !io.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C) miss_nxtstate := Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f)&(!(bus_ifu_wr_en_ff & last_beat)) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C)
miss_state_en := io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f | (bus_ifu_wr_en_ff & last_beat) | io.dec_tlu_force_halt miss_state_en := io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f | (bus_ifu_wr_en_ff & last_beat) | io.dec_mem_ctrl.dec_tlu_force_halt
} }
is (miss_wait_C){ is (miss_wait_C){
miss_nxtstate := Mux((io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C) miss_nxtstate := Mux((io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C)
miss_state_en := io.exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | io.dec_tlu_force_halt miss_state_en := io.exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | io.dec_mem_ctrl.dec_tlu_force_halt
} }
is (hit_u_miss_C){ is (hit_u_miss_C){
miss_nxtstate := Mux((ic_miss_under_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, scnd_miss_C, miss_nxtstate := Mux((ic_miss_under_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, scnd_miss_C,
Mux((ic_ignore_2nd_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, stall_scnd_miss_C, idle_C)) Mux((ic_ignore_2nd_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, stall_scnd_miss_C, idle_C))
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | io.dec_tlu_force_halt miss_state_en := (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | io.dec_mem_ctrl.dec_tlu_force_halt
} }
is (scnd_miss_C){ is (scnd_miss_C){
miss_nxtstate := Mux(io.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final, miss_nxtstate := Mux(io.dec_mem_ctrl.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final,
Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), crit_byp_ok_C)) Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), crit_byp_ok_C))
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_tlu_force_halt miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_force_halt
} }
is (stall_scnd_miss_C){ is (stall_scnd_miss_C){
miss_nxtstate := Mux(io.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final, miss_nxtstate := Mux(io.dec_mem_ctrl.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final,
Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), idle_C)) Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), idle_C))
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_tlu_force_halt miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_force_halt
} }
} }
miss_state := withClock(io.free_clk){RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)} miss_state := withClock(io.free_clk){RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)}
@ -254,7 +269,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
miss_pending := miss_state =/= idle_C miss_pending := miss_state =/= idle_C
val crit_wd_byp_ok_ff = (miss_state === crit_byp_ok_C) | ((miss_state === crit_wrd_rdy_C) & !flush_final_f) val crit_wd_byp_ok_ff = (miss_state === crit_byp_ok_C) | ((miss_state === crit_wrd_rdy_C) & !flush_final_f)
val sel_hold_imb = (miss_pending & !(bus_ifu_wr_en_ff & last_beat) & !((miss_state === crit_wrd_rdy_C) & io.exu_flush_final) & val sel_hold_imb = (miss_pending & !(bus_ifu_wr_en_ff & last_beat) & !((miss_state === crit_wrd_rdy_C) & io.exu_flush_final) &
!((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f | !((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f |
(miss_pending & (miss_nxtstate === crit_wrd_rdy_C)) (miss_pending & (miss_nxtstate === crit_wrd_rdy_C))
val sel_hold_imb_scnd = ((miss_state === scnd_miss_C) | ic_miss_under_miss_f) & !flush_final_f val sel_hold_imb_scnd = ((miss_state === scnd_miss_C) | ic_miss_under_miss_f) & !flush_final_f
@ -295,25 +310,25 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val way_status_mb_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status_mb_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status_rep_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status_rep_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status_mb_in = Mux((scnd_miss_req & !scnd_miss_index_match).asBool, way_status_mb_scnd_ff, val way_status_mb_in = Mux((scnd_miss_req & !scnd_miss_index_match).asBool, way_status_mb_scnd_ff,
Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new, Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new,
Mux(miss_pending.asBool, way_status_mb_ff, way_status))) Mux(miss_pending.asBool, way_status_mb_ff, way_status)))
val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
val tagv_mb_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) val tagv_mb_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val tagv_mb_in = Mux(scnd_miss_req.asBool, tagv_mb_scnd_ff | (Fill(ICACHE_NUM_WAYS, scnd_miss_index_match) & replace_way_mb_any.reverse.reduce(Cat(_,_))), val tagv_mb_in = Mux(scnd_miss_req.asBool, tagv_mb_scnd_ff | (Fill(ICACHE_NUM_WAYS, scnd_miss_index_match) & replace_way_mb_any.reverse.reduce(Cat(_,_))),
Mux(miss_pending.asBool, tagv_mb_ff, io.ic_tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags))) Mux(miss_pending.asBool, tagv_mb_ff, io.ic_tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags)))
val scnd_miss_req_q = WireInit(Bool(), false.B) val scnd_miss_req_q = WireInit(Bool(), false.B)
val reset_ic_ff = WireInit(Bool(), false.B) val reset_ic_ff = WireInit(Bool(), false.B)
val reset_ic_in = miss_pending & !scnd_miss_req_q & (reset_all_tags | reset_ic_ff) val reset_ic_in = miss_pending & !scnd_miss_req_q & (reset_all_tags | reset_ic_ff)
reset_ic_ff := withClock(io.free_clk){RegNext(reset_ic_in)} reset_ic_ff := withClock(io.free_clk){RegNext(reset_ic_in, false.B)}
val fetch_uncacheable_ff = withClock(io.active_clk){RegNext(io.ifc_fetch_uncacheable_bf, 0.U)} val fetch_uncacheable_ff = withClock(io.active_clk){RegNext(io.ifc_fetch_uncacheable_bf, 0.U)}
ifu_fetch_addr_int_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_fetch_addr_bf, 0.U)} ifu_fetch_addr_int_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_fetch_addr_bf, 0.U)}
val vaddr_f = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1, 0) val vaddr_f = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1, 0)
uncacheable_miss_ff := withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_in, 0.U)} uncacheable_miss_ff := withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_in, 0.U)}
imb_ff := withClock(fetch_bf_f_c1_clk){RegNext(imb_in)} imb_ff := withClock(fetch_bf_f_c1_clk){RegNext(imb_in, 0.U)}
val miss_addr = WireInit(UInt((31-ICACHE_BEAT_ADDR_HI).W), 0.U) val miss_addr = WireInit(UInt((31-ICACHE_BEAT_ADDR_HI).W), 0.U)
val miss_addr_in = Mux(!miss_pending, imb_ff(30, ICACHE_BEAT_ADDR_HI), val miss_addr_in = Mux(!miss_pending, imb_ff(30, ICACHE_BEAT_ADDR_HI),
Mux(scnd_miss_req_q.asBool, imb_scnd_ff(30, ICACHE_BEAT_ADDR_HI), miss_addr)) Mux(scnd_miss_req_q.asBool, imb_scnd_ff(30, ICACHE_BEAT_ADDR_HI), miss_addr))
val busclk_reset = rvclkhdr(clock, bus_ifu_bus_clk_en | ic_act_miss_f | io.dec_tlu_force_halt, io.scan_mode) val busclk_reset = rvclkhdr(clock, bus_ifu_bus_clk_en | ic_act_miss_f | io.dec_mem_ctrl.dec_tlu_force_halt, io.scan_mode)
miss_addr := withClock(busclk_reset) {RegNext(miss_addr_in, 0.U)} miss_addr := withClock(busclk_reset) {RegNext(miss_addr_in, 0.U)}
way_status_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(way_status_mb_in, 0.U)} way_status_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(way_status_mb_in, 0.U)}
tagv_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_in, 0.U)} tagv_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_in, 0.U)}
@ -327,14 +342,14 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val ifc_region_acc_fault_f = withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_region_acc_fault_bf, 0.U)} val ifc_region_acc_fault_f = withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_region_acc_fault_bf, 0.U)}
val ifu_ic_req_addr_f = Cat(miss_addr, ic_req_addr_bits_hi_3) val ifu_ic_req_addr_f = Cat(miss_addr, ic_req_addr_bits_hi_3)
io.ifu_ic_mb_empty := (((miss_state===hit_u_miss_C) | (miss_state===stream_C)) & !(bus_ifu_wr_en_ff & last_beat)) | !miss_pending io.ifu_ic_mb_empty := (((miss_state===hit_u_miss_C) | (miss_state===stream_C)) & !(bus_ifu_wr_en_ff & last_beat)) | !miss_pending
io.ifu_miss_state_idle := miss_state === idle_C io.dec_mem_ctrl.ifu_miss_state_idle := miss_state === idle_C
val write_ic_16_bytes = WireInit(Bool(), false.B) val write_ic_16_bytes = WireInit(Bool(), false.B)
val reset_tag_valid_for_miss = WireInit(Bool(), false.B) val reset_tag_valid_for_miss = WireInit(Bool(), false.B)
val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss
val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr -> Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)), val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr -> Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)),
!sel_mb_addr -> io.ifc_fetch_addr_bf)) !sel_mb_addr -> io.ifc_fetch_addr_bf))
val bus_ifu_wr_en_ff_q = WireInit(Bool(), false.B) val bus_ifu_wr_en_ff_q = WireInit(Bool(), false.B)
val sel_mb_status_addr = miss_pending & write_ic_16_bytes & !uncacheable_miss_ff & last_beat & bus_ifu_wr_en_ff_q val sel_mb_status_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff & last_beat & bus_ifu_wr_en_ff_q) | reset_tag_valid_for_miss
val ifu_status_wr_addr = Mux(sel_mb_status_addr, Cat(imb_ff(30, ICACHE_BEAT_ADDR_HI),ic_wr_addr_bits_hi_3, imb_ff(1,0)), ifu_fetch_addr_int_f) val ifu_status_wr_addr = Mux(sel_mb_status_addr, Cat(imb_ff(30, ICACHE_BEAT_ADDR_HI),ic_wr_addr_bits_hi_3, imb_ff(1,0)), ifu_fetch_addr_int_f)
io.ic_rw_addr := ifu_ic_rw_int_addr io.ic_rw_addr := ifu_ic_rw_int_addr
sel_mb_addr_ff := withClock(io.free_clk){RegNext(sel_mb_addr, 0.U)} sel_mb_addr_ff := withClock(io.free_clk){RegNext(sel_mb_addr, 0.U)}
@ -344,15 +359,15 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val ic_miss_buff_ecc = rvecc_encode_64(ic_miss_buff_half) val ic_miss_buff_ecc = rvecc_encode_64(ic_miss_buff_half)
val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U) val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U)
io.ic_wr_data := (0 until ICACHE_BANKS_WAY).map(i=>ic_wr_16bytes_data((i*(if(ICACHE_ECC) 71 else 68))+(if(ICACHE_ECC) 70 else 67),(if(ICACHE_ECC) 71 else 68)*i)) io.ic_wr_data := (0 until ICACHE_BANKS_WAY).map(i=>ic_wr_16bytes_data((i*(if(ICACHE_ECC) 71 else 68))+(if(ICACHE_ECC) 70 else 67),(if(ICACHE_ECC) 71 else 68)*i))
io.ic_debug_wr_data := io.dec_tlu_ic_diag_pkt.icache_wrdata io.ic_debug_wr_data := io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata
val ic_rd_parity_final_err = WireInit(Bool(), 0.U) val ic_rd_parity_final_err = WireInit(Bool(), 0.U)
io.ic_error_start := ((if(ICACHE_ECC)io.ic_eccerr.orR()else io.ic_parerr.orR()) & ic_act_hit_f) | ic_rd_parity_final_err io.dec_mem_ctrl.ifu_ic_error_start := ((if(ICACHE_ECC)io.ic_eccerr.orR()else io.ic_parerr.orR()) & ic_act_hit_f) | ic_rd_parity_final_err
val ic_debug_tag_val_rd_out = WireInit(Bool(), 0.U) val ic_debug_tag_val_rd_out = WireInit(Bool(), 0.U)
val ic_debug_ict_array_sel_ff = WireInit(Bool(), 0.U) val ic_debug_ict_array_sel_ff = WireInit(Bool(), 0.U)
val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ictag_debug_rd_data(25,21),0.U(32.W),io.ictag_debug_rd_data(20,0), 0.U((7-ICACHE_STATUS_BITS).W), way_status, 0.U(3.W),ic_debug_tag_val_rd_out) val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ictag_debug_rd_data(25,21),0.U(32.W),io.ictag_debug_rd_data(20,0), 0.U((7-ICACHE_STATUS_BITS).W), way_status, 0.U(3.W),ic_debug_tag_val_rd_out)
else Cat(0.U(6.W),io.ictag_debug_rd_data(21),0.U(32.W),io.ictag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) , else Cat(0.U(6.W),io.ictag_debug_rd_data(21),0.U(32.W),io.ictag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) ,
io.ic_debug_rd_data) io.ic_debug_rd_data)
io.ifu_ic_debug_rd_data := withClock(debug_data_clk){RegNext(ifu_ic_debug_rd_data_in, 0.U)} io.dec_mem_ctrl.ifu_ic_debug_rd_data := withClock(debug_data_clk){RegNext(ifu_ic_debug_rd_data_in, 0.U)}
val ic_wr_parity = (0 until 4).map(i=>rveven_paritygen(ifu_bus_rdata_ff((16*i)+15,16*i))).reverse.reduce(Cat(_,_)) val ic_wr_parity = (0 until 4).map(i=>rveven_paritygen(ifu_bus_rdata_ff((16*i)+15,16*i))).reverse.reduce(Cat(_,_))
val ic_miss_buff_parity = (0 until 4).map(i=>rveven_paritygen(ic_miss_buff_half((16*i)+15,16*i))).reverse.reduce(Cat(_,_)) val ic_miss_buff_parity = (0 until 4).map(i=>rveven_paritygen(ic_miss_buff_half((16*i)+15,16*i))).reverse.reduce(Cat(_,_))
@ -373,8 +388,14 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val sel_iccm_data = fetch_req_iccm_f val sel_iccm_data = fetch_req_iccm_f
val ic_byp_data_only_new = WireInit(UInt(80.W), 0.U) val ic_byp_data_only_new = WireInit(UInt(80.W), 0.U)
val ic_final_data = Mux1H(Seq((sel_byp_data | (if(ICCM_ICACHE) (sel_iccm_data | sel_ic_data) else if(ICACHE_ONLY) sel_ic_data else 0.U)).asBool-> val final_data_sel1 = VecInit(sel_byp_data | sel_iccm_data | sel_ic_data, sel_byp_data, sel_byp_data | sel_ic_data, sel_byp_data)
(if(ICCM_ICACHE) io.ic_rd_data else ic_byp_data_only_new(63,0)))) val final_data_sel2 = VecInit(true.B, sel_iccm_data, true.B, true.B)
val final_data_out1 = VecInit(io.ic_rd_data, ic_byp_data_only_new, io.ic_rd_data, ic_byp_data_only_new)
val final_data_out2 = VecInit(1.U, io.iccm_rd_data, 1.U, 1.U)
val ic_final_data = if(ICCM_ICACHE) Fill(64, sel_byp_data | sel_iccm_data | sel_ic_data) & io.ic_rd_data else
if (ICCM_ONLY) (Fill(64, sel_byp_data) & ic_byp_data_only_new) | (Fill(64, sel_iccm_data) & io.iccm_rd_data) else
if (ICACHE_ONLY) Fill(64, sel_byp_data | sel_ic_data) & io.ic_rd_data else
if (NO_ICCM_NO_ICACHE) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
val ic_premux_data_temp = if(ICCM_ICACHE) (Fill(64,sel_iccm_data) & io.iccm_rd_data) | (Fill(64, sel_byp_data) & ic_byp_data_only_new) val ic_premux_data_temp = if(ICCM_ICACHE) (Fill(64,sel_iccm_data) & io.iccm_rd_data) | (Fill(64, sel_byp_data) & ic_byp_data_only_new)
else if(ICACHE_ONLY) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U else if(ICACHE_ONLY) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
val ic_sel_premux_data_temp = if(ICCM_ICACHE) sel_iccm_data | sel_byp_data else if(ICACHE_ONLY) sel_byp_data else 0.U val ic_sel_premux_data_temp = if(ICCM_ICACHE) sel_iccm_data | sel_byp_data else if(ICACHE_ONLY) sel_byp_data else 0.U
@ -399,8 +420,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val ic_miss_buff_data = Wire(Vec(2*ICACHE_NUM_BEATS, UInt(32.W))) val ic_miss_buff_data = Wire(Vec(2*ICACHE_NUM_BEATS, UInt(32.W)))
for(i<- 0 until ICACHE_NUM_BEATS){ for(i<- 0 until ICACHE_NUM_BEATS){
val wr_data_c1_clk = write_fill_data.map(rvclkhdr(clock, _ , io.scan_mode)) val wr_data_c1_clk = write_fill_data.map(rvclkhdr(clock, _ , io.scan_mode))
ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)} ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)}
ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}} ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}}
val ic_miss_buff_data_valid = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U) val ic_miss_buff_data_valid = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U)
val ic_miss_buff_data_valid_in = (0 until ICACHE_NUM_BEATS).map(i=>write_fill_data(i)|(ic_miss_buff_data_valid(i)&(!ic_act_miss_f))) val ic_miss_buff_data_valid_in = (0 until ICACHE_NUM_BEATS).map(i=>write_fill_data(i)|(ic_miss_buff_data_valid(i)&(!ic_act_miss_f)))
ic_miss_buff_data_valid := withClock(io.free_clk){RegNext(ic_miss_buff_data_valid_in.map(i=>i.asUInt()).reverse.reduce(Cat(_,_)), 0.U)} ic_miss_buff_data_valid := withClock(io.free_clk){RegNext(ic_miss_buff_data_valid_in.map(i=>i.asUInt()).reverse.reduce(Cat(_,_)), 0.U)}
@ -415,16 +436,16 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val bypass_index_5_3_inc = bypass_index(bypass_index.getWidth-1,2) + 1.U val bypass_index_5_3_inc = bypass_index(bypass_index.getWidth-1,2) + 1.U
val bypass_valid_value_check = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(bypass_index.getWidth-1,2)===i.U).asBool->ic_miss_buff_data_valid_in(i))) val bypass_valid_value_check = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(bypass_index.getWidth-1,2)===i.U).asBool->ic_miss_buff_data_valid_in(i)))
val bypass_data_ready_in = (bypass_valid_value_check & !bypass_index(1) & !bypass_index(0)) | val bypass_data_ready_in = (bypass_valid_value_check & !bypass_index(1) & !bypass_index(0)) |
(bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) | (bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) |
(bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) | (bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) |
(bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) | (bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) |
(bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U)) (bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U))
val ic_crit_wd_rdy_new_ff = WireInit(Bool(), 0.U) val ic_crit_wd_rdy_new_ff = WireInit(Bool(), 0.U)
val ic_crit_wd_rdy_new_in = (bypass_data_ready_in & crit_wd_byp_ok_ff & uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) | val ic_crit_wd_rdy_new_in = (bypass_data_ready_in & crit_wd_byp_ok_ff & uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) | ( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
(ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final) (ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final)
ic_crit_wd_rdy_new_ff := withClock(io.free_clk){RegNext(ic_crit_wd_rdy_new_in, 0.U)} ic_crit_wd_rdy_new_ff := withClock(io.free_clk){RegNext(ic_crit_wd_rdy_new_in, 0.U)}
val byp_fetch_index = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,0) val byp_fetch_index = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,0)
val byp_fetch_index_0 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 0.U) val byp_fetch_index_0 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 0.U)
@ -434,12 +455,12 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val byp_fetch_index_inc_1 = Cat(byp_fetch_index_inc, 1.U) val byp_fetch_index_inc_1 = Cat(byp_fetch_index_inc, 1.U)
val ic_miss_buff_data_error_bypass = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===i.U).asBool->ic_miss_buff_data_error(i))) val ic_miss_buff_data_error_bypass = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===i.U).asBool->ic_miss_buff_data_error(i)))
val ic_miss_buff_data_error_bypass_inc = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc===i.U).asBool->ic_miss_buff_data_error(i))) val ic_miss_buff_data_error_bypass_inc = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc===i.U).asBool->ic_miss_buff_data_error(i)))
ifu_byp_data_err_new := (!ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
(!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
when(ifu_fetch_addr_int_f(1)&ifu_fetch_addr_int_f(0)){ (!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
ifu_byp_data_err_new := ic_miss_buff_data_error_bypass ( ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
} otherwise{ifu_byp_data_err_new := ic_miss_buff_data_error_bypass | ic_miss_buff_data_error_bypass_inc} (ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & (ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2)) |
ic_miss_buff_data_error(byp_fetch_index_inc(ICACHE_BEAT_ADDR_HI-3,0))))
val ic_byp_data_only_pre_new = Mux(!ifu_fetch_addr_int_f(1).asBool, val ic_byp_data_only_pre_new = Mux(!ifu_fetch_addr_int_f(1).asBool,
Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_0===i.U).asBool->ic_miss_buff_data(i)(31,0)))), Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_0===i.U).asBool->ic_miss_buff_data(i)(31,0)))),
Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_1===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0))))) Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_1===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0)))))
@ -467,8 +488,6 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
ic_miss_buff_half := Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,1.U)===i.U).asBool->ic_miss_buff_data(i))), ic_miss_buff_half := Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,1.U)===i.U).asBool->ic_miss_buff_data(i))),
Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,0.U)===i.U).asBool->ic_miss_buff_data(i)))) Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,0.U)===i.U).asBool->ic_miss_buff_data(i))))
ic_rd_parity_final_err := io.ic_tag_perr & sel_ic_data & !(ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f) ic_rd_parity_final_err := io.ic_tag_perr & sel_ic_data & !(ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f)
val ifu_ic_rw_int_addr_ff = WireInit(UInt((ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO+1).W), 0.U) val ifu_ic_rw_int_addr_ff = WireInit(UInt((ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO+1).W), 0.U)
@ -488,21 +507,21 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val iccm_error_start = WireInit(Bool(), false.B) val iccm_error_start = WireInit(Bool(), false.B)
switch(perr_state){ switch(perr_state){
is(err_idle_C){ is(err_idle_C){
perr_nxtstate := Mux(io.iccm_dma_sb_error, dma_sb_err_C, Mux((io.ic_error_start & !io.exu_flush_final).asBool, ic_wff_C, ecc_wff_C)) perr_nxtstate := Mux(io.iccm_dma_sb_error, dma_sb_err_C, Mux((io.dec_mem_ctrl.ifu_ic_error_start & !io.exu_flush_final).asBool, ic_wff_C, ecc_wff_C))
perr_state_en := (((iccm_error_start | io.ic_error_start) & !io.exu_flush_final) | io.iccm_dma_sb_error) & !io.dec_tlu_force_halt perr_state_en := (((iccm_error_start | io.dec_mem_ctrl.ifu_ic_error_start) & !io.exu_flush_final) | io.iccm_dma_sb_error) & !io.dec_mem_ctrl.dec_tlu_force_halt
perr_sb_write_status := perr_state_en perr_sb_write_status := perr_state_en
} }
is(ic_wff_C){ is(ic_wff_C){
perr_nxtstate := err_idle_C perr_nxtstate := err_idle_C
perr_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_force_halt perr_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_force_halt
perr_sel_invalidate := io.dec_tlu_flush_lower_wb & io.dec_tlu_force_halt perr_sel_invalidate := io.dec_mem_ctrl.dec_tlu_flush_lower_wb & io.dec_mem_ctrl.dec_tlu_flush_err_wb
} }
is(ecc_wff_C){ is(ecc_wff_C){
perr_nxtstate := Mux(((!io.dec_tlu_flush_err_wb & io.dec_tlu_flush_lower_wb ) | io.dec_tlu_force_halt).asBool(), err_idle_C, ecc_cor_C) perr_nxtstate := Mux(((!io.dec_mem_ctrl.dec_tlu_flush_err_wb & io.dec_mem_ctrl.dec_tlu_flush_lower_wb ) | io.dec_mem_ctrl.dec_tlu_force_halt).asBool(), err_idle_C, ecc_cor_C)
perr_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_force_halt perr_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_force_halt
} }
is(dma_sb_err_C){ is(dma_sb_err_C){
perr_nxtstate := Mux(io.dec_tlu_force_halt, err_idle_C, ecc_cor_C) perr_nxtstate := Mux(io.dec_mem_ctrl.dec_tlu_force_halt, err_idle_C, ecc_cor_C)
perr_state_en := true.B perr_state_en := true.B
} }
is(ecc_cor_C){ is(ecc_cor_C){
@ -515,39 +534,39 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val err_stop_nxtstate = WireInit(UInt(2.W), 0.U) val err_stop_nxtstate = WireInit(UInt(2.W), 0.U)
val err_stop_state_en = WireInit(Bool(), false.B) val err_stop_state_en = WireInit(Bool(), false.B)
io.iccm_correction_state := false.B io.iccm_correction_state := false.B
// val err_stop_fetch := WireInit(Bool(), false.B) // val err_stop_fetch := WireInit(Bool(), false.B)
switch(err_stop_state){ switch(err_stop_state){
is(err_stop_idle_C){ is(err_stop_idle_C){
err_stop_nxtstate := err_fetch1_C err_stop_nxtstate := err_fetch1_C
err_stop_state_en := io.dec_tlu_flush_err_wb & (perr_state === ecc_wff_C) & !io.dec_tlu_force_halt err_stop_state_en := io.dec_mem_ctrl.dec_tlu_flush_err_wb & (perr_state === ecc_wff_C) & !io.dec_mem_ctrl.dec_tlu_force_halt
} }
is(err_fetch1_C){ is(err_fetch1_C){
err_stop_nxtstate := Mux((io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.dec_tlu_force_halt).asBool(), err_stop_idle_C, err_stop_nxtstate := Mux((io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool(), err_stop_idle_C,
Mux(((io.ifu_fetch_val===3.U)|(io.ifu_fetch_val(0)&two_byte_instr)).asBool(), err_stop_fetch_C, Mux(((io.ifu_fetch_val===3.U)|(io.ifu_fetch_val(0)&two_byte_instr)).asBool(), err_stop_fetch_C,
Mux(io.ifu_fetch_val(0).asBool(), err_fetch2_C, err_fetch1_C))) Mux(io.ifu_fetch_val(0).asBool(), err_fetch2_C, err_fetch1_C)))
err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | ifu_bp_hit_taken_q_f | io.dec_tlu_force_halt err_stop_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | ifu_bp_hit_taken_q_f | io.dec_mem_ctrl.dec_tlu_force_halt
err_stop_fetch := ((io.ifu_fetch_val(1,0)===3.U) | (io.ifu_fetch_val(0) & two_byte_instr)) & !(io.exu_flush_final | io.dec_tlu_i0_commit_cmt) err_stop_fetch := ((io.ifu_fetch_val(1,0)===3.U) | (io.ifu_fetch_val(0) & two_byte_instr)) & !(io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt)
io.iccm_correction_state := true.B io.iccm_correction_state := true.B
} }
is(err_fetch2_C){ is(err_fetch2_C){
err_stop_nxtstate := Mux((io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.dec_tlu_force_halt).asBool, err_stop_nxtstate := Mux((io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool,
err_stop_idle_C, Mux(io.ifu_fetch_val(0).asBool, err_stop_fetch_C, err_fetch2_C)) err_stop_idle_C, Mux(io.ifu_fetch_val(0).asBool, err_stop_fetch_C, err_fetch2_C))
err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | io.dec_tlu_force_halt err_stop_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | io.dec_mem_ctrl.dec_tlu_force_halt
err_stop_fetch := io.ifu_fetch_val(0) & !io.exu_flush_final & !io.dec_tlu_i0_commit_cmt err_stop_fetch := io.ifu_fetch_val(0) & !io.exu_flush_final & !io.dec_mem_ctrl.dec_tlu_i0_commit_cmt
io.iccm_correction_state := true.B io.iccm_correction_state := true.B
} }
is(err_stop_fetch_C){ is(err_stop_fetch_C){
err_stop_nxtstate := Mux(((io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_err_wb) | io.dec_tlu_i0_commit_cmt | io.dec_tlu_force_halt).asBool, err_stop_nxtstate := Mux(((io.dec_mem_ctrl.dec_tlu_flush_lower_wb & !io.dec_mem_ctrl.dec_tlu_flush_err_wb) | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool,
err_stop_idle_C, Mux(io.dec_tlu_flush_err_wb.asBool(), err_fetch1_C, err_stop_fetch_C)) err_stop_idle_C, Mux(io.dec_mem_ctrl.dec_tlu_flush_err_wb.asBool(), err_fetch1_C, err_stop_fetch_C))
err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.dec_tlu_force_halt err_stop_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt
err_stop_fetch := true.B err_stop_fetch := true.B
io.iccm_correction_state := true.B io.iccm_correction_state := true.B
} }
} }
err_stop_state := withClock(io.free_clk){RegEnable(err_stop_nxtstate, 0.U, err_stop_state_en)} err_stop_state := withClock(io.free_clk){RegEnable(err_stop_nxtstate, 0.U, err_stop_state_en)}
bus_ifu_bus_clk_en := io.ifu_bus_clk_en bus_ifu_bus_clk_en := io.ifu_bus_clk_en
val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode) val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode)
val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_tlu_force_halt , io.scan_mode) val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_mem_ctrl.dec_tlu_force_halt , io.scan_mode)
val bus_ifu_bus_clk_en_ff = withClock(io.free_clk){RegNext(bus_ifu_bus_clk_en, 0.U)} val bus_ifu_bus_clk_en_ff = withClock(io.free_clk){RegNext(bus_ifu_bus_clk_en, 0.U)}
scnd_miss_req_q := withClock(io.free_clk){RegNext(scnd_miss_req_in, 0.U)} scnd_miss_req_q := withClock(io.free_clk){RegNext(scnd_miss_req_in, 0.U)}
val scnd_miss_req_ff2 = withClock(io.free_clk){RegNext(scnd_miss_req, 0.U)} val scnd_miss_req_ff2 = withClock(io.free_clk){RegNext(scnd_miss_req, 0.U)}
@ -556,45 +575,45 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val ifu_bus_cmd_valid = WireInit(Bool(), false.B) val ifu_bus_cmd_valid = WireInit(Bool(), false.B)
val bus_cmd_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U) val bus_cmd_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
val ifu_bus_cmd_ready = WireInit(Bool(), false.B) val ifu_bus_cmd_ready = WireInit(Bool(), false.B)
val ifc_bus_ic_req_ff_in = (ic_act_miss_f | bus_cmd_req_hold | ifu_bus_cmd_valid) & !io.dec_tlu_force_halt & !((bus_cmd_beat_count===Fill(ICACHE_BEAT_BITS,1.U)) & ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending) val ifc_bus_ic_req_ff_in = (ic_act_miss_f | bus_cmd_req_hold | ifu_bus_cmd_valid) & !io.dec_mem_ctrl.dec_tlu_force_halt & !((bus_cmd_beat_count===Fill(ICACHE_BEAT_BITS,1.U)) & ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending)
ifu_bus_cmd_valid := withClock(busclk_force){RegNext(ifc_bus_ic_req_ff_in, 0.U)} ifu_bus_cmd_valid := withClock(busclk_force){RegNext(ifc_bus_ic_req_ff_in, 0.U)}
val bus_cmd_sent = WireInit(Bool(), false.B) val bus_cmd_sent = WireInit(Bool(), false.B)
val bus_cmd_req_in = (ic_act_miss_f | bus_cmd_req_hold) & !bus_cmd_sent & !io.dec_tlu_force_halt val bus_cmd_req_in = (ic_act_miss_f | bus_cmd_req_hold) & !bus_cmd_sent & !io.dec_mem_ctrl.dec_tlu_force_halt
bus_cmd_req_hold := withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)} bus_cmd_req_hold := withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)}
// AXI Read-Channel // AXI Read-Channel
io.ifu_axi_arvalid := ifu_bus_cmd_valid io.ifu_axi.ar.valid := ifu_bus_cmd_valid
io.ifu_axi_arid := bus_rd_addr_count & Fill(IFU_BUS_TAG, ifu_bus_cmd_valid) io.ifu_axi.ar.bits.id := bus_rd_addr_count & Fill(IFU_BUS_TAG, ifu_bus_cmd_valid)
io.ifu_axi_araddr := Cat(ifu_ic_req_addr_f, 0.U(3.W)) & Fill(32, ifu_bus_cmd_valid) io.ifu_axi.ar.bits.addr := Cat(ifu_ic_req_addr_f, 0.U(3.W)) & Fill(32, ifu_bus_cmd_valid)
io.ifu_axi_arsize := 3.U(3.W) io.ifu_axi.ar.bits.size := 3.U(3.W)
io.ifu_axi_arcache := 15.U io.ifu_axi.ar.bits.cache := 15.U
io.ifu_axi_arregion := ifu_ic_req_addr_f(28,25) io.ifu_axi.ar.bits.region := ifu_ic_req_addr_f(28,25)
io.ifu_axi_arburst := 1.U io.ifu_axi.ar.bits.burst := 1.U
io.ifu_axi_rready := true.B io.ifu_axi.r.ready := true.B
val ifu_bus_arready_unq = io.ifu_axi_arready val ifu_bus_arready_unq = io.ifu_axi.ar.ready
val ifu_bus_rvalid_unq = io.ifu_axi_rvalid val ifu_bus_rvalid_unq = io.ifu_axi.r.valid
val ifu_bus_arvalid = io.ifu_axi_arvalid val ifu_bus_arvalid = io.ifu_axi.ar.valid
bus_ifu_bus_clk_en bus_ifu_bus_clk_en
val ifu_bus_arready_unq_ff = withClock(busclk){RegNext(ifu_bus_arready_unq, false.B)} val ifu_bus_arready_unq_ff = withClock(busclk){RegNext(ifu_bus_arready_unq, false.B)}
val ifu_bus_rvalid_unq_ff = withClock(busclk){RegNext(ifu_bus_rvalid_unq, false.B)} val ifu_bus_rvalid_unq_ff = withClock(busclk){RegNext(ifu_bus_rvalid_unq, false.B)}
val ifu_bus_arvalid_ff = withClock(busclk){RegNext(ifu_bus_arvalid, false.B)} val ifu_bus_arvalid_ff = withClock(busclk){RegNext(ifu_bus_arvalid, false.B)}
val ifu_bus_rresp_ff = withClock(busclk){RegNext(io.ifu_axi_rresp, 0.U)} val ifu_bus_rresp_ff = withClock(busclk){RegNext(io.ifu_axi.r.bits.resp, 0.U)}
ifu_bus_rdata_ff := withClock(busclk){RegNext(io.ifu_axi_rdata, 0.U)} ifu_bus_rdata_ff := withClock(busclk){RegNext(io.ifu_axi.r.bits.data, 0.U)}
ifu_bus_rid_ff := withClock(busclk){RegNext(io.ifu_axi_rid, 0.U)} ifu_bus_rid_ff := withClock(busclk){RegNext(io.ifu_axi.r.bits.id, 0.U)}
ifu_bus_cmd_ready := io.ifu_axi_arready ifu_bus_cmd_ready := io.ifu_axi.ar.ready
ifu_bus_rsp_valid := io.ifu_axi_rvalid ifu_bus_rsp_valid := io.ifu_axi.r.valid
ifu_bus_rsp_ready := io.ifu_axi_rready ifu_bus_rsp_ready := io.ifu_axi.r.ready
ifu_bus_rsp_tag := io.ifu_axi_rid ifu_bus_rsp_tag := io.ifu_axi.r.bits.id
ifu_bus_rsp_rdata := io.ifu_axi_rdata ifu_bus_rsp_rdata := io.ifu_axi.r.bits.data
val ifu_bus_rsp_opc = io.ifu_axi_rresp val ifu_bus_rsp_opc = io.ifu_axi.r.bits.resp
val ifu_bus_rvalid = ifu_bus_rsp_valid & bus_ifu_bus_clk_en val ifu_bus_rvalid = ifu_bus_rsp_valid & bus_ifu_bus_clk_en
val ifu_bus_arready = ifu_bus_arready_unq & bus_ifu_bus_clk_en val ifu_bus_arready = ifu_bus_arready_unq & bus_ifu_bus_clk_en
val ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff val ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff
val ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff val ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff
bus_cmd_sent := ifu_bus_arvalid & ifu_bus_arready & miss_pending & !io.dec_tlu_force_halt bus_cmd_sent := ifu_bus_arvalid & ifu_bus_arready & miss_pending & !io.dec_mem_ctrl.dec_tlu_force_halt
val bus_last_data_beat = WireInit(Bool(), false.B) val bus_last_data_beat = WireInit(Bool(), false.B)
val bus_inc_data_beat_cnt = bus_ifu_wr_en_ff & !bus_last_data_beat & !io.dec_tlu_force_halt val bus_inc_data_beat_cnt = bus_ifu_wr_en_ff & !bus_last_data_beat & !io.dec_mem_ctrl.dec_tlu_force_halt
val bus_reset_data_beat_cnt = ic_act_miss_f | (bus_ifu_wr_en_ff & bus_last_data_beat) | io.dec_tlu_force_halt val bus_reset_data_beat_cnt = ic_act_miss_f | (bus_ifu_wr_en_ff & bus_last_data_beat) | io.dec_mem_ctrl.dec_tlu_force_halt
val bus_hold_data_beat_cnt = !bus_inc_data_beat_cnt & !bus_reset_data_beat_cnt val bus_hold_data_beat_cnt = !bus_inc_data_beat_cnt & !bus_reset_data_beat_cnt
val bus_data_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U) val bus_data_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
bus_new_data_beat_count := Mux1H(Seq(bus_reset_data_beat_cnt->0.U, bus_inc_data_beat_cnt-> (bus_data_beat_count + 1.U), bus_hold_data_beat_cnt->bus_data_beat_count)) bus_new_data_beat_count := Mux1H(Seq(bus_reset_data_beat_cnt->0.U, bus_inc_data_beat_cnt-> (bus_data_beat_count + 1.U), bus_hold_data_beat_cnt->bus_data_beat_count))
@ -603,15 +622,15 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
last_data_recieved_ff := withClock(io.free_clk){RegNext(last_data_recieved_in, 0.U)} last_data_recieved_ff := withClock(io.free_clk){RegNext(last_data_recieved_in, 0.U)}
// Request Address Count // Request Address Count
val bus_new_rd_addr_count = Mux(!miss_pending, imb_ff(ICACHE_BEAT_ADDR_HI-1, 2), val bus_new_rd_addr_count = Mux(!miss_pending, imb_ff(ICACHE_BEAT_ADDR_HI-1, 2),
Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2), Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2),
Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count))) Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count)))
bus_rd_addr_count := withClock(busclk_reset){RegNext(bus_new_rd_addr_count, 0.U)} bus_rd_addr_count := withClock(busclk_reset){RegNext(bus_new_rd_addr_count, 0.U)}
// Command beat Count // Command beat Count
val bus_inc_cmd_beat_cnt = ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending & !io.dec_tlu_force_halt val bus_inc_cmd_beat_cnt = ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending & !io.dec_mem_ctrl.dec_tlu_force_halt
val bus_reset_cmd_beat_cnt_0 = (ic_act_miss_f & !uncacheable_miss_in) | io.dec_tlu_force_halt val bus_reset_cmd_beat_cnt_0 = (ic_act_miss_f & !uncacheable_miss_in) | io.dec_mem_ctrl.dec_tlu_force_halt
val bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in val bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in
val bus_hold_cmd_beat_cnt = !bus_inc_cmd_beat_cnt & !(ic_act_miss_f | scnd_miss_req | io.dec_tlu_force_halt) val bus_hold_cmd_beat_cnt = !bus_inc_cmd_beat_cnt & !(ic_act_miss_f | scnd_miss_req | io.dec_mem_ctrl.dec_tlu_force_halt)
val bus_cmd_beat_en = bus_inc_cmd_beat_cnt | ic_act_miss_f | io.dec_tlu_force_halt val bus_cmd_beat_en = bus_inc_cmd_beat_cnt | ic_act_miss_f | io.dec_mem_ctrl.dec_tlu_force_halt
val bus_new_cmd_beat_count = Mux1H(Seq(bus_reset_cmd_beat_cnt_0->0.U, bus_reset_cmd_beat_cnt_secondlast.asBool->ICACHE_SCND_LAST.U, val bus_new_cmd_beat_count = Mux1H(Seq(bus_reset_cmd_beat_cnt_0->0.U, bus_reset_cmd_beat_cnt_secondlast.asBool->ICACHE_SCND_LAST.U,
bus_inc_cmd_beat_cnt->(bus_cmd_beat_count+1.U), bus_hold_cmd_beat_cnt->bus_cmd_beat_count)) bus_inc_cmd_beat_cnt->(bus_cmd_beat_count+1.U), bus_hold_cmd_beat_cnt->bus_cmd_beat_count))
bus_cmd_beat_count := withClock(busclk_reset){RegEnable(bus_new_cmd_beat_count, 0.U, bus_cmd_beat_en)} bus_cmd_beat_count := withClock(busclk_reset){RegEnable(bus_new_cmd_beat_count, 0.U, bus_cmd_beat_en)}
@ -670,21 +689,21 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val ic_fetch_val_shift_right = ic_fetch_val_int_f << ifu_fetch_addr_int_f(0) val ic_fetch_val_shift_right = ic_fetch_val_int_f << ifu_fetch_addr_int_f(0)
val iccm_rdmux_data = io.iccm_rd_data_ecc val iccm_rdmux_data = io.iccm_rd_data_ecc
val iccm_ecc_word_enable = (0 until 2).map(i=>((ic_fetch_val_shift_right((2*i+1),(2*i)) & !io.exu_flush_final & sel_iccm_data) | iccm_dma_rvalid_in) & !io.dec_tlu_core_ecc_disable).reverse.reduce(Cat(_,_)) val iccm_ecc_word_enable = (0 until 2).map(i=>((ic_fetch_val_shift_right((2*i+1),(2*i)).orR & !io.exu_flush_final & sel_iccm_data) | iccm_dma_rvalid_in) & !io.dec_mem_ctrl.dec_tlu_core_ecc_disable).reverse.reduce(Cat(_,_))
val ecc_decoded = (0 until 2).map(i=>rvecc_decode(iccm_ecc_word_enable(i), iccm_rdmux_data((39*i+31),(39*i)), iccm_rdmux_data((39*i+38),(39*i+32)), 0.U)) val ecc_decoded = (0 until 2).map(i=>rvecc_decode(iccm_ecc_word_enable(i), iccm_rdmux_data((39*i+31),(39*i)), iccm_rdmux_data((39*i+38),(39*i+32)), 0.U))
val iccm_corrected_ecc = Wire(Vec(2, UInt(7.W))) val iccm_corrected_ecc = Wire(Vec(2, UInt(7.W)))
iccm_corrected_ecc := VecInit(ecc_decoded(0)._1,ecc_decoded(1)._1) iccm_corrected_ecc := VecInit(ecc_decoded(0)._1,ecc_decoded(1)._1)
iccm_corrected_data := VecInit(ecc_decoded(0)._2,ecc_decoded(1)._2) iccm_corrected_data := VecInit(ecc_decoded(0)._2,ecc_decoded(1)._2)
iccm_single_ecc_error := Cat(ecc_decoded(0)._3,ecc_decoded(1)._3) iccm_single_ecc_error := Cat(ecc_decoded(1)._3,ecc_decoded(0)._3)
iccm_double_ecc_error := Cat(ecc_decoded(0)._4,ecc_decoded(1)._4) iccm_double_ecc_error := Cat(ecc_decoded(1)._4,ecc_decoded(0)._4)
io.iccm_rd_ecc_single_err := iccm_single_ecc_error.orR & ifc_iccm_access_f & ifc_fetch_req_f io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err := iccm_single_ecc_error.orR & ifc_iccm_access_f & ifc_fetch_req_f
io.iccm_rd_ecc_double_err := iccm_double_ecc_error.orR & ifc_iccm_access_f io.iccm_rd_ecc_double_err := iccm_double_ecc_error.orR & ifc_iccm_access_f
val iccm_corrected_data_f_mux = Mux(iccm_single_ecc_error(0).asBool, iccm_corrected_data(0), iccm_corrected_data(1)) val iccm_corrected_data_f_mux = Mux(iccm_single_ecc_error(0).asBool, iccm_corrected_data(0), iccm_corrected_data(1))
val iccm_corrected_ecc_f_mux = Mux(iccm_single_ecc_error(0).asBool, iccm_corrected_ecc(0), iccm_corrected_ecc(1)) val iccm_corrected_ecc_f_mux = Mux(iccm_single_ecc_error(0).asBool, iccm_corrected_ecc(0), iccm_corrected_ecc(1))
val iccm_rd_ecc_single_err_ff = WireInit(Bool(), false.B) val iccm_rd_ecc_single_err_ff = WireInit(Bool(), false.B)
val iccm_ecc_write_status = if(ICCM_ENABLE)((io.iccm_rd_ecc_single_err & !iccm_rd_ecc_single_err_ff) & !io.exu_flush_final) | io.iccm_dma_sb_error else 0.U val iccm_ecc_write_status = if(ICCM_ENABLE)((io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err & !iccm_rd_ecc_single_err_ff) & !io.exu_flush_final) | io.iccm_dma_sb_error else 0.U
val iccm_rd_ecc_single_err_hold_in = (io.iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff) & !io.exu_flush_final val iccm_rd_ecc_single_err_hold_in = (io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff) & !io.exu_flush_final
iccm_error_start := io.iccm_rd_ecc_single_err iccm_error_start := io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err
val iccm_rw_addr_f = WireInit(UInt((ICCM_BITS-2).W), 0.U) val iccm_rw_addr_f = WireInit(UInt((ICCM_BITS-2).W), 0.U)
val iccm_ecc_corr_index_in = Mux(iccm_single_ecc_error(0).asBool(), iccm_rw_addr_f, iccm_rw_addr_f + 1.U) val iccm_ecc_corr_index_in = Mux(iccm_single_ecc_error(0).asBool(), iccm_rw_addr_f, iccm_rw_addr_f + 1.U)
iccm_rw_addr_f := withClock(io.free_clk){RegNext(io.iccm_rw_addr(ICCM_BITS-2,1), 0.U)} iccm_rw_addr_f := withClock(io.free_clk){RegNext(io.iccm_rw_addr(ICCM_BITS-2,1), 0.U)}
@ -698,106 +717,106 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
((miss_state===miss_wait_C) & !miss_state_en) | ((miss_state===miss_wait_C) & !miss_state_en) |
((miss_state===crit_wrd_rdy_C) & !miss_state_en) | ((miss_state===crit_wrd_rdy_C) & !miss_state_en) |
((miss_state===crit_byp_ok_C) & miss_state_en & (miss_nxtstate===miss_wait_C)) )) | ((miss_state===crit_byp_ok_C) & miss_state_en & (miss_nxtstate===miss_wait_C)) )) |
(io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf) (io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf)
val bus_ic_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) val bus_ic_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
io.ic_wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes) io.ic_wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes)
io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff))) io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff)))
reset_all_tags := withClock(io.active_clk){RegNext(io.dec_tlu_fence_i_wb, false.B)} reset_all_tags := withClock(io.active_clk){RegNext(io.dec_mem_ctrl.dec_tlu_fence_i_wb, false.B)}
val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss
val ifu_status_wr_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array, io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), val ifu_status_wr_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array, io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3),
ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
val ifu_status_wr_addr_ff = withClock(io.free_clk) { val ifu_status_wr_addr_ff = withClock(io.free_clk) {
RegNext(ifu_status_wr_addr_w_debug, 0.U) RegNext(ifu_status_wr_addr_w_debug, 0.U)
} }
val way_status_wr_en = WireInit(Bool(), false.B) val way_status_wr_en = WireInit(Bool(), false.B)
val way_status_wr_en_w_debug = way_status_wr_en | (io.ic_debug_wr_en & io.ic_debug_tag_array) val way_status_wr_en_w_debug = way_status_wr_en | (io.ic_debug_wr_en & io.ic_debug_tag_array)
val way_status_wr_en_ff = withClock(io.free_clk) { val way_status_wr_en_ff = withClock(io.free_clk) {
RegNext(way_status_wr_en_w_debug, false.B) RegNext(way_status_wr_en_w_debug, false.B)
} }
val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
if (ICACHE_STATUS_BITS == 1) io.ic_debug_wr_data(4) else io.ic_debug_wr_data(6, 4), way_status_new) if (ICACHE_STATUS_BITS == 1) io.ic_debug_wr_data(4) else io.ic_debug_wr_data(6, 4), way_status_new)
val way_status_new_ff = withClock(io.free_clk) { val way_status_new_ff = withClock(io.free_clk) {
RegNext(way_status_new_w_debug, 0.U) RegNext(way_status_new_w_debug, 0.U)
} }
val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U) val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U)
val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode)) val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode))
val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W))) val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W)))
for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8) for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8)
way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)} way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)}
val test_way_status_out = (0 until ICACHE_TAG_DEPTH).map(i=>way_status_out(i).asUInt).reverse.reduce(Cat(_,_)) val test_way_status_out = (0 until ICACHE_TAG_DEPTH).map(i=>way_status_out(i).asUInt).reverse.reduce(Cat(_,_))
// io.test_way_status_out := test_way_status_out // io.test_way_status_out := test_way_status_out
val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_)) val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_))
//io.test_way_status_clken := test_way_status_clken //io.test_way_status_clken := test_way_status_clken
way_status := Mux1H((0 until ICACHE_TAG_DEPTH).map(i=>(ifu_ic_rw_int_addr_ff === i.U) -> way_status_out(i))) way_status := Mux1H((0 until ICACHE_TAG_DEPTH).map(i=>(ifu_ic_rw_int_addr_ff === i.U) -> way_status_out(i)))
val ifu_ic_rw_int_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array, val ifu_ic_rw_int_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array,
io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
ifu_ic_rw_int_addr_ff := withClock(io.free_clk) { ifu_ic_rw_int_addr_ff := withClock(io.free_clk) {
RegNext(ifu_ic_rw_int_addr_w_debug, 0.U) RegNext(ifu_ic_rw_int_addr_w_debug, 0.U)
} }
val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en
val ifu_tag_wren_ff = withClock(io.free_clk) { val ifu_tag_wren_ff = withClock(io.free_clk) {
RegNext(ifu_tag_wren_w_debug, 0.U) RegNext(ifu_tag_wren_w_debug, 0.U)
} }
val ic_valid_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, io.ic_debug_wr_data(0), ic_valid) val ic_valid_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, io.ic_debug_wr_data(0), ic_valid)
val ic_valid_ff = withClock(io.free_clk) { val ic_valid_ff = withClock(io.free_clk) {
RegNext(ic_valid_w_debug, false.B) RegNext(ic_valid_w_debug, false.B)
} }
val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j => val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j =>
if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags
else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) | else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) |
((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) | ((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) |
reset_all_tags).reverse.reduce(Cat(_, _))) reset_all_tags).reverse.reduce(Cat(_, _)))
val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode))) val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode)))
val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool()))) val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool())))
// io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)), // io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)),
// (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_))) // (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_)))
for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32) for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32)
ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B, ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B,
((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)} ((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)}
val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j => val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j =>
Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_)) Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
// Making a sudo LRU // Making a sudo LRU
// val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, Bool())) // val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, Bool()))
val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
if (ICACHE_NUM_WAYS == 4) { if (ICACHE_NUM_WAYS == 4) {
replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
(!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0)) (!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
(!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0)) (!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
(!tagv_mb_ff(1) & tagv_mb_ff(0)) (!tagv_mb_ff(1) & tagv_mb_ff(0))
replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0) replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0)
way_status_hit_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status(2), 3.U), way_status_hit_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status(2), 3.U),
io.ic_rd_hit(1) -> Cat(way_status(2), 1.U(2.W)), io.ic_rd_hit(1) -> Cat(way_status(2), 1.U(2.W)),
io.ic_rd_hit(2) -> Cat(1.U, way_status(1), 0.U), io.ic_rd_hit(2) -> Cat(1.U, way_status(1), 0.U),
io.ic_rd_hit(3) -> Cat(0.U, way_status(1), 0.U))) io.ic_rd_hit(3) -> Cat(0.U, way_status(1), 0.U)))
way_status_rep_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U), way_status_rep_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U),
io.ic_rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)), io.ic_rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)),
io.ic_rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U), io.ic_rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U),
io.ic_rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U))) io.ic_rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U)))
} }
else { else {
replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0) replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0)
replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0) replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0)
way_status_hit_new := io.ic_rd_hit(0) way_status_hit_new := io.ic_rd_hit(0)
way_status_rep_new := replace_way_mb_any(0) way_status_rep_new := replace_way_mb_any(0)
} }
way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new) way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new)
way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f
val bus_wren = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending) val bus_wren = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending)
val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat) val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat)
val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss) val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss)
ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _)) ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _))
bus_ic_wr_en := bus_wren.reverse.reduce(Cat(_,_)) bus_ic_wr_en := bus_wren.reverse.reduce(Cat(_,_))
if(!ICACHE_ENABLE){ if(!ICACHE_ENABLE){
@ -818,34 +837,34 @@ class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val ic_debug_way_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) val ic_debug_way_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
ic_debug_tag_val_rd_out := (ic_tag_valid_unq & (ic_debug_way_ff & Fill(ICACHE_NUM_WAYS, ic_debug_rd_en_ff))).orR() ic_debug_tag_val_rd_out := (ic_tag_valid_unq & (ic_debug_way_ff & Fill(ICACHE_NUM_WAYS, ic_debug_rd_en_ff))).orR()
io.ifu_pmu_ic_miss := withClock(io.active_clk){RegNext(ic_act_miss_f, false.B)} io.dec_mem_ctrl.ifu_pmu_ic_miss := withClock(io.active_clk){RegNext(ic_act_miss_f, false.B)}
io.ifu_pmu_ic_hit := withClock(io.active_clk){RegNext(ic_act_hit_f, false.B)} io.dec_mem_ctrl.ifu_pmu_ic_hit := withClock(io.active_clk){RegNext(ic_act_hit_f, false.B)}
io.ifu_pmu_bus_error := withClock(io.active_clk){RegNext(ifc_bus_acc_fault_f, false.B)} io.dec_mem_ctrl.ifu_pmu_bus_error := withClock(io.active_clk){RegNext(ifc_bus_acc_fault_f, false.B)}
io.ifu_pmu_bus_busy := withClock(io.active_clk){RegNext(ifu_bus_arvalid_ff & !ifu_bus_arready_ff & miss_pending, false.B)} io.dec_mem_ctrl.ifu_pmu_bus_busy := withClock(io.active_clk){RegNext(ifu_bus_arvalid_ff & !ifu_bus_arready_ff & miss_pending, false.B)}
io.ifu_pmu_bus_trxn := withClock(io.active_clk){RegNext(bus_cmd_sent, false.B)} io.dec_mem_ctrl.ifu_pmu_bus_trxn := withClock(io.active_clk){RegNext(bus_cmd_sent, false.B)}
io.ic_debug_addr := io.dec_tlu_ic_diag_pkt.icache_dicawics io.ic_debug_addr := io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics
io.ic_debug_tag_array := io.dec_tlu_ic_diag_pkt.icache_dicawics(16) io.ic_debug_tag_array := io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics(16)
io.ic_debug_rd_en := io.dec_tlu_ic_diag_pkt.icache_rd_valid io.ic_debug_rd_en := io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid
io.ic_debug_wr_en := io.dec_tlu_ic_diag_pkt.icache_wr_valid io.ic_debug_wr_en := io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid
io.ic_debug_way := Cat(io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===3.U, io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===2.U, io.ic_debug_way := Cat(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===3.U, io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===2.U,
io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===1.U, io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===0.U) io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===1.U, io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===0.U)
ic_debug_tag_wr_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way ic_debug_tag_wr_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way
val ic_debug_ict_array_sel_in = io.ic_debug_rd_en & io.ic_debug_tag_array val ic_debug_ict_array_sel_in = io.ic_debug_rd_en & io.ic_debug_tag_array
ic_debug_way_ff := withClock(debug_c1_clk){RegNext(io.ic_debug_way, 0.U)} ic_debug_way_ff := withClock(debug_c1_clk){RegNext(io.ic_debug_way, 0.U)}
ic_debug_ict_array_sel_ff := withClock(debug_c1_clk){RegNext(ic_debug_ict_array_sel_in, 0.U)} ic_debug_ict_array_sel_ff := withClock(debug_c1_clk){RegNext(ic_debug_ict_array_sel_in, 0.U)}
ic_debug_rd_en_ff := withClock(io.free_clk){RegNext(io.ic_debug_rd_en, false.B)} ic_debug_rd_en_ff := withClock(io.free_clk){RegNext(io.ic_debug_rd_en, false.B)}
io.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegEnable(ic_debug_rd_en_ff, 0.U, ic_debug_rd_en_ff.asBool)} io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegNext(ic_debug_rd_en_ff, 0.U)}
val ifc_region_acc_okay = !(Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR()) | val ifc_region_acc_okay = !(Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR()) |
(INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) | (INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) |
(INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) | (INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) |
(INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U))) | (INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U))) |
(INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U))) | (INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U))) |
(INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U))) | (INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U))) |
(INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U))) | (INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U))) |
(INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U))) | (INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U))) |
(INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U))) (INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U)))
val ifc_region_acc_fault_memory_bf = !io.ifc_iccm_access_bf & !ifc_region_acc_okay & io.ifc_fetch_req_bf val ifc_region_acc_fault_memory_bf = !io.ifc_iccm_access_bf & !ifc_region_acc_okay & io.ifc_fetch_req_bf
ifc_region_acc_fault_final_bf := io.ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf ifc_region_acc_fault_final_bf := io.ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf
ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)} ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)}

430
src/main/scala/lsu/el2_lsu.scala
View File

@ -3,22 +3,97 @@ import lib._
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import include._ import include._
import el2_mem._
import ifu._
class lsu_pic extends Bundle {
val picm_wren = Output(Bool())
val picm_rden = Output(Bool())
val picm_mken = Output(Bool())
val picm_rdaddr = Output(UInt(32.W))
val picm_wraddr = Output(UInt(32.W))
val picm_wr_data = Output(UInt(32.W))
val picm_rd_data = Input(UInt(32.W))
}
class lsu_dma extends Bundle{
val dma_lsc_ctl = new dma_lsc_ctl
val dma_dccm_ctl = new dma_dccm_ctl
val dccm_ready = Output(Bool())
val dma_mem_tag = Input(UInt(3.W))
}
class dma_lsc_ctl extends Bundle {
val dma_dccm_req = Input(Bool())
val dma_mem_addr = Input(UInt(32.W))
val dma_mem_sz = Input(UInt(3.W))
val dma_mem_write = Input(Bool())
val dma_mem_wdata = Input(UInt(64.W))
}
class dma_dccm_ctl extends Bundle{
val dma_mem_addr = Input(UInt(32.W))
val dma_mem_wdata = Input(UInt(64.W))
val dccm_dma_rvalid = Output(Bool())
val dccm_dma_ecc_error = Output(Bool())
val dccm_dma_rtag = Output(UInt(3.W))
val dccm_dma_rdata = Output(UInt(64.W))
}
class lsu_exu extends Bundle{
val exu_lsu_rs1_d = Input(UInt(32.W))
val exu_lsu_rs2_d = Input(UInt(32.W))
}
class lsu_dec extends Bundle {
val tlu_busbuff = new tlu_busbuff
val dctl_busbuff = new dctl_busbuff
}
class tlu_busbuff extends Bundle {
val lsu_pmu_bus_trxn = Output(Bool())
val lsu_pmu_bus_misaligned = Output(Bool())
val lsu_pmu_bus_error = Output(Bool())
val lsu_pmu_bus_busy = Output(Bool())
val dec_tlu_external_ldfwd_disable = Input(Bool())
val dec_tlu_wb_coalescing_disable = Input(Bool())
val dec_tlu_sideeffect_posted_disable = Input(Bool())
val lsu_imprecise_error_load_any = Output(Bool())
val lsu_imprecise_error_store_any = Output(Bool())
val lsu_imprecise_error_addr_any = Output(UInt(32.W))
}
class dctl_busbuff extends Bundle with el2_lib{
val lsu_nonblock_load_valid_m = Output(Bool())
val lsu_nonblock_load_tag_m = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_inv_r = Output(Bool())
val lsu_nonblock_load_inv_tag_r = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_data_valid = Output(Bool())
val lsu_nonblock_load_data_error = Output(Bool())
val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_data = Output(UInt(32.W))
}
class lsu_tlu extends Bundle {
val lsu_pmu_load_external_m = Output(Bool())
val lsu_pmu_store_external_m = Output(Bool())
}
class el2_lsu extends Module with RequireAsyncReset with param with el2_lib { class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
val io = IO (new Bundle { val io = IO (new Bundle {
val clk_override = Input(Bool()) val clk_override = Input(Bool())
val lsu_dma = new lsu_dma
val lsu_pic = new lsu_pic
val lsu_exu = new lsu_exu
val lsu_dec = new lsu_dec
val lsu_mem = Flipped(new mem_lsu)
val lsu_tlu = new lsu_tlu
val axi = new axi_channels()
val dec_tlu_flush_lower_r = Input(Bool()) val dec_tlu_flush_lower_r = Input(Bool())
val dec_tlu_i0_kill_writeb_r = Input(Bool()) val dec_tlu_i0_kill_writeb_r = Input(Bool())
val dec_tlu_force_halt = Input(Bool()) val dec_tlu_force_halt = Input(Bool())
// chicken signals // chicken signals
val dec_tlu_external_ldfwd_disable = Input(Bool()) // val dec_tlu_external_ldfwd_disable = Input(Bool())
val dec_tlu_wb_coalescing_disable = Input(Bool()) // val dec_tlu_wb_coalescing_disable = Input(Bool())
val dec_tlu_sideeffect_posted_disable = Input(Bool()) // val dec_tlu_sideeffect_posted_disable = Input(Bool())
val dec_tlu_core_ecc_disable = Input(Bool()) val dec_tlu_core_ecc_disable = Input(Bool())
val exu_lsu_rs1_d = Input(UInt(32.W)) // val exu_lsu_rs1_d = Input(UInt(32.W))
val exu_lsu_rs2_d = Input(UInt(32.W)) // val exu_lsu_rs2_d = Input(UInt(32.W))
val dec_lsu_offset_d = Input(UInt(12.W)) val dec_lsu_offset_d = Input(UInt(12.W))
val lsu_p = Flipped(Valid(new el2_lsu_pkt_t)) val lsu_p = Flipped(Valid(new el2_lsu_pkt_t))
val trigger_pkt_any = Input(Vec(4, new el2_trigger_pkt_t)) val trigger_pkt_any = Input(Vec(4, new el2_trigger_pkt_t))
@ -37,108 +112,64 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
val lsu_fir_error = Output(UInt(2.W)) val lsu_fir_error = Output(UInt(2.W))
val lsu_single_ecc_error_incr = Output(Bool()) val lsu_single_ecc_error_incr = Output(Bool())
val lsu_error_pkt_r = Valid(new el2_lsu_error_pkt_t) val lsu_error_pkt_r = Valid(new el2_lsu_error_pkt_t)
val lsu_imprecise_error_load_any = Output(Bool()) // val lsu_imprecise_error_load_any = Output(Bool())
val lsu_imprecise_error_store_any = Output(Bool()) // val lsu_imprecise_error_store_any = Output(Bool())
val lsu_imprecise_error_addr_any = Output(UInt(32.W)) // val lsu_imprecise_error_addr_any = Output(UInt(32.W))
// Non-blocking loads // Non-blocking loads
val lsu_nonblock_load_valid_m = Output(Bool()) // val lsu_nonblock_load_valid_m = Output(Bool())
val lsu_nonblock_load_tag_m = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // val lsu_nonblock_load_tag_m = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_inv_r = Output(Bool()) // val lsu_nonblock_load_inv_r = Output(Bool())
val lsu_nonblock_load_inv_tag_r = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // val lsu_nonblock_load_inv_tag_r = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_data_valid = Output(Bool()) // val lsu_nonblock_load_data_valid = Output(Bool())
val lsu_nonblock_load_data_error = Output(Bool()) // val lsu_nonblock_load_data_error = Output(Bool())
val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_data = Output(UInt(32.W)) // val lsu_nonblock_load_data = Output(UInt(32.W))
val lsu_pmu_load_external_m = Output(Bool()) // val lsu_pmu_load_external_m = Output(Bool())
val lsu_pmu_store_external_m = Output(Bool()) // val lsu_pmu_store_external_m = Output(Bool())
val lsu_pmu_misaligned_m = Output(Bool()) val lsu_pmu_misaligned_m = Output(Bool())
val lsu_pmu_bus_trxn = Output(Bool()) // val lsu_pmu_bus_trxn = Output(Bool())
val lsu_pmu_bus_misaligned = Output(Bool()) // val lsu_pmu_bus_misaligned = Output(Bool())
val lsu_pmu_bus_error = Output(Bool()) // val lsu_pmu_bus_error = Output(Bool())
val lsu_pmu_bus_busy = Output(Bool()) // val lsu_pmu_bus_busy = Output(Bool())
val lsu_trigger_match_m = Output(UInt(4.W)) val lsu_trigger_match_m = Output(UInt(4.W))
// DCCM ports // DCCM ports
val dccm_wren = Output(Bool()) // val dccm_wren = Output(Bool())
val dccm_rden = Output(Bool()) // val dccm_rden = Output(Bool())
val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W)) // val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W)) // val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W)) // val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W)) // val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
// PIC ports // PIC ports
val picm_wren = Output(Bool()) // val picm_wren = Output(Bool())
val picm_rden = Output(Bool()) // val picm_rden = Output(Bool())
val picm_mken = Output(Bool()) // val picm_mken = Output(Bool())
val picm_rdaddr = Output(UInt(32.W)) // val picm_rdaddr = Output(UInt(32.W))
val picm_wraddr = Output(UInt(32.W)) // val picm_wraddr = Output(UInt(32.W))
val picm_wr_data = Output(UInt(32.W)) // val picm_wr_data = Output(UInt(32.W))
val picm_rd_data = Input(UInt(32.W)) // val picm_rd_data = Input(UInt(32.W))
// AXI Write Channels
val lsu_axi_awvalid = Output(Bool())
val lsu_axi_awlock = Output(Bool())
val lsu_axi_awready = Input(Bool())
val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
val lsu_axi_awaddr = Output(UInt(32.W))
val lsu_axi_awregion = Output(UInt(4.W))
val lsu_axi_awlen = Output(UInt(8.W))
val lsu_axi_awsize = Output(UInt(3.W))
val lsu_axi_awburst = Output(UInt(2.W))
val lsu_axi_awcache = Output(UInt(4.W))
val lsu_axi_awprot = Output(UInt(3.W))
val lsu_axi_awqos = Output(UInt(4.W))
val lsu_axi_wvalid = Output(Bool())
val lsu_axi_wready = Input(Bool())
val lsu_axi_wdata = Output(UInt(64.W))
val lsu_axi_wstrb = Output(UInt(8.W))
val lsu_axi_wlast = Output(Bool())
val lsu_axi_bvalid = Input(Bool())
val lsu_axi_bready = Output(Bool())
val lsu_axi_bresp = Input(UInt(2.W))
val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
// AXI Read Channels
val lsu_axi_arvalid = Output(Bool())
val lsu_axi_arlock = Output(Bool())
val lsu_axi_arready = Input(Bool())
val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
val lsu_axi_araddr = Output(UInt(32.W))
val lsu_axi_arregion = Output(UInt(4.W))
val lsu_axi_arlen = Output(UInt(8.W))
val lsu_axi_arsize = Output(UInt(3.W))
val lsu_axi_arburst = Output(UInt(2.W))
val lsu_axi_arcache = Output(UInt(4.W))
val lsu_axi_arprot = Output(UInt(3.W))
val lsu_axi_arqos = Output(UInt(4.W))
val lsu_axi_rvalid = Input(Bool())
val lsu_axi_rready = Output(Bool())
val lsu_axi_rdata = Input(UInt(64.W))
val lsu_axi_rlast = Input(Bool())
val lsu_axi_rresp = Input(UInt(2.W))
val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
val lsu_bus_clk_en = Input(Bool()) val lsu_bus_clk_en = Input(Bool())
// DMA slave // DMA slave
val dma_dccm_req = Input(Bool()) // val dma_dccm_req = Input(Bool())
val dma_mem_write = Input(Bool()) // val dma_mem_write = Input(Bool())
val dccm_dma_rvalid = Output(Bool()) // val dccm_dma_rvalid = Output(Bool())
val dccm_dma_ecc_error = Output(Bool()) // val dccm_dma_ecc_error = Output(Bool())
val dma_mem_tag = Input(UInt(3.W)) // val dma_mem_tag = Input(UInt(3.W))
val dma_mem_addr = Input(UInt(32.W)) // val dma_mem_addr = Input(UInt(32.W))
val dma_mem_sz = Input(UInt(3.W)) // val dma_mem_sz = Input(UInt(3.W))
val dma_mem_wdata = Input(UInt(64.W)) // val dma_mem_wdata = Input(UInt(64.W))
val dccm_dma_rtag = Output(UInt(3.W)) // val dccm_dma_rtag = Output(UInt(3.W))
val dccm_dma_rdata = Output(UInt(64.W)) // val dccm_dma_rdata = Output(UInt(64.W))
val dccm_ready = Output(Bool()) // val dccm_ready = Output(Bool())
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val free_clk = Input(Clock()) val free_clk = Input(Clock())
@ -171,12 +202,12 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
// Ready to accept dma trxns // Ready to accept dma trxns
// There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m // There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m
val dma_mem_tag_d = io.dma_mem_tag val dma_mem_tag_d = io.lsu_dma.dma_mem_tag
val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store
io.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff) io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff)
val dma_dccm_wen = io.dma_dccm_req & io.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d
val dma_pic_wen = io.dma_dccm_req & io.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d
dma_dccm_wdata := io.dma_mem_wdata >> Cat(io.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
dma_dccm_wdata_hi := dma_dccm_wdata(63,32) dma_dccm_wdata_hi := dma_dccm_wdata(63,32)
dma_dccm_wdata_lo := dma_dccm_wdata(31,0) dma_dccm_wdata_lo := dma_dccm_wdata(31,0)
@ -196,8 +227,8 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int
// PMU signals // PMU signals
io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR)) io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR))
io.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m
io.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m io.lsu_tlu.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m
//LSU_LSC_Control //LSU_LSC_Control
//Inputs //Inputs
@ -215,18 +246,20 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m
lsu_lsc_ctl.io.flush_m_up := flush_m_up lsu_lsc_ctl.io.flush_m_up := flush_m_up
lsu_lsc_ctl.io.flush_r := flush_r lsu_lsc_ctl.io.flush_r := flush_r
lsu_lsc_ctl.io.exu_lsu_rs1_d := io.exu_lsu_rs1_d lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu
lsu_lsc_ctl.io.exu_lsu_rs2_d := io.exu_lsu_rs2_d // lsu_lsc_ctl.io.exu_lsu_rs1_d := io.exu_lsu_rs1_d
// lsu_lsc_ctl.io.exu_lsu_rs2_d := io.exu_lsu_rs2_d
lsu_lsc_ctl.io.lsu_p <> io.lsu_p lsu_lsc_ctl.io.lsu_p <> io.lsu_p
lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d
lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m
lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m
lsu_lsc_ctl.io.dma_dccm_req := io.dma_dccm_req lsu_lsc_ctl.io.dma_lsc_ctl <> io.lsu_dma.dma_lsc_ctl
lsu_lsc_ctl.io.dma_mem_addr := io.dma_mem_addr // lsu_lsc_ctl.io.dma_dccm_req := io.dma_dccm_req
lsu_lsc_ctl.io.dma_mem_sz := io.dma_mem_sz // lsu_lsc_ctl.io.dma_mem_addr := io.dma_mem_addr
lsu_lsc_ctl.io.dma_mem_write := io.dma_mem_write // lsu_lsc_ctl.io.dma_mem_sz := io.dma_mem_sz
lsu_lsc_ctl.io.dma_mem_wdata := io.dma_mem_wdata // lsu_lsc_ctl.io.dma_mem_write := io.dma_mem_write
// lsu_lsc_ctl.io.dma_mem_wdata := io.dma_mem_wdata
lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff
lsu_lsc_ctl.io.scan_mode := io.scan_mode lsu_lsc_ctl.io.scan_mode := io.scan_mode
//Outputs //Outputs
@ -285,35 +318,44 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
dccm_ctl.io.dma_dccm_wen := dma_dccm_wen dccm_ctl.io.dma_dccm_wen := dma_dccm_wen
dccm_ctl.io.dma_pic_wen := dma_pic_wen dccm_ctl.io.dma_pic_wen := dma_pic_wen
dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m
dccm_ctl.io.dma_mem_addr := io.dma_mem_addr // dccm_ctl.io.dma_mem_addr := io.dma_mem_addr
dccm_ctl.io.dma_mem_wdata := io.dma_mem_wdata // dccm_ctl.io.dma_mem_wdata := io.dma_mem_wdata
dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo
dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi
dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi
dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo
dccm_ctl.io.dccm_rd_data_lo := io.dccm_rd_data_lo // dccm_ctl.io.dccm_rd_data_lo := io.dccm_rd_data_lo
dccm_ctl.io.dccm_rd_data_hi := io.dccm_rd_data_hi // dccm_ctl.io.dccm_rd_data_hi := io.dccm_rd_data_hi
dccm_ctl.io.picm_rd_data := io.picm_rd_data // dccm_ctl.io.picm_rd_data := io.picm_rd_data
dccm_ctl.io.scan_mode := io.scan_mode dccm_ctl.io.scan_mode := io.scan_mode
//Outputs //Outputs
io.dccm_dma_rvalid := dccm_ctl.io.dccm_dma_rvalid io.lsu_dma.dma_dccm_ctl <> dccm_ctl.io.dma_dccm_ctl
io.dccm_dma_ecc_error := dccm_ctl.io.dccm_dma_ecc_error // dccm_ctl.io.dma_mem_addr := io.dma_mem_addr
io.dccm_dma_rtag := dccm_ctl.io.dccm_dma_rtag // dccm_ctl.io.dma_mem_wdata := io.dma_mem_wdata
io.dccm_dma_rdata := dccm_ctl.io.dccm_dma_rdata // io.dccm_dma_rvalid := dccm_ctl.io.dccm_dma_rvalid
io.dccm_wren := dccm_ctl.io.dccm_wren // io.dccm_dma_ecc_error := dccm_ctl.io.dccm_dma_ecc_error
io.dccm_rden := dccm_ctl.io.dccm_rden // io.dccm_dma_rtag := dccm_ctl.io.dccm_dma_rtag
io.dccm_wr_addr_lo := dccm_ctl.io.dccm_wr_addr_lo // io.dccm_dma_rdata := dccm_ctl.io.dccm_dma_rdata
io.dccm_wr_data_lo := dccm_ctl.io.dccm_wr_data_lo // io.dccm_wren := dccm_ctl.io.dccm_wren
io.dccm_rd_addr_lo := dccm_ctl.io.dccm_rd_addr_lo // io.dccm_rden := dccm_ctl.io.dccm_rden
io.dccm_wr_addr_hi := dccm_ctl.io.dccm_wr_addr_hi // io.dccm_wr_addr_lo := dccm_ctl.io.dccm_wr_addr_lo
io.dccm_wr_data_hi := dccm_ctl.io.dccm_wr_data_hi // io.dccm_wr_data_lo := dccm_ctl.io.dccm_wr_data_lo
io.dccm_rd_addr_hi := dccm_ctl.io.dccm_rd_addr_hi // io.dccm_rd_addr_lo := dccm_ctl.io.dccm_rd_addr_lo
io.picm_wren := dccm_ctl.io.picm_wren // io.dccm_wr_addr_hi := dccm_ctl.io.dccm_wr_addr_hi
io.picm_rden := dccm_ctl.io.picm_rden // io.dccm_wr_data_hi := dccm_ctl.io.dccm_wr_data_hi
io.picm_mken := dccm_ctl.io.picm_mken // io.dccm_rd_addr_hi := dccm_ctl.io.dccm_rd_addr_hi
io.picm_rdaddr := dccm_ctl.io.picm_rdaddr // dccm_ctl.io.dccm_rd_data_lo := io.dccm_rd_data_lo
io.picm_wraddr := dccm_ctl.io.picm_wraddr // dccm_ctl.io.dccm_rd_data_hi := io.dccm_rd_data_hi
io.picm_wr_data := dccm_ctl.io.picm_wr_data io.lsu_mem <> dccm_ctl.io.lsu_mem
io.lsu_pic <> dccm_ctl.io.lsu_pic
// dccm_ctl.io.picm_rd_data := io.picm_rd_data
// io.picm_wren := dccm_ctl.io.picm_wren
// io.picm_rden := dccm_ctl.io.picm_rden
// io.picm_mken := dccm_ctl.io.picm_mken
// io.picm_rdaddr := dccm_ctl.io.picm_rdaddr
// io.picm_wraddr := dccm_ctl.io.picm_wraddr
// io.picm_wr_data := dccm_ctl.io.picm_wr_data
//dccm_ctl.io.picm_rd_data := io.picm_rd_data
//Store Buffer //Store Buffer
//Inputs //Inputs
stbuf.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk stbuf.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk
@ -385,7 +427,7 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
clkdomain.io.free_clk := io.free_clk clkdomain.io.free_clk := io.free_clk
clkdomain.io.clk_override := io.clk_override clkdomain.io.clk_override := io.clk_override
clkdomain.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m clkdomain.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
clkdomain.io.dma_dccm_req := io.dma_dccm_req clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req
clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r
clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any
clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any
@ -403,9 +445,17 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
//Bus Interface //Bus Interface
//Inputs //Inputs
bus_intf.io.scan_mode := io.scan_mode bus_intf.io.scan_mode := io.scan_mode
bus_intf.io.dec_tlu_external_ldfwd_disable := io.dec_tlu_external_ldfwd_disable io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff
bus_intf.io.dec_tlu_wb_coalescing_disable := io.dec_tlu_wb_coalescing_disable // bus_intf.io.dec_tlu_external_ldfwd_disable := io.dec_tlu_external_ldfwd_disable
bus_intf.io.dec_tlu_sideeffect_posted_disable := io.dec_tlu_sideeffect_posted_disable // bus_intf.io.dec_tlu_wb_coalescing_disable := io.dec_tlu_wb_coalescing_disable
// bus_intf.io.dec_tlu_sideeffect_posted_disable := io.dec_tlu_sideeffect_posted_disable
// io.lsu_pmu_bus_trxn := bus_intf.io.lsu_pmu_bus_trxn
// io.lsu_pmu_bus_misaligned := bus_intf.io.lsu_pmu_bus_misaligned
// io.lsu_pmu_bus_error := bus_intf.io.lsu_pmu_bus_error
// io.lsu_pmu_bus_busy := bus_intf.io.lsu_pmu_bus_busy
// io.lsu_imprecise_error_load_any := bus_intf.io.lsu_imprecise_error_load_any
// io.lsu_imprecise_error_store_any := bus_intf.io.lsu_imprecise_error_store_any
// io.lsu_imprecise_error_addr_any := bus_intf.io.lsu_imprecise_error_addr_any
bus_intf.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk bus_intf.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk
bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
@ -433,60 +483,62 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
bus_intf.io.flush_r := flush_r bus_intf.io.flush_r := flush_r
//Outputs //Outputs
io.lsu_imprecise_error_load_any := bus_intf.io.lsu_imprecise_error_load_any // io.lsu_imprecise_error_load_any := bus_intf.io.lsu_imprecise_error_load_any
io.lsu_imprecise_error_store_any := bus_intf.io.lsu_imprecise_error_store_any // io.lsu_imprecise_error_store_any := bus_intf.io.lsu_imprecise_error_store_any
io.lsu_imprecise_error_addr_any := bus_intf.io.lsu_imprecise_error_addr_any // io.lsu_imprecise_error_addr_any := bus_intf.io.lsu_imprecise_error_addr_any
io.lsu_nonblock_load_valid_m := bus_intf.io.lsu_nonblock_load_valid_m io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff
io.lsu_nonblock_load_tag_m := bus_intf.io.lsu_nonblock_load_tag_m // io.lsu_nonblock_load_valid_m := bus_intf.io.lsu_nonblock_load_valid_m
io.lsu_nonblock_load_inv_r := bus_intf.io.lsu_nonblock_load_inv_r // io.lsu_nonblock_load_tag_m := bus_intf.io.lsu_nonblock_load_tag_m
io.lsu_nonblock_load_inv_tag_r := bus_intf.io.lsu_nonblock_load_inv_tag_r // io.lsu_nonblock_load_inv_r := bus_intf.io.lsu_nonblock_load_inv_r
io.lsu_nonblock_load_data_valid := bus_intf.io.lsu_nonblock_load_data_valid // io.lsu_nonblock_load_inv_tag_r := bus_intf.io.lsu_nonblock_load_inv_tag_r
io.lsu_nonblock_load_data_error := bus_intf.io.lsu_nonblock_load_data_error // io.lsu_nonblock_load_data_valid := bus_intf.io.lsu_nonblock_load_data_valid
io.lsu_nonblock_load_data_tag := bus_intf.io.lsu_nonblock_load_data_tag // io.lsu_nonblock_load_data_error := bus_intf.io.lsu_nonblock_load_data_error
io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data // io.lsu_nonblock_load_data_tag := bus_intf.io.lsu_nonblock_load_data_tag
io.lsu_pmu_bus_trxn := bus_intf.io.lsu_pmu_bus_trxn // io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data
io.lsu_pmu_bus_misaligned := bus_intf.io.lsu_pmu_bus_misaligned // io.lsu_pmu_bus_trxn := bus_intf.io.lsu_pmu_bus_trxn
io.lsu_pmu_bus_error := bus_intf.io.lsu_pmu_bus_error // io.lsu_pmu_bus_misaligned := bus_intf.io.lsu_pmu_bus_misaligned
io.lsu_pmu_bus_busy := bus_intf.io.lsu_pmu_bus_busy // io.lsu_pmu_bus_error := bus_intf.io.lsu_pmu_bus_error
io.lsu_axi_awvalid := bus_intf.io.lsu_axi_awvalid // io.lsu_pmu_bus_busy := bus_intf.io.lsu_pmu_bus_busy
bus_intf.io.lsu_axi_awready := io.lsu_axi_awready io.axi <> bus_intf.io.axi
io.lsu_axi_awid := bus_intf.io.lsu_axi_awid // io.lsu_axi_awvalid := bus_intf.io.lsu_axi_awvalid
io.lsu_axi_awaddr := bus_intf.io.lsu_axi_awaddr // bus_intf.io.lsu_axi_awready := io.lsu_axi_awready
io.lsu_axi_awregion := bus_intf.io.lsu_axi_awregion // io.lsu_axi_awid := bus_intf.io.lsu_axi_awid
io.lsu_axi_awlen := bus_intf.io.lsu_axi_awlen // io.lsu_axi_awaddr := bus_intf.io.lsu_axi_awaddr
io.lsu_axi_awsize := bus_intf.io.lsu_axi_awsize // io.lsu_axi_awregion := bus_intf.io.lsu_axi_awregion
io.lsu_axi_awburst := bus_intf.io.lsu_axi_awburst // io.lsu_axi_awlen := bus_intf.io.lsu_axi_awlen
io.lsu_axi_awlock := bus_intf.io.lsu_axi_awlock // io.lsu_axi_awsize := bus_intf.io.lsu_axi_awsize
io.lsu_axi_awcache := bus_intf.io.lsu_axi_awcache // io.lsu_axi_awburst := bus_intf.io.lsu_axi_awburst
io.lsu_axi_awprot := bus_intf.io.lsu_axi_awprot // io.lsu_axi_awlock := bus_intf.io.lsu_axi_awlock
io.lsu_axi_awqos := bus_intf.io.lsu_axi_awqos // io.lsu_axi_awcache := bus_intf.io.lsu_axi_awcache
io.lsu_axi_wvalid := bus_intf.io.lsu_axi_wvalid // io.lsu_axi_awprot := bus_intf.io.lsu_axi_awprot
bus_intf.io.lsu_axi_wready := io.lsu_axi_wready // io.lsu_axi_awqos := bus_intf.io.lsu_axi_awqos
io.lsu_axi_wdata := bus_intf.io.lsu_axi_wdata // io.lsu_axi_wvalid := bus_intf.io.lsu_axi_wvalid
io.lsu_axi_wstrb := bus_intf.io.lsu_axi_wstrb // bus_intf.io.lsu_axi_wready := io.lsu_axi_wready
io.lsu_axi_wlast := bus_intf.io.lsu_axi_wlast // io.lsu_axi_wdata := bus_intf.io.lsu_axi_wdata
bus_intf.io.lsu_axi_bvalid := io.lsu_axi_bvalid // io.lsu_axi_wstrb := bus_intf.io.lsu_axi_wstrb
io.lsu_axi_bready := bus_intf.io.lsu_axi_bready // io.lsu_axi_wlast := bus_intf.io.lsu_axi_wlast
bus_intf.io.lsu_axi_bresp := io.lsu_axi_bresp // bus_intf.io.lsu_axi_bvalid := io.lsu_axi_bvalid
bus_intf.io.lsu_axi_bid := io.lsu_axi_bid // io.lsu_axi_bready := bus_intf.io.lsu_axi_bready
io.lsu_axi_arvalid := bus_intf.io.lsu_axi_arvalid // bus_intf.io.lsu_axi_bresp := io.lsu_axi_bresp
bus_intf.io.lsu_axi_arready := io.lsu_axi_arready // bus_intf.io.lsu_axi_bid := io.lsu_axi_bid
io.lsu_axi_arid := bus_intf.io.lsu_axi_arid // io.lsu_axi_arvalid := bus_intf.io.lsu_axi_arvalid
io.lsu_axi_araddr := bus_intf.io.lsu_axi_araddr // bus_intf.io.lsu_axi_arready := io.lsu_axi_arready
io.lsu_axi_arregion := bus_intf.io.lsu_axi_arregion // io.lsu_axi_arid := bus_intf.io.lsu_axi_arid
io.lsu_axi_arlen := bus_intf.io.lsu_axi_arlen // io.lsu_axi_araddr := bus_intf.io.lsu_axi_araddr
io.lsu_axi_arsize := bus_intf.io.lsu_axi_arsize // io.lsu_axi_arregion := bus_intf.io.lsu_axi_arregion
io.lsu_axi_arburst := bus_intf.io.lsu_axi_arburst // io.lsu_axi_arlen := bus_intf.io.lsu_axi_arlen
io.lsu_axi_arlock := bus_intf.io.lsu_axi_arlock // io.lsu_axi_arsize := bus_intf.io.lsu_axi_arsize
io.lsu_axi_arcache := bus_intf.io.lsu_axi_arcache // io.lsu_axi_arburst := bus_intf.io.lsu_axi_arburst
io.lsu_axi_arprot := bus_intf.io.lsu_axi_arprot // io.lsu_axi_arlock := bus_intf.io.lsu_axi_arlock
io.lsu_axi_arqos := bus_intf.io.lsu_axi_arqos // io.lsu_axi_arcache := bus_intf.io.lsu_axi_arcache
bus_intf.io.lsu_axi_rvalid := io.lsu_axi_rvalid // io.lsu_axi_arprot := bus_intf.io.lsu_axi_arprot
io.lsu_axi_rready := bus_intf.io.lsu_axi_rready // io.lsu_axi_arqos := bus_intf.io.lsu_axi_arqos
bus_intf.io.lsu_axi_rid := io.lsu_axi_rid // bus_intf.io.lsu_axi_rvalid := io.lsu_axi_rvalid
bus_intf.io.lsu_axi_rdata := io.lsu_axi_rdata // io.lsu_axi_rready := bus_intf.io.lsu_axi_rready
bus_intf.io.lsu_axi_rresp := io.lsu_axi_rresp // bus_intf.io.lsu_axi_rid := io.lsu_axi_rid
bus_intf.io.lsu_axi_rlast := io.lsu_axi_rlast // bus_intf.io.lsu_axi_rdata := io.lsu_axi_rdata
// bus_intf.io.lsu_axi_rresp := io.lsu_axi_rresp
// bus_intf.io.lsu_axi_rlast := io.lsu_axi_rlast
bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en
withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)} withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)}

202
src/main/scala/lsu/el2_lsu_bus_buffer.scala
View File

@ -5,14 +5,17 @@ import lib._
import include._ import include._
import chisel3.experimental.{ChiselEnum, chiselName} import chisel3.experimental.{ChiselEnum, chiselName}
import chisel3.util.ImplicitConversions.intToUInt import chisel3.util.ImplicitConversions.intToUInt
import ifu._
@chiselName @chiselName
class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib { class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
val io = IO(new Bundle { val io = IO(new Bundle {
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val dec_tlu_external_ldfwd_disable = Input(Bool()) val tlu_busbuff = new tlu_busbuff
val dec_tlu_wb_coalescing_disable = Input(Bool()) val dctl_busbuff = new dctl_busbuff
val dec_tlu_sideeffect_posted_disable = Input(Bool()) // val dec_tlu_external_ldfwd_disable = Input(Bool())
// val dec_tlu_wb_coalescing_disable = Input(Bool())
// val dec_tlu_sideeffect_posted_disable = Input(Bool())
val dec_tlu_force_halt = Input(Bool()) val dec_tlu_force_halt = Input(Bool())
val lsu_c2_r_clk = Input(Clock()) val lsu_c2_r_clk = Input(Clock())
val lsu_bus_ibuf_c1_clk = Input(Clock()) val lsu_bus_ibuf_c1_clk = Input(Clock())
@ -40,15 +43,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
val ldst_dual_m = Input(Bool()) val ldst_dual_m = Input(Bool())
val ldst_dual_r = Input(Bool()) val ldst_dual_r = Input(Bool())
val ldst_byteen_ext_m = Input(UInt(8.W)) val ldst_byteen_ext_m = Input(UInt(8.W))
val lsu_axi_wready = Input(Bool()) val lsu_axi = new axi_channels
val lsu_axi_bvalid = Input(Bool())
val lsu_axi_bresp = Input(UInt(2.W))
val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
val lsu_axi_arready = Input(Bool())
val lsu_axi_rvalid = Input(Bool())
val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
val lsu_axi_rdata = Input(UInt(64.W))
val lsu_axi_rresp = Input(UInt(2.W))
val lsu_bus_clk_en = Input(Bool()) val lsu_bus_clk_en = Input(Bool())
val lsu_bus_clk_en_q = Input(Bool()) val lsu_bus_clk_en_q = Input(Bool())
@ -61,52 +56,23 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
val ld_byte_hit_buf_hi = Output((UInt(4.W))) val ld_byte_hit_buf_hi = Output((UInt(4.W)))
val ld_fwddata_buf_lo = Output((UInt(32.W))) val ld_fwddata_buf_lo = Output((UInt(32.W)))
val ld_fwddata_buf_hi = Output((UInt(32.W))) val ld_fwddata_buf_hi = Output((UInt(32.W)))
val lsu_imprecise_error_load_any = Output(Bool()) // val lsu_imprecise_error_load_any = Output(Bool())
val lsu_imprecise_error_store_any = Output(Bool()) // val lsu_imprecise_error_store_any = Output(Bool())
val lsu_imprecise_error_addr_any = Output(UInt(32.W)) // val lsu_imprecise_error_addr_any = Output(UInt(32.W))
val lsu_nonblock_load_valid_m = Output(Bool()) // val lsu_nonblock_load_valid_m = Output(Bool())
val lsu_nonblock_load_tag_m = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // val lsu_nonblock_load_tag_m = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_inv_r = Output(Bool()) // val lsu_nonblock_load_inv_r = Output(Bool())
val lsu_nonblock_load_inv_tag_r = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // val lsu_nonblock_load_inv_tag_r = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_data_valid = Output(Bool()) // val lsu_nonblock_load_data_valid = Output(Bool())
val lsu_nonblock_load_data_error = Output(Bool()) // val lsu_nonblock_load_data_error = Output(Bool())
val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_data = Output(UInt(32.W)) // val lsu_nonblock_load_data = Output(UInt(32.W))
val lsu_pmu_bus_trxn = Output(Bool()) // val lsu_pmu_bus_trxn = Output(Bool())
val lsu_pmu_bus_misaligned = Output(Bool()) // val lsu_pmu_bus_misaligned = Output(Bool())
val lsu_pmu_bus_error = Output(Bool()) // val lsu_pmu_bus_error = Output(Bool())
val lsu_pmu_bus_busy = Output(Bool()) // val lsu_pmu_bus_busy = Output(Bool())
// AXI Signals // AXI Signals
val lsu_axi_awvalid = Output(Bool())
val lsu_axi_awready = Input(Bool())
val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
val lsu_axi_awaddr = Output(UInt(32.W))
val lsu_axi_awregion = Output(UInt(4.W))
val lsu_axi_awlen = Output(UInt(8.W))
val lsu_axi_awsize = Output(UInt(3.W))
val lsu_axi_awburst = Output(UInt(2.W))
val lsu_axi_awlock = Output(Bool())
val lsu_axi_awcache = Output(UInt(4.W))
val lsu_axi_awprot = Output(UInt(3.W))
val lsu_axi_awqos = Output(UInt(4.W))
val lsu_axi_wvalid = Output(Bool())
val lsu_axi_wdata = Output(UInt(64.W))
val lsu_axi_wstrb = Output(UInt(8.W))
val lsu_axi_wlast = Output(Bool())
val lsu_axi_bready = Output(Bool())
val lsu_axi_arvalid = Output(Bool())
val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
val lsu_axi_araddr = Output(UInt(32.W))
val lsu_axi_arregion = Output(UInt(4.W))
val lsu_axi_arlen = Output(UInt(8.W))
val lsu_axi_arsize = Output(UInt(3.W))
val lsu_axi_arburst = Output(UInt(2.W))
val lsu_axi_arlock = Output(Bool())
val lsu_axi_arcache = Output(UInt(4.W))
val lsu_axi_arprot = Output(UInt(3.W))
val lsu_axi_arqos = Output(UInt(4.W))
val lsu_axi_rready = Output(Bool())
}) })
def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
@ -228,7 +194,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
(0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) |
(ld_fwddata_buf_hi_initial & ibuf_data) (ld_fwddata_buf_hi_initial & ibuf_data)
val bus_coalescing_disable = io.dec_tlu_wb_coalescing_disable | BUILD_AHB_LITE.B val bus_coalescing_disable = io.tlu_busbuff.dec_tlu_wb_coalescing_disable | BUILD_AHB_LITE.B
val ldst_byteen_r = Mux1H(Seq(io.lsu_pkt_r.bits.by -> 1.U(4.W), val ldst_byteen_r = Mux1H(Seq(io.lsu_pkt_r.bits.by -> 1.U(4.W),
io.lsu_pkt_r.bits.half -> 3.U(4.W), io.lsu_pkt_r.bits.half -> 3.U(4.W),
io.lsu_pkt_r.bits.word -> 15.U(4.W))) io.lsu_pkt_r.bits.word -> 15.U(4.W)))
@ -373,7 +339,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
val obuf_rdrsp_tag_in = Mux(bus_cmd_sent & !obuf_write, obuf_tag0, obuf_rdrsp_tag) val obuf_rdrsp_tag_in = Mux(bus_cmd_sent & !obuf_write, obuf_tag0, obuf_rdrsp_tag)
val obuf_addr = WireInit(UInt(32.W), 0.U) val obuf_addr = WireInit(UInt(32.W), 0.U)
val obuf_sideeffect = WireInit(Bool(), false.B) val obuf_sideeffect = WireInit(Bool(), false.B)
obuf_nosend_in := (obuf_addr_in(31,3)===obuf_addr(31,3)) & obuf_aligned_in & !obuf_sideeffect & !obuf_write & !obuf_write_in & !io.dec_tlu_external_ldfwd_disable & obuf_nosend_in := (obuf_addr_in(31,3)===obuf_addr(31,3)) & obuf_aligned_in & !obuf_sideeffect & !obuf_write & !obuf_write_in & !io.tlu_busbuff.dec_tlu_external_ldfwd_disable &
((obuf_valid & !obuf_nosend) | (obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)))) ((obuf_valid & !obuf_nosend) | (obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))))
val obuf_byteen0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_lo_r)), val obuf_byteen0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_lo_r)),
Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr0), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr0)))) Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr0), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr0))))
@ -581,95 +547,95 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1).U, buf_numvld_any===DEPTH.U) io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1).U, buf_numvld_any===DEPTH.U)
io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid
io.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & !io.flush_m_up & !io.ld_full_hit_m io.dctl_busbuff.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & !io.flush_m_up & !io.ld_full_hit_m
io.lsu_nonblock_load_tag_m := WrPtr0_m io.dctl_busbuff.lsu_nonblock_load_tag_m := WrPtr0_m
val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B) val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B)
io.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r io.dctl_busbuff.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r
io.lsu_nonblock_load_inv_tag_r := WrPtr0_r io.dctl_busbuff.lsu_nonblock_load_inv_tag_r := WrPtr0_r
val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(BUILD_AXI_NATIVE.B & buf_write(i))))) val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(BUILD_AXI_NATIVE.B & buf_write(i)))))
io.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i)))) io.dctl_busbuff.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i))))
io.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U)) io.dctl_busbuff.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U))
val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i))) val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i)))
val lsu_nonblock_load_data_hi = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (buf_dual(i) & buf_dualhi(i))) -> buf_data(i))) val lsu_nonblock_load_data_hi = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (buf_dual(i) & buf_dualhi(i))) -> buf_data(i)))
val lsu_nonblock_addr_offset = indexing(buf_addr, io.lsu_nonblock_load_data_tag)(1,0) val lsu_nonblock_addr_offset = indexing(buf_addr, io.dctl_busbuff.lsu_nonblock_load_data_tag)(1,0)
val lsu_nonblock_sz = indexing(buf_sz, io.lsu_nonblock_load_data_tag) val lsu_nonblock_sz = indexing(buf_sz, io.dctl_busbuff.lsu_nonblock_load_data_tag)
val lsu_nonblock_unsign = indexing(buf_unsign, io.lsu_nonblock_load_data_tag) val lsu_nonblock_unsign = indexing(buf_unsign, io.dctl_busbuff.lsu_nonblock_load_data_tag)
val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.lsu_nonblock_load_data_tag) val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.dctl_busbuff.lsu_nonblock_load_data_tag)
val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U) val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U)
io.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.lsu_nonblock_load_data_error io.dctl_busbuff.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.dctl_busbuff.lsu_nonblock_load_data_error
io.lsu_nonblock_load_data := Mux1H(Seq((lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(0.U(24.W),lsu_nonblock_data_unalgn(7,0)), io.dctl_busbuff.lsu_nonblock_load_data := Mux1H(Seq((lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(0.U(24.W),lsu_nonblock_data_unalgn(7,0)),
(lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(0.U(16.W),lsu_nonblock_data_unalgn(15,0)), (lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(0.U(16.W),lsu_nonblock_data_unalgn(15,0)),
(!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)), (!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)),
(!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)), (!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)),
(lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn)) (lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn))
bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.dec_tlu_sideeffect_posted_disable).reduce(_|_) bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_)
bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)-> bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)->
(BUILD_AXI_NATIVE.B & obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U)))))) (BUILD_AXI_NATIVE.B & obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U))))))
bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready), io.lsu_axi_awready & io.lsu_axi_awready), io.lsu_axi_arready) bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready), io.lsu_axi.aw.ready & io.lsu_axi.aw.ready), io.lsu_axi.ar.ready)
bus_wcmd_sent := io.lsu_axi_awvalid & io.lsu_axi_awready bus_wcmd_sent := io.lsu_axi.aw.valid & io.lsu_axi.aw.ready
bus_wdata_sent := io.lsu_axi_wvalid & io.lsu_axi_wready bus_wdata_sent := io.lsu_axi.w.valid & io.lsu_axi.w.ready
bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi_arvalid & io.lsu_axi_arready) bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready)
bus_rsp_read := io.lsu_axi_rvalid & io.lsu_axi_rready bus_rsp_read := io.lsu_axi.r.valid & io.lsu_axi.r.ready
bus_rsp_write := io.lsu_axi_bvalid & io.lsu_axi_bready bus_rsp_write := io.lsu_axi.b.valid & io.lsu_axi.b.ready
bus_rsp_read_tag := io.lsu_axi_rid bus_rsp_read_tag := io.lsu_axi.r.bits.id
bus_rsp_write_tag := io.lsu_axi_bid bus_rsp_write_tag := io.lsu_axi.b.bits.id
bus_rsp_write_error := bus_rsp_write & (io.lsu_axi_bresp =/= 0.U) bus_rsp_write_error := bus_rsp_write & (io.lsu_axi.b.bits.resp =/= 0.U)
bus_rsp_read_error := bus_rsp_read & (io.lsu_axi_bresp =/= 0.U) bus_rsp_read_error := bus_rsp_read & (io.lsu_axi.b.bits.resp =/= 0.U)
bus_rsp_rdata := io.lsu_axi_rdata bus_rsp_rdata := io.lsu_axi.r.bits.data
// AXI Command signals // AXI Command signals
io.lsu_axi_awvalid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending io.lsu_axi.aw.valid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending
io.lsu_axi_awid := obuf_tag0 io.lsu_axi.aw.bits.id := obuf_tag0
io.lsu_axi_awaddr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W))) io.lsu_axi.aw.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W)))
io.lsu_axi_awsize := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) io.lsu_axi.aw.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W))
io.lsu_axi_awprot := 0.U io.lsu_axi.aw.bits.prot := 0.U
io.lsu_axi_awcache := Mux(obuf_sideeffect, 0.U, 15.U) io.lsu_axi.aw.bits.cache := Mux(obuf_sideeffect, 0.U, 15.U)
io.lsu_axi_awregion := obuf_addr(31,28) io.lsu_axi.aw.bits.region := obuf_addr(31,28)
io.lsu_axi_awlen := 0.U io.lsu_axi.aw.bits.len := 0.U
io.lsu_axi_awburst := 1.U(2.W) io.lsu_axi.aw.bits.burst := 1.U(2.W)
io.lsu_axi_awqos := 0.U io.lsu_axi.aw.bits.qos := 0.U
io.lsu_axi_awlock := 0.U io.lsu_axi.aw.bits.lock := 0.U
io.lsu_axi_wvalid := obuf_valid & obuf_write & !obuf_data_done & !bus_addr_match_pending io.lsu_axi.w.valid := obuf_valid & obuf_write & !obuf_data_done & !bus_addr_match_pending
io.lsu_axi_wstrb := obuf_byteen & Fill(8, obuf_write) io.lsu_axi.w.bits.strb := obuf_byteen & Fill(8, obuf_write)
io.lsu_axi_wdata := obuf_data io.lsu_axi.w.bits.data := obuf_data
io.lsu_axi_wlast := 1.U io.lsu_axi.w.bits.last := 1.U
io.lsu_axi_arvalid := obuf_valid & !obuf_write & !obuf_nosend & !bus_addr_match_pending io.lsu_axi.ar.valid := obuf_valid & !obuf_write & !obuf_nosend & !bus_addr_match_pending
io.lsu_axi_arid := obuf_tag0 io.lsu_axi.ar.bits.id := obuf_tag0
io.lsu_axi_araddr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W))) io.lsu_axi.ar.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W)))
io.lsu_axi_arsize := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) io.lsu_axi.ar.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W))
io.lsu_axi_arprot := 0.U io.lsu_axi.ar.bits.prot := 0.U
io.lsu_axi_arcache := Mux(obuf_sideeffect, 0.U(4.W), 15.U) io.lsu_axi.ar.bits.cache := Mux(obuf_sideeffect, 0.U(4.W), 15.U)
io.lsu_axi_arregion := obuf_addr(31,28) io.lsu_axi.ar.bits.region := obuf_addr(31,28)
io.lsu_axi_arlen := 0.U io.lsu_axi.ar.bits.len := 0.U
io.lsu_axi_arburst := 1.U(2.W) io.lsu_axi.ar.bits.burst := 1.U(2.W)
io.lsu_axi_arqos := 0.U io.lsu_axi.ar.bits.qos := 0.U
io.lsu_axi_arlock := 0.U io.lsu_axi.ar.bits.lock := 0.U
io.lsu_axi_bready := 1.U io.lsu_axi.b.ready := 1.U
io.lsu_axi_rready := 1.U io.lsu_axi.r.ready := 1.U
io.lsu_imprecise_error_store_any := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C)->(io.lsu_bus_clk_en_q & buf_error(i) & buf_write(i)))) io.tlu_busbuff.lsu_imprecise_error_store_any := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C)->(io.lsu_bus_clk_en_q & buf_error(i) & buf_write(i))))
val lsu_imprecise_error_store_tag = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & buf_error(i) & buf_write(i))->i.U)) val lsu_imprecise_error_store_tag = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & buf_error(i) & buf_write(i))->i.U))
io.lsu_imprecise_error_load_any := io.lsu_nonblock_load_data_error & !io.lsu_imprecise_error_store_any io.tlu_busbuff.lsu_imprecise_error_load_any := io.dctl_busbuff.lsu_nonblock_load_data_error & !io.tlu_busbuff.lsu_imprecise_error_store_any
io.lsu_imprecise_error_addr_any := Mux(io.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.lsu_nonblock_load_data_tag)) io.tlu_busbuff.lsu_imprecise_error_addr_any := Mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.dctl_busbuff.lsu_nonblock_load_data_tag))
lsu_bus_cntr_overflow := 0.U lsu_bus_cntr_overflow := 0.U
io.lsu_bus_idle_any := 1.U io.lsu_bus_idle_any := 1.U
// PMU signals // PMU signals
io.lsu_pmu_bus_trxn := (io.lsu_axi_awvalid & io.lsu_axi_awready) | (io.lsu_axi_wvalid & io.lsu_axi_wready) | (io.lsu_axi_arvalid & io.lsu_axi_arready) io.tlu_busbuff.lsu_pmu_bus_trxn := (io.lsu_axi.aw.valid & io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready)
io.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r io.tlu_busbuff.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r
io.lsu_pmu_bus_error := io.lsu_imprecise_error_load_any | io.lsu_imprecise_error_store_any io.tlu_busbuff.lsu_pmu_bus_error := io.tlu_busbuff.lsu_imprecise_error_load_any | io.tlu_busbuff.lsu_imprecise_error_store_any
io.lsu_pmu_bus_busy := (io.lsu_axi_awvalid & !io.lsu_axi_awready) | (io.lsu_axi_wvalid & !io.lsu_axi_wready) | (io.lsu_axi_arvalid & !io.lsu_axi_arready) io.tlu_busbuff.lsu_pmu_bus_busy := (io.lsu_axi.aw.valid & !io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & !io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & !io.lsu_axi.ar.ready)
WrPtr0_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr0_m, 0.U)} WrPtr0_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr0_m, 0.U)}
WrPtr1_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr1_m, 0.U)} WrPtr1_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr1_m, 0.U)}
io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)} io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)}
lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_nonblock_load_valid_m, false.B)} lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)}
} }
object BusBufmain extends App{ object BusBufmain extends App{

176
src/main/scala/lsu/el2_lsu_bus_intf.scala
View File

@ -1,16 +1,18 @@
package lsu package lsu
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import lib._ import lib._
import include._ import include._
import snapshot._ import snapshot._
import ifu._
class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib { class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib {
val io = IO (new Bundle { val io = IO (new Bundle {
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val dec_tlu_external_ldfwd_disable = Input(Bool()) // disable load to load forwarding for externals val tlu_busbuff = new tlu_busbuff
val dec_tlu_wb_coalescing_disable = Input(Bool()) // disable write buffer coalescing // val dec_tlu_external_ldfwd_disable = Input(Bool()) // disable load to load forwarding for externals
val dec_tlu_sideeffect_posted_disable = Input(Bool()) // disable the posted sideeffect load store to the bus // val dec_tlu_wb_coalescing_disable = Input(Bool()) // disable write buffer coalescing
// val dec_tlu_sideeffect_posted_disable = Input(Bool()) // disable the posted sideeffect load store to the bus
val lsu_c1_m_clk = Input(Clock()) val lsu_c1_m_clk = Input(Clock())
val lsu_c1_r_clk = Input(Clock()) val lsu_c1_r_clk = Input(Clock())
val lsu_c2_r_clk = Input(Clock()) val lsu_c2_r_clk = Input(Clock())
@ -20,7 +22,7 @@ class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib {
val lsu_free_c2_clk = Input(Clock()) val lsu_free_c2_clk = Input(Clock())
val free_clk = Input(Clock()) val free_clk = Input(Clock())
val lsu_busm_clk = Input(Clock()) val lsu_busm_clk = Input(Clock())
val axi = new axi_channels()
val dec_lsu_valid_raw_d = Input(Bool()) val dec_lsu_valid_raw_d = Input(Bool())
val lsu_busreq_m = Input(Bool()) val lsu_busreq_m = Input(Bool())
@ -43,10 +45,6 @@ class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib {
val flush_m_up = Input(Bool()) val flush_m_up = Input(Bool())
val flush_r = Input(Bool()) val flush_r = Input(Bool())
val lsu_busreq_r = Output(Bool()) val lsu_busreq_r = Output(Bool())
val lsu_bus_buffer_pend_any = Output(Bool()) val lsu_bus_buffer_pend_any = Output(Bool())
val lsu_bus_buffer_full_any = Output(Bool()) val lsu_bus_buffer_full_any = Output(Bool())
@ -54,67 +52,23 @@ class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib {
val lsu_bus_idle_any = Output(Bool()) val lsu_bus_idle_any = Output(Bool())
val bus_read_data_m = Output(UInt(32.W)) val bus_read_data_m = Output(UInt(32.W))
val lsu_imprecise_error_load_any = Output(Bool()) // val lsu_imprecise_error_load_any = Output(Bool())
val lsu_imprecise_error_store_any = Output(Bool()) // val lsu_imprecise_error_store_any = Output(Bool())
val lsu_imprecise_error_addr_any = Output(UInt(32.W)) // val lsu_imprecise_error_addr_any = Output(UInt(32.W))
val dctl_busbuff = new dctl_busbuff
// val lsu_nonblock_load_valid_m = Output(Bool())
// val lsu_nonblock_load_tag_m = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
// val lsu_nonblock_load_inv_r = Output(Bool())
// val lsu_nonblock_load_inv_tag_r = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
// val lsu_nonblock_load_data_valid = Output(Bool())
// val lsu_nonblock_load_data_error = Output(Bool())
// val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
// val lsu_nonblock_load_data = Output(UInt(32.W))
val lsu_nonblock_load_valid_m = Output(Bool()) // val lsu_pmu_bus_trxn = Output(Bool())
val lsu_nonblock_load_tag_m = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // val lsu_pmu_bus_misaligned = Output(Bool())
val lsu_nonblock_load_inv_r = Output(Bool()) // val lsu_pmu_bus_error = Output(Bool())
val lsu_nonblock_load_inv_tag_r = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // val lsu_pmu_bus_busy = Output(Bool())
val lsu_nonblock_load_data_valid = Output(Bool())
val lsu_nonblock_load_data_error = Output(Bool())
val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_data = Output(UInt(32.W))
val lsu_pmu_bus_trxn = Output(Bool())
val lsu_pmu_bus_misaligned = Output(Bool())
val lsu_pmu_bus_error = Output(Bool())
val lsu_pmu_bus_busy = Output(Bool())
val lsu_axi_awvalid = Output(Bool())
val lsu_axi_awready = Input(Bool())
val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
val lsu_axi_awaddr = Output(UInt(32.W))
val lsu_axi_awregion = Output(UInt(4.W))
val lsu_axi_awlen = Output(UInt(8.W))
val lsu_axi_awsize = Output(UInt(3.W))
val lsu_axi_awburst = Output(UInt(2.W))
val lsu_axi_awlock = Output(Bool())
val lsu_axi_awcache = Output(UInt(4.W))
val lsu_axi_awprot = Output(UInt(3.W))
val lsu_axi_awqos = Output(UInt(4.W))
val lsu_axi_wvalid = Output(Bool())
val lsu_axi_wready = Input(Bool())
val lsu_axi_wdata = Output(UInt(64.W))
val lsu_axi_wstrb = Output(UInt(8.W))
val lsu_axi_wlast = Output(Bool())
val lsu_axi_bvalid = Input(Bool())
val lsu_axi_bready = Output(Bool())
val lsu_axi_bresp = Input(UInt(2.W))
val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
val lsu_axi_arvalid = Output(Bool())
val lsu_axi_arready = Input(Bool())
val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
val lsu_axi_araddr = Output(UInt(32.W))
val lsu_axi_arregion = Output(UInt(4.W))
val lsu_axi_arlen = Output(UInt(8.W))
val lsu_axi_arsize = Output(UInt(3.W))
val lsu_axi_arburst = Output(UInt(2.W))
val lsu_axi_arlock = Output(Bool())
val lsu_axi_arcache = Output(UInt(4.W))
val lsu_axi_arprot = Output(UInt(3.W))
val lsu_axi_arqos = Output(UInt(4.W))
val lsu_axi_rvalid = Input(Bool())
val lsu_axi_rready = Output(Bool())
val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
val lsu_axi_rdata = Input(UInt(64.W))
val lsu_axi_rresp = Input(UInt(2.W))
val lsu_axi_rlast = Input(Bool())
val lsu_bus_clk_en = Input(Bool()) val lsu_bus_clk_en = Input(Bool())
}) })
@ -167,10 +121,18 @@ class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib {
val bus_buffer = Module(new el2_lsu_bus_buffer) val bus_buffer = Module(new el2_lsu_bus_buffer)
bus_buffer.io.scan_mode := io.scan_mode bus_buffer.io.scan_mode := io.scan_mode
io.tlu_busbuff <> bus_buffer.io.tlu_busbuff
bus_buffer.io.dec_tlu_external_ldfwd_disable := io.dec_tlu_external_ldfwd_disable // bus_buffer.io.dec_tlu_external_ldfwd_disable := io.dec_tlu_external_ldfwd_disable
bus_buffer.io.dec_tlu_wb_coalescing_disable := io.dec_tlu_wb_coalescing_disable // bus_buffer.io.dec_tlu_wb_coalescing_disable := io.dec_tlu_wb_coalescing_disable
bus_buffer.io.dec_tlu_sideeffect_posted_disable := io.dec_tlu_sideeffect_posted_disable // bus_buffer.io.dec_tlu_sideeffect_posted_disable := io.dec_tlu_sideeffect_posted_disable
// io.lsu_imprecise_error_load_any := bus_buffer.io.lsu_imprecise_error_load_any
// io.lsu_imprecise_error_store_any := bus_buffer.io.lsu_imprecise_error_store_any
// io.lsu_imprecise_error_addr_any := bus_buffer.io.lsu_imprecise_error_addr_any
// io.lsu_pmu_bus_trxn := bus_buffer.io.lsu_pmu_bus_trxn
// io.lsu_pmu_bus_misaligned := bus_buffer.io.lsu_pmu_bus_misaligned
// io.lsu_pmu_bus_error := bus_buffer.io.lsu_pmu_bus_error
// io.lsu_pmu_bus_busy := bus_buffer.io.lsu_pmu_bus_busy
bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt
bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk
bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk
@ -195,16 +157,7 @@ class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib {
bus_buffer.io.flush_m_up := io.flush_m_up bus_buffer.io.flush_m_up := io.flush_m_up
bus_buffer.io.flush_r := io.flush_r bus_buffer.io.flush_r := io.flush_r
bus_buffer.io.lsu_commit_r := io.lsu_commit_r bus_buffer.io.lsu_commit_r := io.lsu_commit_r
bus_buffer.io.lsu_axi_awready := io.lsu_axi_awready bus_buffer.io.lsu_axi <> io.axi
bus_buffer.io.lsu_axi_wready := io.lsu_axi_wready
bus_buffer.io.lsu_axi_bvalid := io.lsu_axi_bvalid
bus_buffer.io.lsu_axi_bresp := io.lsu_axi_bresp
bus_buffer.io.lsu_axi_bid := io.lsu_axi_bid
bus_buffer.io.lsu_axi_arready := io.lsu_axi_arready
bus_buffer.io.lsu_axi_rvalid := io.lsu_axi_rvalid
bus_buffer.io.lsu_axi_rid := io.lsu_axi_rid
bus_buffer.io.lsu_axi_rdata := io.lsu_axi_rdata
bus_buffer.io.lsu_axi_rresp := io.lsu_axi_rresp
bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en
io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r
@ -216,49 +169,22 @@ class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib {
ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi
ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo
ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi
io.lsu_imprecise_error_load_any := bus_buffer.io.lsu_imprecise_error_load_any io.dctl_busbuff <> bus_buffer.io.dctl_busbuff
io.lsu_imprecise_error_store_any := bus_buffer.io.lsu_imprecise_error_store_any // io.lsu_imprecise_error_load_any := bus_buffer.io.lsu_imprecise_error_load_any
io.lsu_imprecise_error_addr_any := bus_buffer.io.lsu_imprecise_error_addr_any // io.lsu_imprecise_error_store_any := bus_buffer.io.lsu_imprecise_error_store_any
io.lsu_nonblock_load_valid_m := bus_buffer.io.lsu_nonblock_load_valid_m // io.lsu_imprecise_error_addr_any := bus_buffer.io.lsu_imprecise_error_addr_any
io.lsu_nonblock_load_tag_m := bus_buffer.io.lsu_nonblock_load_tag_m // io.lsu_nonblock_load_valid_m := bus_buffer.io.lsu_nonblock_load_valid_m
io.lsu_nonblock_load_inv_r := bus_buffer.io.lsu_nonblock_load_inv_r // io.lsu_nonblock_load_tag_m := bus_buffer.io.lsu_nonblock_load_tag_m
io.lsu_nonblock_load_inv_tag_r := bus_buffer.io.lsu_nonblock_load_inv_tag_r // io.lsu_nonblock_load_inv_r := bus_buffer.io.lsu_nonblock_load_inv_r
io.lsu_nonblock_load_data_valid := bus_buffer.io.lsu_nonblock_load_data_valid // io.lsu_nonblock_load_inv_tag_r := bus_buffer.io.lsu_nonblock_load_inv_tag_r
io.lsu_nonblock_load_data_error := bus_buffer.io.lsu_nonblock_load_data_error // io.lsu_nonblock_load_data_valid := bus_buffer.io.lsu_nonblock_load_data_valid
io.lsu_nonblock_load_data_tag := bus_buffer.io.lsu_nonblock_load_data_tag // io.lsu_nonblock_load_data_error := bus_buffer.io.lsu_nonblock_load_data_error
io.lsu_nonblock_load_data := bus_buffer.io.lsu_nonblock_load_data // io.lsu_nonblock_load_data_tag := bus_buffer.io.lsu_nonblock_load_data_tag
io.lsu_pmu_bus_trxn := bus_buffer.io.lsu_pmu_bus_trxn // io.lsu_nonblock_load_data := bus_buffer.io.lsu_nonblock_load_data
io.lsu_pmu_bus_misaligned := bus_buffer.io.lsu_pmu_bus_misaligned // io.lsu_pmu_bus_trxn := bus_buffer.io.lsu_pmu_bus_trxn
io.lsu_pmu_bus_error := bus_buffer.io.lsu_pmu_bus_error // io.lsu_pmu_bus_misaligned := bus_buffer.io.lsu_pmu_bus_misaligned
io.lsu_pmu_bus_busy := bus_buffer.io.lsu_pmu_bus_busy // io.lsu_pmu_bus_error := bus_buffer.io.lsu_pmu_bus_error
io.lsu_axi_awvalid := bus_buffer.io.lsu_axi_awvalid // io.lsu_pmu_bus_busy := bus_buffer.io.lsu_pmu_bus_busy
io.lsu_axi_awid := bus_buffer.io.lsu_axi_awid
io.lsu_axi_awaddr := bus_buffer.io.lsu_axi_awaddr
io.lsu_axi_awregion := bus_buffer.io.lsu_axi_awregion
io.lsu_axi_awlen := bus_buffer.io.lsu_axi_awlen
io.lsu_axi_awsize := bus_buffer.io.lsu_axi_awsize
io.lsu_axi_awburst := bus_buffer.io.lsu_axi_awburst
io.lsu_axi_awlock := bus_buffer.io.lsu_axi_awlock
io.lsu_axi_awcache := bus_buffer.io.lsu_axi_awcache
io.lsu_axi_awprot := bus_buffer.io.lsu_axi_awprot
io.lsu_axi_awqos := bus_buffer.io.lsu_axi_awqos
io.lsu_axi_wvalid := bus_buffer.io.lsu_axi_wvalid
io.lsu_axi_wdata := bus_buffer.io.lsu_axi_wdata
io.lsu_axi_wstrb := bus_buffer.io.lsu_axi_wstrb
io.lsu_axi_wlast := bus_buffer.io.lsu_axi_wlast
io.lsu_axi_bready := bus_buffer.io.lsu_axi_bready
io.lsu_axi_arvalid := bus_buffer.io.lsu_axi_arvalid
io.lsu_axi_arid := bus_buffer.io.lsu_axi_arid
io.lsu_axi_araddr := bus_buffer.io.lsu_axi_araddr
io.lsu_axi_arregion := bus_buffer.io.lsu_axi_arregion
io.lsu_axi_arlen := bus_buffer.io.lsu_axi_arlen
io.lsu_axi_arsize := bus_buffer.io.lsu_axi_arsize
io.lsu_axi_arburst := bus_buffer.io.lsu_axi_arburst
io.lsu_axi_arlock := bus_buffer.io.lsu_axi_arlock
io.lsu_axi_arcache := bus_buffer.io.lsu_axi_arcache
io.lsu_axi_arprot := bus_buffer.io.lsu_axi_arprot
io.lsu_axi_arqos := bus_buffer.io.lsu_axi_arqos
io.lsu_axi_rready := bus_buffer.io.lsu_axi_rready
bus_buffer.io.no_word_merge_r := no_word_merge_r bus_buffer.io.no_word_merge_r := no_word_merge_r
bus_buffer.io.no_dword_merge_r := no_dword_merge_r bus_buffer.io.no_dword_merge_r := no_dword_merge_r

109
src/main/scala/lsu/el2_lsu_dccm_ctl.scala
View File

@ -3,9 +3,7 @@ import include._
import lib._ import lib._
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import el2_mem._
import chisel3.experimental.chiselName import chisel3.experimental.chiselName
@chiselName @chiselName
class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
@ -78,9 +76,9 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
val store_data_m = Input(UInt(32.W)) val store_data_m = Input(UInt(32.W))
val dma_dccm_wen = Input(UInt(1.W)) val dma_dccm_wen = Input(UInt(1.W))
val dma_pic_wen = Input(UInt(1.W)) val dma_pic_wen = Input(UInt(1.W))
val dma_mem_tag_m = Input(UInt(3.W)) val dma_mem_tag_m = Input(UInt(3.W))
val dma_mem_addr = Input(UInt(32.W)) // val dma_mem_addr = Input(UInt(32.W))
val dma_mem_wdata = Input(UInt(64.W)) // val dma_mem_wdata = Input(UInt(64.W))
val dma_dccm_wdata_lo = Input(UInt(32.W)) val dma_dccm_wdata_lo = Input(UInt(32.W))
val dma_dccm_wdata_hi = Input(UInt(32.W)) val dma_dccm_wdata_hi = Input(UInt(32.W))
val dma_dccm_wdata_ecc_hi = Input(UInt(DCCM_ECC_WIDTH.W)) val dma_dccm_wdata_ecc_hi = Input(UInt(DCCM_ECC_WIDTH.W))
@ -96,30 +94,33 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
val lsu_stbuf_commit_any = Output(UInt(1.W)) val lsu_stbuf_commit_any = Output(UInt(1.W))
val lsu_dccm_rden_m = Output(UInt(1.W)) val lsu_dccm_rden_m = Output(UInt(1.W))
val lsu_dccm_rden_r = Output(UInt(1.W)) val lsu_dccm_rden_r = Output(UInt(1.W))
val dccm_dma_rvalid = Output(UInt(1.W)) val dma_dccm_ctl = new dma_dccm_ctl
val dccm_dma_ecc_error = Output(UInt(1.W)) // val dccm_dma_rvalid = Output(UInt(1.W))
val dccm_dma_rtag = Output(UInt(3.W)) // val dccm_dma_ecc_error = Output(UInt(1.W))
val dccm_dma_rdata = Output(UInt(64.W)) // val dccm_dma_rtag = Output(UInt(3.W))
val dccm_wren = Output(UInt(1.W)) // val dccm_dma_rdata = Output(UInt(64.W))
val dccm_rden = Output(UInt(1.W)) // val dccm_wren = Output(UInt(1.W))
val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W)) // val dccm_rden = Output(UInt(1.W))
val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W)) // val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W)) // val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W)) // val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W)) // val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
val picm_wren = Output(UInt(1.W)) // val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
val picm_rden = Output(UInt(1.W)) val lsu_mem = Flipped(new mem_lsu)
val picm_mken = Output(UInt(1.W)) val lsu_pic = new lsu_pic
val picm_rdaddr = Output(UInt(32.W)) // val picm_wren = Output(UInt(1.W))
val picm_wraddr = Output(UInt(32.W)) // val picm_rden = Output(UInt(1.W))
val picm_wr_data = Output(UInt(32.W)) // val picm_mken = Output(UInt(1.W))
val picm_rd_data = Input(UInt(32.W)) // val picm_rdaddr = Output(UInt(32.W))
// val picm_wraddr = Output(UInt(32.W))
// val picm_wr_data = Output(UInt(32.W))
// val picm_rd_data = Input(UInt(32.W))
val scan_mode = Input(UInt(1.W)) val scan_mode = Input(UInt(1.W))
}) })
val picm_rd_data_m = Cat(io.picm_rd_data,io.picm_rd_data) //used in both if and else val picm_rd_data_m = Cat(io.lsu_pic.picm_rd_data,io.lsu_pic.picm_rd_data) //used in both if and else
val dccm_rdata_corr_r = Cat(io.sec_data_hi_r,io.sec_data_lo_r) val dccm_rdata_corr_r = Cat(io.sec_data_hi_r,io.sec_data_lo_r)
val dccm_rdata_corr_m = Cat(io.sec_data_hi_m,io.sec_data_lo_m) val dccm_rdata_corr_m = Cat(io.sec_data_hi_m,io.sec_data_lo_m)
val dccm_rdata_r = Cat(io.dccm_rdata_hi_r,io.dccm_rdata_lo_r) val dccm_rdata_r = Cat(io.dccm_rdata_hi_r,io.dccm_rdata_lo_r)
@ -137,9 +138,9 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
//Forwarding stbuf //Forwarding stbuf
if (LOAD_TO_USE_PLUS1 == 1){ if (LOAD_TO_USE_PLUS1 == 1){
io.dccm_dma_rvalid := io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.load & io.lsu_pkt_r.bits.dma io.dma_dccm_ctl.dccm_dma_rvalid := io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.load & io.lsu_pkt_r.bits.dma
io.dccm_dma_ecc_error := io.lsu_double_ecc_error_r //from ecc io.dma_dccm_ctl.dccm_dma_ecc_error := io.lsu_double_ecc_error_r //from ecc
io.dccm_dma_rdata := lsu_rdata_corr_r io.dma_dccm_ctl.dccm_dma_rdata := lsu_rdata_corr_r
//Registers //Registers
io.dccm_rdata_hi_r := rvdffe(io.dccm_rdata_hi_m,io.lsu_dccm_rden_m.asBool,clock,io.scan_mode.asBool) io.dccm_rdata_hi_r := rvdffe(io.dccm_rdata_hi_m,io.lsu_dccm_rden_m.asBool,clock,io.scan_mode.asBool)
io.dccm_rdata_lo_r := rvdffe(io.dccm_rdata_lo_m,io.lsu_dccm_rden_m.asBool,clock,io.scan_mode.asBool) io.dccm_rdata_lo_r := rvdffe(io.dccm_rdata_lo_m,io.lsu_dccm_rden_m.asBool,clock,io.scan_mode.asBool)
@ -149,7 +150,7 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
stbuf_fwddata_r := withClock(io.lsu_c2_r_clk){RegNext(Cat(io.stbuf_fwddata_hi_m ,io.stbuf_fwddata_lo_m ),0.U)} stbuf_fwddata_r := withClock(io.lsu_c2_r_clk){RegNext(Cat(io.stbuf_fwddata_hi_m ,io.stbuf_fwddata_lo_m ),0.U)}
picm_rd_data_r_32 := withClock(io.lsu_c2_r_clk){RegNext(picm_rd_data_m(31,0),0.U)} picm_rd_data_r_32 := withClock(io.lsu_c2_r_clk){RegNext(picm_rd_data_m(31,0),0.U)}
picm_rd_data_r := Cat(picm_rd_data_r_32,picm_rd_data_r_32) picm_rd_data_r := Cat(picm_rd_data_r_32,picm_rd_data_r_32)
io.dccm_dma_rtag := withClock(io.lsu_c1_r_clk){RegNext(io.dma_mem_tag_m,0.U)} io.dma_dccm_ctl.dccm_dma_rtag := withClock(io.lsu_c1_r_clk){RegNext(io.dma_mem_tag_m,0.U)}
lsu_rdata_corr_r := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(stbuf_fwdbyteen_r(i).asBool,stbuf_fwddata_r((8*i)+7,8*i),Mux(io.addr_in_pic_r.asBool,picm_rd_data_r((8*i)+7,8*i),dccm_rdata_corr_r((8*i)+7,8*i))))))) lsu_rdata_corr_r := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(stbuf_fwdbyteen_r(i).asBool,stbuf_fwddata_r((8*i)+7,8*i),Mux(io.addr_in_pic_r.asBool,picm_rd_data_r((8*i)+7,8*i),dccm_rdata_corr_r((8*i)+7,8*i)))))))
lsu_rdata_r := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(stbuf_fwdbyteen_r(i).asBool,stbuf_fwddata_r((8*i)+7,8*i),Mux(io.addr_in_pic_r.asBool,picm_rd_data_r((8*i)+7,8*i),dccm_rdata_r((8*i)+7,8*i))))))) lsu_rdata_r := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(stbuf_fwdbyteen_r(i).asBool,stbuf_fwddata_r((8*i)+7,8*i),Mux(io.addr_in_pic_r.asBool,picm_rd_data_r((8*i)+7,8*i),dccm_rdata_r((8*i)+7,8*i)))))))
@ -158,10 +159,10 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
} }
else{ else{
io.dccm_dma_rvalid := io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & io.lsu_pkt_m.bits.dma io.dma_dccm_ctl.dccm_dma_rvalid := io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & io.lsu_pkt_m.bits.dma
io.dccm_dma_ecc_error := io.lsu_double_ecc_error_m //from ecc io.dma_dccm_ctl.dccm_dma_ecc_error := io.lsu_double_ecc_error_m //from ecc
io.dccm_dma_rdata := lsu_rdata_corr_m io.dma_dccm_ctl.dccm_dma_rdata := lsu_rdata_corr_m
io.dccm_dma_rtag := io.dma_mem_tag_m io.dma_dccm_ctl.dccm_dma_rtag := io.dma_mem_tag_m
io.dccm_rdata_lo_r := 0.U io.dccm_rdata_lo_r := 0.U
io.dccm_rdata_hi_r := 0.U io.dccm_rdata_hi_r := 0.U
io.dccm_data_ecc_hi_r := 0.U io.dccm_data_ecc_hi_r := 0.U
@ -204,27 +205,27 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
//DCCM inputs //DCCM inputs
io.dccm_wren := lsu_dccm_wren_d | io.lsu_stbuf_commit_any | io.ld_single_ecc_error_r_ff io.lsu_mem.dccm_wren := lsu_dccm_wren_d | io.lsu_stbuf_commit_any | io.ld_single_ecc_error_r_ff
io.dccm_rden := lsu_dccm_rden_d & io.addr_in_dccm_d io.lsu_mem.dccm_rden := lsu_dccm_rden_d & io.addr_in_dccm_d
io.dccm_wr_addr_lo := Mux(io.ld_single_ecc_error_r_ff.asBool, io.lsu_mem.dccm_wr_addr_lo := Mux(io.ld_single_ecc_error_r_ff.asBool,
Mux(ld_single_ecc_error_lo_r_ff===1.U,ld_sec_addr_lo_r_ff(DCCM_BITS-1,0),ld_sec_addr_hi_r_ff(DCCM_BITS-1,0)), Mux(ld_single_ecc_error_lo_r_ff===1.U,ld_sec_addr_lo_r_ff(DCCM_BITS-1,0),ld_sec_addr_hi_r_ff(DCCM_BITS-1,0)),
Mux(lsu_dccm_wren_d.asBool,io.lsu_addr_d(DCCM_BITS-1,0),io.stbuf_addr_any(DCCM_BITS-1,0))) Mux(lsu_dccm_wren_d.asBool,io.lsu_addr_d(DCCM_BITS-1,0),io.stbuf_addr_any(DCCM_BITS-1,0)))
io.dccm_wr_addr_hi := Mux(io.ld_single_ecc_error_r_ff.asBool, io.lsu_mem.dccm_wr_addr_hi := Mux(io.ld_single_ecc_error_r_ff.asBool,
Mux(ld_single_ecc_error_hi_r_ff===1.U, ld_sec_addr_hi_r_ff(DCCM_BITS-1,0), ld_sec_addr_lo_r_ff(DCCM_BITS-1,0)), Mux(ld_single_ecc_error_hi_r_ff===1.U, ld_sec_addr_hi_r_ff(DCCM_BITS-1,0), ld_sec_addr_lo_r_ff(DCCM_BITS-1,0)),
Mux(lsu_dccm_wren_d.asBool, io.end_addr_d(DCCM_BITS-1,0),io.stbuf_addr_any(DCCM_BITS-1,0))) Mux(lsu_dccm_wren_d.asBool, io.end_addr_d(DCCM_BITS-1,0),io.stbuf_addr_any(DCCM_BITS-1,0)))
io.dccm_rd_addr_lo := io.lsu_addr_d(DCCM_BITS-1,0) io.lsu_mem.dccm_rd_addr_lo := io.lsu_addr_d(DCCM_BITS-1,0)
io.dccm_rd_addr_hi := io.end_addr_d(DCCM_BITS-1,0) io.lsu_mem.dccm_rd_addr_hi := io.end_addr_d(DCCM_BITS-1,0)
io.dccm_wr_data_lo := Mux(io.ld_single_ecc_error_r_ff.asBool, io.lsu_mem.dccm_wr_data_lo := Mux(io.ld_single_ecc_error_r_ff.asBool,
Mux(ld_single_ecc_error_lo_r_ff===1.U,Cat(io.sec_data_ecc_lo_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(DCCM_DATA_WIDTH-1,0)) , Mux(ld_single_ecc_error_lo_r_ff===1.U,Cat(io.sec_data_ecc_lo_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(DCCM_DATA_WIDTH-1,0)) ,
Cat(io.sec_data_ecc_hi_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(DCCM_DATA_WIDTH-1,0))) , Cat(io.sec_data_ecc_hi_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(DCCM_DATA_WIDTH-1,0))) ,
Mux(io.dma_dccm_wen.asBool,Cat(io.dma_dccm_wdata_ecc_lo(DCCM_ECC_WIDTH-1,0),io.dma_dccm_wdata_lo(DCCM_DATA_WIDTH-1,0)), Mux(io.dma_dccm_wen.asBool,Cat(io.dma_dccm_wdata_ecc_lo(DCCM_ECC_WIDTH-1,0),io.dma_dccm_wdata_lo(DCCM_DATA_WIDTH-1,0)),
Cat(io.stbuf_ecc_any(DCCM_ECC_WIDTH-1,0),io.stbuf_data_any(DCCM_DATA_WIDTH-1,0)))) Cat(io.stbuf_ecc_any(DCCM_ECC_WIDTH-1,0),io.stbuf_data_any(DCCM_DATA_WIDTH-1,0))))
io.dccm_wr_data_hi := Mux(io.ld_single_ecc_error_r_ff.asBool, io.lsu_mem.dccm_wr_data_hi := Mux(io.ld_single_ecc_error_r_ff.asBool,
Mux(ld_single_ecc_error_hi_r_ff===1.U, Cat(io.sec_data_ecc_hi_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(DCCM_DATA_WIDTH-1,0)), Mux(ld_single_ecc_error_hi_r_ff===1.U, Cat(io.sec_data_ecc_hi_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(DCCM_DATA_WIDTH-1,0)),
Cat(io.sec_data_ecc_lo_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(DCCM_DATA_WIDTH-1,0))), Cat(io.sec_data_ecc_lo_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(DCCM_DATA_WIDTH-1,0))),
Mux(io.dma_dccm_wen.asBool, Cat(io.dma_dccm_wdata_ecc_hi(DCCM_ECC_WIDTH-1,0),io.dma_dccm_wdata_hi(DCCM_DATA_WIDTH-1,0)), Mux(io.dma_dccm_wen.asBool, Cat(io.dma_dccm_wdata_ecc_hi(DCCM_ECC_WIDTH-1,0),io.dma_dccm_wdata_hi(DCCM_DATA_WIDTH-1,0)),
@ -286,18 +287,18 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
io.store_datafn_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi & !store_byteen_ext_r(i+4)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_hi_r((8*i)+7,8*i)))))) io.store_datafn_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi & !store_byteen_ext_r(i+4)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_hi_r((8*i)+7,8*i))))))
io.store_data_r := (Cat(io.store_data_hi_r(31,0),io.store_data_lo_r(31,0)) >> 8.U*io.lsu_addr_r(1,0)) & Reverse(Cat(VecInit.tabulate(4)(i=> Fill(8,store_byteen_r(i))))) io.store_data_r := (Cat(io.store_data_hi_r(31,0),io.store_data_lo_r(31,0)) >> 8.U*io.lsu_addr_r(1,0)) & Reverse(Cat(VecInit.tabulate(4)(i=> Fill(8,store_byteen_r(i)))))
} }
io.dccm_rdata_lo_m := io.dccm_rd_data_lo(DCCM_DATA_WIDTH-1,0) //4 lines io.dccm_rdata_lo_m := io.lsu_mem.dccm_rd_data_lo(DCCM_DATA_WIDTH-1,0) //4 lines
io.dccm_rdata_hi_m := io.dccm_rd_data_hi(DCCM_DATA_WIDTH-1,0) io.dccm_rdata_hi_m := io.lsu_mem.dccm_rd_data_hi(DCCM_DATA_WIDTH-1,0)
io.dccm_data_ecc_lo_m := io.dccm_rd_data_lo(DCCM_FDATA_WIDTH-1,DCCM_DATA_WIDTH) io.dccm_data_ecc_lo_m := io.lsu_mem.dccm_rd_data_lo(DCCM_FDATA_WIDTH-1,DCCM_DATA_WIDTH)
io.dccm_data_ecc_hi_m := io.dccm_rd_data_hi(DCCM_FDATA_WIDTH-1,DCCM_DATA_WIDTH) io.dccm_data_ecc_hi_m := io.lsu_mem.dccm_rd_data_hi(DCCM_FDATA_WIDTH-1,DCCM_DATA_WIDTH)
io.picm_wren := (io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.addr_in_pic_r & io.lsu_commit_r) | io.dma_pic_wen io.lsu_pic.picm_wren := (io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.addr_in_pic_r & io.lsu_commit_r) | io.dma_pic_wen
io.picm_rden := io.lsu_pkt_d.valid & io.lsu_pkt_d.bits.load & io.addr_in_pic_d io.lsu_pic.picm_rden := io.lsu_pkt_d.valid & io.lsu_pkt_d.bits.load & io.addr_in_pic_d
io.picm_mken := io.lsu_pkt_d.valid & io.lsu_pkt_d.bits.store & io.addr_in_pic_d io.lsu_pic.picm_mken := io.lsu_pkt_d.valid & io.lsu_pkt_d.bits.store & io.addr_in_pic_d
io.picm_rdaddr := aslong(PIC_BASE_ADDR).U | Cat(Fill(32-PIC_BITS,0.U),io.lsu_addr_d(PIC_BITS-1,0)) io.lsu_pic.picm_rdaddr := aslong(PIC_BASE_ADDR).U | Cat(Fill(32-PIC_BITS,0.U),io.lsu_addr_d(PIC_BITS-1,0))
io.picm_wraddr := aslong(PIC_BASE_ADDR).U | Cat(Fill(32-PIC_BITS,0.U),Mux(io.dma_pic_wen.asBool,io.dma_mem_addr(PIC_BITS-1,0),io.lsu_addr_r(PIC_BITS-1,0))) io.lsu_pic.picm_wraddr := aslong(PIC_BASE_ADDR).U | Cat(Fill(32-PIC_BITS,0.U),Mux(io.dma_pic_wen.asBool,io.dma_dccm_ctl.dma_mem_addr(PIC_BITS-1,0),io.lsu_addr_r(PIC_BITS-1,0)))
io.picm_mask_data_m := picm_rd_data_m(31,0) io.picm_mask_data_m := picm_rd_data_m(31,0)
io.picm_wr_data := Mux(io.dma_pic_wen.asBool,io.dma_mem_wdata(31,0),io.store_datafn_lo_r(31,0)) io.lsu_pic.picm_wr_data := Mux(io.dma_pic_wen.asBool,io.dma_dccm_ctl.dma_mem_wdata(31,0),io.store_datafn_lo_r(31,0))
if(DCCM_ENABLE){ if(DCCM_ENABLE){
io.lsu_dccm_rden_m := withClock(io.lsu_c2_m_clk){RegNext(lsu_dccm_rden_d,0.U)} io.lsu_dccm_rden_m := withClock(io.lsu_c2_m_clk){RegNext(lsu_dccm_rden_d,0.U)}

39
src/main/scala/lsu/el2_lsu_lsc_ctl.scala
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@ -29,8 +29,10 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
val flush_m_up = Input(UInt(1.W)) val flush_m_up = Input(UInt(1.W))
val flush_r = Input(UInt(1.W)) val flush_r = Input(UInt(1.W))
val exu_lsu_rs1_d = Input(UInt(32.W)) // address val lsu_exu = new lsu_exu
val exu_lsu_rs2_d = Input(UInt(32.W)) // store data
// val exu_lsu_rs1_d = Input(UInt(32.W)) // address
// val exu_lsu_rs2_d = Input(UInt(32.W)) // store data
val lsu_p = Flipped(Valid(new el2_lsu_pkt_t())) // lsu control packet //coming from decode val lsu_p = Flipped(Valid(new el2_lsu_pkt_t())) // lsu control packet //coming from decode
val dec_lsu_valid_raw_d = Input(UInt(1.W)) // Raw valid for address computation val dec_lsu_valid_raw_d = Input(UInt(1.W)) // Raw valid for address computation
@ -78,11 +80,12 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
val addr_external_m = Output(UInt(1.W)) val addr_external_m = Output(UInt(1.W))
// DMA slave // DMA slave
val dma_dccm_req = Input(UInt(1.W)) val dma_lsc_ctl = new dma_lsc_ctl
val dma_mem_addr = Input(UInt(32.W)) // val dma_dccm_req = Input(UInt(1.W))
val dma_mem_sz = Input(UInt(3.W)) // val dma_mem_addr = Input(UInt(32.W))
val dma_mem_write = Input(UInt(1.W)) // val dma_mem_sz = Input(UInt(3.W))
val dma_mem_wdata = Input(UInt(64.W)) // val dma_mem_write = Input(UInt(1.W))
// val dma_mem_wdata = Input(UInt(64.W))
// Store buffer related signals // Store buffer related signals
val lsu_pkt_d = Valid(new el2_lsu_pkt_t()) val lsu_pkt_d = Valid(new el2_lsu_pkt_t())
@ -98,7 +101,7 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
val lsu_pkt_r_in = Wire(Valid(new el2_lsu_pkt_t())) val lsu_pkt_r_in = Wire(Valid(new el2_lsu_pkt_t()))
val lsu_error_pkt_m = Wire(Valid(new el2_lsu_error_pkt_t())) val lsu_error_pkt_m = Wire(Valid(new el2_lsu_error_pkt_t()))
val lsu_rs1_d = Mux(io.dec_lsu_valid_raw_d.asBool,io.exu_lsu_rs1_d,io.dma_mem_addr) val lsu_rs1_d = Mux(io.dec_lsu_valid_raw_d.asBool,io.lsu_exu.exu_lsu_rs1_d,io.dma_lsc_ctl.dma_mem_addr)
val lsu_offset_d = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d) val lsu_offset_d = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d)
val rs1_d_raw = lsu_rs1_d val rs1_d_raw = lsu_rs1_d
val offset_d = lsu_offset_d val offset_d = lsu_offset_d
@ -188,14 +191,14 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
} }
dma_pkt_d.bits.unsign := 0.U dma_pkt_d.bits.unsign := 0.U
dma_pkt_d.bits.fast_int := 0.U dma_pkt_d.bits.fast_int := 0.U
dma_pkt_d.valid := io.dma_dccm_req dma_pkt_d.valid := io.dma_lsc_ctl.dma_dccm_req
dma_pkt_d.bits.dma := 1.U dma_pkt_d.bits.dma := 1.U
dma_pkt_d.bits.store := io.dma_mem_write dma_pkt_d.bits.store := io.dma_lsc_ctl.dma_mem_write
dma_pkt_d.bits.load := ~io.dma_mem_write dma_pkt_d.bits.load := ~io.dma_lsc_ctl.dma_mem_write
dma_pkt_d.bits.by := (io.dma_mem_sz(2,0) === 0.U(3.W)) dma_pkt_d.bits.by := (io.dma_lsc_ctl.dma_mem_sz(2,0) === 0.U(3.W))
dma_pkt_d.bits.half := (io.dma_mem_sz(2,0) === 1.U(3.W)) dma_pkt_d.bits.half := (io.dma_lsc_ctl.dma_mem_sz(2,0) === 1.U(3.W))
dma_pkt_d.bits.word := (io.dma_mem_sz(2,0) === 2.U(3.W)) dma_pkt_d.bits.word := (io.dma_lsc_ctl.dma_mem_sz(2,0) === 2.U(3.W))
dma_pkt_d.bits.dword := (io.dma_mem_sz(2,0) === 3.U(3.W)) dma_pkt_d.bits.dword := (io.dma_lsc_ctl.dma_mem_sz(2,0) === 3.U(3.W))
dma_pkt_d.bits.store_data_bypass_d := 0.U dma_pkt_d.bits.store_data_bypass_d := 0.U
dma_pkt_d.bits.load_ldst_bypass_d := 0.U dma_pkt_d.bits.load_ldst_bypass_d := 0.U
dma_pkt_d.bits.store_data_bypass_m := 0.U dma_pkt_d.bits.store_data_bypass_m := 0.U
@ -208,7 +211,7 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
lsu_pkt_m_in := io.lsu_pkt_d lsu_pkt_m_in := io.lsu_pkt_d
lsu_pkt_r_in := io.lsu_pkt_m lsu_pkt_r_in := io.lsu_pkt_m
io.lsu_pkt_d.valid := (io.lsu_p.valid & !(io.flush_m_up & !io.lsu_p.bits.fast_int)) | io.dma_dccm_req io.lsu_pkt_d.valid := (io.lsu_p.valid & !(io.flush_m_up & !io.lsu_p.bits.fast_int)) | io.dma_lsc_ctl.dma_dccm_req
lsu_pkt_m_in.valid := io.lsu_pkt_d.valid & !(io.flush_m_up & !io.lsu_pkt_d.bits.dma) lsu_pkt_m_in.valid := io.lsu_pkt_d.valid & !(io.flush_m_up & !io.lsu_pkt_d.bits.dma)
lsu_pkt_r_in.valid := io.lsu_pkt_m.valid & !(io.flush_m_up & !io.lsu_pkt_m.bits.dma) lsu_pkt_r_in.valid := io.lsu_pkt_m.valid & !(io.flush_m_up & !io.lsu_pkt_m.bits.dma)
@ -217,8 +220,8 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
io.lsu_pkt_m.valid := withClock(io.lsu_c2_m_clk){RegNext(lsu_pkt_m_in.valid,0.U)} io.lsu_pkt_m.valid := withClock(io.lsu_c2_m_clk){RegNext(lsu_pkt_m_in.valid,0.U)}
io.lsu_pkt_r.valid := withClock(io.lsu_c2_r_clk){RegNext(lsu_pkt_r_in.valid,0.U)} io.lsu_pkt_r.valid := withClock(io.lsu_c2_r_clk){RegNext(lsu_pkt_r_in.valid,0.U)}
val dma_mem_wdata_shifted = io.dma_mem_wdata(63,0) >> Cat(io.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores val dma_mem_wdata_shifted = io.dma_lsc_ctl.dma_mem_wdata(63,0) >> Cat(io.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
val store_data_d = Mux(io.dma_dccm_req.asBool,dma_mem_wdata_shifted(31,0),io.exu_lsu_rs2_d(31,0)) // Write to PIC still happens in r stage val store_data_d = Mux(io.dma_lsc_ctl.dma_dccm_req.asBool,dma_mem_wdata_shifted(31,0),io.lsu_exu.exu_lsu_rs2_d(31,0)) // Write to PIC still happens in r stage
val store_data_m_in = Mux(io.lsu_pkt_d.bits.store_data_bypass_d.asBool,io.lsu_result_m(31,0),store_data_d(31,0)) val store_data_m_in = Mux(io.lsu_pkt_d.bits.store_data_bypass_d.asBool,io.lsu_result_m(31,0),store_data_d(31,0))
val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)} val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)}

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