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Quotient new corrected

This commit is contained in:
​Laraib Khan 2021-01-07 16:18:42 +05:00
parent c874128938
commit dbe63e1ae6
8 changed files with 2155 additions and 2192 deletions
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3256
exu_div_new_4bit_fullshortq.fir
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exu_div_new_4bit_fullshortq.v
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19
src/main/scala/exu/exu_div_ctl.scala
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@ -796,7 +796,6 @@ class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib
val rq_enable = io.valid_in | valid_ff | running_state val rq_enable = io.valid_in | valid_ff | running_state
val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case
val r_adder_sel = (0 to 15 ).map(i=> (running_state & (quotient_new === i.asUInt) & !shortq_enable_ff)) val r_adder_sel = (0 to 15 ).map(i=> (running_state & (quotient_new === i.asUInt) & !shortq_enable_ff))
val adder1_out = Cat(r_ff(30,0),a_ff(31,28)) + b_ff(34,0) val adder1_out = Cat(r_ff(30,0),a_ff(31,28)) + b_ff(34,0)
val adder2_out = Cat(r_ff(31,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U) val adder2_out = Cat(r_ff(31,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U)
val adder3_out = Cat(r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U) + b_ff(36,0) val adder3_out = Cat(r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U) + b_ff(36,0)
@ -812,6 +811,7 @@ class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib
val adder13_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + b_ff val adder13_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + b_ff
val adder14_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) val adder14_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U)
val adder15_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) + b_ff val adder15_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) + b_ff
quotient_raw := Cat( quotient_raw := Cat(
(!adder15_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder15_out === 0.U)), (!adder15_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder15_out === 0.U)),
(!adder14_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder14_out === 0.U)), (!adder14_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder14_out === 0.U)),
@ -830,18 +830,17 @@ class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib
(!adder1_out(34) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder1_out === 0.U)), 0.U) (!adder1_out(34) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder1_out === 0.U)), 0.U)
quotient_new := Cat( quotient_new := Cat(
((quotient_raw(15)===1.U) | Mux1H((8 to 14).map(i=> (quotient_raw(15,i)=== Cat(Fill(15-i,0.U),1.U)).asBool -> 1.U))), (Mux1H((8 to 14).map(i=> (quotient_raw(15,i)=== Cat(Fill(15-i,0.U),1.U)).asBool -> 1.U)) | (quotient_raw(15)===1.U)),
( quotient_raw(15,4) === "b000000000001".U(12.U))| ( quotient_raw(15,5) === "b00000000001".U(11.U)) | ( quotient_raw(15,6) === "b0000000001".U(10.U)) | ( quotient_raw(15,4) === "b000000000001".U(12.W))| ( quotient_raw(15,5) === "b00000000001".U(11.W)) | ( quotient_raw(15,6) === "b0000000001".U(10.W)) |
( quotient_raw(15,7) === "b000000001".U(9.U)) | ( quotient_raw(15,12)=== "b0001".U(4.U)) | ( quotient_raw(15,13)=== "b001".U(3.U)) | ( quotient_raw(15,7) === "b000000001".U(9.W)) | ( quotient_raw(15,12)=== "b0001".U(4.W)) | ( quotient_raw(15,13)=== "b001".U(3.W)) |
( quotient_raw(15,14)=== "b01".U(2.U)) | ( quotient_raw(15) === "b1".U), ( quotient_raw(15,14)=== "b01".U(2.W)) | ( quotient_raw(15) === "b1".U),
( quotient_raw(15,2) === "b00000000000001".U(14.U))| ( quotient_raw(15,3) === "b0000000000001".U(13.U)) | ( quotient_raw(15,6) === "b0000000001".U(10.U)) | ( quotient_raw(15,2) === "b00000000000001".U(14.W))| ( quotient_raw(15,3) === "b0000000000001".U(13.W)) | ( quotient_raw(15,6) === "b0000000001".U(10.W)) |
( quotient_raw(15,7) === "b0000000_01".U(9.U)) | ( quotient_raw(15,10)=== "b000001".U(6.U)) | ( quotient_raw(15,11)=== "b00001".U(5.U)) | ( quotient_raw(15,7) === "b000000001".U(9.W)) | ( quotient_raw(15,10)=== "b000001".U(6.W)) | ( quotient_raw(15,11)=== "b00001".U(5.W)) |
( quotient_raw(15,14)=== "b01".U(2.U)) | ( quotient_raw(15) === "b1".U), ( quotient_raw(15,14)=== "b01".U(2.W)) | ( quotient_raw(15) === "b1".U),
((quotient_raw(15)===1.U) | Mux1H((1 to 13 by 2).map(i=> (quotient_raw(15,i)=== Cat(Fill(15-i,0.U),1.U)).asBool -> 1.U))))
(Mux1H((1 to 13 by 2).map(i=> (quotient_raw(15,i)=== Cat(Fill(15-i,0.U),1.U)).asBool -> 1.U)) | (quotient_raw(15)===1.U) ))
val twos_comp_in = Mux1H(Seq ( val twos_comp_in = Mux1H(Seq (
twos_comp_q_sel -> q_ff, twos_comp_q_sel -> q_ff,
twos_comp_b_sel -> b_ff(31,0) twos_comp_b_sel -> b_ff(31,0)

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target/scala-2.12/classes/exu/div_main5$.class
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target/scala-2.12/classes/exu/div_main5$delayedInit$body.class
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target/scala-2.12/classes/exu/exu_div_cls$$anon$7.class
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target/scala-2.12/classes/exu/exu_div_cls.class
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target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class
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