imp-ID to 1

quasar_wrapper.anno.json

@@ -982,7 +982,7 @@
   },
   {
     "class":"firrtl.transforms.DontTouchAnnotation",
-    "target":"~quasar_wrapper|csr_tlu>_T_755"
+    "target":"~quasar_wrapper|csr_tlu>_T_745"
   },
   {
     "class":"firrtl.transforms.BlackBoxResourceAnno",

src/main/scala/dec/dec.scala

@@ -245,10 +245,6 @@ class dec extends Module with param with RequireAsyncReset{
   tlu.io.dbg_resume_req                     :=  io.dbg_resume_req
   tlu.io.lsu_idle_any                       :=  io.lsu_idle_any
   tlu.io.dec_div_active                     :=  decode.io.dec_div_active
-//  tlu.io.pic_claimid                        :=  io.dec_pic.pic_claimid
-//  tlu.io.pic_pl                             :=  io.dec_pic.pic_pl
-//  tlu.io.mhwakeup                           :=  io.dec_pic.mhwakeup
-//  tlu.io.mexintpend                         :=  io.mexintpend
   tlu.io.timer_int                          :=  io.timer_int
   tlu.io.soft_int                           :=  io.soft_int
   tlu.io.core_id                            :=  io.core_id
@@ -269,8 +265,6 @@ class dec extends Module with param with RequireAsyncReset{
   io.mpc_debug_halt_ack     := tlu.io.mpc_debug_halt_ack
   io.mpc_debug_run_ack      := tlu.io.mpc_debug_run_ack
   io.debug_brkpt_status     := tlu.io.debug_brkpt_status
-//  io.dec_pic.dec_tlu_meicurpl       := tlu.io.dec_tlu_meicurpl
-//  io.dec_pic.dec_tlu_meipt          := tlu.io.dec_tlu_meipt
   io.dec_tlu_i0_kill_writeb_r    := tlu.io.dec_tlu_i0_kill_writeb_r
   io.dec_tlu_perfcnt0       := tlu.io.dec_tlu_perfcnt0
   io.dec_tlu_perfcnt1       := tlu.io.dec_tlu_perfcnt1

src/main/scala/dec/dec_tlu_ctl.scala

@@ -560,8 +560,6 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
    // o_cpu_halt_status _______________|---------------------|_________
    // i_cpu_run_req                              ______|----------|____
    // o_cpu_run_ack                              ____________|------|________
-   //
-
 
    // debug mode has priority, ignore PMU/FW halt/run while in debug mode
 	val i_cpu_halt_req_sync_qual = i_cpu_halt_req_sync & ~io.dec_tlu_debug_mode & ~ext_int_freeze_d1
@@ -797,7 +795,6 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
 	val tlu_flush_path_r_d1=withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this
 
    	io.dec_tlu_flush_lower_wb 	:= tlu_flush_lower_r_d1
-//    io.tlu_mem.dec_tlu_flush_lower_wb 	:= io.dec_tlu_flush_lower_wb
    	io.tlu_exu.dec_tlu_flush_lower_r 	:= tlu_flush_lower_r
    	io.tlu_exu.dec_tlu_flush_path_r 	:= tlu_flush_path_r ///After Combining Code revisit this
 
@@ -1165,8 +1162,6 @@ trait CSRs{
  val MHPME_DMA_WRITE_ALL   	= 514.U // OOP
  val MHPME_DMA_READ_DCCM   	= 515.U // OOP
  val MHPME_DMA_WRITE_DCCM  	= 516.U // OOP
-
-
 }
 class CSR_IO extends Bundle with lib {
   val free_clk                          = Input(Clock())
@@ -1200,8 +1195,6 @@ class CSR_IO extends Bundle with lib {
   val dec_tlu_i0_exc_valid_wb1          = Output(UInt(1.W))
   val dec_tlu_i0_valid_wb1              = Output(UInt(1.W))
   val dec_csr_wen_r                     = Input(UInt(1.W))
-  //val dec_tlu_force_halt                = Output(UInt(1.W))
-  //val dec_tlu_flush_extint              = Output(UInt(1.W))
   val dec_tlu_mtval_wb1                 = Output(UInt(32.W))
   val dec_tlu_exc_cause_wb1             = Output(UInt(5.W))
   val dec_tlu_perfcnt0                  = Output(UInt(1.W))
@@ -1226,17 +1219,7 @@ class CSR_IO extends Bundle with lib {
   val dec_tlu_pic_clk_override          = Output(UInt(1.W)) 
   val dec_tlu_dccm_clk_override         = Output(UInt(1.W))
   val dec_tlu_icm_clk_override          = Output(UInt(1.W))
-  //val dec_csr_legal_d                   = Output(UInt(1.W))
   val dec_csr_rddata_d                  = Output(UInt(32.W))
-  //val dec_tlu_postsync_d                = Output(UInt(1.W)) 
-  //val dec_tlu_presync_d                 = Output(UInt(1.W))
-  //val dec_tlu_flush_pause_r             = Output(UInt(1.W))
-  //val dec_tlu_flush_lower_r             = Output(UInt(1.W))
-  //val dec_tlu_i0_kill_writeb_r          = Output(UInt(1.W))
-  //val dec_tlu_flush_lower_wb            = Output(UInt(1.W))
-  //val dec_tlu_i0_kill_writeb_wb         = Output(UInt(1.W))
- // val dec_tlu_flush_leak_one_wb          = Output(UInt(1.W))
-  //val dec_tlu_debug_stall               = Output(UInt(1.W))
   val dec_tlu_pipelining_disable        = Output(UInt(1.W))
   val dec_tlu_wr_pause_r                = Output(UInt(1.W))
   val ifu_pmu_bus_busy                  = Input(UInt(1.W))
@@ -1396,7 +1379,6 @@ val wr_mcycleh_r                = WireInit(UInt(1.W), 0.U)
   val force_halt_ctr_f			      = WireInit(UInt(32.W),0.U) 
   val mdccmect_inc                = WireInit(UInt(27.W),0.U) 
   val miccmect_inc                = WireInit(UInt(27.W),0.U)
-  //val fw_halted                   = WireInit(UInt(1.W),0.U)
   val micect_inc                  = WireInit(UInt(27.W),0.U) 
   val mdseac_en                   = WireInit(UInt(1.W),0.U) 
   val mie                         = WireInit(UInt(6.W),0.U)

src/main/scala/exu/exu.scala

@@ -141,7 +141,7 @@ class exu extends Module with lib with RequireAsyncReset{
   csr_rs1_in_d       := Mux(io.dec_exu.dec_alu.dec_csr_ren_d.asBool, i0_rs1_d, io.dec_exu.decode_exu.exu_csr_rs1_x)
 
 
-  val i_alu=Module(new exu_alu_ctl)
+  val i_alu=Module(new exu_alu_ctl())
   i_alu.io.dec_alu <> io.dec_exu.dec_alu
   i_alu.io.scan_mode		:=io.scan_mode
   i_alu.io.enable			:=x_ctl_en
@@ -159,14 +159,14 @@ class exu extends Module with lib with RequireAsyncReset{
   i0_predict_p_d			:=i_alu.io.predict_p_out
   i0_pred_correct_upper_d :=i_alu.io.pred_correct_out
 
-  val i_mul=Module(new exu_mul_ctl)
+  val i_mul = Module(new exu_mul_ctl())
   i_mul.io.scan_mode	:= io.scan_mode
   i_mul.io.mul_p			:= io.dec_exu.decode_exu.mul_p
   i_mul.io.rs1_in			:= muldiv_rs1_d
   i_mul.io.rs2_in			:= muldiv_rs2_d
   val mul_result_x		=  i_mul.io.result_x
 
-  val i_div=Module(new exu_div_ctl)
+  val i_div = Module(new exu_div_ctl())
   i_div.io.dec_div <> io.dec_exu.dec_div
   i_div.io.scan_mode		:= io.scan_mode
 

src/main/scala/include/bundle.scala

@@ -34,7 +34,6 @@ class tlu_dma extends Bundle{
 
 class dec_bp extends Bundle{
   val dec_tlu_br0_r_pkt = Flipped(Valid(new br_tlu_pkt_t))
-  //  val dec_tlu_flush_lower_wb = Input(Bool())
   val dec_tlu_flush_leak_one_wb = Input(Bool())
   val dec_tlu_bpred_disable = Input(Bool())
 }
@@ -71,8 +70,8 @@ class ahb_out extends Bundle{
   val hwdata        = Output(UInt(64.W)) // [63:0]  // ahb bus write data
 }
 class ahb_channel extends Bundle{
-  val in  = new ahb_in
+  val in  = new ahb_in()
-  val out = new ahb_out
+  val out = new ahb_out()
 }
 class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{
   val aw = Decoupled(new write_addr(BUS_TAG))
@@ -272,13 +271,16 @@ class ifu_dec extends Bundle{
   val dec_ifc = new dec_ifc
   val dec_bp = new dec_bp
 }
+
 class exu_ifu extends Bundle{
   val exu_bp = Flipped(new exu_bp())
 }
+
 class ifu_dma extends Bundle{
   val dma_ifc  = new dma_ifc
   val dma_mem_ctl = new dma_mem_ctl
 }
+
 class dma_mem_ctl extends Bundle{
   val dma_iccm_req = Input(Bool())
   val dma_mem_addr = Input(UInt(32.W))
@@ -287,6 +289,7 @@ class dma_mem_ctl extends Bundle{
   val dma_mem_wdata = Input(UInt(64.W))
   val dma_mem_tag = Input(UInt(3.W))
 }
+
 class dma_ifc extends  Bundle{
   val dma_iccm_stall_any = Input(Bool())
 }
@@ -301,14 +304,11 @@ class trace_pkt_t extends Bundle{
   val rv_i_tval_ip       = Output(UInt(32.W) )
 }
 
-
-
-
 class dec_dbg extends Bundle{
   val dbg_ib = new dbg_ib
   val dbg_dctl = new dbg_dctl
-
 }
+
 class dbg_ib extends Bundle{
   val dbg_cmd_valid           = Input(Bool())    // debugger abstract command valid
   val dbg_cmd_write           = Input(Bool())    // command is a write
@@ -320,8 +320,6 @@ class dbg_dctl extends Bundle{
   val dbg_cmd_wrdata          = Input(UInt(32.W))    // command write data, for fence/fence_i
 }
 
-
-
 class dec_alu extends Bundle {
   val                  dec_i0_alu_decode_d          = Input(UInt(1.W))          // Valid
   val                  dec_csr_ren_d                = Input(Bool())          // extra decode
@@ -418,7 +416,6 @@ object inst_pkt_t extends Enumeration{
 }
 
 class load_cam_pkt_t extends Bundle {
-  //val valid = UInt(1.W)
   val wb    = UInt(1.W)
   val tag   = UInt(3.W)
   val rd    = UInt(5.W)
@@ -431,7 +428,6 @@ class rets_pkt_t extends Bundle {
 }
 
 class br_pkt_t extends Bundle {
-  // val valid          = UInt(1.W)
   val toffset        = UInt(12.W)
   val hist           = UInt(2.W)
   val br_error       = UInt(1.W)
@@ -444,7 +440,6 @@ class br_pkt_t extends Bundle {
 
 
 class br_tlu_pkt_t extends Bundle {
-  // val valid           = UInt(1.W)
   val hist            = UInt(2.W)
   val br_error        = UInt(1.W)
   val br_start_error  = UInt(1.W)
@@ -459,7 +454,6 @@ class predict_pkt_t extends Bundle {
   val pc4        = UInt(1.W)
   val hist       = UInt(2.W)
   val toffset    = UInt(12.W)
-  // val valid      = UInt(1.W)
   val br_error   = UInt(1.W)
   val br_start_error = UInt(1.W)
   val prett      = UInt(31.W)
@@ -477,7 +471,7 @@ class trap_pkt_t extends Bundle {
   val icaf_type = UInt(2.W)
   val fence_i   = UInt(1.W)
   val i0trigger = UInt(4.W)
-  val pmu_i0_itype =UInt(4.W) //new inst_pkt_t   //pmu-instructiontype
+  val pmu_i0_itype =UInt(4.W) //pmu-instructiontype
   val pmu_i0_br_unpred   = UInt(1.W)  //pmu
   val pmu_divide         = UInt(1.W)
   val pmu_lsu_misaligned = UInt(1.W)
@@ -489,7 +483,6 @@ class dest_pkt_t extends Bundle {
   val i0store   = UInt(1.W)
   val i0div     = UInt(1.W)
   val i0v       = UInt(1.W)
-  // val i0valid   = UInt(1.W)
   val csrwen    = UInt(1.W)
   val csrwonly  = UInt(1.W)
   val csrwaddr  = UInt(12.W)
@@ -543,11 +536,9 @@ class lsu_pkt_t extends Bundle {
   val store_data_bypass_d  = Bool()
   val load_ldst_bypass_d   = Bool()
   val store_data_bypass_m  = Bool()
-  //  val valid      = Bool()
 }
 
 class lsu_error_pkt_t extends Bundle {
-  // val exc_valid   = UInt(1.W)
   val single_ecc_error  = UInt(1.W)
   val inst_type    = UInt(1.W)    //0: Load, 1: Store
   val exc_type     = UInt(1.W)    //0: MisAligned, 1: Access Fault
@@ -609,7 +600,6 @@ class dec_pkt_t extends Bundle {
 }
 
 class mul_pkt_t extends Bundle {
-  // val valid     = UInt(1.W)
   val rs1_sign  = UInt(1.W)
   val rs2_sign  = UInt(1.W)
   val low       = UInt(1.W)
@@ -631,7 +621,6 @@ class mul_pkt_t extends Bundle {
 }
 
 class div_pkt_t extends Bundle {
-  // val valid     = UInt(1.W)
   val unsign    = UInt(1.W)
   val rem       = UInt(1.W)
 }
@@ -640,7 +629,6 @@ class ccm_ext_in_pkt_t extends Bundle {
   val        TEST1    = UInt(1.W)
   val        RME      = UInt(1.W)
   val        RM       = UInt(4.W)
-
   val        LS        = UInt(1.W)
   val        DS        = UInt(1.W)
   val        SD        = UInt(1.W)

src/main/scala/lib/param.scala

@@ -21,8 +21,8 @@ trait param {
   val BTB_INDEX3_HI          = 	0x19
   val BTB_INDEX3_LO          = 	0x12
   val BTB_SIZE               = 	0x200
-  val BUILD_AHB_LITE         = 	0x0
+  val BUILD_AHB_LITE         = 	0x1
-  val BUILD_AXI4             = 	0x1
+  val BUILD_AXI4             = 	0x0
   val BUILD_AXI_NATIVE       = 	0x1
   val BUS_PRTY_DEFAULT       = 	0x3
   val DATA_ACCESS_ADDR0      = 	0x00000000

src/main/scala/lsu/lsu_ecc.scala

@@ -71,8 +71,6 @@ class lsu_ecc extends Module with lib with RequireAsyncReset {
   val dccm_wdata_lo_any            = WireInit(0.U(DCCM_DATA_WIDTH.W))
   val dccm_rdata_hi_any            = WireInit(0.U(DCCM_DATA_WIDTH.W))
   val dccm_rdata_lo_any            = WireInit(0.U(DCCM_DATA_WIDTH.W))
-  // val dccm_wdata_ecc_hi_any        = WireInit(0.U(DCCM_ECC_WIDTH.W))
-  //val dccm_wdata_ecc_lo_any        = WireInit(0.U(DCCM_ECC_WIDTH.W))
   val dccm_data_ecc_hi_any         = WireInit(0.U(DCCM_ECC_WIDTH.W))
   val dccm_data_ecc_lo_any         = WireInit(0.U(DCCM_ECC_WIDTH.W))
   val double_ecc_error_hi_m	       = WireInit(Bool(),init = 0.U)

src/main/scala/lsu/lsu_stbuf.scala

@@ -264,7 +264,4 @@ class lsu_stbuf extends Module with lib with RequireAsyncReset {
   val stbuf_fwdpipe3_hi = Mux(ld_byte_rhit_hi(2),ld_fwddata_rpipe_hi(23,16),stbuf_fwddata_hi_pre_m(23,16))
   val stbuf_fwdpipe4_hi = Mux(ld_byte_rhit_hi(3),ld_fwddata_rpipe_hi(31,24),stbuf_fwddata_hi_pre_m(31,24))
   io.stbuf_fwddata_hi_m := Cat(stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi,stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi)
-
-
-
 }

src/main/scala/lsu/lsu_trigger.scala

@@ -18,5 +18,4 @@ class lsu_trigger extends Module with RequireAsyncReset with lib {
   io.lsu_trigger_match_m :=  (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.bits.dma & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.bits.store)|
     (io.trigger_pkt_any(i).load & io.lsu_pkt_m.bits.load & !io.trigger_pkt_any(i).select) )&
     rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_pkt.asBool())).reverse.reduce(Cat(_,_))
-
 }

src/main/scala/quasar_wrapper.scala

@@ -71,8 +71,6 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
   dmi_wrapper.io.core_clk := clock
   dmi_wrapper.io.jtag_id := io.jtag_id
   dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
-
-
   dmi_wrapper.io.core_rst_n := io.dbg_rst_l
   core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
   core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
@@ -144,7 +142,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
 
   // Outputs
   val core_rst_l = core.io.core_rst_l
-  io.rv_trace_pkt := core.io.rv_trace_pkt
+  io.rv_trace_pkt <> core.io.rv_trace_pkt
 
   // external halt/run interface
   io.o_cpu_halt_ack := core.io.o_cpu_halt_ack