imp-ID to 1
This commit is contained in:
parent
158e702716
commit
f36c650bf3
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@ -982,7 +982,7 @@
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~quasar_wrapper|csr_tlu>_T_755"
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"target":"~quasar_wrapper|csr_tlu>_T_745"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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18164
quasar_wrapper.fir
18164
quasar_wrapper.fir
File diff suppressed because it is too large
Load Diff
10428
quasar_wrapper.v
10428
quasar_wrapper.v
File diff suppressed because it is too large
Load Diff
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@ -245,10 +245,6 @@ class dec extends Module with param with RequireAsyncReset{
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tlu.io.dbg_resume_req := io.dbg_resume_req
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tlu.io.lsu_idle_any := io.lsu_idle_any
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tlu.io.dec_div_active := decode.io.dec_div_active
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// tlu.io.pic_claimid := io.dec_pic.pic_claimid
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// tlu.io.pic_pl := io.dec_pic.pic_pl
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// tlu.io.mhwakeup := io.dec_pic.mhwakeup
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// tlu.io.mexintpend := io.mexintpend
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tlu.io.timer_int := io.timer_int
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tlu.io.soft_int := io.soft_int
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tlu.io.core_id := io.core_id
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@ -269,8 +265,6 @@ class dec extends Module with param with RequireAsyncReset{
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io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack
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io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack
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io.debug_brkpt_status := tlu.io.debug_brkpt_status
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// io.dec_pic.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl
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// io.dec_pic.dec_tlu_meipt := tlu.io.dec_tlu_meipt
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io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
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io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0
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io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1
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@ -560,8 +560,6 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
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// o_cpu_halt_status _______________|---------------------|_________
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// i_cpu_run_req ______|----------|____
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// o_cpu_run_ack ____________|------|________
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//
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// debug mode has priority, ignore PMU/FW halt/run while in debug mode
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val i_cpu_halt_req_sync_qual = i_cpu_halt_req_sync & ~io.dec_tlu_debug_mode & ~ext_int_freeze_d1
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@ -797,7 +795,6 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
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val tlu_flush_path_r_d1=withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this
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io.dec_tlu_flush_lower_wb := tlu_flush_lower_r_d1
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// io.tlu_mem.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
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io.tlu_exu.dec_tlu_flush_lower_r := tlu_flush_lower_r
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io.tlu_exu.dec_tlu_flush_path_r := tlu_flush_path_r ///After Combining Code revisit this
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@ -1165,8 +1162,6 @@ trait CSRs{
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val MHPME_DMA_WRITE_ALL = 514.U // OOP
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val MHPME_DMA_READ_DCCM = 515.U // OOP
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val MHPME_DMA_WRITE_DCCM = 516.U // OOP
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}
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class CSR_IO extends Bundle with lib {
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val free_clk = Input(Clock())
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@ -1200,8 +1195,6 @@ class CSR_IO extends Bundle with lib {
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val dec_tlu_i0_exc_valid_wb1 = Output(UInt(1.W))
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val dec_tlu_i0_valid_wb1 = Output(UInt(1.W))
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val dec_csr_wen_r = Input(UInt(1.W))
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//val dec_tlu_force_halt = Output(UInt(1.W))
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//val dec_tlu_flush_extint = Output(UInt(1.W))
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val dec_tlu_mtval_wb1 = Output(UInt(32.W))
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val dec_tlu_exc_cause_wb1 = Output(UInt(5.W))
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val dec_tlu_perfcnt0 = Output(UInt(1.W))
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@ -1226,17 +1219,7 @@ class CSR_IO extends Bundle with lib {
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val dec_tlu_pic_clk_override = Output(UInt(1.W))
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val dec_tlu_dccm_clk_override = Output(UInt(1.W))
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val dec_tlu_icm_clk_override = Output(UInt(1.W))
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//val dec_csr_legal_d = Output(UInt(1.W))
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val dec_csr_rddata_d = Output(UInt(32.W))
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//val dec_tlu_postsync_d = Output(UInt(1.W))
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//val dec_tlu_presync_d = Output(UInt(1.W))
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//val dec_tlu_flush_pause_r = Output(UInt(1.W))
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//val dec_tlu_flush_lower_r = Output(UInt(1.W))
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//val dec_tlu_i0_kill_writeb_r = Output(UInt(1.W))
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//val dec_tlu_flush_lower_wb = Output(UInt(1.W))
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//val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W))
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// val dec_tlu_flush_leak_one_wb = Output(UInt(1.W))
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//val dec_tlu_debug_stall = Output(UInt(1.W))
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val dec_tlu_pipelining_disable = Output(UInt(1.W))
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val dec_tlu_wr_pause_r = Output(UInt(1.W))
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val ifu_pmu_bus_busy = Input(UInt(1.W))
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@ -1396,7 +1379,6 @@ val wr_mcycleh_r = WireInit(UInt(1.W), 0.U)
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val force_halt_ctr_f = WireInit(UInt(32.W),0.U)
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val mdccmect_inc = WireInit(UInt(27.W),0.U)
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val miccmect_inc = WireInit(UInt(27.W),0.U)
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//val fw_halted = WireInit(UInt(1.W),0.U)
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val micect_inc = WireInit(UInt(27.W),0.U)
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val mdseac_en = WireInit(UInt(1.W),0.U)
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val mie = WireInit(UInt(6.W),0.U)
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@ -141,7 +141,7 @@ class exu extends Module with lib with RequireAsyncReset{
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csr_rs1_in_d := Mux(io.dec_exu.dec_alu.dec_csr_ren_d.asBool, i0_rs1_d, io.dec_exu.decode_exu.exu_csr_rs1_x)
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val i_alu=Module(new exu_alu_ctl)
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val i_alu=Module(new exu_alu_ctl())
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i_alu.io.dec_alu <> io.dec_exu.dec_alu
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i_alu.io.scan_mode :=io.scan_mode
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i_alu.io.enable :=x_ctl_en
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@ -159,14 +159,14 @@ class exu extends Module with lib with RequireAsyncReset{
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i0_predict_p_d :=i_alu.io.predict_p_out
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i0_pred_correct_upper_d :=i_alu.io.pred_correct_out
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val i_mul=Module(new exu_mul_ctl)
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val i_mul = Module(new exu_mul_ctl())
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i_mul.io.scan_mode := io.scan_mode
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i_mul.io.mul_p := io.dec_exu.decode_exu.mul_p
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i_mul.io.rs1_in := muldiv_rs1_d
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i_mul.io.rs2_in := muldiv_rs2_d
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val mul_result_x = i_mul.io.result_x
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val i_div=Module(new exu_div_ctl)
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val i_div = Module(new exu_div_ctl())
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i_div.io.dec_div <> io.dec_exu.dec_div
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i_div.io.scan_mode := io.scan_mode
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@ -34,7 +34,6 @@ class tlu_dma extends Bundle{
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class dec_bp extends Bundle{
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val dec_tlu_br0_r_pkt = Flipped(Valid(new br_tlu_pkt_t))
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// val dec_tlu_flush_lower_wb = Input(Bool())
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val dec_tlu_flush_leak_one_wb = Input(Bool())
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val dec_tlu_bpred_disable = Input(Bool())
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}
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@ -71,8 +70,8 @@ class ahb_out extends Bundle{
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val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data
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}
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class ahb_channel extends Bundle{
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val in = new ahb_in
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val out = new ahb_out
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val in = new ahb_in()
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val out = new ahb_out()
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}
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class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{
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val aw = Decoupled(new write_addr(BUS_TAG))
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@ -272,13 +271,16 @@ class ifu_dec extends Bundle{
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val dec_ifc = new dec_ifc
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val dec_bp = new dec_bp
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}
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class exu_ifu extends Bundle{
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val exu_bp = Flipped(new exu_bp())
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}
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class ifu_dma extends Bundle{
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val dma_ifc = new dma_ifc
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val dma_mem_ctl = new dma_mem_ctl
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}
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class dma_mem_ctl extends Bundle{
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val dma_iccm_req = Input(Bool())
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val dma_mem_addr = Input(UInt(32.W))
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@ -287,6 +289,7 @@ class dma_mem_ctl extends Bundle{
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val dma_mem_wdata = Input(UInt(64.W))
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val dma_mem_tag = Input(UInt(3.W))
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}
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class dma_ifc extends Bundle{
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val dma_iccm_stall_any = Input(Bool())
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}
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@ -301,14 +304,11 @@ class trace_pkt_t extends Bundle{
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val rv_i_tval_ip = Output(UInt(32.W) )
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}
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class dec_dbg extends Bundle{
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val dbg_ib = new dbg_ib
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val dbg_dctl = new dbg_dctl
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}
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class dbg_ib extends Bundle{
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val dbg_cmd_valid = Input(Bool()) // debugger abstract command valid
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val dbg_cmd_write = Input(Bool()) // command is a write
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@ -320,8 +320,6 @@ class dbg_dctl extends Bundle{
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val dbg_cmd_wrdata = Input(UInt(32.W)) // command write data, for fence/fence_i
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}
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class dec_alu extends Bundle {
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val dec_i0_alu_decode_d = Input(UInt(1.W)) // Valid
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val dec_csr_ren_d = Input(Bool()) // extra decode
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@ -418,7 +416,6 @@ object inst_pkt_t extends Enumeration{
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}
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class load_cam_pkt_t extends Bundle {
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//val valid = UInt(1.W)
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val wb = UInt(1.W)
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val tag = UInt(3.W)
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val rd = UInt(5.W)
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@ -431,7 +428,6 @@ class rets_pkt_t extends Bundle {
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}
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class br_pkt_t extends Bundle {
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// val valid = UInt(1.W)
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val toffset = UInt(12.W)
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val hist = UInt(2.W)
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val br_error = UInt(1.W)
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@ -444,7 +440,6 @@ class br_pkt_t extends Bundle {
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class br_tlu_pkt_t extends Bundle {
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// val valid = UInt(1.W)
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val hist = UInt(2.W)
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val br_error = UInt(1.W)
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val br_start_error = UInt(1.W)
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@ -459,7 +454,6 @@ class predict_pkt_t extends Bundle {
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val pc4 = UInt(1.W)
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val hist = UInt(2.W)
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val toffset = UInt(12.W)
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// val valid = UInt(1.W)
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val br_error = UInt(1.W)
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val br_start_error = UInt(1.W)
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val prett = UInt(31.W)
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@ -477,7 +471,7 @@ class trap_pkt_t extends Bundle {
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val icaf_type = UInt(2.W)
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val fence_i = UInt(1.W)
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val i0trigger = UInt(4.W)
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val pmu_i0_itype =UInt(4.W) //new inst_pkt_t //pmu-instructiontype
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val pmu_i0_itype =UInt(4.W) //pmu-instructiontype
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val pmu_i0_br_unpred = UInt(1.W) //pmu
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val pmu_divide = UInt(1.W)
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val pmu_lsu_misaligned = UInt(1.W)
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@ -489,7 +483,6 @@ class dest_pkt_t extends Bundle {
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val i0store = UInt(1.W)
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val i0div = UInt(1.W)
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val i0v = UInt(1.W)
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// val i0valid = UInt(1.W)
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val csrwen = UInt(1.W)
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val csrwonly = UInt(1.W)
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val csrwaddr = UInt(12.W)
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@ -543,11 +536,9 @@ class lsu_pkt_t extends Bundle {
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val store_data_bypass_d = Bool()
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val load_ldst_bypass_d = Bool()
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val store_data_bypass_m = Bool()
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// val valid = Bool()
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}
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class lsu_error_pkt_t extends Bundle {
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// val exc_valid = UInt(1.W)
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val single_ecc_error = UInt(1.W)
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val inst_type = UInt(1.W) //0: Load, 1: Store
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val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault
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@ -609,7 +600,6 @@ class dec_pkt_t extends Bundle {
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}
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class mul_pkt_t extends Bundle {
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// val valid = UInt(1.W)
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val rs1_sign = UInt(1.W)
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val rs2_sign = UInt(1.W)
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val low = UInt(1.W)
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@ -631,7 +621,6 @@ class mul_pkt_t extends Bundle {
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}
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class div_pkt_t extends Bundle {
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// val valid = UInt(1.W)
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val unsign = UInt(1.W)
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val rem = UInt(1.W)
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}
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@ -640,7 +629,6 @@ class ccm_ext_in_pkt_t extends Bundle {
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val TEST1 = UInt(1.W)
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val RME = UInt(1.W)
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val RM = UInt(4.W)
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val LS = UInt(1.W)
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val DS = UInt(1.W)
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val SD = UInt(1.W)
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@ -21,8 +21,8 @@ trait param {
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val BTB_INDEX3_HI = 0x19
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val BTB_INDEX3_LO = 0x12
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val BTB_SIZE = 0x200
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val BUILD_AHB_LITE = 0x0
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val BUILD_AXI4 = 0x1
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val BUILD_AHB_LITE = 0x1
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val BUILD_AXI4 = 0x0
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val BUILD_AXI_NATIVE = 0x1
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val BUS_PRTY_DEFAULT = 0x3
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val DATA_ACCESS_ADDR0 = 0x00000000
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@ -71,8 +71,6 @@ class lsu_ecc extends Module with lib with RequireAsyncReset {
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val dccm_wdata_lo_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
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val dccm_rdata_hi_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
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val dccm_rdata_lo_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
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// val dccm_wdata_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
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//val dccm_wdata_ecc_lo_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
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val dccm_data_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
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val dccm_data_ecc_lo_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
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val double_ecc_error_hi_m = WireInit(Bool(),init = 0.U)
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@ -264,7 +264,4 @@ class lsu_stbuf extends Module with lib with RequireAsyncReset {
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val stbuf_fwdpipe3_hi = Mux(ld_byte_rhit_hi(2),ld_fwddata_rpipe_hi(23,16),stbuf_fwddata_hi_pre_m(23,16))
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val stbuf_fwdpipe4_hi = Mux(ld_byte_rhit_hi(3),ld_fwddata_rpipe_hi(31,24),stbuf_fwddata_hi_pre_m(31,24))
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io.stbuf_fwddata_hi_m := Cat(stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi,stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi)
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}
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@ -18,5 +18,4 @@ class lsu_trigger extends Module with RequireAsyncReset with lib {
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io.lsu_trigger_match_m := (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.bits.dma & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.bits.store)|
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(io.trigger_pkt_any(i).load & io.lsu_pkt_m.bits.load & !io.trigger_pkt_any(i).select) )&
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rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_pkt.asBool())).reverse.reduce(Cat(_,_))
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}
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@ -71,8 +71,6 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
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dmi_wrapper.io.core_clk := clock
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dmi_wrapper.io.jtag_id := io.jtag_id
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dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
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dmi_wrapper.io.core_rst_n := io.dbg_rst_l
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core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
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core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
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@ -144,7 +142,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
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// Outputs
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val core_rst_l = core.io.core_rst_l
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io.rv_trace_pkt := core.io.rv_trace_pkt
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io.rv_trace_pkt <> core.io.rv_trace_pkt
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// external halt/run interface
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io.o_cpu_halt_ack := core.io.o_cpu_halt_ack
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